Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3188434

1

T1

111

T3

2835

T4

2417

auto[1]

28615

1

T5

27

T10

2

T31

146

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

943155

1

T1

111

T3

2835

T4

2417

auto[1]

2273894

1

T5

3759

T10

3

T31

4352

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	590996	1			T3	400		T4	17		T5	132
auto[524288:1048575]	367877	1			T1	52		T3	255		T4	2394
auto[1048576:1572863]	391269	1			T3	52		T5	642		T6	62
auto[1572864:2097151]	406387	1			T3	254		T5	2485		T6	49
auto[2097152:2621439]	368100	1			T3	497		T6	1		T31	129
auto[2621440:3145727]	348774	1			T1	31		T3	487		T6	206
auto[3145728:3670015]	350489	1			T1	28		T3	414		T4	6
auto[3670016:4194303]	393157	1			T3	476		T5	257		T6	28

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2305247

1

T1

6

T3

118

T4

6

auto[1]

911802

1

T1

105

T3

2717

T4

2411

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2780234

1

T1

111

T3

2835

T4

2417

auto[1]

436815

1

T5

2725

T6

176

T10

2

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	189942	1			T3	400		T4	17		T5	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	352349	1			T5	131		T31	1376		T49	5750
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	125262	1			T1	52		T3	255		T4	2394
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	188130	1			T31	644		T37	260		T27	1454
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	95354	1			T3	52		T5	1		T6	62
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	235195	1			T5	640		T37	256		T13	8
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	129359	1			T3	254		T5	3		T6	48
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	213134	1			T5	257		T37	262		T23	2
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	91594	1			T3	497		T6	1		T31	3
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	208035	1			T31	117		T37	1635		T27	768
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	90491	1			T1	31		T3	487		T6	206
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	204543	1			T10	1		T31	386		T27	9
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	89460	1			T1	28		T3	414		T4	6
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	220781	1			T37	512		T27	5		T13	372
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	109909	1			T3	476		T6	28		T31	6
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	213744	1			T10	1		T31	1435		T37	2246
auto[0]	auto[1]	auto[0:524287]	auto[0]	926	1			T6	110		T37	5		T27	1
auto[0]	auto[1]	auto[0:524287]	auto[1]	43073	1			T13	512		T45	324		T71	2005
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1734	1			T5	2		T6	64		T10	1
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	50187	1			T5	256		T31	1		T27	2078
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	2792	1			T5	1		T37	18		T27	2
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	55161	1			T37	47		T27	3		T38	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1826	1			T5	4		T6	1		T10	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	58111	1			T5	2194		T34	4		T39	2238
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	3143	1			T37	9		T13	1		T38	5
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	60294	1			T27	591		T13	512		T38	745
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	1282	1			T37	5		T27	7		T13	1
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	49417	1			T37	4		T27	643		T43	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	1788	1			T6	1		T31	2		T37	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	35083	1			T31	1		T13	2614		T34	260
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	4542	1			T5	1		T31	7		T37	33
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	61793	1			T5	256		T31	258		T37	646
auto[1]	auto[0]	auto[0:524287]	auto[0]	526	1			T31	2		T37	21		T23	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3455	1			T31	2		T37	49		T23	23
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	315	1			T31	1		T37	5		T27	4
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1506	1			T31	33		T27	6		T13	43
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	396	1			T37	12		T13	8		T38	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1996	1			T13	124		T38	31		T44	17
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	378	1			T5	1		T37	3		T23	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2541	1			T5	15		T23	12		T27	5
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	414	1			T31	2		T13	2		T38	6
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3799	1			T31	7		T13	1		T38	112
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	360	1			T10	1		T31	2		T37	2
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2298	1			T10	1		T31	61		T27	9
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	368	1			T27	1		T13	3		T38	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1815	1			T27	3		T13	59		T38	12
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	319	1			T31	1		T13	4		T33	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2466	1			T31	1		T13	57		T44	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	100	1			T45	1		T71	3		T17	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	625	1			T71	4		T17	1		T160	48
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	104	1			T31	1		T37	2		T34	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	639	1			T31	23		T34	8		T153	13
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	74	1			T37	10		T38	1		T259	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	301	1			T38	31		T259	5		T180	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	108	1			T5	1		T39	3		T153	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	930	1			T5	10		T153	34		T150	4
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	96	1			T37	9		T47	7		T35	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	725	1			T47	88		T271	12		T148	4
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	62	1			T37	7		T27	3		T150	2
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	321	1			T27	3		T150	2		T17	17
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	72	1			T31	1		T13	2		T78	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	1122	1			T13	7		T14	1		T17	27
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	59	1			T31	2		T13	1		T35	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	325	1			T31	7		T13	8		T35	1

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1859291	1			T1	6		T3	118		T4	6
auto[0]	auto[0]	auto[1]	897991	1			T1	105		T3	2717		T4	2411
auto[0]	auto[1]	auto[0]	417962	1			T5	2714		T6	7		T10	2
auto[0]	auto[1]	auto[1]	13190	1			T6	169		T31	3		T54	70
auto[1]	auto[0]	auto[0]	22442	1			T5	16		T10	2		T31	111
auto[1]	auto[0]	auto[1]	510	1			T31	1		T37	8		T24	2
auto[1]	auto[1]	auto[0]	5552	1			T5	11		T31	33		T37	24
auto[1]	auto[1]	auto[1]	111	1			T31	1		T37	4		T78	1