Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2150425	1			T1	1		T2	1838		T3	1
all_pins[1]	2150425	1			T1	1		T2	1838		T3	1
all_pins[2]	2150425	1			T1	1		T2	1838		T3	1
all_pins[3]	2150425	1			T1	1		T2	1838		T3	1
all_pins[4]	2150425	1			T1	1		T2	1838		T3	1
all_pins[5]	2150425	1			T1	1		T2	1838		T3	1
all_pins[6]	2150425	1			T1	1		T2	1838		T3	1
all_pins[7]	2150425	1			T1	1		T2	1838		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	17119075	1			T1	8		T2	14704		T3	8
values[0x1]	84325	1			T12	13		T13	12		T15	34
transitions[0x0=>0x1]	82645	1			T12	13		T13	9		T15	25
transitions[0x1=>0x0]	82653	1			T12	13		T13	9		T15	25

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2150029	1			T1	1		T2	1838		T3	1
all_pins[0]	values[0x1]	396	1			T12	3		T13	1		T15	3
all_pins[0]	transitions[0x0=>0x1]	300	1			T12	3		T13	1		T15	2
all_pins[0]	transitions[0x1=>0x0]	406	1			T12	1		T13	4		T15	4
all_pins[1]	values[0x0]	2149923	1			T1	1		T2	1838		T3	1
all_pins[1]	values[0x1]	502	1			T12	1		T13	4		T15	5
all_pins[1]	transitions[0x0=>0x1]	465	1			T12	1		T13	4		T15	4
all_pins[1]	transitions[0x1=>0x0]	181	1			T12	2		T15	2		T18	5
all_pins[2]	values[0x0]	2150207	1			T1	1		T2	1838		T3	1
all_pins[2]	values[0x1]	218	1			T12	2		T15	3		T18	5
all_pins[2]	transitions[0x0=>0x1]	159	1			T12	2		T15	2		T18	4
all_pins[2]	transitions[0x1=>0x0]	174	1			T15	3		T18	3		T19	3
all_pins[3]	values[0x0]	2150192	1			T1	1		T2	1838		T3	1
all_pins[3]	values[0x1]	233	1			T15	4		T18	4		T19	3
all_pins[3]	transitions[0x0=>0x1]	176	1			T15	4		T18	4		T19	1
all_pins[3]	transitions[0x1=>0x0]	163	1			T12	3		T13	2		T15	3
all_pins[4]	values[0x0]	2150205	1			T1	1		T2	1838		T3	1
all_pins[4]	values[0x1]	220	1			T12	3		T13	2		T15	3
all_pins[4]	transitions[0x0=>0x1]	167	1			T12	3		T13	2		T15	1
all_pins[4]	transitions[0x1=>0x0]	1714	1			T12	2		T15	3		T18	3
all_pins[5]	values[0x0]	2148658	1			T1	1		T2	1838		T3	1
all_pins[5]	values[0x1]	1767	1			T12	2		T15	5		T18	3
all_pins[5]	transitions[0x0=>0x1]	517	1			T12	2		T15	4		T18	3
all_pins[5]	transitions[0x1=>0x0]	79506	1			T13	2		T15	5		T18	3
all_pins[6]	values[0x0]	2069669	1			T1	1		T2	1838		T3	1
all_pins[6]	values[0x1]	80756	1			T13	2		T15	6		T18	3
all_pins[6]	transitions[0x0=>0x1]	80692	1			T15	4		T18	3		T20	4
all_pins[6]	transitions[0x1=>0x0]	169	1			T12	2		T13	1		T15	3
all_pins[7]	values[0x0]	2150192	1			T1	1		T2	1838		T3	1
all_pins[7]	values[0x1]	233	1			T12	2		T13	3		T15	5
all_pins[7]	transitions[0x0=>0x1]	169	1			T12	2		T13	2		T15	4
all_pins[7]	transitions[0x1=>0x0]	340	1			T12	3		T15	2		T18	4