Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

16433

1

T1

4

T3

12

T6

6

auto[1]

11885

1

T7

12

T31

171

T23

6

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3800	1			T11	6		T31	191		T24	66
values[1]	3705	1			T43	20		T34	20		T44	40
values[2]	3839	1			T7	12		T49	4		T23	58
values[3]	3584	1			T8	2		T31	26		T33	21
values[4]	3589	1			T3	12		T33	27		T34	20
values[5]	3055	1			T31	21		T54	2		T33	21
values[6]	3323	1			T1	4		T48	2		T44	29
values[7]	3423	1			T6	6		T9	8		T31	28

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3676	1			T1	4		T9	8		T31	45
values[1]	3657	1			T8	2		T31	54		T34	41
values[2]	3863	1			T31	54		T24	66		T43	20
values[3]	3204	1			T11	6		T54	2		T33	48
values[4]	3154	1			T7	12		T23	58		T43	20
values[5]	3437	1			T34	79		T44	20		T45	40
values[6]	3284	1			T3	12		T31	113		T48	2
values[7]	4043	1			T6	6		T34	20		T44	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	319	1			T31	40		T45	16		T151	13
auto[0]	values[0]	values[1]	246	1			T31	8		T159	13		T180	15
auto[0]	values[0]	values[2]	360	1			T24	66		T161	4		T35	8
auto[0]	values[0]	values[3]	204	1			T11	6		T36	14		T179	14
auto[0]	values[0]	values[4]	313	1			T39	9		T17	17		T151	16
auto[0]	values[0]	values[5]	274	1			T35	10		T36	10		T168	36
auto[0]	values[0]	values[6]	248	1			T31	10		T47	12		T282	46
auto[0]	values[0]	values[7]	255	1			T47	8		T151	15		T193	2
auto[0]	values[1]	values[0]	301	1			T194	4		T179	12		T182	9
auto[0]	values[1]	values[1]	231	1			T151	14		T179	10		T168	10
auto[0]	values[1]	values[2]	632	1			T35	25		T180	11		T177	19
auto[0]	values[1]	values[3]	181	1			T173	39		T199	6		T184	13
auto[0]	values[1]	values[4]	289	1			T43	13		T44	13		T47	8
auto[0]	values[1]	values[5]	278	1			T44	5		T45	12		T39	20
auto[0]	values[1]	values[6]	165	1			T34	14		T66	8		T159	9
auto[0]	values[1]	values[7]	219	1			T180	11		T184	12		T201	16
auto[0]	values[2]	values[0]	365	1			T29	58		T44	56		T36	11
auto[0]	values[2]	values[1]	231	1			T35	24		T164	17		T166	4
auto[0]	values[2]	values[2]	423	1			T43	15		T34	8		T185	18
auto[0]	values[2]	values[3]	274	1			T35	12		T283	6		T173	92
auto[0]	values[2]	values[4]	223	1			T23	52		T39	15		T180	12
auto[0]	values[2]	values[5]	339	1			T45	12		T179	19		T180	12
auto[0]	values[2]	values[6]	286	1			T49	4		T43	10		T177	12
auto[0]	values[2]	values[7]	227	1			T278	20		T191	14		T188	12
auto[0]	values[3]	values[0]	156	1			T45	22		T47	6		T184	11
auto[0]	values[3]	values[1]	304	1			T8	2		T45	19		T162	11
auto[0]	values[3]	values[2]	269	1			T31	9		T39	16		T35	10
auto[0]	values[3]	values[3]	247	1			T33	13		T160	61		T168	11
auto[0]	values[3]	values[4]	220	1			T164	19		T156	8		T180	35
auto[0]	values[3]	values[5]	207	1			T34	75		T151	14		T162	10
auto[0]	values[3]	values[6]	194	1			T47	7		T164	21		T179	11
auto[0]	values[3]	values[7]	320	1			T44	7		T150	9		T173	60
auto[0]	values[4]	values[0]	368	1			T39	8		T17	11		T170	4
auto[0]	values[4]	values[1]	342	1			T34	7		T151	11		T212	16
auto[0]	values[4]	values[2]	150	1			T180	12		T284	8		T255	22
auto[0]	values[4]	values[3]	254	1			T33	6		T39	9		T151	9
auto[0]	values[4]	values[4]	90	1			T182	9		T285	4		T201	9
auto[0]	values[4]	values[5]	222	1			T35	7		T225	12		T265	16
auto[0]	values[4]	values[6]	213	1			T3	12		T17	14		T156	14
auto[0]	values[4]	values[7]	371	1			T14	11		T151	28		T36	7
auto[0]	values[5]	values[0]	251	1			T33	17		T36	14		T190	13
auto[0]	values[5]	values[1]	343	1			T158	2		T164	8		T258	6
auto[0]	values[5]	values[2]	160	1			T47	10		T173	12		T189	8
auto[0]	values[5]	values[3]	205	1			T54	2		T79	12		T162	12
auto[0]	values[5]	values[4]	162	1			T195	10		T159	17		T212	6
auto[0]	values[5]	values[5]	280	1			T17	7		T175	4		T36	11
auto[0]	values[5]	values[6]	199	1			T31	13		T179	15		T162	17
auto[0]	values[5]	values[7]	200	1			T39	7		T36	8		T286	6
auto[0]	values[6]	values[0]	282	1			T1	4		T44	8		T148	22
auto[0]	values[6]	values[1]	287	1			T47	18		T148	7		T202	8
auto[0]	values[6]	values[2]	319	1			T45	10		T35	27		T149	14
auto[0]	values[6]	values[3]	348	1			T45	10		T47	8		T35	9
auto[0]	values[6]	values[4]	310	1			T39	16		T150	13		T17	19
auto[0]	values[6]	values[5]	143	1			T39	17		T148	14		T273	4
auto[0]	values[6]	values[6]	164	1			T48	2		T151	11		T182	45
auto[0]	values[6]	values[7]	248	1			T45	10		T47	11		T287	2
auto[0]	values[7]	values[0]	208	1			T9	8		T17	8		T47	10
auto[0]	values[7]	values[1]	255	1			T34	9		T45	11		T35	9
auto[0]	values[7]	values[2]	193	1			T31	15		T181	6		T288	6
auto[0]	values[7]	values[3]	185	1			T45	8		T155	6		T173	12
auto[0]	values[7]	values[4]	227	1			T39	11		T147	10		T47	14
auto[0]	values[7]	values[5]	207	1			T154	8		T162	11		T184	14
auto[0]	values[7]	values[6]	227	1			T150	21		T164	12		T173	13
auto[0]	values[7]	values[7]	220	1			T6	6		T34	11		T35	12
auto[1]	values[0]	values[0]	236	1			T31	5		T45	4		T151	7
auto[1]	values[0]	values[1]	249	1			T31	46		T159	14		T180	11
auto[1]	values[0]	values[2]	236	1			T35	14		T151	9		T173	11
auto[1]	values[0]	values[3]	145	1			T36	6		T179	6		T114	15
auto[1]	values[0]	values[4]	169	1			T39	11		T17	7		T151	4
auto[1]	values[0]	values[5]	258	1			T35	10		T167	8		T36	10
auto[1]	values[0]	values[6]	180	1			T31	82		T47	8		T268	14
auto[1]	values[0]	values[7]	108	1			T47	12		T151	5		T289	4
auto[1]	values[1]	values[0]	172	1			T179	8		T182	30		T122	10
auto[1]	values[1]	values[1]	238	1			T151	6		T179	10		T168	30
auto[1]	values[1]	values[2]	227	1			T198	4		T35	17		T180	9
auto[1]	values[1]	values[3]	83	1			T173	13		T184	18		T268	6
auto[1]	values[1]	values[4]	266	1			T43	7		T44	7		T47	12
auto[1]	values[1]	values[5]	165	1			T44	15		T45	8		T39	20
auto[1]	values[1]	values[6]	140	1			T34	6		T159	18		T290	9
auto[1]	values[1]	values[7]	118	1			T180	14		T184	20		T201	4
auto[1]	values[2]	values[0]	195	1			T44	8		T36	9		T173	8
auto[1]	values[2]	values[1]	196	1			T35	4		T164	7		T180	7
auto[1]	values[2]	values[2]	165	1			T43	5		T34	21		T17	10
auto[1]	values[2]	values[3]	197	1			T35	10		T173	18		T168	29
auto[1]	values[2]	values[4]	133	1			T7	12		T23	6		T39	5
auto[1]	values[2]	values[5]	272	1			T45	8		T172	20		T179	10
auto[1]	values[2]	values[6]	152	1			T43	10		T270	18		T177	55
auto[1]	values[2]	values[7]	161	1			T191	6		T188	8		T210	12
auto[1]	values[3]	values[0]	153	1			T45	6		T47	14		T184	56
auto[1]	values[3]	values[1]	162	1			T45	12		T162	9		T177	9
auto[1]	values[3]	values[2]	181	1			T31	17		T39	4		T35	14
auto[1]	values[3]	values[3]	189	1			T33	8		T160	8		T168	10
auto[1]	values[3]	values[4]	160	1			T164	3		T156	12		T180	48
auto[1]	values[3]	values[5]	219	1			T34	4		T151	6		T162	10
auto[1]	values[3]	values[6]	231	1			T47	13		T164	2		T179	9
auto[1]	values[3]	values[7]	372	1			T44	13		T150	11		T173	7
auto[1]	values[4]	values[0]	185	1			T39	12		T17	9		T164	10
auto[1]	values[4]	values[1]	141	1			T34	13		T151	9		T212	4
auto[1]	values[4]	values[2]	73	1			T180	14		T114	10		T205	18
auto[1]	values[4]	values[3]	138	1			T33	21		T39	11		T151	11
auto[1]	values[4]	values[4]	201	1			T182	38		T201	11		T216	5
auto[1]	values[4]	values[5]	296	1			T35	13		T225	153		T210	7
auto[1]	values[4]	values[6]	181	1			T17	6		T156	6		T50	12
auto[1]	values[4]	values[7]	364	1			T14	9		T151	12		T36	13
auto[1]	values[5]	values[0]	132	1			T33	4		T36	6		T190	17
auto[1]	values[5]	values[1]	131	1			T164	12		T156	11		T177	8
auto[1]	values[5]	values[2]	79	1			T47	10		T171	8		T173	8
auto[1]	values[5]	values[3]	96	1			T162	8		T157	32		T114	11
auto[1]	values[5]	values[4]	104	1			T159	3		T212	14		T115	34
auto[1]	values[5]	values[5]	96	1			T17	18		T36	19		T173	12
auto[1]	values[5]	values[6]	342	1			T31	8		T174	10		T179	5
auto[1]	values[5]	values[7]	275	1			T39	13		T36	120		T208	8
auto[1]	values[6]	values[0]	173	1			T44	21		T148	7		T180	20
auto[1]	values[6]	values[1]	169	1			T47	2		T148	42		T180	12
auto[1]	values[6]	values[2]	214	1			T45	10		T35	18		T149	6
auto[1]	values[6]	values[3]	217	1			T45	10		T47	12		T35	15
auto[1]	values[6]	values[4]	108	1			T39	4		T150	13		T17	8
auto[1]	values[6]	values[5]	30	1			T39	3		T148	6		T231	8
auto[1]	values[6]	values[6]	161	1			T151	9		T182	14		T188	11
auto[1]	values[6]	values[7]	150	1			T45	11		T47	9		T215	6
auto[1]	values[7]	values[0]	180	1			T17	12		T47	10		T163	14
auto[1]	values[7]	values[1]	132	1			T34	12		T45	9		T35	18
auto[1]	values[7]	values[2]	182	1			T31	13		T168	11		T184	43
auto[1]	values[7]	values[3]	241	1			T45	12		T173	8		T162	8
auto[1]	values[7]	values[4]	179	1			T39	9		T147	10		T47	6
auto[1]	values[7]	values[5]	151	1			T162	9		T184	6		T191	13
auto[1]	values[7]	values[6]	201	1			T150	24		T164	8		T173	33
auto[1]	values[7]	values[7]	435	1			T34	9		T35	8		T180	6