Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	363	1			T34	2		T44	1		T45	1
auto[ReadAddrCrossIntoMailbox]	273	1			T31	2		T33	2		T43	1
auto[ReadAddrCrossOutOfMailbox]	258	1			T31	3		T33	1		T34	1
auto[ReadAddrCrossAllMailbox]	186	1			T8	2		T31	2		T33	1
auto[ReadAddrOutsideMailbox]	3386	1			T3	8		T7	6		T9	4

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2186

1

T3

4

T7

3

T8

1

auto[1]

2280

1

T3

4

T7

3

T8

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	757	1			T3	2		T7	2		T31	7
read_ops[0x0b]	744	1			T31	2		T23	1		T34	7
read_ops[0x3b]	769	1			T8	2		T31	6		T23	1
read_ops[0x6b]	747	1			T9	2		T31	2		T23	1
read_ops[0xbb]	749	1			T3	2		T7	4		T31	6
read_ops[0xeb]	700	1			T3	4		T9	2		T31	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	40	1			T34	1		T150	1		T17	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T14	1		T151	2		T170	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T150	1		T17	1		T36	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	19	1			T31	1		T33	1		T39	2
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T173	2		T179	2		T168	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T33	1		T45	1		T148	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T44	1		T39	3		T17	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T33	1		T45	1		T14	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	269	1			T3	1		T7	1		T31	5
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	291	1			T3	1		T7	1		T31	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T45	1		T150	2		T183	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T39	1		T149	1		T164	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T14	1		T36	1		T173	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T151	1		T148	1		T164	3
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	23	1			T45	1		T150	1		T151	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	18	1			T39	1		T17	1		T156	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	12	1			T150	1		T173	1		T180	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T47	1		T35	1		T36	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	280	1			T31	1		T34	5		T44	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	283	1			T31	1		T23	1		T34	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	23	1			T34	1		T150	1		T164	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T39	1		T150	1		T35	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T164	1		T173	1		T179	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T43	1		T34	1		T44	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T34	1		T17	1		T151	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T31	2		T35	1		T173	2
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T8	1		T164	1		T182	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T8	1		T31	2		T44	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	291	1			T29	1		T33	1		T43	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	305	1			T31	2		T23	1		T29	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T164	1		T156	1		T180	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	22	1			T36	1		T148	1		T173	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T44	1		T17	1		T36	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T44	1		T45	1		T39	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T36	1		T184	1		T182	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	20	1			T45	1		T47	1		T35	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T150	1		T17	1		T209	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	20	1			T44	1		T39	3		T173	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	295	1			T9	1		T31	2		T23	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T9	1		T34	1		T44	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T39	1		T150	1		T17	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T151	1		T170	1		T164	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T31	1		T156	1		T184	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T45	1		T39	1		T150	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T17	1		T35	1		T36	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	19	1			T45	1		T148	1		T164	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T35	1		T36	2		T114	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T45	1		T148	1		T159	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	274	1			T3	1		T7	2		T31	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	292	1			T3	1		T7	2		T31	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T17	2		T47	1		T173	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	33	1			T44	1		T17	1		T148	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T39	1		T35	2		T151	2
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T33	1		T45	1		T173	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T31	1		T150	1		T17	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	14	1			T151	2		T36	1		T225	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T17	1		T173	2		T179	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T45	1		T39	1		T36	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	242	1			T3	2		T9	1		T31	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	287	1			T3	2		T9	1		T31	1