Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4167	1			T31	54		T49	4		T33	27
values[1]	3909	1			T31	45		T33	21		T43	20
values[2]	3497	1			T7	12		T31	92		T29	58
values[3]	3187	1			T6	6		T48	2		T43	20
values[4]	3615	1			T1	4		T8	2		T31	49
values[5]	3242	1			T3	12		T11	6		T34	79
values[6]	2946	1			T31	26		T44	20		T45	48
values[7]	3755	1			T9	8		T24	66		T43	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3721	1			T23	58		T43	20		T44	20
values[1]	3436	1			T34	20		T39	40		T150	24
values[2]	3702	1			T3	12		T31	26		T33	27
values[3]	3189	1			T31	137		T49	4		T34	21
values[4]	3498	1			T7	12		T31	75		T43	20
values[5]	3879	1			T1	4		T11	6		T48	2
values[6]	3638	1			T8	2		T9	8		T31	28
values[7]	3255	1			T6	6		T54	2		T33	21

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

27661

1

T1

4

T3

12

T6

6

auto[1]

657

1

T31

9

T23

2

T33

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[7]]	[values[1]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	395	1			T155	6		T156	20		T157	22
auto[0]	values[0]	values[1]	688	1			T35	20		T158	2		T159	20
auto[0]	values[0]	values[2]	616	1			T33	26		T45	20		T160	68
auto[0]	values[0]	values[3]	307	1			T49	4		T66	8		T151	19
auto[0]	values[0]	values[4]	305	1			T31	54		T161	4		T162	20
auto[0]	values[0]	values[5]	538	1			T147	20		T35	27		T163	14
auto[0]	values[0]	values[6]	535	1			T34	29		T17	24		T164	21
auto[0]	values[0]	values[7]	700	1			T44	61		T39	20		T151	38
auto[0]	values[1]	values[0]	713	1			T165	16		T36	20		T166	4
auto[0]	values[1]	values[1]	586	1			T167	6		T168	42		T169	12
auto[0]	values[1]	values[2]	451	1			T47	19		T170	4		T171	8
auto[0]	values[1]	values[3]	310	1			T31	42		T39	20		T172	12
auto[0]	values[1]	values[4]	366	1			T43	20		T36	20		T173	20
auto[0]	values[1]	values[5]	590	1			T174	6		T175	4		T176	10
auto[0]	values[1]	values[6]	397	1			T33	20		T47	20		T36	21
auto[0]	values[1]	values[7]	398	1			T164	20		T177	24		T178	8
auto[0]	values[2]	values[0]	303	1			T179	22		T156	39		T180	24
auto[0]	values[2]	values[1]	231	1			T39	20		T150	24		T151	20
auto[0]	values[2]	values[2]	286	1			T35	22		T36	32		T148	20
auto[0]	values[2]	values[3]	449	1			T31	90		T39	20		T47	20
auto[0]	values[2]	values[4]	547	1			T7	12		T181	6		T182	97
auto[0]	values[2]	values[5]	537	1			T29	58		T45	29		T183	10
auto[0]	values[2]	values[6]	618	1			T35	23		T173	20		T184	20
auto[0]	values[2]	values[7]	451	1			T33	16		T185	18		T159	20
auto[0]	values[3]	values[0]	588	1			T45	20		T47	19		T186	76
auto[0]	values[3]	values[1]	284	1			T151	20		T187	12		T188	51
auto[0]	values[3]	values[2]	396	1			T43	20		T35	41		T151	20
auto[0]	values[3]	values[3]	329	1			T151	39		T149	19		T173	86
auto[0]	values[3]	values[4]	242	1			T39	20		T150	26		T173	52
auto[0]	values[3]	values[5]	415	1			T48	2		T180	24		T189	8
auto[0]	values[3]	values[6]	270	1			T44	27		T45	20		T35	25
auto[0]	values[3]	values[7]	582	1			T6	6		T45	21		T17	20
auto[0]	values[4]	values[0]	493	1			T23	56		T44	20		T35	21
auto[0]	values[4]	values[1]	487	1			T179	30		T190	34		T81	20
auto[0]	values[4]	values[2]	468	1			T46	10		T148	48		T191	17
auto[0]	values[4]	values[3]	323	1			T14	20		T36	20		T192	4
auto[0]	values[4]	values[4]	618	1			T31	17		T34	19		T47	19
auto[0]	values[4]	values[5]	274	1			T1	4		T34	20		T45	19
auto[0]	values[4]	values[6]	584	1			T8	2		T31	28		T150	40
auto[0]	values[4]	values[7]	252	1			T54	2		T190	29		T180	22
auto[0]	values[5]	values[0]	409	1			T17	20		T35	20		T79	12
auto[0]	values[5]	values[1]	386	1			T17	26		T36	20		T162	21
auto[0]	values[5]	values[2]	350	1			T3	12		T45	20		T36	20
auto[0]	values[5]	values[3]	545	1			T180	20		T184	32		T193	2
auto[0]	values[5]	values[4]	264	1			T148	32		T179	20		T168	23
auto[0]	values[5]	values[5]	589	1			T11	6		T34	79		T39	20
auto[0]	values[5]	values[6]	360	1			T194	4		T47	20		T164	22
auto[0]	values[5]	values[7]	252	1			T39	19		T195	10		T196	16
auto[0]	values[6]	values[0]	231	1			T39	20		T35	23		T36	20
auto[0]	values[6]	values[1]	330	1			T39	20		T197	8		T188	44
auto[0]	values[6]	values[2]	599	1			T31	26		T45	45		T35	24
auto[0]	values[6]	values[3]	415	1			T198	4		T148	25		T179	40
auto[0]	values[6]	values[4]	368	1			T44	20		T17	20		T199	6
auto[0]	values[6]	values[5]	388	1			T47	19		T151	20		T173	33
auto[0]	values[6]	values[6]	353	1			T17	20		T190	25		T182	32
auto[0]	values[6]	values[7]	204	1			T36	20		T156	18		T180	57
auto[0]	values[7]	values[0]	517	1			T43	20		T45	20		T180	26
auto[0]	values[7]	values[1]	383	1			T34	20		T200	20		T201	22
auto[0]	values[7]	values[2]	462	1			T44	19		T154	8		T47	20
auto[0]	values[7]	values[3]	423	1			T34	20		T151	19		T173	63
auto[0]	values[7]	values[4]	712	1			T39	37		T47	20		T50	57
auto[0]	values[7]	values[5]	465	1			T24	66		T202	8		T173	67
auto[0]	values[7]	values[6]	405	1			T9	8		T148	18		T180	34
auto[0]	values[7]	values[7]	329	1			T17	22		T47	40		T148	20
auto[1]	values[0]	values[0]	8	1			T157	1		T203	1		T204	2
auto[1]	values[0]	values[1]	5	1			T205	1		T206	2		T207	2
auto[1]	values[0]	values[2]	7	1			T33	1		T160	1		T184	1
auto[1]	values[0]	values[3]	13	1			T151	1		T180	1		T208	2
auto[1]	values[0]	values[4]	6	1			T209	1		T201	2		T210	2
auto[1]	values[0]	values[5]	9	1			T36	5		T182	2		T211	2
auto[1]	values[0]	values[6]	21	1			T17	1		T157	2		T212	1
auto[1]	values[0]	values[7]	14	1			T44	3		T151	2		T213	2
auto[1]	values[1]	values[0]	19	1			T50	1		T214	1		T215	2
auto[1]	values[1]	values[1]	15	1			T167	2		T168	1		T182	2
auto[1]	values[1]	values[2]	7	1			T47	1		T213	4		T216	1
auto[1]	values[1]	values[3]	18	1			T31	3		T172	8		T52	3
auto[1]	values[1]	values[4]	11	1			T201	1		T217	1		T82	6
auto[1]	values[1]	values[5]	11	1			T174	4		T214	1		T114	2
auto[1]	values[1]	values[6]	11	1			T33	1		T179	1		T51	2
auto[1]	values[1]	values[7]	6	1			T177	3		T115	2		T218	1
auto[1]	values[2]	values[0]	4	1			T156	1		T180	1		T219	2
auto[1]	values[2]	values[1]	4	1			T220	2		T221	2		-	-
auto[1]	values[2]	values[2]	4	1			T222	2		T223	2		-	-
auto[1]	values[2]	values[3]	9	1			T31	2		T179	1		T162	5
auto[1]	values[2]	values[4]	11	1			T182	2		T191	4		T224	2
auto[1]	values[2]	values[5]	11	1			T45	2		T213	1		T210	2
auto[1]	values[2]	values[6]	20	1			T35	5		T225	3		T226	4
auto[1]	values[2]	values[7]	12	1			T33	5		T212	2		T214	1
auto[1]	values[3]	values[0]	11	1			T47	1		T184	5		T227	3
auto[1]	values[3]	values[1]	8	1			T228	1		T229	1		T230	5
auto[1]	values[3]	values[2]	16	1			T35	1		T149	1		T164	1
auto[1]	values[3]	values[3]	9	1			T151	1		T149	1		T173	4
auto[1]	values[3]	values[4]	4	1			T115	1		T51	2		T223	1
auto[1]	values[3]	values[5]	15	1			T180	3		T209	2		T231	2
auto[1]	values[3]	values[6]	8	1			T44	2		T180	1		T232	3
auto[1]	values[3]	values[7]	10	1			T35	2		T149	1		T36	2
auto[1]	values[4]	values[0]	10	1			T23	2		T35	1		T168	1
auto[1]	values[4]	values[1]	15	1			T179	1		T190	2		T233	3
auto[1]	values[4]	values[2]	13	1			T46	2		T148	1		T191	3
auto[1]	values[4]	values[3]	4	1			T115	1		T234	1		T82	1
auto[1]	values[4]	values[4]	20	1			T31	4		T34	1		T47	1
auto[1]	values[4]	values[5]	19	1			T45	1		T200	1		T235	5
auto[1]	values[4]	values[6]	19	1			T150	1		T173	1		T209	2
auto[1]	values[4]	values[7]	16	1			T190	1		T180	4		T51	4
auto[1]	values[5]	values[0]	11	1			T180	3		T201	1		T217	1
auto[1]	values[5]	values[1]	11	1			T17	1		T225	1		T213	1
auto[1]	values[5]	values[2]	5	1			T148	1		T188	2		T236	2
auto[1]	values[5]	values[3]	18	1			T115	5		T237	2		T238	1
auto[1]	values[5]	values[4]	8	1			T148	2		T168	1		T191	3
auto[1]	values[5]	values[5]	11	1			T151	1		T159	4		T179	1
auto[1]	values[5]	values[6]	13	1			T164	1		T203	3		T52	3
auto[1]	values[5]	values[7]	10	1			T39	1		T196	2		T51	2
auto[1]	values[6]	values[0]	3	1			T35	1		T188	1		T213	1
auto[1]	values[6]	values[1]	3	1			T115	1		T231	1		T239	1
auto[1]	values[6]	values[2]	13	1			T45	3		T159	3		T240	1
auto[1]	values[6]	values[3]	6	1			T184	1		T212	2		T201	2
auto[1]	values[6]	values[4]	8	1			T162	1		T177	2		T200	1
auto[1]	values[6]	values[5]	6	1			T47	1		T50	1		T177	1
auto[1]	values[6]	values[6]	10	1			T190	1		T182	1		T201	2
auto[1]	values[6]	values[7]	9	1			T156	2		T180	4		T225	1
auto[1]	values[7]	values[0]	6	1			T240	3		T229	1		T241	1
auto[1]	values[7]	values[2]	9	1			T44	1		T35	3		T214	1
auto[1]	values[7]	values[3]	11	1			T34	1		T151	1		T173	3
auto[1]	values[7]	values[4]	8	1			T39	3		T234	1		T52	1
auto[1]	values[7]	values[5]	1	1			T209	1		-	-		-	-
auto[1]	values[7]	values[6]	14	1			T148	2		T180	2		T168	1
auto[1]	values[7]	values[7]	10	1			T17	2		T50	2		T234	2