Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	947	1			T12	11		T13	7		T15	14
all_values[1]	947	1			T12	11		T13	7		T15	14
all_values[2]	947	1			T12	11		T13	7		T15	14
all_values[3]	947	1			T12	11		T13	7		T15	14
all_values[4]	947	1			T12	11		T13	7		T15	14
all_values[5]	947	1			T12	11		T13	7		T15	14
all_values[6]	947	1			T12	11		T13	7		T15	14
all_values[7]	947	1			T12	11		T13	7		T15	14

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3948

1

T12

59

T13

32

T15

57

auto[1]

3628

1

T12

29

T13

24

T15

55

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3032

1

T12

26

T13

26

T15

48

auto[1]

4544

1

T12

62

T13

30

T15

64

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4340

1

T12

48

T13

35

T15

70

auto[1]

3236

1

T12

40

T13

21

T15

42

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	187	1			T13	3		T15	6		T18	5
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T12	1		T15	3		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	172	1			T12	2		T15	2		T18	1
all_values[0]	auto[0]	auto[1]	auto[1]	88	1			T12	2		T18	1		T19	1
all_values[0]	auto[1]	auto[0]	auto[1]	218	1			T12	6		T13	2		T15	1
all_values[0]	auto[1]	auto[1]	auto[1]	195	1			T13	2		T15	2		T18	3
all_values[1]	auto[0]	auto[0]	auto[0]	200	1			T12	1		T15	5		T18	1
all_values[1]	auto[0]	auto[0]	auto[1]	84	1			T12	4		T13	2		T15	1
all_values[1]	auto[0]	auto[1]	auto[0]	192	1			T12	1		T15	1		T18	4
all_values[1]	auto[0]	auto[1]	auto[1]	78	1			T13	2		T15	2		T18	2
all_values[1]	auto[1]	auto[0]	auto[1]	197	1			T12	3		T13	1		T15	1
all_values[1]	auto[1]	auto[1]	auto[1]	196	1			T12	2		T13	2		T15	4
all_values[2]	auto[0]	auto[0]	auto[0]	174	1			T12	1		T13	3		T15	2
all_values[2]	auto[0]	auto[0]	auto[1]	108	1			T12	4		T15	1		T18	1
all_values[2]	auto[0]	auto[1]	auto[0]	158	1			T12	1		T13	1		T15	2
all_values[2]	auto[0]	auto[1]	auto[1]	92	1			T15	1		T18	3		T20	1
all_values[2]	auto[1]	auto[0]	auto[1]	246	1			T12	5		T13	3		T15	4
all_values[2]	auto[1]	auto[1]	auto[1]	169	1			T15	4		T18	3		T19	1
all_values[3]	auto[0]	auto[0]	auto[0]	192	1			T12	1		T13	4		T15	1
all_values[3]	auto[0]	auto[0]	auto[1]	88	1			T12	2		T18	2		T20	3
all_values[3]	auto[0]	auto[1]	auto[0]	157	1			T12	1		T15	6		T19	3
all_values[3]	auto[0]	auto[1]	auto[1]	109	1			T13	1		T15	2		T18	1
all_values[3]	auto[1]	auto[0]	auto[1]	211	1			T12	7		T13	2		T15	1
all_values[3]	auto[1]	auto[1]	auto[1]	190	1			T15	4		T18	7		T19	4
all_values[4]	auto[0]	auto[0]	auto[0]	188	1			T15	4		T18	2		T19	3
all_values[4]	auto[0]	auto[0]	auto[1]	99	1			T12	4		T13	2		T15	2
all_values[4]	auto[0]	auto[1]	auto[0]	166	1			T13	2		T15	2		T18	4
all_values[4]	auto[0]	auto[1]	auto[1]	91	1			T12	1		T15	1		T18	2
all_values[4]	auto[1]	auto[0]	auto[1]	220	1			T12	6		T15	3		T18	2
all_values[4]	auto[1]	auto[1]	auto[1]	183	1			T13	3		T15	2		T18	4
all_values[5]	auto[0]	auto[0]	auto[0]	279	1			T12	1		T13	5		T15	4
all_values[5]	auto[0]	auto[1]	auto[0]	261	1			T12	5		T13	2		T15	4
all_values[5]	auto[1]	auto[0]	auto[1]	212	1			T12	3		T15	1		T18	4
all_values[5]	auto[1]	auto[1]	auto[1]	195	1			T12	2		T15	5		T18	3
all_values[6]	auto[0]	auto[0]	auto[0]	174	1			T12	2		T13	1		T15	4
all_values[6]	auto[0]	auto[0]	auto[1]	93	1			T15	3		T19	2		T20	4
all_values[6]	auto[0]	auto[1]	auto[0]	179	1			T12	6		T13	2		T15	1
all_values[6]	auto[0]	auto[1]	auto[1]	103	1			T13	1		T15	2		T18	1
all_values[6]	auto[1]	auto[0]	auto[1]	209	1			T12	1		T13	1		T15	2
all_values[6]	auto[1]	auto[1]	auto[1]	189	1			T12	2		T13	2		T15	2
all_values[7]	auto[0]	auto[0]	auto[0]	192	1			T12	3		T13	2		T15	4
all_values[7]	auto[0]	auto[0]	auto[1]	87	1			T12	3		T15	2		T18	1
all_values[7]	auto[0]	auto[1]	auto[0]	161	1			T12	1		T13	1		T18	4
all_values[7]	auto[0]	auto[1]	auto[1]	101	1			T12	1		T13	1		T15	2
all_values[7]	auto[1]	auto[0]	auto[1]	203	1			T12	1		T13	1		T15	2
all_values[7]	auto[1]	auto[1]	auto[1]	203	1			T12	2		T13	2		T15	4

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal