Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1720

1

T10

6

T30

17

T31

3

auto[1]

1728

1

T10

6

T30

13

T31

5

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1900

1

T10

12

T31

8

T12

13

auto[1]

1548

1

T30

30

T12

6

T13

5

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2712

1

T10

8

T30

30

T31

4

auto[1]

736

1

T10

4

T31

4

T12

9

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	707	1			T10	3		T30	5		T31	1
valid[1]	660	1			T10	3		T30	6		T31	1
valid[2]	698	1			T10	1		T30	10		T31	1
valid[3]	674	1			T10	2		T30	5		T31	2
valid[4]	709	1			T10	3		T30	4		T31	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	130	1			T12	2		T27	1		T13	3
auto[0]	auto[0]	valid[0]	auto[1]	157	1			T30	4		T12	2		T77	1
auto[0]	auto[0]	valid[1]	auto[0]	111	1			T31	1		T12	1		T13	1
auto[0]	auto[0]	valid[1]	auto[1]	166	1			T30	4		T13	1		T45	1
auto[0]	auto[0]	valid[2]	auto[0]	106	1			T23	1		T13	1		T33	1
auto[0]	auto[0]	valid[2]	auto[1]	149	1			T30	5		T45	2		T76	2
auto[0]	auto[0]	valid[3]	auto[0]	116	1			T10	1		T31	1		T23	1
auto[0]	auto[0]	valid[3]	auto[1]	150	1			T30	4		T12	1		T33	1
auto[0]	auto[0]	valid[4]	auto[0]	105	1			T10	1		T27	1		T13	2
auto[0]	auto[0]	valid[4]	auto[1]	163	1			T13	1		T45	1		T14	1
auto[0]	auto[1]	valid[0]	auto[0]	126	1			T10	2		T31	1		T45	3
auto[0]	auto[1]	valid[0]	auto[1]	157	1			T30	1		T13	1		T45	1
auto[0]	auto[1]	valid[1]	auto[0]	118	1			T10	1		T12	1		T27	3
auto[0]	auto[1]	valid[1]	auto[1]	124	1			T30	2		T12	1		T45	1
auto[0]	auto[1]	valid[2]	auto[0]	123	1			T23	1		T27	1		T13	2
auto[0]	auto[1]	valid[2]	auto[1]	163	1			T30	5		T13	1		T76	2
auto[0]	auto[1]	valid[3]	auto[0]	116	1			T10	1		T27	1		T13	2
auto[0]	auto[1]	valid[3]	auto[1]	154	1			T30	1		T12	1		T76	1
auto[0]	auto[1]	valid[4]	auto[0]	113	1			T10	2		T31	1		T23	1
auto[0]	auto[1]	valid[4]	auto[1]	165	1			T30	4		T12	1		T13	1
auto[1]	auto[0]	valid[0]	auto[0]	68	1			T10	1		T12	1		T13	4
auto[1]	auto[0]	valid[1]	auto[0]	64	1			T10	2		T12	1		T23	1
auto[1]	auto[0]	valid[2]	auto[0]	80	1			T10	1		T31	1		T23	1
auto[1]	auto[0]	valid[3]	auto[0]	69	1			T13	2		T34	1		T45	1
auto[1]	auto[0]	valid[4]	auto[0]	86	1			T12	1		T13	4		T45	1
auto[1]	auto[1]	valid[0]	auto[0]	69	1			T12	3		T13	3		T44	1
auto[1]	auto[1]	valid[1]	auto[0]	77	1			T12	1		T27	2		T13	3
auto[1]	auto[1]	valid[2]	auto[0]	77	1			T27	2		T13	1		T45	2
auto[1]	auto[1]	valid[3]	auto[0]	69	1			T31	1		T12	1		T27	1
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T31	2		T12	1		T27	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal