Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45842

1

T2

7

T10

230

T31

78

auto[1]

15970

1

T30

292

T12

90

T13

92

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45182

1

T2

3

T10

161

T30

292

auto[1]

16630

1

T2

4

T10

69

T31

30

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	31769	1			T2	5		T10	121		T30	148
others[1]	5295	1			T2	1		T10	20		T30	34
others[2]	5279	1			T10	25		T30	14		T31	9
others[3]	5790	1			T2	1		T10	27		T30	18
interest[1]	3387	1			T10	7		T30	12		T31	3
interest[4]	20732	1			T2	3		T10	74		T30	90
interest[64]	10292	1			T10	30		T30	66		T31	13

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14893	1			T2	3		T10	85		T31	28
auto[0]	auto[0]	others[1]	2453	1			T10	13		T31	4		T12	14
auto[0]	auto[0]	others[2]	2544	1			T10	20		T31	5		T12	20
auto[0]	auto[0]	others[3]	2798	1			T10	19		T31	3		T12	13
auto[0]	auto[0]	interest[1]	1599	1			T10	5		T12	6		T23	9
auto[0]	auto[0]	interest[4]	9666	1			T2	2		T10	55		T31	16
auto[0]	auto[0]	interest[64]	4925	1			T10	19		T31	8		T12	42
auto[0]	auto[1]	others[0]	8368	1			T30	148		T12	38		T13	50
auto[0]	auto[1]	others[1]	1385	1			T30	34		T12	7		T13	4
auto[0]	auto[1]	others[2]	1332	1			T30	14		T12	8		T13	7
auto[0]	auto[1]	others[3]	1416	1			T30	18		T12	12		T13	10
auto[0]	auto[1]	interest[1]	887	1			T30	12		T12	5		T13	6
auto[0]	auto[1]	interest[4]	5534	1			T30	90		T12	19		T13	37
auto[0]	auto[1]	interest[64]	2582	1			T30	66		T12	20		T13	15
auto[1]	auto[0]	others[0]	8508	1			T2	2		T10	36		T31	14
auto[1]	auto[0]	others[1]	1457	1			T2	1		T10	7		T31	3
auto[1]	auto[0]	others[2]	1403	1			T10	5		T31	4		T12	14
auto[1]	auto[0]	others[3]	1576	1			T2	1		T10	8		T31	1
auto[1]	auto[0]	interest[1]	901	1			T10	2		T31	3		T12	10
auto[1]	auto[0]	interest[4]	5532	1			T2	1		T10	19		T31	8
auto[1]	auto[0]	interest[64]	2785	1			T10	11		T31	5		T12	24

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal