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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.03 98.38 93.99 98.62 89.36 97.21 95.45 99.21


Total test records in report: 1131
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T108 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3920261528 Jul 04 05:07:26 PM PDT 24 Jul 04 05:08:07 PM PDT 24 5178047893 ps
T1028 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4289298389 Jul 04 05:07:44 PM PDT 24 Jul 04 05:07:45 PM PDT 24 19210343 ps
T1029 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.821678256 Jul 04 05:07:50 PM PDT 24 Jul 04 05:07:51 PM PDT 24 18847252 ps
T140 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.32646665 Jul 04 05:07:47 PM PDT 24 Jul 04 05:07:49 PM PDT 24 122277599 ps
T1030 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2787982925 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:28 PM PDT 24 12743034 ps
T249 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1694006861 Jul 04 05:07:42 PM PDT 24 Jul 04 05:07:51 PM PDT 24 286499336 ps
T88 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.144646893 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:50 PM PDT 24 83357984 ps
T1031 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.970819673 Jul 04 05:07:33 PM PDT 24 Jul 04 05:07:42 PM PDT 24 5489779774 ps
T109 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.900269807 Jul 04 05:07:39 PM PDT 24 Jul 04 05:07:41 PM PDT 24 281819688 ps
T90 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3645921126 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:30 PM PDT 24 801649083 ps
T1032 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.463355394 Jul 04 05:07:45 PM PDT 24 Jul 04 05:07:48 PM PDT 24 673100100 ps
T245 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2258401870 Jul 04 05:07:43 PM PDT 24 Jul 04 05:08:03 PM PDT 24 1176036657 ps
T91 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3580938638 Jul 04 05:07:42 PM PDT 24 Jul 04 05:07:48 PM PDT 24 723962586 ps
T139 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3006945197 Jul 04 05:07:40 PM PDT 24 Jul 04 05:07:43 PM PDT 24 262967091 ps
T92 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1598727271 Jul 04 05:07:27 PM PDT 24 Jul 04 05:07:31 PM PDT 24 1248749862 ps
T1033 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1610326667 Jul 04 05:07:41 PM PDT 24 Jul 04 05:07:44 PM PDT 24 540246147 ps
T1034 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3861394774 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:46 PM PDT 24 11301876 ps
T110 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2574727481 Jul 04 05:07:42 PM PDT 24 Jul 04 05:07:44 PM PDT 24 75249313 ps
T1035 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2306035831 Jul 04 05:07:48 PM PDT 24 Jul 04 05:07:49 PM PDT 24 15614689 ps
T246 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1376982741 Jul 04 05:07:33 PM PDT 24 Jul 04 05:07:45 PM PDT 24 393722093 ps
T1036 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3578943306 Jul 04 05:07:56 PM PDT 24 Jul 04 05:07:57 PM PDT 24 56865870 ps
T1037 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1503655189 Jul 04 05:07:35 PM PDT 24 Jul 04 05:07:37 PM PDT 24 59376494 ps
T1038 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2724178308 Jul 04 05:07:36 PM PDT 24 Jul 04 05:07:37 PM PDT 24 39442338 ps
T1039 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3589018930 Jul 04 05:07:57 PM PDT 24 Jul 04 05:07:58 PM PDT 24 24343970 ps
T1040 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2531617059 Jul 04 05:07:44 PM PDT 24 Jul 04 05:07:48 PM PDT 24 586992014 ps
T1041 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4079712764 Jul 04 05:07:35 PM PDT 24 Jul 04 05:07:36 PM PDT 24 42823646 ps
T93 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3233978773 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:28 PM PDT 24 88545931 ps
T251 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2983115124 Jul 04 05:07:50 PM PDT 24 Jul 04 05:07:58 PM PDT 24 1187620825 ps
T1042 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1223763672 Jul 04 05:07:44 PM PDT 24 Jul 04 05:07:45 PM PDT 24 14503131 ps
T1043 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2047090530 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:48 PM PDT 24 20494098 ps
T141 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1545544459 Jul 04 05:07:47 PM PDT 24 Jul 04 05:07:50 PM PDT 24 111143725 ps
T1044 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1207885193 Jul 04 05:07:51 PM PDT 24 Jul 04 05:07:54 PM PDT 24 77196386 ps
T94 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.365321469 Jul 04 05:07:34 PM PDT 24 Jul 04 05:07:39 PM PDT 24 82175109 ps
T111 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.968099767 Jul 04 05:07:34 PM PDT 24 Jul 04 05:07:35 PM PDT 24 25526509 ps
T250 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1375283066 Jul 04 05:07:47 PM PDT 24 Jul 04 05:08:10 PM PDT 24 4788229961 ps
T1045 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1268360388 Jul 04 05:07:43 PM PDT 24 Jul 04 05:07:48 PM PDT 24 779432885 ps
T113 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.798545474 Jul 04 05:07:27 PM PDT 24 Jul 04 05:07:39 PM PDT 24 888010752 ps
T1046 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4000549104 Jul 04 05:07:50 PM PDT 24 Jul 04 05:07:52 PM PDT 24 47163165 ps
T1047 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1281768469 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:49 PM PDT 24 195920280 ps
T72 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3908030764 Jul 04 05:07:33 PM PDT 24 Jul 04 05:07:35 PM PDT 24 49465479 ps
T1048 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3915921657 Jul 04 05:07:45 PM PDT 24 Jul 04 05:08:06 PM PDT 24 836266406 ps
T1049 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3908653542 Jul 04 05:07:51 PM PDT 24 Jul 04 05:07:55 PM PDT 24 107775755 ps
T1050 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1381839230 Jul 04 05:07:47 PM PDT 24 Jul 04 05:07:48 PM PDT 24 28775599 ps
T1051 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2494475010 Jul 04 05:07:25 PM PDT 24 Jul 04 05:07:41 PM PDT 24 1366012305 ps
T1052 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2492398637 Jul 04 05:07:48 PM PDT 24 Jul 04 05:07:49 PM PDT 24 14851944 ps
T1053 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4167819483 Jul 04 05:07:41 PM PDT 24 Jul 04 05:07:43 PM PDT 24 220625879 ps
T1054 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3846337888 Jul 04 05:07:43 PM PDT 24 Jul 04 05:07:44 PM PDT 24 17441228 ps
T1055 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.342577256 Jul 04 05:07:33 PM PDT 24 Jul 04 05:07:37 PM PDT 24 105688905 ps
T1056 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.446269093 Jul 04 05:07:32 PM PDT 24 Jul 04 05:07:34 PM PDT 24 122581362 ps
T1057 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3998172235 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:47 PM PDT 24 17799263 ps
T1058 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.9518677 Jul 04 05:07:32 PM PDT 24 Jul 04 05:07:35 PM PDT 24 134723898 ps
T73 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1507790514 Jul 04 05:07:27 PM PDT 24 Jul 04 05:07:29 PM PDT 24 101201424 ps
T1059 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4094034140 Jul 04 05:07:42 PM PDT 24 Jul 04 05:07:45 PM PDT 24 106522313 ps
T1060 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2460186698 Jul 04 05:07:48 PM PDT 24 Jul 04 05:07:51 PM PDT 24 290303333 ps
T1061 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.689992127 Jul 04 05:07:40 PM PDT 24 Jul 04 05:07:45 PM PDT 24 1453555154 ps
T1062 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1054356937 Jul 04 05:07:41 PM PDT 24 Jul 04 05:07:43 PM PDT 24 20517451 ps
T1063 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3584511212 Jul 04 05:07:42 PM PDT 24 Jul 04 05:07:46 PM PDT 24 227223217 ps
T1064 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.91033819 Jul 04 05:07:40 PM PDT 24 Jul 04 05:07:47 PM PDT 24 311056162 ps
T1065 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1946154465 Jul 04 05:07:48 PM PDT 24 Jul 04 05:07:49 PM PDT 24 37227603 ps
T1066 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.39486787 Jul 04 05:07:43 PM PDT 24 Jul 04 05:07:44 PM PDT 24 40074182 ps
T1067 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1831327817 Jul 04 05:07:47 PM PDT 24 Jul 04 05:07:51 PM PDT 24 142995413 ps
T1068 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2134023870 Jul 04 05:07:41 PM PDT 24 Jul 04 05:07:46 PM PDT 24 757264836 ps
T1069 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2288695375 Jul 04 05:07:35 PM PDT 24 Jul 04 05:07:37 PM PDT 24 129662852 ps
T1070 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1239340565 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:30 PM PDT 24 165543111 ps
T1071 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1846081499 Jul 04 05:07:35 PM PDT 24 Jul 04 05:07:39 PM PDT 24 1282428828 ps
T1072 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3258732852 Jul 04 05:07:42 PM PDT 24 Jul 04 05:07:47 PM PDT 24 249077236 ps
T1073 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.651151354 Jul 04 05:07:27 PM PDT 24 Jul 04 05:07:29 PM PDT 24 46748914 ps
T1074 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3165627545 Jul 04 05:07:40 PM PDT 24 Jul 04 05:07:49 PM PDT 24 551659626 ps
T1075 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1872874080 Jul 04 05:07:57 PM PDT 24 Jul 04 05:07:58 PM PDT 24 28293320 ps
T1076 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2069785700 Jul 04 05:07:34 PM PDT 24 Jul 04 05:07:38 PM PDT 24 144806375 ps
T1077 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3827736236 Jul 04 05:07:47 PM PDT 24 Jul 04 05:07:48 PM PDT 24 23767428 ps
T1078 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4042409126 Jul 04 05:07:42 PM PDT 24 Jul 04 05:07:47 PM PDT 24 643941527 ps
T1079 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1373387167 Jul 04 05:07:49 PM PDT 24 Jul 04 05:07:52 PM PDT 24 167934995 ps
T1080 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.30503448 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:27 PM PDT 24 29206395 ps
T1081 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2001320370 Jul 04 05:07:34 PM PDT 24 Jul 04 05:08:12 PM PDT 24 7464680786 ps
T242 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.381638056 Jul 04 05:07:41 PM PDT 24 Jul 04 05:07:44 PM PDT 24 39060440 ps
T1082 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.872526978 Jul 04 05:07:43 PM PDT 24 Jul 04 05:07:45 PM PDT 24 49766729 ps
T1083 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3423425258 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:47 PM PDT 24 15069249 ps
T1084 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.188059362 Jul 04 05:07:27 PM PDT 24 Jul 04 05:07:30 PM PDT 24 22643775 ps
T1085 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3283095644 Jul 04 05:07:41 PM PDT 24 Jul 04 05:07:44 PM PDT 24 212534789 ps
T1086 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1602974766 Jul 04 05:07:40 PM PDT 24 Jul 04 05:07:43 PM PDT 24 635976420 ps
T1087 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1720416476 Jul 04 05:07:50 PM PDT 24 Jul 04 05:07:51 PM PDT 24 17680461 ps
T244 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4168729474 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:54 PM PDT 24 222297914 ps
T1088 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1706697925 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:28 PM PDT 24 176793905 ps
T1089 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2073993772 Jul 04 05:07:35 PM PDT 24 Jul 04 05:07:38 PM PDT 24 361327802 ps
T74 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2667114359 Jul 04 05:07:25 PM PDT 24 Jul 04 05:07:27 PM PDT 24 115782497 ps
T1090 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.886259876 Jul 04 05:07:55 PM PDT 24 Jul 04 05:07:56 PM PDT 24 16342103 ps
T1091 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2231693185 Jul 04 05:07:41 PM PDT 24 Jul 04 05:07:43 PM PDT 24 31790031 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2632206517 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:29 PM PDT 24 446422267 ps
T1093 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3743228545 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:50 PM PDT 24 316497676 ps
T1094 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1131224215 Jul 04 05:07:35 PM PDT 24 Jul 04 05:07:36 PM PDT 24 54054506 ps
T1095 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1376641146 Jul 04 05:07:42 PM PDT 24 Jul 04 05:07:51 PM PDT 24 4651956067 ps
T1096 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2944838452 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:28 PM PDT 24 29017034 ps
T1097 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2680172799 Jul 04 05:07:56 PM PDT 24 Jul 04 05:07:57 PM PDT 24 285636614 ps
T1098 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3304528383 Jul 04 05:07:45 PM PDT 24 Jul 04 05:07:46 PM PDT 24 13925215 ps
T1099 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.527375592 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:28 PM PDT 24 92674356 ps
T1100 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.634172150 Jul 04 05:07:49 PM PDT 24 Jul 04 05:07:50 PM PDT 24 40423056 ps
T1101 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3121569940 Jul 04 05:07:36 PM PDT 24 Jul 04 05:07:38 PM PDT 24 28960975 ps
T243 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2870939515 Jul 04 05:07:43 PM PDT 24 Jul 04 05:07:46 PM PDT 24 92264433 ps
T1102 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1526966063 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:40 PM PDT 24 2167007931 ps
T1103 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2765809301 Jul 04 05:07:55 PM PDT 24 Jul 04 05:07:56 PM PDT 24 21779938 ps
T1104 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3090961173 Jul 04 05:07:48 PM PDT 24 Jul 04 05:07:49 PM PDT 24 34270039 ps
T1105 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3874648648 Jul 04 05:07:40 PM PDT 24 Jul 04 05:07:41 PM PDT 24 89546299 ps
T1106 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2565134840 Jul 04 05:07:32 PM PDT 24 Jul 04 05:08:00 PM PDT 24 1843380435 ps
T1107 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1990216216 Jul 04 05:07:40 PM PDT 24 Jul 04 05:07:42 PM PDT 24 229077184 ps
T1108 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1518216462 Jul 04 05:08:00 PM PDT 24 Jul 04 05:08:01 PM PDT 24 21866144 ps
T1109 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2600378070 Jul 04 05:07:25 PM PDT 24 Jul 04 05:07:32 PM PDT 24 111029298 ps
T1110 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2987530046 Jul 04 05:07:34 PM PDT 24 Jul 04 05:07:36 PM PDT 24 207299051 ps
T1111 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4242224514 Jul 04 05:07:55 PM PDT 24 Jul 04 05:07:56 PM PDT 24 146149421 ps
T1112 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1526514815 Jul 04 05:07:42 PM PDT 24 Jul 04 05:07:44 PM PDT 24 200342454 ps
T1113 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2432685268 Jul 04 05:07:33 PM PDT 24 Jul 04 05:07:36 PM PDT 24 523618265 ps
T1114 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1014075945 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:28 PM PDT 24 277334882 ps
T1115 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2572935902 Jul 04 05:07:27 PM PDT 24 Jul 04 05:07:28 PM PDT 24 42627210 ps
T1116 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3134502969 Jul 04 05:07:51 PM PDT 24 Jul 04 05:07:52 PM PDT 24 43646648 ps
T1117 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.63166779 Jul 04 05:07:40 PM PDT 24 Jul 04 05:07:43 PM PDT 24 226745479 ps
T1118 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.343495735 Jul 04 05:07:34 PM PDT 24 Jul 04 05:07:36 PM PDT 24 238839444 ps
T1119 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1746432225 Jul 04 05:07:25 PM PDT 24 Jul 04 05:07:26 PM PDT 24 33189173 ps
T1120 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.134287723 Jul 04 05:07:35 PM PDT 24 Jul 04 05:07:36 PM PDT 24 31700954 ps
T1121 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.456740136 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:47 PM PDT 24 19668157 ps
T1122 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1852919197 Jul 04 05:07:44 PM PDT 24 Jul 04 05:07:49 PM PDT 24 160903336 ps
T1123 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2729435108 Jul 04 05:07:25 PM PDT 24 Jul 04 05:07:26 PM PDT 24 42406473 ps
T248 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3244196271 Jul 04 05:07:33 PM PDT 24 Jul 04 05:07:57 PM PDT 24 829761464 ps
T1124 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2968489145 Jul 04 05:07:46 PM PDT 24 Jul 04 05:07:48 PM PDT 24 15090833 ps
T1125 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2005519688 Jul 04 05:07:49 PM PDT 24 Jul 04 05:07:50 PM PDT 24 17886867 ps
T1126 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.270357020 Jul 04 05:07:43 PM PDT 24 Jul 04 05:07:48 PM PDT 24 163209296 ps
T1127 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3112768724 Jul 04 05:07:47 PM PDT 24 Jul 04 05:07:52 PM PDT 24 194944147 ps
T1128 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3412740890 Jul 04 05:07:27 PM PDT 24 Jul 04 05:07:42 PM PDT 24 493251699 ps
T75 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.807237329 Jul 04 05:07:26 PM PDT 24 Jul 04 05:07:29 PM PDT 24 25486666 ps
T1129 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4283832270 Jul 04 05:07:59 PM PDT 24 Jul 04 05:08:00 PM PDT 24 34314400 ps
T1130 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1233788233 Jul 04 05:07:57 PM PDT 24 Jul 04 05:07:58 PM PDT 24 15469483 ps
T1131 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.504978739 Jul 04 05:07:50 PM PDT 24 Jul 04 05:07:51 PM PDT 24 15360336 ps

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.3170913675
Short name T10
Test name
Test status
Simulation time 6368964618 ps
CPU time 46.28 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:14:37 PM PDT 24
Peak memory 240996 kb
Host smart-8121f00a-ac71-4dc5-8718-c5d1bfcc00e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170913675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.3170913675
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.679808796
Short name T13
Test name
Test status
Simulation time 24088244716 ps
CPU time 228.03 seconds
Started Jul 04 05:15:19 PM PDT 24
Finished Jul 04 05:19:08 PM PDT 24
Peak memory 263952 kb
Host smart-3fb12da8-914c-400d-bb3a-29ee294da773
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679808796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.679808796
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3057819918
Short name T31
Test name
Test status
Simulation time 27375455205 ps
CPU time 152.94 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:17:07 PM PDT 24
Peak memory 265600 kb
Host smart-44045de1-66a2-42c0-b403-2109abb9698d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3057819918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3057819918
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1297571526
Short name T85
Test name
Test status
Simulation time 689029355 ps
CPU time 16.48 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:57 PM PDT 24
Peak memory 215856 kb
Host smart-9dfd2c4c-b60d-446a-835d-9dbc04110d74
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297571526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1297571526
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.1751738351
Short name T17
Test name
Test status
Simulation time 14548269063 ps
CPU time 211.58 seconds
Started Jul 04 05:15:50 PM PDT 24
Finished Jul 04 05:19:22 PM PDT 24
Peak memory 272964 kb
Host smart-4722527b-f460-49e3-b7b9-621344db4074
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751738351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.1751738351
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3819731883
Short name T180
Test name
Test status
Simulation time 883582054381 ps
CPU time 779.32 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:28:26 PM PDT 24
Peak memory 281960 kb
Host smart-fdcc44e9-ce9c-4edb-bfdc-bac390a0158a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819731883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3819731883
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.810217593
Short name T60
Test name
Test status
Simulation time 111089619 ps
CPU time 0.83 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 216048 kb
Host smart-63cde705-e76a-414f-9b62-efc41db1bc87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810217593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.810217593
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1496201750
Short name T35
Test name
Test status
Simulation time 329603639589 ps
CPU time 710.5 seconds
Started Jul 04 05:15:12 PM PDT 24
Finished Jul 04 05:27:02 PM PDT 24
Peak memory 273704 kb
Host smart-291a7977-5fe1-428d-9549-c7f4063ea9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496201750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1496201750
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1733419767
Short name T36
Test name
Test status
Simulation time 45055152740 ps
CPU time 276.25 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:18:29 PM PDT 24
Peak memory 270916 kb
Host smart-8789c142-2ba6-45bc-a267-faabef9ee641
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1733419767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1733419767
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3625240189
Short name T45
Test name
Test status
Simulation time 44016530964 ps
CPU time 172.78 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:17:11 PM PDT 24
Peak memory 251552 kb
Host smart-68e99cf5-6cf4-4be1-b0f3-24b5749e83af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625240189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3625240189
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.302610099
Short name T59
Test name
Test status
Simulation time 121382806 ps
CPU time 3.18 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:30 PM PDT 24
Peak memory 215756 kb
Host smart-5baadc95-c528-4a3c-8f30-f97b28ba45cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302610099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.302610099
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.253494100
Short name T151
Test name
Test status
Simulation time 20668389609 ps
CPU time 88.91 seconds
Started Jul 04 05:15:09 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 264064 kb
Host smart-62f9cff0-3005-46a2-82d7-06c36cdfd9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253494100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.253494100
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.2477563724
Short name T16
Test name
Test status
Simulation time 280072345 ps
CPU time 1.12 seconds
Started Jul 04 05:12:25 PM PDT 24
Finished Jul 04 05:12:26 PM PDT 24
Peak memory 236060 kb
Host smart-54e13ccc-c5b5-4dda-b2a9-a91b1a9d80fa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477563724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.2477563724
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2333955972
Short name T131
Test name
Test status
Simulation time 1017827751 ps
CPU time 19.36 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:42 PM PDT 24
Peak memory 235868 kb
Host smart-e98c91e5-b8f4-409f-be0d-a10cb59842ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2333955972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2333955972
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.629062166
Short name T164
Test name
Test status
Simulation time 136814699283 ps
CPU time 321.73 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:19:16 PM PDT 24
Peak memory 250856 kb
Host smart-790dce12-a950-4eaa-852b-e086f9a001f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629062166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idle
.629062166
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1286325306
Short name T114
Test name
Test status
Simulation time 64931591099 ps
CPU time 276.96 seconds
Started Jul 04 05:14:39 PM PDT 24
Finished Jul 04 05:19:16 PM PDT 24
Peak memory 282944 kb
Host smart-28819f7e-438c-4e0d-9e60-7b8413531ea8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1286325306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1286325306
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1246548318
Short name T102
Test name
Test status
Simulation time 1510259311 ps
CPU time 21.88 seconds
Started Jul 04 05:07:28 PM PDT 24
Finished Jul 04 05:07:50 PM PDT 24
Peak memory 215668 kb
Host smart-ef734fea-ff1b-4c6f-b789-999fd2b4e1ea
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246548318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1246548318
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.922588456
Short name T115
Test name
Test status
Simulation time 284947266027 ps
CPU time 511.63 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:24:04 PM PDT 24
Peak memory 273584 kb
Host smart-34088274-0394-4fed-89f1-5b43b6105a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922588456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.922588456
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.36866675
Short name T33
Test name
Test status
Simulation time 7159754649 ps
CPU time 94.98 seconds
Started Jul 04 05:14:58 PM PDT 24
Finished Jul 04 05:16:33 PM PDT 24
Peak memory 252584 kb
Host smart-4f1804cc-6642-4206-83e2-7fa0777f79cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36866675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.36866675
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.3377188861
Short name T182
Test name
Test status
Simulation time 88705959205 ps
CPU time 649.1 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:26:15 PM PDT 24
Peak memory 272828 kb
Host smart-7edc3371-c38a-49b3-bcc3-3572cf6542f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377188861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.3377188861
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2628071784
Short name T162
Test name
Test status
Simulation time 87144063350 ps
CPU time 139.49 seconds
Started Jul 04 05:12:26 PM PDT 24
Finished Jul 04 05:14:45 PM PDT 24
Peak memory 263288 kb
Host smart-6c9e2c89-02ac-4edc-9106-37f66c269618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628071784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2628071784
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.2651815902
Short name T148
Test name
Test status
Simulation time 18852842382 ps
CPU time 163.71 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:18:09 PM PDT 24
Peak memory 262312 kb
Host smart-d836074e-d55b-470e-8342-44347079eec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651815902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.2651815902
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.743628962
Short name T150
Test name
Test status
Simulation time 18234828070 ps
CPU time 174.06 seconds
Started Jul 04 05:14:32 PM PDT 24
Finished Jul 04 05:17:26 PM PDT 24
Peak memory 249156 kb
Host smart-2fcd31de-a41c-42bc-b3ab-08497bfa1292
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743628962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.743628962
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1580769195
Short name T201
Test name
Test status
Simulation time 61917590866 ps
CPU time 608.21 seconds
Started Jul 04 05:16:06 PM PDT 24
Finished Jul 04 05:26:15 PM PDT 24
Peak memory 270616 kb
Host smart-52ed36cb-25e7-4dda-9d54-22940f0b328f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580769195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1580769195
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.4083770291
Short name T58
Test name
Test status
Simulation time 1365319964 ps
CPU time 20.08 seconds
Started Jul 04 05:07:39 PM PDT 24
Finished Jul 04 05:07:59 PM PDT 24
Peak memory 216400 kb
Host smart-76406b7c-7eba-43a9-88b7-a44b339b83ae
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4083770291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.4083770291
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.2270621529
Short name T310
Test name
Test status
Simulation time 19072149673 ps
CPU time 127.68 seconds
Started Jul 04 05:15:06 PM PDT 24
Finished Jul 04 05:17:14 PM PDT 24
Peak memory 273224 kb
Host smart-7effd7bf-d182-40db-9f65-3dc7f6cb923d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270621529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.2270621529
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.1459997748
Short name T25
Test name
Test status
Simulation time 18558189 ps
CPU time 0.74 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 205452 kb
Host smart-7a7f694b-71a0-40db-aaa5-70d16b6db835
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459997748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
1459997748
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3928676121
Short name T205
Test name
Test status
Simulation time 4723815425 ps
CPU time 110.72 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:15:40 PM PDT 24
Peak memory 254888 kb
Host smart-cdc0ac4a-d4d8-4f40-81dd-9bb46446dd58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928676121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3928676121
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.2061557496
Short name T47
Test name
Test status
Simulation time 40607236914 ps
CPU time 326.12 seconds
Started Jul 04 05:13:57 PM PDT 24
Finished Jul 04 05:19:23 PM PDT 24
Peak memory 263760 kb
Host smart-e71ae392-2990-41cf-9937-72715ae26110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061557496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.2061557496
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3326882625
Short name T153
Test name
Test status
Simulation time 9390671076 ps
CPU time 98.25 seconds
Started Jul 04 05:15:59 PM PDT 24
Finished Jul 04 05:17:38 PM PDT 24
Peak memory 254728 kb
Host smart-99253831-65a4-4daf-90b3-20b5e7b03ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326882625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3326882625
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.541532490
Short name T82
Test name
Test status
Simulation time 59910433986 ps
CPU time 566.57 seconds
Started Jul 04 05:12:31 PM PDT 24
Finished Jul 04 05:21:58 PM PDT 24
Peak memory 270320 kb
Host smart-66c8378b-7371-4558-94ac-2d347a7782a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541532490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.541532490
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.350243891
Short name T231
Test name
Test status
Simulation time 45199707318 ps
CPU time 81.4 seconds
Started Jul 04 05:16:08 PM PDT 24
Finished Jul 04 05:17:30 PM PDT 24
Peak memory 265220 kb
Host smart-46aaf1eb-b70a-4f00-beb0-c2c68965d737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350243891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idle
.350243891
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.1072279508
Short name T229
Test name
Test status
Simulation time 126903209849 ps
CPU time 191.1 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:19:22 PM PDT 24
Peak memory 252736 kb
Host smart-0db0fddd-0933-49f9-b34a-d5ac8553c3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072279508 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.1072279508
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_intercept.2001609073
Short name T3
Test name
Test status
Simulation time 4500673310 ps
CPU time 9.87 seconds
Started Jul 04 05:14:48 PM PDT 24
Finished Jul 04 05:14:58 PM PDT 24
Peak memory 224504 kb
Host smart-909eb655-d675-4737-88b3-17e1acdc26da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001609073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.2001609073
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.365321469
Short name T94
Test name
Test status
Simulation time 82175109 ps
CPU time 4.75 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:39 PM PDT 24
Peak memory 215936 kb
Host smart-858ee510-061e-4c25-8767-e5671170eb7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365321469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.365321469
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1965845838
Short name T57
Test name
Test status
Simulation time 1980551212 ps
CPU time 18.17 seconds
Started Jul 04 05:07:47 PM PDT 24
Finished Jul 04 05:08:06 PM PDT 24
Peak memory 215764 kb
Host smart-016efb4a-83c7-4c9e-85bf-971fc14b0e34
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965845838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1965845838
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.1108437933
Short name T130
Test name
Test status
Simulation time 217614990 ps
CPU time 5.88 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 232640 kb
Host smart-d56df10f-2f0c-47e2-81ff-2b874e6c2835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108437933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.1108437933
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.1834093912
Short name T20
Test name
Test status
Simulation time 56022898 ps
CPU time 1.07 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:53 PM PDT 24
Peak memory 206676 kb
Host smart-c774cd0a-d915-4934-87b5-05ac62dcbc33
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834093912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.1834093912
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1915354344
Short name T295
Test name
Test status
Simulation time 1282043015 ps
CPU time 10.42 seconds
Started Jul 04 05:15:50 PM PDT 24
Finished Jul 04 05:16:01 PM PDT 24
Peak memory 224432 kb
Host smart-dbd60eea-baa4-45c4-b450-10c0d23ece6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1915354344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1915354344
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2870939515
Short name T243
Test name
Test status
Simulation time 92264433 ps
CPU time 2.55 seconds
Started Jul 04 05:07:43 PM PDT 24
Finished Jul 04 05:07:46 PM PDT 24
Peak memory 216980 kb
Host smart-ee20a8a1-87c4-4352-b7d5-30c4ed3017cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870939515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2870939515
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.4220003410
Short name T39
Test name
Test status
Simulation time 244823265177 ps
CPU time 354.51 seconds
Started Jul 04 05:12:24 PM PDT 24
Finished Jul 04 05:18:18 PM PDT 24
Peak memory 257160 kb
Host smart-897bcefc-5880-468c-8fb1-4c2f0971971b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220003410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.4220003410
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.3242269214
Short name T241
Test name
Test status
Simulation time 17820244779 ps
CPU time 256.87 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:18:05 PM PDT 24
Peak memory 281948 kb
Host smart-77c294c7-2e7d-4409-ae97-e0ee97680ce8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242269214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.3242269214
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.4224652128
Short name T223
Test name
Test status
Simulation time 161739757175 ps
CPU time 392.21 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:20:23 PM PDT 24
Peak memory 266984 kb
Host smart-b28f6608-33d0-4f0f-902a-3e6dbba58afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224652128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.4224652128
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.293272688
Short name T303
Test name
Test status
Simulation time 14010622093 ps
CPU time 8.35 seconds
Started Jul 04 05:14:05 PM PDT 24
Finished Jul 04 05:14:14 PM PDT 24
Peak memory 216404 kb
Host smart-58222527-a654-48bf-9877-89d0c3613f2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=293272688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.293272688
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.1813180099
Short name T279
Test name
Test status
Simulation time 85262201875 ps
CPU time 152.08 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:16:58 PM PDT 24
Peak memory 253708 kb
Host smart-0fab05d3-7846-47d7-844f-c523f02fca52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813180099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.1813180099
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2599500036
Short name T209
Test name
Test status
Simulation time 22379590976 ps
CPU time 174.3 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:17:38 PM PDT 24
Peak memory 254668 kb
Host smart-6a5fd488-30cf-49f4-bd07-30d1c989fcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2599500036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2599500036
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.3944861860
Short name T291
Test name
Test status
Simulation time 1875261666 ps
CPU time 17.59 seconds
Started Jul 04 05:14:51 PM PDT 24
Finished Jul 04 05:15:08 PM PDT 24
Peak memory 236316 kb
Host smart-b39f3138-a9a7-45ef-b15e-ffc583c14c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944861860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.3944861860
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2358187724
Short name T221
Test name
Test status
Simulation time 186487094450 ps
CPU time 560.97 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:25:43 PM PDT 24
Peak memory 267504 kb
Host smart-c50a1566-c7dc-441b-b4b5-7d8e2e1f8c9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358187724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2358187724
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1507790514
Short name T73
Test name
Test status
Simulation time 101201424 ps
CPU time 1.52 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:29 PM PDT 24
Peak memory 215568 kb
Host smart-0bcb11fb-39e4-4b4d-aa39-3bff3f8ff7cf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507790514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1507790514
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3412740890
Short name T1128
Test name
Test status
Simulation time 493251699 ps
CPU time 14.55 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:42 PM PDT 24
Peak memory 207492 kb
Host smart-d572ee63-3a12-4b6b-b919-75308064173f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3412740890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3412740890
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.1526966063
Short name T1102
Test name
Test status
Simulation time 2167007931 ps
CPU time 13.94 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:40 PM PDT 24
Peak memory 207480 kb
Host smart-0d457e76-1105-473b-8c25-d6778f4046c0
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526966063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.1526966063
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2667114359
Short name T74
Test name
Test status
Simulation time 115782497 ps
CPU time 1.18 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:27 PM PDT 24
Peak memory 207428 kb
Host smart-f182cc95-8342-4b31-b3f8-9e0a0530b6a6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667114359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2667114359
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.1984471236
Short name T1026
Test name
Test status
Simulation time 216379128 ps
CPU time 3.72 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:32 PM PDT 24
Peak memory 217404 kb
Host smart-7b753a30-20c1-4400-902f-7e3522497368
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984471236 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.1984471236
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.1959728632
Short name T112
Test name
Test status
Simulation time 80211439 ps
CPU time 1.94 seconds
Started Jul 04 05:07:24 PM PDT 24
Finished Jul 04 05:07:26 PM PDT 24
Peak memory 215584 kb
Host smart-913ea85a-ff4f-477e-81ba-3d125bba11a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959728632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.1
959728632
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2944838452
Short name T1096
Test name
Test status
Simulation time 29017034 ps
CPU time 0.75 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 204528 kb
Host smart-d5a2d2d9-4ac3-4ce2-a8e5-bc88a082550a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944838452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
944838452
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.651151354
Short name T1073
Test name
Test status
Simulation time 46748914 ps
CPU time 1.76 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:29 PM PDT 24
Peak memory 215684 kb
Host smart-1339080c-cf4d-4cd8-a8d6-4b9d0ff32d85
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651151354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_
device_mem_partial_access.651151354
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2729435108
Short name T1123
Test name
Test status
Simulation time 42406473 ps
CPU time 0.65 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:26 PM PDT 24
Peak memory 204300 kb
Host smart-e0668d06-e57d-48b0-a5c4-f88ab7eec8fc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2729435108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2729435108
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.2632206517
Short name T1092
Test name
Test status
Simulation time 446422267 ps
CPU time 2.97 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:29 PM PDT 24
Peak memory 215588 kb
Host smart-08c12042-755d-43a6-827e-84d92eebd459
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632206517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.2632206517
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2494475010
Short name T1051
Test name
Test status
Simulation time 1366012305 ps
CPU time 14.99 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:41 PM PDT 24
Peak memory 215776 kb
Host smart-c2a1acd7-954c-4792-aa96-95a9d5d313fe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494475010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2494475010
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.3920261528
Short name T108
Test name
Test status
Simulation time 5178047893 ps
CPU time 40.64 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:08:07 PM PDT 24
Peak memory 207604 kb
Host smart-0f61e3c8-55cd-4d02-8710-bdd72d43d653
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3920261528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.3920261528
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.807237329
Short name T75
Test name
Test status
Simulation time 25486666 ps
CPU time 1.37 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:29 PM PDT 24
Peak memory 217668 kb
Host smart-c08bcfde-0e3d-457a-b98a-c5dc48a9ca23
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807237329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.807237329
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.2073993772
Short name T1089
Test name
Test status
Simulation time 361327802 ps
CPU time 2.91 seconds
Started Jul 04 05:07:35 PM PDT 24
Finished Jul 04 05:07:38 PM PDT 24
Peak memory 217232 kb
Host smart-0b25c83a-5c74-4e19-bc3e-e29df0c4afe2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073993772 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.2073993772
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.1239340565
Short name T1070
Test name
Test status
Simulation time 165543111 ps
CPU time 2.54 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:30 PM PDT 24
Peak memory 215564 kb
Host smart-b05013c1-4d5c-4b14-8517-2042b07e5691
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1239340565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.1
239340565
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1746432225
Short name T1119
Test name
Test status
Simulation time 33189173 ps
CPU time 0.73 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:26 PM PDT 24
Peak memory 204152 kb
Host smart-8e811fe7-2c64-425a-8701-f877dc91b217
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746432225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
746432225
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.188059362
Short name T1084
Test name
Test status
Simulation time 22643775 ps
CPU time 1.91 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:30 PM PDT 24
Peak memory 215712 kb
Host smart-76440a9c-e372-46ca-94a9-0c635e912273
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188059362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.188059362
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.1285995584
Short name T1020
Test name
Test status
Simulation time 13424195 ps
CPU time 0.72 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 204384 kb
Host smart-64eb8e85-f8bb-4c8b-be56-3def5f7a7f62
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285995584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.1285995584
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.1503655189
Short name T1037
Test name
Test status
Simulation time 59376494 ps
CPU time 2.09 seconds
Started Jul 04 05:07:35 PM PDT 24
Finished Jul 04 05:07:37 PM PDT 24
Peak memory 215580 kb
Host smart-3756c7df-7c5c-4348-9048-1e316c794fd8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503655189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.1503655189
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3233978773
Short name T93
Test name
Test status
Simulation time 88545931 ps
CPU time 1.92 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 215904 kb
Host smart-02cea6ae-6428-44eb-a4a7-5d15f7ad6b82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233978773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
233978773
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2600378070
Short name T1109
Test name
Test status
Simulation time 111029298 ps
CPU time 6.71 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:32 PM PDT 24
Peak memory 215708 kb
Host smart-6af4bb9f-9800-47ef-897d-faf41cd2c163
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600378070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2600378070
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1545544459
Short name T141
Test name
Test status
Simulation time 111143725 ps
CPU time 2.76 seconds
Started Jul 04 05:07:47 PM PDT 24
Finished Jul 04 05:07:50 PM PDT 24
Peak memory 217256 kb
Host smart-a3f1e87d-f18c-4f5e-8036-0875f4022b60
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545544459 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1545544459
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1054356937
Short name T1062
Test name
Test status
Simulation time 20517451 ps
CPU time 1.41 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:43 PM PDT 24
Peak memory 215700 kb
Host smart-3acc58cf-b6cd-48a1-9f7e-6002bde2f454
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054356937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1054356937
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.3874648648
Short name T1105
Test name
Test status
Simulation time 89546299 ps
CPU time 0.75 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:41 PM PDT 24
Peak memory 204172 kb
Host smart-8ce9b2da-fce4-4580-b2f3-561116edc9c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874648648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
3874648648
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.4167819483
Short name T1053
Test name
Test status
Simulation time 220625879 ps
CPU time 2.16 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:43 PM PDT 24
Peak memory 215632 kb
Host smart-53b7abf6-4dc5-45ae-a1c3-c25d0141a5ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4167819483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.4167819483
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.1664126417
Short name T86
Test name
Test status
Simulation time 369096550 ps
CPU time 4.02 seconds
Started Jul 04 05:07:45 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 216868 kb
Host smart-97ea9ac2-c322-4765-bbbc-1be27c336254
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664126417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
1664126417
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2983115124
Short name T251
Test name
Test status
Simulation time 1187620825 ps
CPU time 7.18 seconds
Started Jul 04 05:07:50 PM PDT 24
Finished Jul 04 05:07:58 PM PDT 24
Peak memory 215732 kb
Host smart-d26f3c4b-58be-4dd4-a56c-a6e80290eaf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2983115124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2983115124
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.3611397130
Short name T99
Test name
Test status
Simulation time 58852020 ps
CPU time 1.74 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 216832 kb
Host smart-2c54c60e-b5a5-4998-b2a3-5a781d66419a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3611397130 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.3611397130
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4243586162
Short name T106
Test name
Test status
Simulation time 48639196 ps
CPU time 1.79 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:43 PM PDT 24
Peak memory 215656 kb
Host smart-c7f08af8-47e5-4869-93e5-e04f9636db58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4243586162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4243586162
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.39486787
Short name T1066
Test name
Test status
Simulation time 40074182 ps
CPU time 0.69 seconds
Started Jul 04 05:07:43 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 204576 kb
Host smart-7c04cf65-f44d-4660-a975-249425ba119b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39486787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.39486787
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.3258732852
Short name T1072
Test name
Test status
Simulation time 249077236 ps
CPU time 4.4 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 215620 kb
Host smart-c9cef108-2cb5-4257-b46a-d173252e3b36
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3258732852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.3258732852
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3580938638
Short name T91
Test name
Test status
Simulation time 723962586 ps
CPU time 4.7 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 215932 kb
Host smart-7c7e168c-bacb-4dbd-8fd3-5ebf9a4d6b50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3580938638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3580938638
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.270357020
Short name T1126
Test name
Test status
Simulation time 163209296 ps
CPU time 4.01 seconds
Started Jul 04 05:07:43 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 218092 kb
Host smart-eca85dc3-9cda-45ae-bb3c-e0b5d7845878
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270357020 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.270357020
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.900269807
Short name T109
Test name
Test status
Simulation time 281819688 ps
CPU time 1.34 seconds
Started Jul 04 05:07:39 PM PDT 24
Finished Jul 04 05:07:41 PM PDT 24
Peak memory 215680 kb
Host smart-5f7ecd5c-671f-4add-acdd-c6df08459f89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900269807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.900269807
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.2861842596
Short name T1027
Test name
Test status
Simulation time 38609238 ps
CPU time 0.7 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:41 PM PDT 24
Peak memory 204160 kb
Host smart-c67453a6-2f40-4504-ab76-71787a88f693
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861842596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
2861842596
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1610326667
Short name T1033
Test name
Test status
Simulation time 540246147 ps
CPU time 2.87 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 215772 kb
Host smart-ad87a8f4-512b-44df-b983-f81c1c183cbe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610326667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1610326667
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.1852919197
Short name T1122
Test name
Test status
Simulation time 160903336 ps
CPU time 4.84 seconds
Started Jul 04 05:07:44 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 216000 kb
Host smart-0e8e082d-cc10-4417-8f3b-53f80092b606
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852919197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
1852919197
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.3915921657
Short name T1048
Test name
Test status
Simulation time 836266406 ps
CPU time 21.2 seconds
Started Jul 04 05:07:45 PM PDT 24
Finished Jul 04 05:08:06 PM PDT 24
Peak memory 215728 kb
Host smart-260cbe40-d72a-45fb-95a8-c88c952f260c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915921657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.3915921657
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.3328047493
Short name T89
Test name
Test status
Simulation time 129235872 ps
CPU time 3.87 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 218344 kb
Host smart-9fab6f51-35cc-4e12-93eb-89b95677b045
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328047493 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.3328047493
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2574727481
Short name T110
Test name
Test status
Simulation time 75249313 ps
CPU time 1.36 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 215600 kb
Host smart-63d81c52-adbf-46e0-9109-40f4de43f507
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574727481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2574727481
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4289298389
Short name T1028
Test name
Test status
Simulation time 19210343 ps
CPU time 0.8 seconds
Started Jul 04 05:07:44 PM PDT 24
Finished Jul 04 05:07:45 PM PDT 24
Peak memory 204264 kb
Host smart-be4f59c1-8f6a-4349-9d1e-6c67f5c6f7ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289298389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
4289298389
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2531617059
Short name T1040
Test name
Test status
Simulation time 586992014 ps
CPU time 4.17 seconds
Started Jul 04 05:07:44 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 215696 kb
Host smart-6d141271-41cb-4cf0-afdb-1cf69872f6c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531617059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2531617059
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.1376641146
Short name T1095
Test name
Test status
Simulation time 4651956067 ps
CPU time 8.9 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:51 PM PDT 24
Peak memory 215780 kb
Host smart-dc51305e-457f-4e5e-91a5-fecb85dd8b15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376641146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.1376641146
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.1602974766
Short name T1086
Test name
Test status
Simulation time 635976420 ps
CPU time 3.56 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:43 PM PDT 24
Peak memory 216964 kb
Host smart-8e90930a-56ea-4d37-9223-eacd08f77194
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602974766 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.1602974766
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4000549104
Short name T1046
Test name
Test status
Simulation time 47163165 ps
CPU time 1.34 seconds
Started Jul 04 05:07:50 PM PDT 24
Finished Jul 04 05:07:52 PM PDT 24
Peak memory 207340 kb
Host smart-ab91a6c8-4040-4708-b3c8-8ff72700c7be
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4000549104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4000549104
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.504978739
Short name T1131
Test name
Test status
Simulation time 15360336 ps
CPU time 0.72 seconds
Started Jul 04 05:07:50 PM PDT 24
Finished Jul 04 05:07:51 PM PDT 24
Peak memory 204468 kb
Host smart-42307189-522f-41cf-91bb-216ec0c45e34
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504978739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.504978739
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.463355394
Short name T1032
Test name
Test status
Simulation time 673100100 ps
CPU time 2.87 seconds
Started Jul 04 05:07:45 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 215720 kb
Host smart-c6b9444e-49ba-43ab-a02e-2f2de4c20166
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463355394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.463355394
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4042409126
Short name T1078
Test name
Test status
Simulation time 643941527 ps
CPU time 4.56 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 215872 kb
Host smart-133a1ab4-aa51-42ef-9378-93d1a1bca6ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042409126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4042409126
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.91033819
Short name T1064
Test name
Test status
Simulation time 311056162 ps
CPU time 6.95 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 215808 kb
Host smart-74eb45b1-7efb-439b-ae8b-082d03af9736
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91033819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_
tl_intg_err.91033819
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3599559043
Short name T95
Test name
Test status
Simulation time 173889177 ps
CPU time 1.82 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 216832 kb
Host smart-09473a5d-19ab-44cd-a8f6-a13f41abc3ae
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599559043 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3599559043
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2231693185
Short name T1091
Test name
Test status
Simulation time 31790031 ps
CPU time 1.9 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:43 PM PDT 24
Peak memory 215568 kb
Host smart-a0a36a8a-fa2a-41c4-aa23-efe4e16f9c72
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2231693185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2231693185
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1223763672
Short name T1042
Test name
Test status
Simulation time 14503131 ps
CPU time 0.73 seconds
Started Jul 04 05:07:44 PM PDT 24
Finished Jul 04 05:07:45 PM PDT 24
Peak memory 204264 kb
Host smart-b2da0d99-05c4-49d9-b0fd-b49115fad168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223763672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1223763672
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.3006945197
Short name T139
Test name
Test status
Simulation time 262967091 ps
CPU time 2.87 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:43 PM PDT 24
Peak memory 215644 kb
Host smart-939c600a-6350-407b-86f8-592767bed638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006945197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.3006945197
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.689992127
Short name T1061
Test name
Test status
Simulation time 1453555154 ps
CPU time 4.46 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:45 PM PDT 24
Peak memory 215848 kb
Host smart-0c82d5e1-b143-4484-bcde-7886afb69b05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689992127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.689992127
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.4168729474
Short name T244
Test name
Test status
Simulation time 222297914 ps
CPU time 6.78 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:54 PM PDT 24
Peak memory 215752 kb
Host smart-7f3b25f1-f431-4c11-a718-6720f3ef5561
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168729474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.4168729474
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3359422770
Short name T137
Test name
Test status
Simulation time 99670045 ps
CPU time 2.77 seconds
Started Jul 04 05:07:44 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 215996 kb
Host smart-2c715941-5f26-4139-8ca8-783d4d5c4145
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3359422770 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3359422770
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.1596926473
Short name T104
Test name
Test status
Simulation time 346836653 ps
CPU time 1.79 seconds
Started Jul 04 05:07:50 PM PDT 24
Finished Jul 04 05:07:52 PM PDT 24
Peak memory 215620 kb
Host smart-46fa4cc5-8374-4dcd-96c1-73978ad1a7a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596926473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
1596926473
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3423425258
Short name T1083
Test name
Test status
Simulation time 15069249 ps
CPU time 0.76 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 204200 kb
Host smart-3b06a50d-5121-4cb8-9e00-641cee1a8787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3423425258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3423425258
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.87902102
Short name T128
Test name
Test status
Simulation time 57889044 ps
CPU time 1.8 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 215644 kb
Host smart-853cbc13-db69-4fc8-877d-9925692408ba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87902102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sp
i_device_same_csr_outstanding.87902102
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.144646893
Short name T88
Test name
Test status
Simulation time 83357984 ps
CPU time 3.16 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:50 PM PDT 24
Peak memory 216948 kb
Host smart-07272299-64e3-4113-a3ba-ad3cb6c7b397
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=144646893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.144646893
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.3165627545
Short name T1074
Test name
Test status
Simulation time 551659626 ps
CPU time 7.85 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 215688 kb
Host smart-90b82930-7d92-44f8-a6fa-a10d7622583f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165627545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.3165627545
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2611858359
Short name T83
Test name
Test status
Simulation time 136814645 ps
CPU time 3.35 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:43 PM PDT 24
Peak memory 217932 kb
Host smart-db7ceb17-b696-4a6d-9577-27364852ef0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611858359 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2611858359
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3584511212
Short name T1063
Test name
Test status
Simulation time 227223217 ps
CPU time 3.01 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:46 PM PDT 24
Peak memory 215584 kb
Host smart-fab7b42d-b143-483e-9dd6-995bd114582e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584511212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3584511212
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3998172235
Short name T1057
Test name
Test status
Simulation time 17799263 ps
CPU time 0.7 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 204228 kb
Host smart-df6b8ae6-d189-43e6-aad4-c952fe8e5061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3998172235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3998172235
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3743228545
Short name T1093
Test name
Test status
Simulation time 316497676 ps
CPU time 4.16 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:50 PM PDT 24
Peak memory 215740 kb
Host smart-a052b463-9a29-4c9b-acfe-dc60bf26c1ad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743228545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3743228545
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.1831327817
Short name T1067
Test name
Test status
Simulation time 142995413 ps
CPU time 3.55 seconds
Started Jul 04 05:07:47 PM PDT 24
Finished Jul 04 05:07:51 PM PDT 24
Peak memory 216984 kb
Host smart-f35755fa-76ce-4d5c-bf4a-5326a9c72140
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831327817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
1831327817
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.73527679
Short name T247
Test name
Test status
Simulation time 417453540 ps
CPU time 6.47 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 215708 kb
Host smart-6cfc674f-67f3-498a-882f-4bbb588a4e23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73527679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_
tl_intg_err.73527679
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.32646665
Short name T140
Test name
Test status
Simulation time 122277599 ps
CPU time 1.85 seconds
Started Jul 04 05:07:47 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 216816 kb
Host smart-eb367e1f-267c-4f66-8634-8d249ee8f9b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32646665 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.32646665
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.634172150
Short name T1100
Test name
Test status
Simulation time 40423056 ps
CPU time 1.42 seconds
Started Jul 04 05:07:49 PM PDT 24
Finished Jul 04 05:07:50 PM PDT 24
Peak memory 207364 kb
Host smart-4bb9667b-77eb-4852-936a-3008c2b65cc2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=634172150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.634172150
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2790664139
Short name T1014
Test name
Test status
Simulation time 17310146 ps
CPU time 0.8 seconds
Started Jul 04 05:07:49 PM PDT 24
Finished Jul 04 05:07:50 PM PDT 24
Peak memory 204212 kb
Host smart-5694e1ea-689c-4ef9-8943-d9d6857a4dc5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2790664139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2790664139
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.3112768724
Short name T1127
Test name
Test status
Simulation time 194944147 ps
CPU time 4 seconds
Started Jul 04 05:07:47 PM PDT 24
Finished Jul 04 05:07:52 PM PDT 24
Peak memory 215736 kb
Host smart-aec3f691-9e4c-44bf-bb5e-60a8d0d4779f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3112768724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.3112768724
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.3908653542
Short name T1049
Test name
Test status
Simulation time 107775755 ps
CPU time 3.6 seconds
Started Jul 04 05:07:51 PM PDT 24
Finished Jul 04 05:07:55 PM PDT 24
Peak memory 216052 kb
Host smart-adb7c7ed-7fb9-42e2-b813-7324ff9f45b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908653542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
3908653542
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1375283066
Short name T250
Test name
Test status
Simulation time 4788229961 ps
CPU time 23.19 seconds
Started Jul 04 05:07:47 PM PDT 24
Finished Jul 04 05:08:10 PM PDT 24
Peak memory 215932 kb
Host smart-dba9277f-16aa-4b6e-8a22-55387c487172
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1375283066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1375283066
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.1281768469
Short name T1047
Test name
Test status
Simulation time 195920280 ps
CPU time 1.78 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 215760 kb
Host smart-045809f1-9b62-48a2-92bc-1c044d32a8eb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1281768469 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.1281768469
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1373387167
Short name T1079
Test name
Test status
Simulation time 167934995 ps
CPU time 2.63 seconds
Started Jul 04 05:07:49 PM PDT 24
Finished Jul 04 05:07:52 PM PDT 24
Peak memory 215624 kb
Host smart-9b8c3ac7-3844-4963-ad9d-3eb680aae91c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1373387167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1373387167
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.2005519688
Short name T1125
Test name
Test status
Simulation time 17886867 ps
CPU time 0.78 seconds
Started Jul 04 05:07:49 PM PDT 24
Finished Jul 04 05:07:50 PM PDT 24
Peak memory 204484 kb
Host smart-d85deafb-76a4-4cfa-bbe7-c0d77aa406f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005519688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
2005519688
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.2460186698
Short name T1060
Test name
Test status
Simulation time 290303333 ps
CPU time 3.08 seconds
Started Jul 04 05:07:48 PM PDT 24
Finished Jul 04 05:07:51 PM PDT 24
Peak memory 215632 kb
Host smart-b4738e82-45f3-4330-9f6e-1822e6aca8df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2460186698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.2460186698
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1207885193
Short name T1044
Test name
Test status
Simulation time 77196386 ps
CPU time 2.23 seconds
Started Jul 04 05:07:51 PM PDT 24
Finished Jul 04 05:07:54 PM PDT 24
Peak memory 215900 kb
Host smart-f2645b84-e646-4c0f-ae3b-073b27e05833
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207885193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1207885193
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.1335151791
Short name T107
Test name
Test status
Simulation time 773594208 ps
CPU time 16.67 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 215476 kb
Host smart-659baf6f-b599-46e4-a0a7-470ec4a23579
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335151791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.1335151791
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.798545474
Short name T113
Test name
Test status
Simulation time 888010752 ps
CPU time 11.43 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:39 PM PDT 24
Peak memory 207324 kb
Host smart-d371706c-1169-4d5f-af3e-b5afdb538637
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798545474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.798545474
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.4012742562
Short name T97
Test name
Test status
Simulation time 436850859 ps
CPU time 3.46 seconds
Started Jul 04 05:07:25 PM PDT 24
Finished Jul 04 05:07:29 PM PDT 24
Peak memory 217880 kb
Host smart-1d8ea973-47d1-4d82-9848-49961ea8d19e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012742562 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.4012742562
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.1014075945
Short name T1114
Test name
Test status
Simulation time 277334882 ps
CPU time 1.38 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 215676 kb
Host smart-2ff60b0e-6c90-455e-8594-4c6fef79016e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014075945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.1
014075945
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.30503448
Short name T1080
Test name
Test status
Simulation time 29206395 ps
CPU time 0.71 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:27 PM PDT 24
Peak memory 204268 kb
Host smart-472d4fba-4e00-415d-9ed2-f73ac2b81e2d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30503448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.30503448
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.1706697925
Short name T1088
Test name
Test status
Simulation time 176793905 ps
CPU time 1.85 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 215804 kb
Host smart-86de9f29-05fb-4955-ad7d-ee56ae71210d
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706697925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.1706697925
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2787982925
Short name T1030
Test name
Test status
Simulation time 12743034 ps
CPU time 0.69 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 204040 kb
Host smart-dcb292a0-15ea-4384-880b-10b3cb3f9d10
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2787982925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2787982925
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.4105347245
Short name T127
Test name
Test status
Simulation time 46469655 ps
CPU time 2.84 seconds
Started Jul 04 05:07:36 PM PDT 24
Finished Jul 04 05:07:39 PM PDT 24
Peak memory 215652 kb
Host smart-b3286fd7-52ed-4367-aae5-e9934ccd8193
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105347245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.4105347245
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1598727271
Short name T92
Test name
Test status
Simulation time 1248749862 ps
CPU time 3.23 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:31 PM PDT 24
Peak memory 215872 kb
Host smart-26996e89-de75-44a0-9d2a-d60cd73e23c4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598727271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
598727271
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.1982537293
Short name T101
Test name
Test status
Simulation time 573249343 ps
CPU time 7.78 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:34 PM PDT 24
Peak memory 215752 kb
Host smart-553d2abb-57ac-4baa-92b6-e6631b697173
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1982537293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.1982537293
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3827736236
Short name T1077
Test name
Test status
Simulation time 23767428 ps
CPU time 0.72 seconds
Started Jul 04 05:07:47 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 204432 kb
Host smart-f97f55ce-ae5f-4d72-a26a-70c851a01798
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827736236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3827736236
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.1946154465
Short name T1065
Test name
Test status
Simulation time 37227603 ps
CPU time 0.72 seconds
Started Jul 04 05:07:48 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 204484 kb
Host smart-b0dccaa3-82a9-4c61-8e2d-72babab0953e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946154465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
1946154465
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2306035831
Short name T1035
Test name
Test status
Simulation time 15614689 ps
CPU time 0.73 seconds
Started Jul 04 05:07:48 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 204580 kb
Host smart-50b86d2b-f4a7-4647-b2e9-027c210a319d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306035831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2306035831
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2492398637
Short name T1052
Test name
Test status
Simulation time 14851944 ps
CPU time 0.71 seconds
Started Jul 04 05:07:48 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 204176 kb
Host smart-1dd45e32-e014-46cc-af8e-e7a9e76ded5e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492398637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2492398637
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1381839230
Short name T1050
Test name
Test status
Simulation time 28775599 ps
CPU time 0.76 seconds
Started Jul 04 05:07:47 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 204156 kb
Host smart-787d7412-59e1-45df-b0c0-c6d16a60db76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381839230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1381839230
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3134502969
Short name T1116
Test name
Test status
Simulation time 43646648 ps
CPU time 0.75 seconds
Started Jul 04 05:07:51 PM PDT 24
Finished Jul 04 05:07:52 PM PDT 24
Peak memory 204496 kb
Host smart-e64b9cda-db9d-482b-ae56-65b8365ff025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134502969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3134502969
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.456740136
Short name T1121
Test name
Test status
Simulation time 19668157 ps
CPU time 0.72 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:47 PM PDT 24
Peak memory 204584 kb
Host smart-fe8ba2f6-9f7d-40dc-bc59-9086c9206d54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456740136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.456740136
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.1340730035
Short name T1024
Test name
Test status
Simulation time 13892905 ps
CPU time 0.72 seconds
Started Jul 04 05:07:51 PM PDT 24
Finished Jul 04 05:07:52 PM PDT 24
Peak memory 204140 kb
Host smart-4b92e288-e111-4688-9b31-6fffe440be6d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340730035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
1340730035
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.76441462
Short name T1022
Test name
Test status
Simulation time 51356431 ps
CPU time 0.74 seconds
Started Jul 04 05:07:47 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 204128 kb
Host smart-092ca11d-0ede-482f-beef-1cecce7ac24e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76441462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.76441462
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.3090961173
Short name T1104
Test name
Test status
Simulation time 34270039 ps
CPU time 0.76 seconds
Started Jul 04 05:07:48 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 204236 kb
Host smart-6f43c9fa-f759-4f19-8ea1-fd3bf61adea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090961173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
3090961173
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2917367285
Short name T138
Test name
Test status
Simulation time 370515386 ps
CPU time 8.14 seconds
Started Jul 04 05:07:33 PM PDT 24
Finished Jul 04 05:07:41 PM PDT 24
Peak memory 215508 kb
Host smart-06d2cf49-c11a-464a-80e3-b5c26674d9b2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917367285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2917367285
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2001320370
Short name T1081
Test name
Test status
Simulation time 7464680786 ps
CPU time 37.75 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:08:12 PM PDT 24
Peak memory 207520 kb
Host smart-bb28792a-e11f-4931-9aff-90daaef401a8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2001320370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2001320370
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.3908030764
Short name T72
Test name
Test status
Simulation time 49465479 ps
CPU time 1.54 seconds
Started Jul 04 05:07:33 PM PDT 24
Finished Jul 04 05:07:35 PM PDT 24
Peak memory 215600 kb
Host smart-ad8d151c-d27a-4184-843e-f52f5c4d1514
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908030764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.3908030764
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.342577256
Short name T1055
Test name
Test status
Simulation time 105688905 ps
CPU time 4.2 seconds
Started Jul 04 05:07:33 PM PDT 24
Finished Jul 04 05:07:37 PM PDT 24
Peak memory 217392 kb
Host smart-e9d2327b-71df-486e-9442-bde09995c2ca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342577256 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.342577256
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.2724178308
Short name T1038
Test name
Test status
Simulation time 39442338 ps
CPU time 1.22 seconds
Started Jul 04 05:07:36 PM PDT 24
Finished Jul 04 05:07:37 PM PDT 24
Peak memory 207444 kb
Host smart-69cf45d0-ddc9-4f99-bb80-9b386664833a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724178308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.2
724178308
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.2572935902
Short name T1115
Test name
Test status
Simulation time 42627210 ps
CPU time 0.72 seconds
Started Jul 04 05:07:27 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 204228 kb
Host smart-8635e438-fe71-4e7f-867f-ecb5a5efc809
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572935902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.2
572935902
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.343495735
Short name T1118
Test name
Test status
Simulation time 238839444 ps
CPU time 1.82 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:36 PM PDT 24
Peak memory 215808 kb
Host smart-ebdcade6-dc46-4739-8c2f-4e8a1910d592
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343495735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_
device_mem_partial_access.343495735
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.527375592
Short name T1099
Test name
Test status
Simulation time 92674356 ps
CPU time 0.67 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:28 PM PDT 24
Peak memory 204056 kb
Host smart-258d437d-26ec-47a5-abc8-d9783350a38e
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527375592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_mem
_walk.527375592
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1846081499
Short name T1071
Test name
Test status
Simulation time 1282428828 ps
CPU time 4.28 seconds
Started Jul 04 05:07:35 PM PDT 24
Finished Jul 04 05:07:39 PM PDT 24
Peak memory 215636 kb
Host smart-7313350d-5360-45fb-bef6-cd6e295e833a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1846081499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1846081499
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3645921126
Short name T90
Test name
Test status
Simulation time 801649083 ps
CPU time 2.57 seconds
Started Jul 04 05:07:26 PM PDT 24
Finished Jul 04 05:07:30 PM PDT 24
Peak memory 215892 kb
Host smart-0ca1faa3-ee43-452b-9a59-f987edd17dc6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645921126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
645921126
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.776459282
Short name T98
Test name
Test status
Simulation time 207267441 ps
CPU time 12.17 seconds
Started Jul 04 05:07:36 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 215580 kb
Host smart-48acf011-d3b3-40a3-93c0-c9b203aa4921
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=776459282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.776459282
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.3861394774
Short name T1034
Test name
Test status
Simulation time 11301876 ps
CPU time 0.74 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:46 PM PDT 24
Peak memory 204144 kb
Host smart-2d296315-8e43-45e4-af6d-9581a0862d32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861394774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
3861394774
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.2047090530
Short name T1043
Test name
Test status
Simulation time 20494098 ps
CPU time 0.73 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 204500 kb
Host smart-0d6d1dda-8dee-4f88-8d96-755a58bdc079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047090530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
2047090530
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.821678256
Short name T1029
Test name
Test status
Simulation time 18847252 ps
CPU time 0.76 seconds
Started Jul 04 05:07:50 PM PDT 24
Finished Jul 04 05:07:51 PM PDT 24
Peak memory 204480 kb
Host smart-0cd5ff19-bf8b-4acb-b502-77816f205460
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821678256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.821678256
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2968489145
Short name T1124
Test name
Test status
Simulation time 15090833 ps
CPU time 0.71 seconds
Started Jul 04 05:07:46 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 204172 kb
Host smart-eb5fca1d-c3eb-4eb8-80b2-6e42c38e27a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968489145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2968489145
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.1720416476
Short name T1087
Test name
Test status
Simulation time 17680461 ps
CPU time 0.74 seconds
Started Jul 04 05:07:50 PM PDT 24
Finished Jul 04 05:07:51 PM PDT 24
Peak memory 204168 kb
Host smart-09cef82e-2e5e-4018-be59-ab96394dab8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720416476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
1720416476
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3240621924
Short name T1017
Test name
Test status
Simulation time 12492360 ps
CPU time 0.8 seconds
Started Jul 04 05:07:56 PM PDT 24
Finished Jul 04 05:07:57 PM PDT 24
Peak memory 204148 kb
Host smart-426b3bb9-df7e-457c-a8d0-a733fc9b07d0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240621924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3240621924
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.3578943306
Short name T1036
Test name
Test status
Simulation time 56865870 ps
CPU time 0.78 seconds
Started Jul 04 05:07:56 PM PDT 24
Finished Jul 04 05:07:57 PM PDT 24
Peak memory 204240 kb
Host smart-ebb28d39-2155-45bb-90b0-5425e769a33e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578943306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
3578943306
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4242224514
Short name T1111
Test name
Test status
Simulation time 146149421 ps
CPU time 0.74 seconds
Started Jul 04 05:07:55 PM PDT 24
Finished Jul 04 05:07:56 PM PDT 24
Peak memory 204492 kb
Host smart-f63138ab-2193-4df3-9d53-bc08908da330
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4242224514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4242224514
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.1233788233
Short name T1130
Test name
Test status
Simulation time 15469483 ps
CPU time 0.73 seconds
Started Jul 04 05:07:57 PM PDT 24
Finished Jul 04 05:07:58 PM PDT 24
Peak memory 204252 kb
Host smart-c3a7b8df-81f8-457c-9436-b65de5fe14c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1233788233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
1233788233
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.4135149445
Short name T1015
Test name
Test status
Simulation time 24394357 ps
CPU time 0.8 seconds
Started Jul 04 05:08:00 PM PDT 24
Finished Jul 04 05:08:02 PM PDT 24
Peak memory 204224 kb
Host smart-85bd7fdf-5b92-4d20-a457-13e9a9177d38
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135149445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
4135149445
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.4094229697
Short name T136
Test name
Test status
Simulation time 3615690796 ps
CPU time 17.32 seconds
Started Jul 04 05:07:32 PM PDT 24
Finished Jul 04 05:07:49 PM PDT 24
Peak memory 207420 kb
Host smart-828abadd-5b5e-470e-972b-f579a5280dec
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094229697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.4094229697
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.2565134840
Short name T1106
Test name
Test status
Simulation time 1843380435 ps
CPU time 27.52 seconds
Started Jul 04 05:07:32 PM PDT 24
Finished Jul 04 05:08:00 PM PDT 24
Peak memory 207308 kb
Host smart-d594abc1-d429-4278-bbb0-d6148690c290
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565134840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.2565134840
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.968099767
Short name T111
Test name
Test status
Simulation time 25526509 ps
CPU time 0.98 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:35 PM PDT 24
Peak memory 207208 kb
Host smart-1247c2cc-737f-49cd-9fff-2b912bf8ba14
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968099767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.968099767
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.999356219
Short name T100
Test name
Test status
Simulation time 314952015 ps
CPU time 4.07 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:39 PM PDT 24
Peak memory 217336 kb
Host smart-6a257873-c036-4ac9-a87e-6ce48cf88ec4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=999356219 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.999356219
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.446269093
Short name T1056
Test name
Test status
Simulation time 122581362 ps
CPU time 2.08 seconds
Started Jul 04 05:07:32 PM PDT 24
Finished Jul 04 05:07:34 PM PDT 24
Peak memory 207444 kb
Host smart-15bcc2b2-930f-46c4-b804-6d63276882f7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446269093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.446269093
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.1131224215
Short name T1094
Test name
Test status
Simulation time 54054506 ps
CPU time 0.74 seconds
Started Jul 04 05:07:35 PM PDT 24
Finished Jul 04 05:07:36 PM PDT 24
Peak memory 204144 kb
Host smart-ef4dea8d-04f0-45a7-8b46-e5ccded633c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131224215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.1
131224215
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.772254255
Short name T103
Test name
Test status
Simulation time 232047565 ps
CPU time 2.07 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:37 PM PDT 24
Peak memory 215612 kb
Host smart-5880e1ff-731d-41bf-869c-c887d796ea7a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=772254255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.772254255
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.134287723
Short name T1120
Test name
Test status
Simulation time 31700954 ps
CPU time 0.67 seconds
Started Jul 04 05:07:35 PM PDT 24
Finished Jul 04 05:07:36 PM PDT 24
Peak memory 202932 kb
Host smart-6301b757-53c4-4aee-87d9-ed6634f721aa
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134287723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.134287723
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.9518677
Short name T1058
Test name
Test status
Simulation time 134723898 ps
CPU time 2.67 seconds
Started Jul 04 05:07:32 PM PDT 24
Finished Jul 04 05:07:35 PM PDT 24
Peak memory 215768 kb
Host smart-b96b61de-54c4-49fe-b0fa-d84230313cbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9518677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_same_csr_outstanding.9518677
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.3803996228
Short name T87
Test name
Test status
Simulation time 299234473 ps
CPU time 2.19 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:37 PM PDT 24
Peak memory 216160 kb
Host smart-abbe1ccc-8f00-43ef-8592-24e06ea248cb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803996228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.3
803996228
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.970819673
Short name T1031
Test name
Test status
Simulation time 5489779774 ps
CPU time 8.45 seconds
Started Jul 04 05:07:33 PM PDT 24
Finished Jul 04 05:07:42 PM PDT 24
Peak memory 215952 kb
Host smart-2e9fddf7-7c7d-403a-a2a4-f8b4588e3631
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970819673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_
tl_intg_err.970819673
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.4283832270
Short name T1129
Test name
Test status
Simulation time 34314400 ps
CPU time 0.73 seconds
Started Jul 04 05:07:59 PM PDT 24
Finished Jul 04 05:08:00 PM PDT 24
Peak memory 204256 kb
Host smart-9cea86fb-e5e7-47aa-a05d-c4afb1e72f30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283832270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
4283832270
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2765809301
Short name T1103
Test name
Test status
Simulation time 21779938 ps
CPU time 0.7 seconds
Started Jul 04 05:07:55 PM PDT 24
Finished Jul 04 05:07:56 PM PDT 24
Peak memory 204572 kb
Host smart-267097d9-84b2-4c75-b192-b1e64f519094
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765809301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2765809301
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1518216462
Short name T1108
Test name
Test status
Simulation time 21866144 ps
CPU time 0.76 seconds
Started Jul 04 05:08:00 PM PDT 24
Finished Jul 04 05:08:01 PM PDT 24
Peak memory 204556 kb
Host smart-42fac69d-d8ab-47f1-b2f3-e9685f881ead
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518216462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1518216462
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.2680172799
Short name T1097
Test name
Test status
Simulation time 285636614 ps
CPU time 0.81 seconds
Started Jul 04 05:07:56 PM PDT 24
Finished Jul 04 05:07:57 PM PDT 24
Peak memory 204108 kb
Host smart-619a9de9-39bf-4104-967f-dbb6fbaa9397
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680172799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
2680172799
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.298546421
Short name T1016
Test name
Test status
Simulation time 33351034 ps
CPU time 0.78 seconds
Started Jul 04 05:07:57 PM PDT 24
Finished Jul 04 05:07:58 PM PDT 24
Peak memory 204148 kb
Host smart-ac88c143-4375-40fb-8288-f5fafeb59216
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298546421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.298546421
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1872874080
Short name T1075
Test name
Test status
Simulation time 28293320 ps
CPU time 0.76 seconds
Started Jul 04 05:07:57 PM PDT 24
Finished Jul 04 05:07:58 PM PDT 24
Peak memory 204512 kb
Host smart-28673148-c958-4ed7-93f7-2e0e283c3737
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872874080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1872874080
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.3589018930
Short name T1039
Test name
Test status
Simulation time 24343970 ps
CPU time 0.79 seconds
Started Jul 04 05:07:57 PM PDT 24
Finished Jul 04 05:07:58 PM PDT 24
Peak memory 204156 kb
Host smart-4c55bc2f-ed7c-4ecf-9d79-71e5b7d2bc1f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3589018930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
3589018930
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.1328023210
Short name T1018
Test name
Test status
Simulation time 22903531 ps
CPU time 0.73 seconds
Started Jul 04 05:07:55 PM PDT 24
Finished Jul 04 05:07:57 PM PDT 24
Peak memory 204144 kb
Host smart-f24cb59a-fdba-4481-8104-ee1d81fcc41f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1328023210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
1328023210
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.3991046212
Short name T1025
Test name
Test status
Simulation time 13236965 ps
CPU time 0.94 seconds
Started Jul 04 05:07:56 PM PDT 24
Finished Jul 04 05:07:57 PM PDT 24
Peak memory 204172 kb
Host smart-2336082f-078c-4a4a-b271-ac4a9de188fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991046212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
3991046212
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.886259876
Short name T1090
Test name
Test status
Simulation time 16342103 ps
CPU time 0.75 seconds
Started Jul 04 05:07:55 PM PDT 24
Finished Jul 04 05:07:56 PM PDT 24
Peak memory 204252 kb
Host smart-6254ebc8-7e23-42eb-9501-046e5f262787
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886259876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.886259876
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1035130337
Short name T96
Test name
Test status
Simulation time 262522954 ps
CPU time 2.43 seconds
Started Jul 04 05:07:33 PM PDT 24
Finished Jul 04 05:07:35 PM PDT 24
Peak memory 217336 kb
Host smart-827911f8-8026-4a2c-a31e-1f14efb1789f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035130337 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1035130337
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3121569940
Short name T1101
Test name
Test status
Simulation time 28960975 ps
CPU time 1.77 seconds
Started Jul 04 05:07:36 PM PDT 24
Finished Jul 04 05:07:38 PM PDT 24
Peak memory 215700 kb
Host smart-44ab5659-ff19-41b3-bdfd-5c89431e1052
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121569940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
121569940
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.4079712764
Short name T1041
Test name
Test status
Simulation time 42823646 ps
CPU time 0.74 seconds
Started Jul 04 05:07:35 PM PDT 24
Finished Jul 04 05:07:36 PM PDT 24
Peak memory 204152 kb
Host smart-20313c16-5c04-4524-92ff-4a46fdbca38d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079712764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.4
079712764
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2288695375
Short name T1069
Test name
Test status
Simulation time 129662852 ps
CPU time 1.97 seconds
Started Jul 04 05:07:35 PM PDT 24
Finished Jul 04 05:07:37 PM PDT 24
Peak memory 214728 kb
Host smart-062d40a6-a088-402d-a43a-ba91ad8e22de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288695375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2288695375
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.3244196271
Short name T248
Test name
Test status
Simulation time 829761464 ps
CPU time 23.88 seconds
Started Jul 04 05:07:33 PM PDT 24
Finished Jul 04 05:07:57 PM PDT 24
Peak memory 216032 kb
Host smart-c6cabc45-db28-42e0-806e-17b341d8d17b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244196271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.3244196271
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.2040971401
Short name T1023
Test name
Test status
Simulation time 40163236 ps
CPU time 2.64 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:36 PM PDT 24
Peak memory 216856 kb
Host smart-8dcc7713-1323-4b55-8c52-4226e2e3ed4a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2040971401 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.2040971401
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.2987530046
Short name T1110
Test name
Test status
Simulation time 207299051 ps
CPU time 1.76 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:36 PM PDT 24
Peak memory 207436 kb
Host smart-d9847e5c-7399-455f-86b7-4944357dad7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2987530046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.2
987530046
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.352993124
Short name T1021
Test name
Test status
Simulation time 54657000 ps
CPU time 0.76 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:35 PM PDT 24
Peak memory 204496 kb
Host smart-ecbf94f1-2cd4-4c49-a9ab-47224abb0752
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=352993124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.352993124
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.2432685268
Short name T1113
Test name
Test status
Simulation time 523618265 ps
CPU time 3.23 seconds
Started Jul 04 05:07:33 PM PDT 24
Finished Jul 04 05:07:36 PM PDT 24
Peak memory 215696 kb
Host smart-76f3a802-f2bb-4601-a150-a1f3081aa00e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432685268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.2432685268
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2069785700
Short name T1076
Test name
Test status
Simulation time 144806375 ps
CPU time 3.9 seconds
Started Jul 04 05:07:34 PM PDT 24
Finished Jul 04 05:07:38 PM PDT 24
Peak memory 215940 kb
Host smart-b6cb35bb-4c8a-49fb-90d6-a1aa39d11a49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069785700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
069785700
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1376982741
Short name T246
Test name
Test status
Simulation time 393722093 ps
CPU time 11.89 seconds
Started Jul 04 05:07:33 PM PDT 24
Finished Jul 04 05:07:45 PM PDT 24
Peak memory 215640 kb
Host smart-de752e09-7087-467b-aaf5-22494c6a77a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376982741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1376982741
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.3374196057
Short name T84
Test name
Test status
Simulation time 142671735 ps
CPU time 3.96 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:46 PM PDT 24
Peak memory 218436 kb
Host smart-f9615f7c-1b50-45e5-8167-fa85087506aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374196057 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.3374196057
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3283095644
Short name T1085
Test name
Test status
Simulation time 212534789 ps
CPU time 2.36 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 215568 kb
Host smart-04c74ebe-09a4-4ab4-b54e-7197d39d82c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283095644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
283095644
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3304528383
Short name T1098
Test name
Test status
Simulation time 13925215 ps
CPU time 0.68 seconds
Started Jul 04 05:07:45 PM PDT 24
Finished Jul 04 05:07:46 PM PDT 24
Peak memory 204244 kb
Host smart-118674c1-8e3f-4492-a3b0-086f72bfb0d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304528383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
304528383
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1268360388
Short name T1045
Test name
Test status
Simulation time 779432885 ps
CPU time 4.49 seconds
Started Jul 04 05:07:43 PM PDT 24
Finished Jul 04 05:07:48 PM PDT 24
Peak memory 215784 kb
Host smart-2aaee0a1-3112-4463-b153-23d158e88fcf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268360388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1268360388
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.63166779
Short name T1117
Test name
Test status
Simulation time 226745479 ps
CPU time 3.23 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:43 PM PDT 24
Peak memory 215876 kb
Host smart-73ec98b3-9997-46d0-959d-581d716828e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63166779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.63166779
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.4094034140
Short name T1059
Test name
Test status
Simulation time 106522313 ps
CPU time 2.56 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:45 PM PDT 24
Peak memory 216828 kb
Host smart-c51eed54-a890-42b0-a0c7-844f92989b6c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094034140 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.4094034140
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1990216216
Short name T1107
Test name
Test status
Simulation time 229077184 ps
CPU time 2 seconds
Started Jul 04 05:07:40 PM PDT 24
Finished Jul 04 05:07:42 PM PDT 24
Peak memory 215712 kb
Host smart-c8f24541-2ca4-4fdf-a78d-c4022788bc53
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990216216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
990216216
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3846337888
Short name T1054
Test name
Test status
Simulation time 17441228 ps
CPU time 0.72 seconds
Started Jul 04 05:07:43 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 204272 kb
Host smart-be7ec2eb-04f0-4266-9a69-4b8e8a8c718c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846337888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
846337888
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.602988807
Short name T126
Test name
Test status
Simulation time 958715184 ps
CPU time 3.05 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 215668 kb
Host smart-1dab9ad3-c6e8-4eda-83c6-dbd0bf759d9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602988807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.602988807
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.872526978
Short name T1082
Test name
Test status
Simulation time 49766729 ps
CPU time 1.61 seconds
Started Jul 04 05:07:43 PM PDT 24
Finished Jul 04 05:07:45 PM PDT 24
Peak memory 215956 kb
Host smart-1e09445f-ab8e-4711-be30-73f148a07ea4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872526978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.872526978
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2258401870
Short name T245
Test name
Test status
Simulation time 1176036657 ps
CPU time 19.22 seconds
Started Jul 04 05:07:43 PM PDT 24
Finished Jul 04 05:08:03 PM PDT 24
Peak memory 216156 kb
Host smart-2a672b19-2c76-4362-bd8f-4a8e60d14d50
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2258401870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2258401870
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1526514815
Short name T1112
Test name
Test status
Simulation time 200342454 ps
CPU time 1.85 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 215848 kb
Host smart-d43ef256-23c6-44af-905f-87c2c7fece0d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526514815 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1526514815
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.3256214548
Short name T105
Test name
Test status
Simulation time 321416117 ps
CPU time 2.62 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 215612 kb
Host smart-dbd5fc52-7e54-48bc-ae66-896ea0aa7c44
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256214548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.3
256214548
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1034192356
Short name T1019
Test name
Test status
Simulation time 108858561 ps
CPU time 0.76 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:43 PM PDT 24
Peak memory 204168 kb
Host smart-bebc3c98-0d4a-421c-8947-93104a979b5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1034192356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
034192356
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2134023870
Short name T1068
Test name
Test status
Simulation time 757264836 ps
CPU time 4.06 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:46 PM PDT 24
Peak memory 215700 kb
Host smart-200857e8-327b-4540-a410-b059c676348d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2134023870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2134023870
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.381638056
Short name T242
Test name
Test status
Simulation time 39060440 ps
CPU time 2.44 seconds
Started Jul 04 05:07:41 PM PDT 24
Finished Jul 04 05:07:44 PM PDT 24
Peak memory 216024 kb
Host smart-170d4942-44ed-4fad-8125-0172d7ffa71b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=381638056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.381638056
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.1694006861
Short name T249
Test name
Test status
Simulation time 286499336 ps
CPU time 8.09 seconds
Started Jul 04 05:07:42 PM PDT 24
Finished Jul 04 05:07:51 PM PDT 24
Peak memory 216184 kb
Host smart-ab2879bf-8bfb-4bef-89f5-87d693dcf35c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1694006861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.1694006861
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.1195177288
Short name T802
Test name
Test status
Simulation time 50908420 ps
CPU time 0.75 seconds
Started Jul 04 05:12:29 PM PDT 24
Finished Jul 04 05:12:30 PM PDT 24
Peak memory 205800 kb
Host smart-5bb01502-227f-4f68-b27f-bdf61fbb951a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195177288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.1
195177288
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2698034
Short name T468
Test name
Test status
Simulation time 710546990 ps
CPU time 3.36 seconds
Started Jul 04 05:12:24 PM PDT 24
Finished Jul 04 05:12:27 PM PDT 24
Peak memory 224388 kb
Host smart-2a4801fc-66fd-4fff-9be7-dca462694406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2698034
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.3805227677
Short name T661
Test name
Test status
Simulation time 16117266 ps
CPU time 0.8 seconds
Started Jul 04 05:12:19 PM PDT 24
Finished Jul 04 05:12:20 PM PDT 24
Peak memory 205772 kb
Host smart-dd4531b6-4a71-4a1c-ab34-f385d27ec762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805227677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.3805227677
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2640602351
Short name T271
Test name
Test status
Simulation time 5464432640 ps
CPU time 25.46 seconds
Started Jul 04 05:12:26 PM PDT 24
Finished Jul 04 05:12:52 PM PDT 24
Peak memory 249072 kb
Host smart-cc4b68df-f85e-4ec7-b832-f3d9924d717b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640602351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2640602351
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.366756241
Short name T237
Test name
Test status
Simulation time 7820599102 ps
CPU time 118.79 seconds
Started Jul 04 05:12:26 PM PDT 24
Finished Jul 04 05:14:25 PM PDT 24
Peak memory 256780 kb
Host smart-61c93885-58e1-409c-b499-115c74f17843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366756241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.366756241
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2783159112
Short name T27
Test name
Test status
Simulation time 37972667605 ps
CPU time 118.63 seconds
Started Jul 04 05:12:23 PM PDT 24
Finished Jul 04 05:14:22 PM PDT 24
Peak memory 254280 kb
Host smart-1fff5995-8fe4-4136-9026-f1cffa0034bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783159112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2783159112
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.812637305
Short name T618
Test name
Test status
Simulation time 1174925009 ps
CPU time 6.41 seconds
Started Jul 04 05:12:25 PM PDT 24
Finished Jul 04 05:12:32 PM PDT 24
Peak memory 239240 kb
Host smart-6ca198eb-42da-4df5-bada-dfc571cff780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812637305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.812637305
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1347061884
Short name T571
Test name
Test status
Simulation time 474252267 ps
CPU time 7.59 seconds
Started Jul 04 05:12:25 PM PDT 24
Finished Jul 04 05:12:32 PM PDT 24
Peak memory 232660 kb
Host smart-125da4bc-3c92-41ce-bf65-f8f07817ad38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347061884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1347061884
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.421676736
Short name T1
Test name
Test status
Simulation time 373111757 ps
CPU time 3.32 seconds
Started Jul 04 05:12:24 PM PDT 24
Finished Jul 04 05:12:28 PM PDT 24
Peak memory 232612 kb
Host smart-1ba55101-581f-4bce-8a6e-af6bccb07764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421676736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.421676736
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2521307404
Short name T756
Test name
Test status
Simulation time 507518380 ps
CPU time 3.99 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:21 PM PDT 24
Peak memory 232596 kb
Host smart-5275a9eb-219b-4b17-b7f1-ce9567f0ace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521307404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2521307404
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.2876407330
Short name T256
Test name
Test status
Simulation time 82037404905 ps
CPU time 15.3 seconds
Started Jul 04 05:12:18 PM PDT 24
Finished Jul 04 05:12:34 PM PDT 24
Peak memory 232712 kb
Host smart-8f973894-2ad1-4f62-9ecc-13e32e35ef07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876407330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.2876407330
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.2388276530
Short name T487
Test name
Test status
Simulation time 152683457 ps
CPU time 4.05 seconds
Started Jul 04 05:12:29 PM PDT 24
Finished Jul 04 05:12:34 PM PDT 24
Peak memory 219068 kb
Host smart-e4df96eb-9513-419a-82a5-66af1021993a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2388276530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.2388276530
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.3126457054
Short name T523
Test name
Test status
Simulation time 2723774402 ps
CPU time 10.49 seconds
Started Jul 04 05:12:17 PM PDT 24
Finished Jul 04 05:12:28 PM PDT 24
Peak memory 216196 kb
Host smart-aaaa684a-c33d-4fea-a84f-686ca36dd3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3126457054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.3126457054
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.4151064904
Short name T936
Test name
Test status
Simulation time 4195379809 ps
CPU time 7.63 seconds
Started Jul 04 05:12:18 PM PDT 24
Finished Jul 04 05:12:26 PM PDT 24
Peak memory 216272 kb
Host smart-d15c056a-8ec1-47d1-83d4-0e3aae6776bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151064904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.4151064904
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2584897844
Short name T481
Test name
Test status
Simulation time 79677181 ps
CPU time 1.34 seconds
Started Jul 04 05:12:15 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 216032 kb
Host smart-aa98933e-c1a6-4955-91cd-065900da35db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584897844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2584897844
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.4194507008
Short name T526
Test name
Test status
Simulation time 879480463 ps
CPU time 0.98 seconds
Started Jul 04 05:12:16 PM PDT 24
Finished Jul 04 05:12:17 PM PDT 24
Peak memory 206476 kb
Host smart-f885bd85-1eef-48ea-bde6-e7b61d8d69b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194507008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.4194507008
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3079339028
Short name T503
Test name
Test status
Simulation time 11991337394 ps
CPU time 19.54 seconds
Started Jul 04 05:12:24 PM PDT 24
Finished Jul 04 05:12:44 PM PDT 24
Peak memory 237156 kb
Host smart-86fcdc93-86c1-4df2-9b26-c3cbefd6be17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079339028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3079339028
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.2553193262
Short name T314
Test name
Test status
Simulation time 18051902 ps
CPU time 0.69 seconds
Started Jul 04 05:12:25 PM PDT 24
Finished Jul 04 05:12:26 PM PDT 24
Peak memory 205424 kb
Host smart-50aec21a-4fd1-418f-bef0-e920e31b63db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553193262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.2
553193262
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2182832175
Short name T169
Test name
Test status
Simulation time 4485478849 ps
CPU time 21.89 seconds
Started Jul 04 05:12:24 PM PDT 24
Finished Jul 04 05:12:46 PM PDT 24
Peak memory 232720 kb
Host smart-c9ef1b24-98a4-458b-b863-9b1beeb55190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182832175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2182832175
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.2564764640
Short name T421
Test name
Test status
Simulation time 58684096 ps
CPU time 0.8 seconds
Started Jul 04 05:12:26 PM PDT 24
Finished Jul 04 05:12:27 PM PDT 24
Peak memory 206860 kb
Host smart-248b5534-2705-40ac-9022-cfda17ccac57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564764640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.2564764640
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.2983524763
Short name T813
Test name
Test status
Simulation time 9213049581 ps
CPU time 65.87 seconds
Started Jul 04 05:12:25 PM PDT 24
Finished Jul 04 05:13:31 PM PDT 24
Peak memory 251176 kb
Host smart-78b75212-5ee4-4363-83d7-cb96735b35b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983524763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.2983524763
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.1678289527
Short name T590
Test name
Test status
Simulation time 2734065559 ps
CPU time 49.77 seconds
Started Jul 04 05:12:30 PM PDT 24
Finished Jul 04 05:13:20 PM PDT 24
Peak memory 251688 kb
Host smart-73bc5506-ada2-4f79-b421-5b5570c83315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678289527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.1678289527
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3967159342
Short name T125
Test name
Test status
Simulation time 93815906475 ps
CPU time 300.12 seconds
Started Jul 04 05:12:23 PM PDT 24
Finished Jul 04 05:17:23 PM PDT 24
Peak memory 266380 kb
Host smart-414b6c95-6a53-4849-a260-37e0984182aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967159342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3967159342
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.2034277423
Short name T135
Test name
Test status
Simulation time 12195158974 ps
CPU time 52.21 seconds
Started Jul 04 05:12:24 PM PDT 24
Finished Jul 04 05:13:16 PM PDT 24
Peak memory 240908 kb
Host smart-520c0bf1-c7f8-4739-8b09-f78072fcc0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034277423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.2034277423
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.97900787
Short name T191
Test name
Test status
Simulation time 56058631104 ps
CPU time 243.67 seconds
Started Jul 04 05:12:29 PM PDT 24
Finished Jul 04 05:16:33 PM PDT 24
Peak memory 262020 kb
Host smart-b02f50c3-f5a7-401a-a6b7-9ca50c6ee616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97900787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.97900787
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.864091910
Short name T189
Test name
Test status
Simulation time 510334532 ps
CPU time 4.3 seconds
Started Jul 04 05:12:22 PM PDT 24
Finished Jul 04 05:12:26 PM PDT 24
Peak memory 232616 kb
Host smart-b036e2ec-3859-4960-a462-027434f0e5d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864091910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.864091910
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3778902057
Short name T283
Test name
Test status
Simulation time 3375121225 ps
CPU time 23.42 seconds
Started Jul 04 05:12:22 PM PDT 24
Finished Jul 04 05:12:45 PM PDT 24
Peak memory 251152 kb
Host smart-35fa6060-017b-4cfb-b16a-8976d49f5227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3778902057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3778902057
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.3220873414
Short name T270
Test name
Test status
Simulation time 5144954428 ps
CPU time 20.47 seconds
Started Jul 04 05:12:26 PM PDT 24
Finished Jul 04 05:12:46 PM PDT 24
Peak memory 224516 kb
Host smart-1a2071ee-6140-43ce-aa41-744c59f62277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220873414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.3220873414
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.1569810921
Short name T287
Test name
Test status
Simulation time 36657077 ps
CPU time 2.32 seconds
Started Jul 04 05:12:25 PM PDT 24
Finished Jul 04 05:12:27 PM PDT 24
Peak memory 224384 kb
Host smart-ac80d408-6465-4ecb-8b59-b3c0c949c411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569810921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.1569810921
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3582253867
Short name T848
Test name
Test status
Simulation time 6692857341 ps
CPU time 17.67 seconds
Started Jul 04 05:12:24 PM PDT 24
Finished Jul 04 05:12:41 PM PDT 24
Peak memory 221680 kb
Host smart-8191596a-f9b3-42f6-b25f-189019c9a879
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3582253867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3582253867
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.3179490800
Short name T64
Test name
Test status
Simulation time 41060198 ps
CPU time 0.96 seconds
Started Jul 04 05:12:26 PM PDT 24
Finished Jul 04 05:12:27 PM PDT 24
Peak memory 235876 kb
Host smart-08254d65-9031-4f8a-b0b2-fe645517b23d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179490800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.3179490800
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1872906414
Short name T970
Test name
Test status
Simulation time 90563618 ps
CPU time 1.1 seconds
Started Jul 04 05:12:23 PM PDT 24
Finished Jul 04 05:12:25 PM PDT 24
Peak memory 207048 kb
Host smart-7727e62d-513a-486e-9183-9080b635f5d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872906414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1872906414
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3740605196
Short name T413
Test name
Test status
Simulation time 12176262 ps
CPU time 0.75 seconds
Started Jul 04 05:12:26 PM PDT 24
Finished Jul 04 05:12:27 PM PDT 24
Peak memory 205604 kb
Host smart-ab67c3b1-70d5-4d85-b3cf-857a87505c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3740605196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3740605196
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.326758977
Short name T842
Test name
Test status
Simulation time 3233434531 ps
CPU time 6.37 seconds
Started Jul 04 05:12:23 PM PDT 24
Finished Jul 04 05:12:29 PM PDT 24
Peak memory 216288 kb
Host smart-76be9f71-4417-4a0c-b48b-b96bbf06b040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326758977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.326758977
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.1079976004
Short name T355
Test name
Test status
Simulation time 146741521 ps
CPU time 7.16 seconds
Started Jul 04 05:12:25 PM PDT 24
Finished Jul 04 05:12:33 PM PDT 24
Peak memory 216144 kb
Host smart-1c8f7da5-7f03-4a0e-a364-daef1a7f7a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079976004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.1079976004
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.1416513110
Short name T556
Test name
Test status
Simulation time 324340177 ps
CPU time 0.99 seconds
Started Jul 04 05:12:26 PM PDT 24
Finished Jul 04 05:12:27 PM PDT 24
Peak memory 206892 kb
Host smart-1f541ca1-21cf-4e0f-bb36-31c6d5ee108d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416513110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.1416513110
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1045932905
Short name T265
Test name
Test status
Simulation time 12375871046 ps
CPU time 12.39 seconds
Started Jul 04 05:12:28 PM PDT 24
Finished Jul 04 05:12:41 PM PDT 24
Peak memory 232732 kb
Host smart-b71534cb-0952-4bf1-92cf-81c3f03913cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045932905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1045932905
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.792478620
Short name T697
Test name
Test status
Simulation time 102965323 ps
CPU time 0.67 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 204884 kb
Host smart-14d27273-b948-44b4-a9b5-344c32b6bd25
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792478620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.792478620
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.4100714553
Short name T807
Test name
Test status
Simulation time 5026478866 ps
CPU time 9.51 seconds
Started Jul 04 05:13:43 PM PDT 24
Finished Jul 04 05:13:53 PM PDT 24
Peak memory 232680 kb
Host smart-34a98fdb-0e83-4360-8525-5b35316de2c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100714553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.4100714553
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2147237643
Short name T872
Test name
Test status
Simulation time 14465979 ps
CPU time 0.77 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:36 PM PDT 24
Peak memory 205544 kb
Host smart-13dd16a6-c0b7-42d3-be6a-4087dd75d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147237643 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2147237643
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.623339904
Short name T157
Test name
Test status
Simulation time 269751083207 ps
CPU time 278.79 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:18:26 PM PDT 24
Peak memory 265524 kb
Host smart-222b531c-2d41-402f-ab6e-b62eeb2fd0fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=623339904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.623339904
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3691612572
Short name T409
Test name
Test status
Simulation time 3676087102 ps
CPU time 58.3 seconds
Started Jul 04 05:13:45 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 249264 kb
Host smart-ec37fbd3-91dc-4496-ba8f-bddfaaed43f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691612572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3691612572
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3857475868
Short name T704
Test name
Test status
Simulation time 92678761176 ps
CPU time 178.56 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:16:48 PM PDT 24
Peak memory 249576 kb
Host smart-7091f162-0b1d-4975-8b52-7c2c9f29d185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857475868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3857475868
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2412419936
Short name T1003
Test name
Test status
Simulation time 26894400 ps
CPU time 0.78 seconds
Started Jul 04 05:13:45 PM PDT 24
Finished Jul 04 05:13:46 PM PDT 24
Peak memory 215692 kb
Host smart-eaef7f1c-5bd2-40c8-98d4-c7759a24ced3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2412419936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2412419936
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.3902311795
Short name T574
Test name
Test status
Simulation time 299681136 ps
CPU time 4.46 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 232580 kb
Host smart-9c1d5874-7aaf-40f3-8ef5-c6386bbf3c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902311795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.3902311795
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1826654815
Short name T685
Test name
Test status
Simulation time 952969503 ps
CPU time 13.61 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:14:05 PM PDT 24
Peak memory 240852 kb
Host smart-63200228-4d16-4a7b-8ba1-f270ffbafd8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1826654815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1826654815
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2958338118
Short name T520
Test name
Test status
Simulation time 2615173932 ps
CPU time 13.15 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:14:01 PM PDT 24
Peak memory 232560 kb
Host smart-253272cd-313a-4bdc-bd87-ca2d688865e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958338118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2958338118
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2702131266
Short name T600
Test name
Test status
Simulation time 237397131 ps
CPU time 2.5 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 224448 kb
Host smart-f396c445-1460-4826-a8d1-b01295f4f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702131266 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2702131266
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1709073928
Short name T939
Test name
Test status
Simulation time 2618845416 ps
CPU time 6.1 seconds
Started Jul 04 05:13:45 PM PDT 24
Finished Jul 04 05:13:51 PM PDT 24
Peak memory 223168 kb
Host smart-491c15c3-316e-41bb-9e7a-8f0f686b860a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1709073928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1709073928
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1934970281
Short name T304
Test name
Test status
Simulation time 6882773452 ps
CPU time 37.44 seconds
Started Jul 04 05:13:43 PM PDT 24
Finished Jul 04 05:14:21 PM PDT 24
Peak memory 216248 kb
Host smart-5fb1e899-c1b7-4c58-a337-eda9ef3e6eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934970281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1934970281
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1495659112
Short name T502
Test name
Test status
Simulation time 4324970773 ps
CPU time 14.2 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:08 PM PDT 24
Peak memory 216220 kb
Host smart-a6908f4f-9118-4558-b3e9-f5765c8b7000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495659112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1495659112
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.469954411
Short name T612
Test name
Test status
Simulation time 250086129 ps
CPU time 6.18 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 216208 kb
Host smart-9183cb2a-27ae-4ede-8a02-83f5cef9381e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469954411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.469954411
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.1271094043
Short name T960
Test name
Test status
Simulation time 175595935 ps
CPU time 0.78 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 205936 kb
Host smart-4311a0fd-9fcb-448a-9087-78a1f62e61f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271094043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.1271094043
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1323193328
Short name T711
Test name
Test status
Simulation time 604013531 ps
CPU time 4.46 seconds
Started Jul 04 05:13:45 PM PDT 24
Finished Jul 04 05:13:50 PM PDT 24
Peak memory 224488 kb
Host smart-eae0edcb-f462-49f0-8484-ad1fa90ebfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323193328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1323193328
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.1260490339
Short name T643
Test name
Test status
Simulation time 21018522 ps
CPU time 0.74 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 205760 kb
Host smart-c98afcd9-7690-4ae7-aef9-8d7d006a509d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260490339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
1260490339
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1705843559
Short name T742
Test name
Test status
Simulation time 216619075 ps
CPU time 2.71 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:53 PM PDT 24
Peak memory 224392 kb
Host smart-abc000f4-9eef-4fa3-8c82-c1a02311056b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1705843559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1705843559
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3528744176
Short name T362
Test name
Test status
Simulation time 41098294 ps
CPU time 0.78 seconds
Started Jul 04 05:13:44 PM PDT 24
Finished Jul 04 05:13:45 PM PDT 24
Peak memory 205808 kb
Host smart-c57f4414-2fbb-46f8-a3c3-70630278b67c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528744176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3528744176
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3968859052
Short name T864
Test name
Test status
Simulation time 19289522120 ps
CPU time 127.18 seconds
Started Jul 04 05:13:45 PM PDT 24
Finished Jul 04 05:15:53 PM PDT 24
Peak memory 257272 kb
Host smart-76389574-744b-4b45-aacf-abb29453f70c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968859052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3968859052
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.240949177
Short name T297
Test name
Test status
Simulation time 396137758 ps
CPU time 7.08 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:59 PM PDT 24
Peak memory 232624 kb
Host smart-9bd9c7b7-5665-406c-824c-c55508e15ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240949177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.240949177
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.2505254676
Short name T214
Test name
Test status
Simulation time 3649630517 ps
CPU time 50.47 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:43 PM PDT 24
Peak memory 251884 kb
Host smart-9aade727-f5bc-46fb-9fc4-6ff06ae485cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505254676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.2505254676
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.3343681011
Short name T778
Test name
Test status
Simulation time 4414008963 ps
CPU time 8.52 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 227264 kb
Host smart-6ac0b266-65d2-478c-a399-4947f8022de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343681011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.3343681011
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.781285979
Short name T806
Test name
Test status
Simulation time 843033994 ps
CPU time 8.78 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:59 PM PDT 24
Peak memory 224384 kb
Host smart-d8d0a8d1-5c28-476c-854a-b6e0c0ab8fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781285979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.781285979
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1518034874
Short name T236
Test name
Test status
Simulation time 9857564040 ps
CPU time 28.89 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:14:19 PM PDT 24
Peak memory 232684 kb
Host smart-73d88f53-8811-4e5e-be02-97b17faa5e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518034874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1518034874
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2621679840
Short name T48
Test name
Test status
Simulation time 12864276221 ps
CPU time 9.05 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:13:59 PM PDT 24
Peak memory 232772 kb
Host smart-c7885d01-365b-4b2d-88d3-c2f3dc5c52d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621679840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2621679840
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.2390867021
Short name T133
Test name
Test status
Simulation time 4285447165 ps
CPU time 19.48 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:14:11 PM PDT 24
Peak memory 219428 kb
Host smart-6a9d6971-fec4-4f00-8ba2-ca73a30fc3ff
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2390867021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.2390867021
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.2247195847
Short name T797
Test name
Test status
Simulation time 4184291531 ps
CPU time 30.26 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:14:16 PM PDT 24
Peak memory 218420 kb
Host smart-8de701c1-0480-46c9-af82-095d21586603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247195847 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.2247195847
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.3423476211
Short name T729
Test name
Test status
Simulation time 1081183353 ps
CPU time 7.72 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:55 PM PDT 24
Peak memory 216208 kb
Host smart-4244461f-d80e-4edc-99a0-5546b8544fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423476211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.3423476211
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.4159279606
Short name T911
Test name
Test status
Simulation time 160734455 ps
CPU time 1.21 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 216172 kb
Host smart-96770433-cbed-4bab-829e-c7d60d9b59fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159279606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.4159279606
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.4271629752
Short name T651
Test name
Test status
Simulation time 81630856 ps
CPU time 0.87 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:50 PM PDT 24
Peak memory 205940 kb
Host smart-d14501af-5a51-4eb0-8168-65a82a79a382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271629752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.4271629752
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.695301458
Short name T720
Test name
Test status
Simulation time 18458393690 ps
CPU time 14.83 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:14:05 PM PDT 24
Peak memory 224512 kb
Host smart-0d30d9de-0b60-4b12-a6dc-0cca4cc49e7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695301458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.695301458
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.2200577806
Short name T941
Test name
Test status
Simulation time 33361853936 ps
CPU time 22.9 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:17 PM PDT 24
Peak memory 224572 kb
Host smart-f7f59f48-9302-454b-a2c5-7d2ed0005fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200577806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.2200577806
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2073300990
Short name T784
Test name
Test status
Simulation time 16130785 ps
CPU time 0.74 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 206556 kb
Host smart-73aa7d4b-899b-4229-95be-5029ac8ddca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073300990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2073300990
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2495945097
Short name T688
Test name
Test status
Simulation time 2020060196 ps
CPU time 9.34 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 240816 kb
Host smart-2c0f786f-4109-410e-bcc9-ae6f53b56f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495945097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2495945097
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1862653877
Short name T615
Test name
Test status
Simulation time 27069401211 ps
CPU time 267.02 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:18:21 PM PDT 24
Peak memory 250232 kb
Host smart-4df4e095-49e7-4069-b611-62ceef9696b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862653877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1862653877
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3763004801
Short name T540
Test name
Test status
Simulation time 1297644411 ps
CPU time 7.04 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:00 PM PDT 24
Peak memory 232648 kb
Host smart-1d747f45-d161-4ebc-b720-a19ab8f63088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763004801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3763004801
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.466093752
Short name T318
Test name
Test status
Simulation time 2718995030 ps
CPU time 9.09 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:03 PM PDT 24
Peak memory 234816 kb
Host smart-1a5746c0-a64a-4cdd-89c3-841ad066f39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466093752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.466093752
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.1159956988
Short name T358
Test name
Test status
Simulation time 1594452197 ps
CPU time 7.82 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:59 PM PDT 24
Peak memory 232616 kb
Host smart-cf985f99-ef23-4225-ba1f-21eda1b684a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159956988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.1159956988
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.149382426
Short name T549
Test name
Test status
Simulation time 37581640 ps
CPU time 2.49 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 232344 kb
Host smart-fe473e11-6d88-4d6e-bbab-2c92b7cad348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=149382426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.149382426
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.856229093
Short name T385
Test name
Test status
Simulation time 194214407 ps
CPU time 2.71 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 232632 kb
Host smart-4fba74b6-ce7c-473d-b8a8-251751b2b9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856229093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.856229093
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.3278073171
Short name T944
Test name
Test status
Simulation time 21764938419 ps
CPU time 18.24 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:14:06 PM PDT 24
Peak memory 224564 kb
Host smart-093611ef-13f8-4df8-b0f3-e41ca53ead34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278073171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.3278073171
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.102497155
Short name T132
Test name
Test status
Simulation time 3670730184 ps
CPU time 7.36 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:01 PM PDT 24
Peak memory 223032 kb
Host smart-1552bac8-42d0-4beb-92ed-04553a3186f6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=102497155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dire
ct.102497155
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3024297620
Short name T544
Test name
Test status
Simulation time 49335707 ps
CPU time 1.09 seconds
Started Jul 04 05:13:54 PM PDT 24
Finished Jul 04 05:13:56 PM PDT 24
Peak memory 207532 kb
Host smart-bd8b8c87-c5fe-4f66-86cc-27ab7d9370cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024297620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3024297620
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3113320597
Short name T427
Test name
Test status
Simulation time 11791980080 ps
CPU time 41.53 seconds
Started Jul 04 05:13:52 PM PDT 24
Finished Jul 04 05:14:36 PM PDT 24
Peak memory 216264 kb
Host smart-735961b4-6ce1-4fff-b0ee-6b4c2eed61ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113320597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3113320597
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.1691152117
Short name T689
Test name
Test status
Simulation time 1290046050 ps
CPU time 3.85 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:56 PM PDT 24
Peak memory 216128 kb
Host smart-e4fddb46-56c3-4e15-aa9e-5be4fa8feed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691152117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.1691152117
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1259386459
Short name T857
Test name
Test status
Simulation time 88717448 ps
CPU time 1.73 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:51 PM PDT 24
Peak memory 216192 kb
Host smart-d0acfd9e-581d-4301-b046-1ed2ad0db55b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259386459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1259386459
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.1631002260
Short name T968
Test name
Test status
Simulation time 91770050 ps
CPU time 0.78 seconds
Started Jul 04 05:13:46 PM PDT 24
Finished Jul 04 05:13:48 PM PDT 24
Peak memory 205896 kb
Host smart-07fcc1d1-3edc-445d-82e0-64cb83c40094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631002260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.1631002260
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.2517582488
Short name T365
Test name
Test status
Simulation time 104263214 ps
CPU time 2.45 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 232260 kb
Host smart-b68a8d13-e99c-4794-bb83-16443d27006b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517582488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.2517582488
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.742985295
Short name T577
Test name
Test status
Simulation time 42526064 ps
CPU time 0.71 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 205408 kb
Host smart-d825aa10-b565-4c38-9a06-a60562e3af70
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=742985295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.742985295
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1949088068
Short name T411
Test name
Test status
Simulation time 436583540 ps
CPU time 2.38 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:13:56 PM PDT 24
Peak memory 224416 kb
Host smart-e0b33a67-cd14-4c89-a401-a9c201dad890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949088068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1949088068
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.534133034
Short name T451
Test name
Test status
Simulation time 43768098 ps
CPU time 0.8 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 206568 kb
Host smart-9700e5f2-08cb-4c5d-bc5e-b3887d325e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534133034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.534133034
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.2087467630
Short name T184
Test name
Test status
Simulation time 11942666811 ps
CPU time 153.42 seconds
Started Jul 04 05:13:57 PM PDT 24
Finished Jul 04 05:16:30 PM PDT 24
Peak memory 265400 kb
Host smart-d7046102-aafa-4e66-9ba0-6754912da3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087467630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.2087467630
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3266306122
Short name T562
Test name
Test status
Simulation time 1646537920 ps
CPU time 28.56 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:14:27 PM PDT 24
Peak memory 224460 kb
Host smart-f12d320b-2aa3-43ab-960f-633cdd05c6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266306122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3266306122
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1217851457
Short name T296
Test name
Test status
Simulation time 1993879264 ps
CPU time 29.41 seconds
Started Jul 04 05:14:06 PM PDT 24
Finished Jul 04 05:14:35 PM PDT 24
Peak memory 224400 kb
Host smart-bace9617-cbbe-4bf6-b96b-ff77a6f28f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217851457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1217851457
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1819873491
Short name T216
Test name
Test status
Simulation time 40558990478 ps
CPU time 297.95 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:18:48 PM PDT 24
Peak memory 251348 kb
Host smart-1f4232cc-63c6-4b05-bb35-7c94d9dd4eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819873491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1819873491
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3206570437
Short name T794
Test name
Test status
Simulation time 3753098305 ps
CPU time 21.41 seconds
Started Jul 04 05:13:54 PM PDT 24
Finished Jul 04 05:14:16 PM PDT 24
Peak memory 224472 kb
Host smart-ad77e637-6d90-4113-a9dc-2240763ca216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3206570437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3206570437
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.1011013859
Short name T683
Test name
Test status
Simulation time 125213987 ps
CPU time 2.5 seconds
Started Jul 04 05:13:57 PM PDT 24
Finished Jul 04 05:14:00 PM PDT 24
Peak memory 232228 kb
Host smart-ba8ed887-bbfd-4e3a-97c3-c79402d288e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011013859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.1011013859
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.3418236313
Short name T954
Test name
Test status
Simulation time 7947093124 ps
CPU time 21.28 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:15 PM PDT 24
Peak memory 232652 kb
Host smart-481103a9-74e7-42b9-8bb8-43339ea1bc6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418236313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.3418236313
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.1328012302
Short name T987
Test name
Test status
Simulation time 6886301102 ps
CPU time 26.88 seconds
Started Jul 04 05:13:53 PM PDT 24
Finished Jul 04 05:14:21 PM PDT 24
Peak memory 224488 kb
Host smart-772765a0-fb94-4b47-9dff-1d103b532c40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328012302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.1328012302
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.4036356130
Short name T134
Test name
Test status
Simulation time 1128094388 ps
CPU time 8.76 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:02 PM PDT 24
Peak memory 221972 kb
Host smart-8f3da0f2-64bb-42f6-81ec-7f828da951b0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4036356130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.4036356130
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.2127789106
Short name T1007
Test name
Test status
Simulation time 3985496200 ps
CPU time 4.81 seconds
Started Jul 04 05:13:48 PM PDT 24
Finished Jul 04 05:13:54 PM PDT 24
Peak memory 216304 kb
Host smart-765f79ad-1dca-41bf-9878-5657a090a935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127789106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.2127789106
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3272757137
Short name T410
Test name
Test status
Simulation time 1260494439 ps
CPU time 7.44 seconds
Started Jul 04 05:13:54 PM PDT 24
Finished Jul 04 05:14:02 PM PDT 24
Peak memory 216108 kb
Host smart-92010893-901b-4f06-91e2-1db959a25dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272757137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3272757137
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2351205896
Short name T715
Test name
Test status
Simulation time 26525376 ps
CPU time 0.83 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 206580 kb
Host smart-fe4f125c-c632-46db-a4f7-5ca14f3781cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351205896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2351205896
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.2278477303
Short name T695
Test name
Test status
Simulation time 229682973 ps
CPU time 1.01 seconds
Started Jul 04 05:13:47 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 206960 kb
Host smart-97aef292-3f36-46f0-b18f-90e5acf396f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278477303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.2278477303
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.2664703493
Short name T635
Test name
Test status
Simulation time 2858698420 ps
CPU time 11.85 seconds
Started Jul 04 05:13:49 PM PDT 24
Finished Jul 04 05:14:02 PM PDT 24
Peak memory 224460 kb
Host smart-96ec783e-f760-44ca-9004-ab1f2f571826
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664703493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.2664703493
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.1381669377
Short name T586
Test name
Test status
Simulation time 22434876 ps
CPU time 0.71 seconds
Started Jul 04 05:14:05 PM PDT 24
Finished Jul 04 05:14:06 PM PDT 24
Peak memory 204936 kb
Host smart-326261fa-d13f-4408-bdd6-062c2f3bc7c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381669377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
1381669377
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.1070353422
Short name T973
Test name
Test status
Simulation time 80029784 ps
CPU time 3.59 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:14:02 PM PDT 24
Peak memory 232568 kb
Host smart-e0d9f2ec-7772-4e02-b1b2-11772c3b04be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070353422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.1070353422
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.4255012
Short name T457
Test name
Test status
Simulation time 46038574 ps
CPU time 0.75 seconds
Started Jul 04 05:14:06 PM PDT 24
Finished Jul 04 05:14:07 PM PDT 24
Peak memory 205536 kb
Host smart-dd8fba29-e29d-437a-bb8d-1128b81bf7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.4255012
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2620055990
Short name T168
Test name
Test status
Simulation time 14864741684 ps
CPU time 124.21 seconds
Started Jul 04 05:14:09 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 254904 kb
Host smart-a692795d-4e37-4816-8169-2d0ed265c960
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620055990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2620055990
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2741423871
Short name T179
Test name
Test status
Simulation time 81480043675 ps
CPU time 274.69 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:18:27 PM PDT 24
Peak memory 253528 kb
Host smart-e1286b45-1642-4f1f-a595-153dddf1b9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741423871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2741423871
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.124310520
Short name T953
Test name
Test status
Simulation time 3016062463 ps
CPU time 71.24 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:15:09 PM PDT 24
Peak memory 249424 kb
Host smart-3f3e0590-e2ed-4a1a-8907-cbd2171fb29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124310520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle
.124310520
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.2374139899
Short name T555
Test name
Test status
Simulation time 1826863644 ps
CPU time 28.19 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:14:26 PM PDT 24
Peak memory 233652 kb
Host smart-a40012af-7ddb-432e-a1af-b3a070edb49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374139899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.2374139899
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3079872490
Short name T999
Test name
Test status
Simulation time 36068291877 ps
CPU time 26.18 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:14:25 PM PDT 24
Peak memory 224472 kb
Host smart-a4f1b002-63bc-421a-bef3-bb8534895ec4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079872490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3079872490
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3741389583
Short name T267
Test name
Test status
Simulation time 834890896 ps
CPU time 7.2 seconds
Started Jul 04 05:13:51 PM PDT 24
Finished Jul 04 05:14:01 PM PDT 24
Peak memory 224396 kb
Host smart-6040e25f-4167-415e-b8f8-0a4e3bfcabe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741389583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3741389583
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.2391808069
Short name T755
Test name
Test status
Simulation time 201627555 ps
CPU time 2.93 seconds
Started Jul 04 05:13:53 PM PDT 24
Finished Jul 04 05:13:57 PM PDT 24
Peak memory 232616 kb
Host smart-edbf3cff-bf66-4d6c-a968-c6256bd31b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391808069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.2391808069
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1397827192
Short name T993
Test name
Test status
Simulation time 2157561913 ps
CPU time 9.33 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:14:01 PM PDT 24
Peak memory 232640 kb
Host smart-5c39666b-1918-4de9-90ad-ea16be1d4f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397827192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1397827192
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.2379871028
Short name T753
Test name
Test status
Simulation time 173821174 ps
CPU time 4.59 seconds
Started Jul 04 05:13:56 PM PDT 24
Finished Jul 04 05:14:01 PM PDT 24
Peak memory 222948 kb
Host smart-4d8cf458-2182-4fa7-be9f-59e4dbdf4f6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2379871028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.2379871028
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1453541204
Short name T885
Test name
Test status
Simulation time 44698188015 ps
CPU time 425.98 seconds
Started Jul 04 05:14:08 PM PDT 24
Finished Jul 04 05:21:15 PM PDT 24
Peak memory 255488 kb
Host smart-f280f339-ddf1-4a35-8e4d-46e853f4aa1c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453541204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1453541204
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.4001358843
Short name T799
Test name
Test status
Simulation time 2597875682 ps
CPU time 15.56 seconds
Started Jul 04 05:14:06 PM PDT 24
Finished Jul 04 05:14:21 PM PDT 24
Peak memory 216292 kb
Host smart-4ea8f489-f7f1-48b2-8682-d20cc26af018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001358843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.4001358843
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2417462210
Short name T619
Test name
Test status
Simulation time 3154715934 ps
CPU time 11.77 seconds
Started Jul 04 05:13:59 PM PDT 24
Finished Jul 04 05:14:11 PM PDT 24
Peak memory 216212 kb
Host smart-f2e87d7d-0bf9-45f0-a00e-d18aecdc6f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417462210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2417462210
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.175007283
Short name T546
Test name
Test status
Simulation time 55460002 ps
CPU time 0.98 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 207840 kb
Host smart-1ea87e83-bf51-4722-a554-8ee3c7c24f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175007283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.175007283
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3375540893
Short name T564
Test name
Test status
Simulation time 124104438 ps
CPU time 0.82 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:13:59 PM PDT 24
Peak memory 205916 kb
Host smart-579c5147-f0ac-4b5a-82f9-e8cbd01a1210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375540893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3375540893
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3607181494
Short name T524
Test name
Test status
Simulation time 2655930225 ps
CPU time 4.89 seconds
Started Jul 04 05:13:50 PM PDT 24
Finished Jul 04 05:13:57 PM PDT 24
Peak memory 236256 kb
Host smart-1cf1a6ae-96e1-423b-860a-d7b695721284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607181494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3607181494
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.1333126245
Short name T588
Test name
Test status
Simulation time 41075665 ps
CPU time 0.73 seconds
Started Jul 04 05:14:18 PM PDT 24
Finished Jul 04 05:14:19 PM PDT 24
Peak memory 204844 kb
Host smart-8ab271a1-9553-4719-a356-5e9ee515d08f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333126245 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
1333126245
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2040962065
Short name T165
Test name
Test status
Simulation time 644049101 ps
CPU time 5.99 seconds
Started Jul 04 05:14:09 PM PDT 24
Finished Jul 04 05:14:15 PM PDT 24
Peak memory 233680 kb
Host smart-e331a051-e67c-42ab-983b-096afef17bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040962065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2040962065
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2521664351
Short name T388
Test name
Test status
Simulation time 22442733 ps
CPU time 0.8 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:13:59 PM PDT 24
Peak memory 206568 kb
Host smart-bf942b61-89fa-40b9-8003-218a2c08ec9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2521664351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2521664351
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.3264016506
Short name T800
Test name
Test status
Simulation time 9576583705 ps
CPU time 65.92 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:15:23 PM PDT 24
Peak memory 257180 kb
Host smart-4f085a37-672a-4972-ad88-eaafe98a3eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264016506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.3264016506
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.521727698
Short name T650
Test name
Test status
Simulation time 2176197413 ps
CPU time 10.04 seconds
Started Jul 04 05:14:19 PM PDT 24
Finished Jul 04 05:14:29 PM PDT 24
Peak memory 217396 kb
Host smart-cd1007b8-7ee2-4029-80e0-fb4d25feb938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=521727698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.521727698
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3713292225
Short name T415
Test name
Test status
Simulation time 6440172711 ps
CPU time 8.13 seconds
Started Jul 04 05:14:14 PM PDT 24
Finished Jul 04 05:14:23 PM PDT 24
Peak memory 224548 kb
Host smart-0cc627f9-9380-470d-8e5c-d2169b3630c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713292225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3713292225
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.3823545794
Short name T232
Test name
Test status
Simulation time 92044061123 ps
CPU time 151.66 seconds
Started Jul 04 05:14:11 PM PDT 24
Finished Jul 04 05:16:43 PM PDT 24
Peak memory 250960 kb
Host smart-ddb3deac-f96c-4959-bfdd-9948d86b42d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823545794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.3823545794
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3359055116
Short name T890
Test name
Test status
Simulation time 116747731 ps
CPU time 2.24 seconds
Started Jul 04 05:14:11 PM PDT 24
Finished Jul 04 05:14:14 PM PDT 24
Peak memory 232240 kb
Host smart-8cdb136b-b50c-4fa9-a269-d1def38e2d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359055116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3359055116
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2088681447
Short name T603
Test name
Test status
Simulation time 2824932884 ps
CPU time 17.88 seconds
Started Jul 04 05:14:10 PM PDT 24
Finished Jul 04 05:14:28 PM PDT 24
Peak memory 240540 kb
Host smart-b4c9a493-48a1-4b95-8af6-9250f92dad12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088681447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2088681447
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1476864392
Short name T163
Test name
Test status
Simulation time 3589267341 ps
CPU time 8.73 seconds
Started Jul 04 05:14:04 PM PDT 24
Finished Jul 04 05:14:13 PM PDT 24
Peak memory 232760 kb
Host smart-9f22cd9a-d8c5-4fbc-86f8-c67f8d77f62e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476864392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1476864392
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.2146722741
Short name T154
Test name
Test status
Simulation time 255117396 ps
CPU time 3.4 seconds
Started Jul 04 05:14:08 PM PDT 24
Finished Jul 04 05:14:12 PM PDT 24
Peak memory 224320 kb
Host smart-4efd272e-2441-43fa-9982-22b9cceabead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146722741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.2146722741
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.4164855036
Short name T733
Test name
Test status
Simulation time 1890647418 ps
CPU time 5.79 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:23 PM PDT 24
Peak memory 218976 kb
Host smart-74315972-91a7-49e4-be68-b3f3b405515f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4164855036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.4164855036
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.3124315354
Short name T378
Test name
Test status
Simulation time 6992933437 ps
CPU time 61.51 seconds
Started Jul 04 05:14:20 PM PDT 24
Finished Jul 04 05:15:22 PM PDT 24
Peak memory 241016 kb
Host smart-31c995eb-5abc-4d64-a10c-7920e2714a55
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124315354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.3124315354
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3240345109
Short name T548
Test name
Test status
Simulation time 16644324204 ps
CPU time 19.46 seconds
Started Jul 04 05:13:58 PM PDT 24
Finished Jul 04 05:14:18 PM PDT 24
Peak memory 216228 kb
Host smart-c2f14737-1bb9-4a46-93ea-d5978c128b45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240345109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3240345109
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3937745659
Short name T313
Test name
Test status
Simulation time 29903608 ps
CPU time 0.79 seconds
Started Jul 04 05:14:04 PM PDT 24
Finished Jul 04 05:14:05 PM PDT 24
Peak memory 205872 kb
Host smart-55eca543-5d75-43fb-81ba-af8922a98393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937745659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3937745659
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.3690779315
Short name T375
Test name
Test status
Simulation time 98571445 ps
CPU time 0.92 seconds
Started Jul 04 05:14:02 PM PDT 24
Finished Jul 04 05:14:03 PM PDT 24
Peak memory 205952 kb
Host smart-5f64cfc0-6db2-4882-b45a-5cd93268a622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3690779315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.3690779315
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1039980975
Short name T945
Test name
Test status
Simulation time 3661419886 ps
CPU time 13.74 seconds
Started Jul 04 05:14:11 PM PDT 24
Finished Jul 04 05:14:25 PM PDT 24
Peak memory 224464 kb
Host smart-e30c4d8f-4e23-4a46-ac50-4b295c75ede4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039980975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1039980975
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2673159650
Short name T338
Test name
Test status
Simulation time 20588685 ps
CPU time 0.75 seconds
Started Jul 04 05:14:26 PM PDT 24
Finished Jul 04 05:14:27 PM PDT 24
Peak memory 204872 kb
Host smart-2078d585-4623-457d-9183-05e8b5293dc9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673159650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2673159650
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1047077138
Short name T66
Test name
Test status
Simulation time 139974381 ps
CPU time 2.73 seconds
Started Jul 04 05:14:24 PM PDT 24
Finished Jul 04 05:14:27 PM PDT 24
Peak memory 224464 kb
Host smart-c06a6b31-08b9-48b5-bc1b-0ef99859e9af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047077138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1047077138
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.3269856485
Short name T315
Test name
Test status
Simulation time 15136423 ps
CPU time 0.78 seconds
Started Jul 04 05:14:16 PM PDT 24
Finished Jul 04 05:14:17 PM PDT 24
Peak memory 206832 kb
Host smart-c2f9d8dd-8ef2-4e2f-b106-7534bfe2166a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269856485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.3269856485
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.803001108
Short name T942
Test name
Test status
Simulation time 11123326034 ps
CPU time 76.13 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 262144 kb
Host smart-94672b69-1399-469b-8c4e-a5f059e99477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803001108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.803001108
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3542129857
Short name T511
Test name
Test status
Simulation time 15370463013 ps
CPU time 52.36 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:15:18 PM PDT 24
Peak memory 235120 kb
Host smart-b49878a2-1364-41f9-8d88-c45a0c0bd25f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542129857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3542129857
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.1575185792
Short name T833
Test name
Test status
Simulation time 1731757175 ps
CPU time 9.59 seconds
Started Jul 04 05:14:25 PM PDT 24
Finished Jul 04 05:14:35 PM PDT 24
Peak memory 240688 kb
Host smart-c7844906-4394-4520-9da6-d8786c56283b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575185792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.1575185792
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.3970988629
Short name T218
Test name
Test status
Simulation time 78511209737 ps
CPU time 74.4 seconds
Started Jul 04 05:14:26 PM PDT 24
Finished Jul 04 05:15:41 PM PDT 24
Peak memory 257312 kb
Host smart-a1e23f65-5ca1-4b0d-9b6d-0a6822fda9d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970988629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.3970988629
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1766398631
Short name T176
Test name
Test status
Simulation time 1943165643 ps
CPU time 13.14 seconds
Started Jul 04 05:14:16 PM PDT 24
Finished Jul 04 05:14:30 PM PDT 24
Peak memory 232556 kb
Host smart-32242d1e-1eec-47d8-8774-0167bf3a2708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766398631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1766398631
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.4059344592
Short name T175
Test name
Test status
Simulation time 7488238026 ps
CPU time 22.42 seconds
Started Jul 04 05:14:23 PM PDT 24
Finished Jul 04 05:14:46 PM PDT 24
Peak memory 224572 kb
Host smart-d50992f7-63b8-48f8-b68f-7f30e2ff2958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059344592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.4059344592
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.873769735
Short name T373
Test name
Test status
Simulation time 536928005 ps
CPU time 2.54 seconds
Started Jul 04 05:14:19 PM PDT 24
Finished Jul 04 05:14:22 PM PDT 24
Peak memory 224376 kb
Host smart-78fa68b5-ac7b-4992-adcc-649503113007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873769735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swap
.873769735
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3996881558
Short name T839
Test name
Test status
Simulation time 127138847 ps
CPU time 3.14 seconds
Started Jul 04 05:14:19 PM PDT 24
Finished Jul 04 05:14:22 PM PDT 24
Peak memory 232536 kb
Host smart-808509f3-c00e-43fa-9910-a8a2f74eba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996881558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3996881558
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1692003635
Short name T900
Test name
Test status
Simulation time 156660694 ps
CPU time 3.14 seconds
Started Jul 04 05:14:24 PM PDT 24
Finished Jul 04 05:14:28 PM PDT 24
Peak memory 219120 kb
Host smart-43f5a4ce-5f6c-436c-8ee9-c97e8e081803
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1692003635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1692003635
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.4235758718
Short name T19
Test name
Test status
Simulation time 3245409157 ps
CPU time 39.23 seconds
Started Jul 04 05:14:27 PM PDT 24
Finished Jul 04 05:15:06 PM PDT 24
Peak memory 234640 kb
Host smart-d56cc7d2-f9b1-4942-abb2-f96d0c12c541
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235758718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.4235758718
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.3168223138
Short name T757
Test name
Test status
Simulation time 197436470 ps
CPU time 2.85 seconds
Started Jul 04 05:14:20 PM PDT 24
Finished Jul 04 05:14:23 PM PDT 24
Peak memory 216380 kb
Host smart-2306430e-cf47-434c-98c5-265bf878d42a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3168223138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.3168223138
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1523008990
Short name T699
Test name
Test status
Simulation time 41377869 ps
CPU time 0.71 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:18 PM PDT 24
Peak memory 205652 kb
Host smart-1f234a88-1f65-46d2-880d-89aa70ee5304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523008990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1523008990
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.178350475
Short name T343
Test name
Test status
Simulation time 327487627 ps
CPU time 1.03 seconds
Started Jul 04 05:14:18 PM PDT 24
Finished Jul 04 05:14:19 PM PDT 24
Peak memory 207828 kb
Host smart-9049be70-1a81-4000-b282-b64ed7390083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178350475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.178350475
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3764905035
Short name T76
Test name
Test status
Simulation time 149217897 ps
CPU time 0.88 seconds
Started Jul 04 05:14:17 PM PDT 24
Finished Jul 04 05:14:18 PM PDT 24
Peak memory 205936 kb
Host smart-c89ba9fb-79e7-499c-b539-21875a9325ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764905035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3764905035
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1315395040
Short name T786
Test name
Test status
Simulation time 2535603674 ps
CPU time 7.4 seconds
Started Jul 04 05:14:27 PM PDT 24
Finished Jul 04 05:14:35 PM PDT 24
Peak memory 224572 kb
Host smart-d1d97f02-a9ab-4113-817b-02d882568e5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315395040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1315395040
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.4020038775
Short name T589
Test name
Test status
Simulation time 12618635 ps
CPU time 0.71 seconds
Started Jul 04 05:14:34 PM PDT 24
Finished Jul 04 05:14:35 PM PDT 24
Peak memory 204876 kb
Host smart-dd016d26-c2d0-4c73-b9da-c70c18e8862e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020038775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
4020038775
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.125270540
Short name T516
Test name
Test status
Simulation time 1407952818 ps
CPU time 3.28 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:14:37 PM PDT 24
Peak memory 224460 kb
Host smart-1cb45c54-8ea9-4ca3-a8f9-fe6d4e367823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125270540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.125270540
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.3430471332
Short name T644
Test name
Test status
Simulation time 23185930 ps
CPU time 0.72 seconds
Started Jul 04 05:14:24 PM PDT 24
Finished Jul 04 05:14:25 PM PDT 24
Peak memory 205504 kb
Host smart-f653a469-34f5-40a4-9b8e-d1275bfdc35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430471332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.3430471332
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.2029078391
Short name T213
Test name
Test status
Simulation time 10189741746 ps
CPU time 93.41 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:16:09 PM PDT 24
Peak memory 252236 kb
Host smart-9fb84fb2-bbfd-4d24-897b-9bd4177d192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029078391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.2029078391
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.257373741
Short name T268
Test name
Test status
Simulation time 3669856081 ps
CPU time 27.18 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:15:08 PM PDT 24
Peak memory 248776 kb
Host smart-9a7ecb3f-e117-4a84-9786-cefb02d47a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257373741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.257373741
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3580978754
Short name T622
Test name
Test status
Simulation time 532826520 ps
CPU time 7.69 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:43 PM PDT 24
Peak memory 240752 kb
Host smart-255edd52-8adc-44b3-9f2d-2288870d8958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580978754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3580978754
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.1442707470
Short name T522
Test name
Test status
Simulation time 34975650 ps
CPU time 0.77 seconds
Started Jul 04 05:14:37 PM PDT 24
Finished Jul 04 05:14:38 PM PDT 24
Peak memory 215720 kb
Host smart-52055d78-506d-4a16-aa7c-b138c69dc7e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1442707470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.1442707470
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2489792561
Short name T183
Test name
Test status
Simulation time 16599759968 ps
CPU time 16.51 seconds
Started Jul 04 05:14:37 PM PDT 24
Finished Jul 04 05:14:54 PM PDT 24
Peak memory 232764 kb
Host smart-ef3656ee-6fd3-487f-8545-70de440465f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2489792561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2489792561
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3262510798
Short name T751
Test name
Test status
Simulation time 7185533343 ps
CPU time 22.14 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:14:56 PM PDT 24
Peak memory 249116 kb
Host smart-307f604f-f5fd-4e1d-bb42-1f1043358cbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262510798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3262510798
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.2245887416
Short name T171
Test name
Test status
Simulation time 2406772212 ps
CPU time 8.34 seconds
Started Jul 04 05:14:39 PM PDT 24
Finished Jul 04 05:14:47 PM PDT 24
Peak memory 232768 kb
Host smart-b355e2ac-f56a-4c8e-9241-a63885bb42d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245887416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.2245887416
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2980029214
Short name T915
Test name
Test status
Simulation time 2353927636 ps
CPU time 4.99 seconds
Started Jul 04 05:14:34 PM PDT 24
Finished Jul 04 05:14:39 PM PDT 24
Peak memory 224568 kb
Host smart-8870889b-181c-4078-8d31-05c4a5987668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980029214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2980029214
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2670076580
Short name T414
Test name
Test status
Simulation time 1495141732 ps
CPU time 13.54 seconds
Started Jul 04 05:14:36 PM PDT 24
Finished Jul 04 05:14:50 PM PDT 24
Peak memory 220552 kb
Host smart-ea27e2d3-c8fa-4250-be41-e792999278f1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2670076580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2670076580
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.410091474
Short name T306
Test name
Test status
Simulation time 2462583079 ps
CPU time 6.9 seconds
Started Jul 04 05:14:24 PM PDT 24
Finished Jul 04 05:14:31 PM PDT 24
Peak memory 216272 kb
Host smart-a539b9f7-d3df-4162-94b4-7522c27a86a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410091474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.410091474
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1051357225
Short name T327
Test name
Test status
Simulation time 1597523121 ps
CPU time 4.74 seconds
Started Jul 04 05:14:28 PM PDT 24
Finished Jul 04 05:14:33 PM PDT 24
Peak memory 216092 kb
Host smart-d540f375-c79f-4d77-8dfb-f6bbb39525b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051357225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1051357225
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2358165055
Short name T948
Test name
Test status
Simulation time 63118586 ps
CPU time 1.48 seconds
Started Jul 04 05:14:26 PM PDT 24
Finished Jul 04 05:14:27 PM PDT 24
Peak memory 216108 kb
Host smart-3769e372-ec52-47a3-b2fa-f6a18d884a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358165055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2358165055
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1853337051
Short name T698
Test name
Test status
Simulation time 32250732 ps
CPU time 0.84 seconds
Started Jul 04 05:14:24 PM PDT 24
Finished Jul 04 05:14:26 PM PDT 24
Peak memory 205896 kb
Host smart-eb99e748-2154-44e5-8db3-52dc9ce5e8d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853337051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1853337051
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.579913226
Short name T570
Test name
Test status
Simulation time 23989290694 ps
CPU time 18.18 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:54 PM PDT 24
Peak memory 232792 kb
Host smart-1aec07fe-0a81-4b2e-b56b-17663b5eb811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579913226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.579913226
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.1661439605
Short name T613
Test name
Test status
Simulation time 38303475 ps
CPU time 0.74 seconds
Started Jul 04 05:14:37 PM PDT 24
Finished Jul 04 05:14:38 PM PDT 24
Peak memory 205456 kb
Host smart-d7c76f99-67f5-4309-b03a-ddbe79ff15ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661439605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
1661439605
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.659953211
Short name T565
Test name
Test status
Simulation time 3976279693 ps
CPU time 8.99 seconds
Started Jul 04 05:14:37 PM PDT 24
Finished Jul 04 05:14:47 PM PDT 24
Peak memory 224560 kb
Host smart-f322f4cd-acf2-419c-a324-eeef46a4e3f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659953211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.659953211
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3368041382
Short name T572
Test name
Test status
Simulation time 26684887 ps
CPU time 0.82 seconds
Started Jul 04 05:14:34 PM PDT 24
Finished Jul 04 05:14:35 PM PDT 24
Peak memory 206524 kb
Host smart-f62cd170-a9b3-4fba-9482-655d59ef6e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368041382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3368041382
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2387772976
Short name T901
Test name
Test status
Simulation time 26716055637 ps
CPU time 188.53 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:17:44 PM PDT 24
Peak memory 265524 kb
Host smart-83e93763-35ef-4ff3-9f83-70bc0bd520e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387772976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2387772976
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2709568902
Short name T706
Test name
Test status
Simulation time 40152399406 ps
CPU time 194.24 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:17:55 PM PDT 24
Peak memory 241000 kb
Host smart-2b0879fb-b350-43be-9a1e-cf13d91d6c52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709568902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2709568902
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.1003249340
Short name T439
Test name
Test status
Simulation time 1467168033 ps
CPU time 4.99 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:14:38 PM PDT 24
Peak memory 232652 kb
Host smart-9c7d6873-ac20-4be0-9ccf-8ba929968a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1003249340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.1003249340
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.953649963
Short name T212
Test name
Test status
Simulation time 180623110459 ps
CPU time 305.25 seconds
Started Jul 04 05:14:37 PM PDT 24
Finished Jul 04 05:19:42 PM PDT 24
Peak memory 249176 kb
Host smart-03e9cd6f-0bd3-4989-b88e-423173900fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953649963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmds
.953649963
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.433309983
Short name T202
Test name
Test status
Simulation time 7723394971 ps
CPU time 15.91 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:51 PM PDT 24
Peak memory 232708 kb
Host smart-2425a931-05d8-4357-b741-5e150d4dc0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433309983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.433309983
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.193710719
Short name T860
Test name
Test status
Simulation time 8226220268 ps
CPU time 23.64 seconds
Started Jul 04 05:14:36 PM PDT 24
Finished Jul 04 05:15:00 PM PDT 24
Peak memory 248504 kb
Host smart-2ca6562f-a40e-4416-b852-56f6071ef90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193710719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.193710719
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2066142580
Short name T7
Test name
Test status
Simulation time 1247210270 ps
CPU time 6.2 seconds
Started Jul 04 05:14:36 PM PDT 24
Finished Jul 04 05:14:42 PM PDT 24
Peak memory 232608 kb
Host smart-091ef9d9-94a0-4158-866c-64d090e77792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066142580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2066142580
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.764667789
Short name T458
Test name
Test status
Simulation time 8038907237 ps
CPU time 17.28 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:53 PM PDT 24
Peak memory 240612 kb
Host smart-0e9e3fc8-a489-4f4f-90e8-bcb089055d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764667789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.764667789
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.639563635
Short name T437
Test name
Test status
Simulation time 2526881537 ps
CPU time 11.38 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:47 PM PDT 24
Peak memory 220124 kb
Host smart-02119c9a-52d4-4ff7-b1ad-09488e1b4c88
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=639563635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dire
ct.639563635
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3363461058
Short name T18
Test name
Test status
Simulation time 363707080 ps
CPU time 1.1 seconds
Started Jul 04 05:14:37 PM PDT 24
Finished Jul 04 05:14:39 PM PDT 24
Peak memory 206928 kb
Host smart-6b29aa46-ae82-41ec-ad49-aa539b7da975
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363461058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3363461058
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.2807225291
Short name T976
Test name
Test status
Simulation time 11818074 ps
CPU time 0.71 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:14:34 PM PDT 24
Peak memory 205596 kb
Host smart-e71929cf-ab9f-41f5-abfe-ea0c5e326a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2807225291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.2807225291
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2484917881
Short name T940
Test name
Test status
Simulation time 2785498268 ps
CPU time 3.67 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 216176 kb
Host smart-6c654198-8bb7-436e-a791-8aa9ce93e294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484917881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2484917881
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2853598928
Short name T417
Test name
Test status
Simulation time 26255000 ps
CPU time 0.81 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:14:34 PM PDT 24
Peak memory 205908 kb
Host smart-b23eaf4f-eecf-4e5d-aa23-de077e425d29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853598928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2853598928
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1974650173
Short name T419
Test name
Test status
Simulation time 17059823 ps
CPU time 0.69 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:36 PM PDT 24
Peak memory 205612 kb
Host smart-ad5d0708-c558-4e8f-b4bd-85c3ef2c6bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1974650173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1974650173
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.464912982
Short name T473
Test name
Test status
Simulation time 3076985454 ps
CPU time 12.03 seconds
Started Jul 04 05:14:32 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 232776 kb
Host smart-cfa5d242-7fa4-403f-9af1-d77c3263358b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464912982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.464912982
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.3533480220
Short name T56
Test name
Test status
Simulation time 33565670 ps
CPU time 0.76 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:14:42 PM PDT 24
Peak memory 205428 kb
Host smart-b550e76f-f156-4102-8319-f87ed7d102e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533480220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
3533480220
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.1114831057
Short name T6
Test name
Test status
Simulation time 183468058 ps
CPU time 5.65 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:41 PM PDT 24
Peak memory 224412 kb
Host smart-d41206d8-0ff1-4846-b214-77ace7c1e359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114831057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.1114831057
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.4095834327
Short name T770
Test name
Test status
Simulation time 18173333 ps
CPU time 0.76 seconds
Started Jul 04 05:14:32 PM PDT 24
Finished Jul 04 05:14:33 PM PDT 24
Peak memory 205820 kb
Host smart-45bca2ff-2c45-47a9-982f-9fff767d7b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095834327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.4095834327
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.1435388536
Short name T994
Test name
Test status
Simulation time 38118300 ps
CPU time 0.87 seconds
Started Jul 04 05:14:34 PM PDT 24
Finished Jul 04 05:14:35 PM PDT 24
Peak memory 215740 kb
Host smart-8c607636-32fa-48e7-ac04-be6755e07aba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435388536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.1435388536
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4249904588
Short name T217
Test name
Test status
Simulation time 7960880558 ps
CPU time 108.81 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:16:29 PM PDT 24
Peak memory 265912 kb
Host smart-a64b5f2a-2640-4ef7-849c-1358d0886025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4249904588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4249904588
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3653555028
Short name T51
Test name
Test status
Simulation time 3648325556 ps
CPU time 81.69 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:16:03 PM PDT 24
Peak memory 256768 kb
Host smart-67005abe-c841-4c93-a910-cfc74171c979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653555028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3653555028
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1877927208
Short name T962
Test name
Test status
Simulation time 550707205 ps
CPU time 11.07 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:46 PM PDT 24
Peak memory 232644 kb
Host smart-5b04a425-95c1-482e-b1b2-8fdc839eb28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877927208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1877927208
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.4290556660
Short name T156
Test name
Test status
Simulation time 8226853197 ps
CPU time 100.61 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 254672 kb
Host smart-0060fb28-8c37-481a-af2f-43b37dec51cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290556660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.4290556660
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.849159295
Short name T274
Test name
Test status
Simulation time 1564166754 ps
CPU time 15.62 seconds
Started Jul 04 05:14:33 PM PDT 24
Finished Jul 04 05:14:49 PM PDT 24
Peak memory 232584 kb
Host smart-e51f2773-557f-4bc2-ba32-3553b128747a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849159295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.849159295
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.663227985
Short name T657
Test name
Test status
Simulation time 12211742362 ps
CPU time 61.75 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 249084 kb
Host smart-0aeecc30-0bc7-40f7-a82a-dcea2d56be01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663227985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.663227985
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.3892738352
Short name T387
Test name
Test status
Simulation time 84304331 ps
CPU time 2.78 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:38 PM PDT 24
Peak memory 232588 kb
Host smart-558cc483-2c71-4743-8e4a-9d547a135568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3892738352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.3892738352
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.2620228966
Short name T889
Test name
Test status
Simulation time 3773786837 ps
CPU time 13.61 seconds
Started Jul 04 05:14:36 PM PDT 24
Finished Jul 04 05:14:50 PM PDT 24
Peak memory 240820 kb
Host smart-6404404c-f1d4-40b3-9fbc-0f744608dcde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620228966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.2620228966
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.4217723123
Short name T515
Test name
Test status
Simulation time 275947583 ps
CPU time 7.13 seconds
Started Jul 04 05:14:35 PM PDT 24
Finished Jul 04 05:14:43 PM PDT 24
Peak memory 222028 kb
Host smart-845284c9-f627-427d-b87e-0df6eb7df6ea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4217723123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.4217723123
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.4198053176
Short name T906
Test name
Test status
Simulation time 36153210956 ps
CPU time 46.86 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:15:30 PM PDT 24
Peak memory 224456 kb
Host smart-8ea554e2-4371-4c0b-8997-f8d93790df35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198053176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.4198053176
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1866389052
Short name T347
Test name
Test status
Simulation time 5273610053 ps
CPU time 4.24 seconds
Started Jul 04 05:14:36 PM PDT 24
Finished Jul 04 05:14:41 PM PDT 24
Peak memory 216636 kb
Host smart-c88ab99d-afb4-4309-b19c-8d14e8c31c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866389052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1866389052
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.600710339
Short name T486
Test name
Test status
Simulation time 2472914649 ps
CPU time 4.94 seconds
Started Jul 04 05:14:36 PM PDT 24
Finished Jul 04 05:14:42 PM PDT 24
Peak memory 216312 kb
Host smart-44065439-9894-4028-b996-581c0f622a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600710339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.600710339
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.1315074358
Short name T317
Test name
Test status
Simulation time 127849040 ps
CPU time 1.22 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:14:42 PM PDT 24
Peak memory 207960 kb
Host smart-82afc564-ed9d-486e-8b50-5523f9560e21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315074358 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.1315074358
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1616487421
Short name T767
Test name
Test status
Simulation time 34792496 ps
CPU time 0.76 seconds
Started Jul 04 05:14:36 PM PDT 24
Finished Jul 04 05:14:38 PM PDT 24
Peak memory 205916 kb
Host smart-0a26f1f4-1352-4274-9ba2-ede954c3f8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616487421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1616487421
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.3262604691
Short name T674
Test name
Test status
Simulation time 8765513632 ps
CPU time 28.97 seconds
Started Jul 04 05:14:32 PM PDT 24
Finished Jul 04 05:15:01 PM PDT 24
Peak memory 232680 kb
Host smart-e1ddcb51-eb76-4b7f-844a-107cfd6e8ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262604691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.3262604691
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1755339772
Short name T793
Test name
Test status
Simulation time 12297377 ps
CPU time 0.77 seconds
Started Jul 04 05:12:35 PM PDT 24
Finished Jul 04 05:12:36 PM PDT 24
Peak memory 205400 kb
Host smart-989d8b37-392a-4c24-aa6c-cf658a34d0cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755339772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
755339772
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.2320553672
Short name T677
Test name
Test status
Simulation time 4237818569 ps
CPU time 6.11 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 224508 kb
Host smart-ef6e3f28-204f-47cd-865b-1a5f001c2331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2320553672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.2320553672
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1307058470
Short name T781
Test name
Test status
Simulation time 66259098 ps
CPU time 0.78 seconds
Started Jul 04 05:12:30 PM PDT 24
Finished Jul 04 05:12:31 PM PDT 24
Peak memory 206488 kb
Host smart-59f59c04-83d6-4bd2-bea6-20a36c1bde9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1307058470 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1307058470
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.1913978063
Short name T5
Test name
Test status
Simulation time 599388906 ps
CPU time 11.53 seconds
Started Jul 04 05:12:35 PM PDT 24
Finished Jul 04 05:12:47 PM PDT 24
Peak memory 240872 kb
Host smart-dc94657c-5e4a-4782-97b2-dc87c3924ff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1913978063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.1913978063
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.1559919121
Short name T966
Test name
Test status
Simulation time 12609263620 ps
CPU time 52 seconds
Started Jul 04 05:12:32 PM PDT 24
Finished Jul 04 05:13:24 PM PDT 24
Peak memory 238600 kb
Host smart-1021ef92-9bfc-4636-afc8-a4f924ae52c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559919121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.1559919121
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.1480449204
Short name T275
Test name
Test status
Simulation time 8322082452 ps
CPU time 104.17 seconds
Started Jul 04 05:12:35 PM PDT 24
Finished Jul 04 05:14:20 PM PDT 24
Peak memory 252560 kb
Host smart-de0398ae-0ce9-45ee-bb01-fee34f2f7cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1480449204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.1480449204
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.4258987687
Short name T700
Test name
Test status
Simulation time 542297981 ps
CPU time 7.29 seconds
Started Jul 04 05:12:35 PM PDT 24
Finished Jul 04 05:12:42 PM PDT 24
Peak memory 224352 kb
Host smart-00ea8f49-5708-4db9-a4ea-2eca17cdd67f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258987687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.4258987687
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.2371007859
Short name T538
Test name
Test status
Simulation time 66841533279 ps
CPU time 154.22 seconds
Started Jul 04 05:12:34 PM PDT 24
Finished Jul 04 05:15:09 PM PDT 24
Peak memory 256840 kb
Host smart-a57a20c6-00a4-4cba-823c-840fe18bc45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371007859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.2371007859
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3521583761
Short name T964
Test name
Test status
Simulation time 2234496491 ps
CPU time 10.19 seconds
Started Jul 04 05:12:38 PM PDT 24
Finished Jul 04 05:12:48 PM PDT 24
Peak memory 224408 kb
Host smart-b837501e-65f2-4f24-9581-b9186d40a5ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521583761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3521583761
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.3484058648
Short name T1006
Test name
Test status
Simulation time 15146125088 ps
CPU time 28.98 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:13:02 PM PDT 24
Peak memory 232656 kb
Host smart-4f1198fe-4ed7-46b6-af59-f851fb4bb001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3484058648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.3484058648
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.2884953363
Short name T627
Test name
Test status
Simulation time 495533987 ps
CPU time 6.3 seconds
Started Jul 04 05:12:32 PM PDT 24
Finished Jul 04 05:12:38 PM PDT 24
Peak memory 224408 kb
Host smart-d69a8132-3226-4308-9fb0-97ddda3ef4e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2884953363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.2884953363
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.590456805
Short name T676
Test name
Test status
Simulation time 2747796884 ps
CPU time 5.78 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 232676 kb
Host smart-dab2724e-0373-49cb-8726-1f8fc8dd5c1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=590456805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.590456805
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2676648815
Short name T28
Test name
Test status
Simulation time 646253441 ps
CPU time 6.95 seconds
Started Jul 04 05:12:31 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 218752 kb
Host smart-af9196c4-68de-4b0a-8c0f-c1607cb13264
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2676648815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2676648815
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.1953873258
Short name T63
Test name
Test status
Simulation time 77841649 ps
CPU time 1.12 seconds
Started Jul 04 05:12:34 PM PDT 24
Finished Jul 04 05:12:35 PM PDT 24
Peak memory 236512 kb
Host smart-e75b8bb9-63ac-4e6c-b22f-10d7ce8616ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953873258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.1953873258
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.130074630
Short name T642
Test name
Test status
Simulation time 106891246695 ps
CPU time 242.01 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:16:35 PM PDT 24
Peak memory 251368 kb
Host smart-e22358aa-f78b-42fa-bbae-ab3fd7b08425
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=130074630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.130074630
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.329686287
Short name T907
Test name
Test status
Simulation time 15367704 ps
CPU time 0.69 seconds
Started Jul 04 05:12:29 PM PDT 24
Finished Jul 04 05:12:30 PM PDT 24
Peak memory 205580 kb
Host smart-5ecb3adc-a558-46b0-899c-e43a1956cfd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=329686287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.329686287
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2501781751
Short name T525
Test name
Test status
Simulation time 3197047393 ps
CPU time 6.52 seconds
Started Jul 04 05:12:25 PM PDT 24
Finished Jul 04 05:12:31 PM PDT 24
Peak memory 216176 kb
Host smart-87b32e2e-4ef3-454a-b2aa-0e8a2bdcd211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501781751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2501781751
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.2992660916
Short name T418
Test name
Test status
Simulation time 20465756 ps
CPU time 0.76 seconds
Started Jul 04 05:12:34 PM PDT 24
Finished Jul 04 05:12:35 PM PDT 24
Peak memory 205932 kb
Host smart-f2b477a5-c50f-43c9-bf45-2e9a9e59c5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992660916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.2992660916
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.2098181911
Short name T743
Test name
Test status
Simulation time 14045837 ps
CPU time 0.72 seconds
Started Jul 04 05:12:36 PM PDT 24
Finished Jul 04 05:12:36 PM PDT 24
Peak memory 205592 kb
Host smart-c07aed0e-286a-4056-bd17-92cda09b8bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098181911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.2098181911
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.3368575487
Short name T884
Test name
Test status
Simulation time 1588307332 ps
CPU time 10.19 seconds
Started Jul 04 05:12:32 PM PDT 24
Finished Jul 04 05:12:43 PM PDT 24
Peak memory 232660 kb
Host smart-89e46fe1-66e6-4ea5-ba4f-d6823442bcc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368575487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.3368575487
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.3764423768
Short name T334
Test name
Test status
Simulation time 49093130 ps
CPU time 0.72 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 205764 kb
Host smart-00170bb4-5a1b-49d3-9d06-cf7083342ec4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764423768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
3764423768
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.2494172897
Short name T641
Test name
Test status
Simulation time 215878700 ps
CPU time 4.17 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:14:48 PM PDT 24
Peak memory 224452 kb
Host smart-d10cfaa2-1d61-4329-8728-5bede85d4c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494172897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.2494172897
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2291938048
Short name T120
Test name
Test status
Simulation time 21434895 ps
CPU time 0.75 seconds
Started Jul 04 05:14:45 PM PDT 24
Finished Jul 04 05:14:46 PM PDT 24
Peak memory 206496 kb
Host smart-726a2b66-f86b-4c49-b0bf-61cf94c292fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291938048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2291938048
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.1031761442
Short name T801
Test name
Test status
Simulation time 4856834593 ps
CPU time 43.84 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:15:27 PM PDT 24
Peak memory 239420 kb
Host smart-6b2a95f8-6d41-4549-9bc2-ffebf55a4ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031761442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.1031761442
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1268629145
Short name T883
Test name
Test status
Simulation time 2557620192 ps
CPU time 30.61 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:15:11 PM PDT 24
Peak memory 224632 kb
Host smart-96373e54-cf30-43eb-b854-964ba0ddb760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268629145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1268629145
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3533532368
Short name T252
Test name
Test status
Simulation time 3414080391 ps
CPU time 54.82 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:15:35 PM PDT 24
Peak memory 249160 kb
Host smart-36d0c49d-e9ff-4f6e-86e0-5e4bc5c72b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533532368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3533532368
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3059219150
Short name T40
Test name
Test status
Simulation time 633857548 ps
CPU time 5.93 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:14:47 PM PDT 24
Peak memory 234680 kb
Host smart-6150467a-3155-48a0-adc8-1c2b89b08342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059219150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3059219150
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.952192589
Short name T420
Test name
Test status
Simulation time 11040858104 ps
CPU time 83.93 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:16:06 PM PDT 24
Peak memory 240932 kb
Host smart-6c811b31-1dcd-419f-a4d1-d7173b3f3ad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952192589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmds
.952192589
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2796278812
Short name T55
Test name
Test status
Simulation time 250381322 ps
CPU time 2.25 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 222600 kb
Host smart-5d4af486-2a52-4702-bd2c-47e6c7ffc0d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796278812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2796278812
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.4089540658
Short name T815
Test name
Test status
Simulation time 609089021 ps
CPU time 2.56 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:14:47 PM PDT 24
Peak memory 232560 kb
Host smart-3e71e409-f4a5-4395-8ce2-cd6a6cfae83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089540658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.4089540658
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.694962166
Short name T623
Test name
Test status
Simulation time 1027245593 ps
CPU time 5.05 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:14:45 PM PDT 24
Peak memory 232568 kb
Host smart-acecb766-67e6-441d-9cfd-384c95bf858f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694962166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.694962166
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2819508489
Short name T483
Test name
Test status
Simulation time 21366506613 ps
CPU time 18.01 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:14:59 PM PDT 24
Peak memory 232696 kb
Host smart-2ad4af71-365b-4248-b59b-ffe9345605b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819508489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2819508489
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.2236470548
Short name T981
Test name
Test status
Simulation time 292002386 ps
CPU time 3.83 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:46 PM PDT 24
Peak memory 218408 kb
Host smart-e9db3afb-751c-4acf-90fc-f3f9575f76e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2236470548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.2236470548
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.3219979424
Short name T446
Test name
Test status
Simulation time 12222383680 ps
CPU time 97.42 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:16:20 PM PDT 24
Peak memory 232748 kb
Host smart-a28d1c3c-eb04-4294-bcc6-4778f3ad5cd0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219979424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.3219979424
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.867781888
Short name T351
Test name
Test status
Simulation time 9871442717 ps
CPU time 22.97 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:15:08 PM PDT 24
Peak memory 216220 kb
Host smart-91415432-e0eb-4d38-b657-eaa1e0e52fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=867781888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.867781888
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.1751354629
Short name T887
Test name
Test status
Simulation time 17564374 ps
CPU time 0.72 seconds
Started Jul 04 05:14:45 PM PDT 24
Finished Jul 04 05:14:46 PM PDT 24
Peak memory 205588 kb
Host smart-a9c41405-36c9-4df7-b165-f6cf1a6afc7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751354629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.1751354629
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.990935750
Short name T401
Test name
Test status
Simulation time 133520707 ps
CPU time 1.75 seconds
Started Jul 04 05:14:46 PM PDT 24
Finished Jul 04 05:14:48 PM PDT 24
Peak memory 216132 kb
Host smart-c45566b7-ac8e-45e4-ab38-7e8895bb5772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990935750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.990935750
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2953005589
Short name T455
Test name
Test status
Simulation time 638846611 ps
CPU time 0.88 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:43 PM PDT 24
Peak memory 205908 kb
Host smart-45fd8f17-e639-4ef5-96c9-83b6d2553a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953005589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2953005589
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.50198819
Short name T440
Test name
Test status
Simulation time 6834431272 ps
CPU time 22.33 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:15:03 PM PDT 24
Peak memory 232688 kb
Host smart-4e9b16e1-8509-4fbe-b400-396e92dcc15c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50198819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.50198819
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.4008310023
Short name T675
Test name
Test status
Simulation time 32781714 ps
CPU time 0.72 seconds
Started Jul 04 05:14:47 PM PDT 24
Finished Jul 04 05:14:47 PM PDT 24
Peak memory 205456 kb
Host smart-0712685c-ca1c-45a0-aa28-74415dbb3df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008310023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
4008310023
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.4032133472
Short name T798
Test name
Test status
Simulation time 6806214748 ps
CPU time 14.63 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:14:58 PM PDT 24
Peak memory 224456 kb
Host smart-3800101a-92bf-4f2e-897e-392408fa69d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032133472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.4032133472
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.769459745
Short name T891
Test name
Test status
Simulation time 46473325 ps
CPU time 0.77 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 206868 kb
Host smart-241d2f71-0712-4f07-9c90-baa5e2aec68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769459745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.769459745
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.4000673116
Short name T290
Test name
Test status
Simulation time 61010196170 ps
CPU time 104.56 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:16:25 PM PDT 24
Peak memory 234788 kb
Host smart-78b5d528-532e-4aca-8231-539e71b3e238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000673116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.4000673116
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.4191593911
Short name T447
Test name
Test status
Simulation time 175200243158 ps
CPU time 321.9 seconds
Started Jul 04 05:14:47 PM PDT 24
Finished Jul 04 05:20:09 PM PDT 24
Peak memory 250260 kb
Host smart-dc4fa5d2-21dc-4a99-96dc-0ee07706b12f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191593911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.4191593911
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.3880981258
Short name T300
Test name
Test status
Simulation time 378344492 ps
CPU time 9.34 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:52 PM PDT 24
Peak memory 224440 kb
Host smart-e30cce57-7718-4c0a-9e4b-a00b4765a4ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880981258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.3880981258
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.3004494754
Short name T463
Test name
Test status
Simulation time 24661231097 ps
CPU time 182.11 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:17:44 PM PDT 24
Peak memory 256968 kb
Host smart-8c4c2371-8703-4e01-9315-e5de427a7ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004494754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.3004494754
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1948875800
Short name T543
Test name
Test status
Simulation time 3093287958 ps
CPU time 16.4 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:15:00 PM PDT 24
Peak memory 232708 kb
Host smart-66135334-eb12-4da2-aebf-6e9f403fd5bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948875800 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1948875800
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.538476125
Short name T909
Test name
Test status
Simulation time 9646173274 ps
CPU time 23.45 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:15:05 PM PDT 24
Peak memory 224504 kb
Host smart-da1a2e48-58e1-4045-8693-f83eb4e92109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538476125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.538476125
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.1782219907
Short name T580
Test name
Test status
Simulation time 37206010956 ps
CPU time 26.64 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:15:11 PM PDT 24
Peak memory 224492 kb
Host smart-564022ee-e997-463c-a462-d70abea02d7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782219907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.1782219907
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.177783326
Short name T476
Test name
Test status
Simulation time 2027377771 ps
CPU time 12.74 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:14:56 PM PDT 24
Peak memory 232528 kb
Host smart-fc500108-84a3-424a-b9c0-80bb9f227d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177783326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.177783326
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.3573490426
Short name T593
Test name
Test status
Simulation time 703918572 ps
CPU time 6.63 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:49 PM PDT 24
Peak memory 219976 kb
Host smart-22752bb5-5cc1-4b8b-aa4d-1bffc8d46f55
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3573490426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.3573490426
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2804962610
Short name T119
Test name
Test status
Simulation time 10938010842 ps
CPU time 81.28 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:16:04 PM PDT 24
Peak memory 257372 kb
Host smart-8ba0820b-7f4f-4bc0-ab05-f78c0bdb2397
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2804962610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2804962610
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2714102438
Short name T554
Test name
Test status
Simulation time 602783134 ps
CPU time 2.32 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 217128 kb
Host smart-1674f336-c8f1-459b-825a-1e81a954f413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2714102438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2714102438
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.226398787
Short name T311
Test name
Test status
Simulation time 12503869 ps
CPU time 0.75 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:14:42 PM PDT 24
Peak memory 205652 kb
Host smart-5ec121c5-9153-445a-a098-ebf8550ba239
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226398787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.226398787
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3831288744
Short name T789
Test name
Test status
Simulation time 31017311 ps
CPU time 1.07 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 207412 kb
Host smart-e145042e-5879-49eb-984e-e3fc6a2da78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831288744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3831288744
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3390244033
Short name T828
Test name
Test status
Simulation time 104242320 ps
CPU time 0.94 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:14:45 PM PDT 24
Peak memory 206948 kb
Host smart-bc4dfa30-8322-464e-b1e6-6a0fc03e7b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390244033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3390244033
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2361837830
Short name T258
Test name
Test status
Simulation time 117367155 ps
CPU time 3.03 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 224396 kb
Host smart-98b674a4-5c69-4e56-9318-a6ba1951996a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361837830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2361837830
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.2877594232
Short name T449
Test name
Test status
Simulation time 16748927 ps
CPU time 0.73 seconds
Started Jul 04 05:14:43 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 205744 kb
Host smart-b532e0fd-bcfb-403e-8087-cf959a429924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877594232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
2877594232
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2155473289
Short name T81
Test name
Test status
Simulation time 231475398 ps
CPU time 4.28 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:14:49 PM PDT 24
Peak memory 224428 kb
Host smart-afbca917-7283-426c-9f56-4b1a6ccea0a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155473289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2155473289
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1512160370
Short name T868
Test name
Test status
Simulation time 20423644 ps
CPU time 0.8 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:14:45 PM PDT 24
Peak memory 206540 kb
Host smart-bdfb641f-55dd-45ea-a2e2-6467e04e5ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512160370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1512160370
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1180037509
Short name T400
Test name
Test status
Simulation time 9523832479 ps
CPU time 66.26 seconds
Started Jul 04 05:14:48 PM PDT 24
Finished Jul 04 05:15:54 PM PDT 24
Peak memory 250556 kb
Host smart-5c7ffb57-868b-41e1-b7d8-6082d986b95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180037509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1180037509
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.204897368
Short name T398
Test name
Test status
Simulation time 30338259457 ps
CPU time 115.27 seconds
Started Jul 04 05:14:45 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 254100 kb
Host smart-19824f87-ea64-4eb3-abe4-fb9315dabffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204897368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.204897368
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.3470522645
Short name T765
Test name
Test status
Simulation time 13556292119 ps
CPU time 110.68 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:16:33 PM PDT 24
Peak memory 236132 kb
Host smart-bd57f374-70e9-4146-a1cd-c2eda66bd458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470522645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.3470522645
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.487854300
Short name T1001
Test name
Test status
Simulation time 363733690 ps
CPU time 4.87 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:14:50 PM PDT 24
Peak memory 224396 kb
Host smart-e9c260a1-acb0-4f2f-a254-14b213c96bd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487854300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.487854300
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3359712885
Short name T539
Test name
Test status
Simulation time 2798407257 ps
CPU time 57.26 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:15:40 PM PDT 24
Peak memory 254332 kb
Host smart-612d6475-576c-4c58-803a-f8b832f6b0b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359712885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3359712885
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.325941347
Short name T840
Test name
Test status
Simulation time 78586187 ps
CPU time 3.12 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 232664 kb
Host smart-43fba5ef-c30f-40fa-b846-40af30be3e81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325941347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.325941347
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.2050624752
Short name T8
Test name
Test status
Simulation time 22238625126 ps
CPU time 53.66 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:15:36 PM PDT 24
Peak memory 240496 kb
Host smart-996d1a95-a146-4eba-b6fb-0b3f9d605e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050624752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.2050624752
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3713654565
Short name T172
Test name
Test status
Simulation time 1139612924 ps
CPU time 7.76 seconds
Started Jul 04 05:14:48 PM PDT 24
Finished Jul 04 05:14:56 PM PDT 24
Peak memory 224364 kb
Host smart-80162b89-f4d5-4108-91e8-dfc0a3928ba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713654565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3713654565
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2440392202
Short name T278
Test name
Test status
Simulation time 32581482486 ps
CPU time 24.41 seconds
Started Jul 04 05:14:41 PM PDT 24
Finished Jul 04 05:15:06 PM PDT 24
Peak memory 237324 kb
Host smart-69ffcc6c-1061-467a-82b5-e2d1fb4eaa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440392202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2440392202
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.1221150695
Short name T496
Test name
Test status
Simulation time 846027212 ps
CPU time 7.23 seconds
Started Jul 04 05:14:46 PM PDT 24
Finished Jul 04 05:14:54 PM PDT 24
Peak memory 220184 kb
Host smart-e93f9d72-804c-45e6-8562-578956586314
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1221150695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.1221150695
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.735049347
Short name T145
Test name
Test status
Simulation time 195777349 ps
CPU time 0.99 seconds
Started Jul 04 05:14:46 PM PDT 24
Finished Jul 04 05:14:47 PM PDT 24
Peak memory 206724 kb
Host smart-1e9300ff-255e-4a7d-8653-8083185ea886
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735049347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stres
s_all.735049347
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.953052668
Short name T368
Test name
Test status
Simulation time 2911330095 ps
CPU time 16.48 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:59 PM PDT 24
Peak memory 216396 kb
Host smart-70244441-7047-4c8d-8c62-b2dee1b9b9c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953052668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.953052668
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3103824340
Short name T510
Test name
Test status
Simulation time 1484293500 ps
CPU time 5.54 seconds
Started Jul 04 05:14:45 PM PDT 24
Finished Jul 04 05:14:51 PM PDT 24
Peak memory 216064 kb
Host smart-ab563381-067a-4e5b-9d4a-1e59321d8e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3103824340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3103824340
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.3108610526
Short name T2
Test name
Test status
Simulation time 252789542 ps
CPU time 3.29 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:46 PM PDT 24
Peak memory 216244 kb
Host smart-8ae9c397-1df3-4f38-ab46-c5fce0f02220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108610526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.3108610526
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.2641630419
Short name T339
Test name
Test status
Simulation time 104876220 ps
CPU time 1.08 seconds
Started Jul 04 05:14:45 PM PDT 24
Finished Jul 04 05:14:46 PM PDT 24
Peak memory 206404 kb
Host smart-fe784737-df73-4c5d-b8a4-f02133587705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641630419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.2641630419
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3825601944
Short name T29
Test name
Test status
Simulation time 11594372848 ps
CPU time 5.65 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:14:50 PM PDT 24
Peak memory 224448 kb
Host smart-a13d44f5-8eaf-40e8-9aac-fb119ff384b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825601944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3825601944
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.3632973301
Short name T843
Test name
Test status
Simulation time 138517387 ps
CPU time 0.69 seconds
Started Jul 04 05:14:49 PM PDT 24
Finished Jul 04 05:14:50 PM PDT 24
Peak memory 205456 kb
Host smart-65d59744-3730-47b1-9442-aee7a3ecf8dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632973301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
3632973301
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3139353884
Short name T855
Test name
Test status
Simulation time 263516271 ps
CPU time 2.79 seconds
Started Jul 04 05:14:40 PM PDT 24
Finished Jul 04 05:14:43 PM PDT 24
Peak memory 224324 kb
Host smart-f8d5fcd2-bec9-4221-a558-a8a8300e8971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139353884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3139353884
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.3145927869
Short name T26
Test name
Test status
Simulation time 65910481 ps
CPU time 0.8 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:43 PM PDT 24
Peak memory 206568 kb
Host smart-59353cc9-3495-4d26-9aa4-598ac54c060f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145927869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.3145927869
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.872196092
Short name T780
Test name
Test status
Simulation time 27517677455 ps
CPU time 200.25 seconds
Started Jul 04 05:14:54 PM PDT 24
Finished Jul 04 05:18:14 PM PDT 24
Peak memory 254500 kb
Host smart-658335ee-d2f6-43ee-80e4-20efe2b6007d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872196092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.872196092
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.1337944644
Short name T963
Test name
Test status
Simulation time 16163850224 ps
CPU time 27.27 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:15:23 PM PDT 24
Peak memory 217576 kb
Host smart-c768b290-61b2-46f4-9f6c-b9d052256fe7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337944644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.1337944644
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.742165891
Short name T536
Test name
Test status
Simulation time 52238270317 ps
CPU time 100.38 seconds
Started Jul 04 05:14:50 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 267220 kb
Host smart-5d51f38e-71ba-4b1d-945f-ddf64b7cfdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742165891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.742165891
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3095173375
Short name T461
Test name
Test status
Simulation time 4195453518 ps
CPU time 12.07 seconds
Started Jul 04 05:14:49 PM PDT 24
Finished Jul 04 05:15:01 PM PDT 24
Peak memory 249076 kb
Host smart-1ca8a15e-ff1b-47cd-bb4c-d7835a7b9bdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095173375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3095173375
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.3820155185
Short name T203
Test name
Test status
Simulation time 7684717337 ps
CPU time 46.67 seconds
Started Jul 04 05:14:51 PM PDT 24
Finished Jul 04 05:15:37 PM PDT 24
Peak memory 249108 kb
Host smart-c9530501-953c-401a-beae-5c4f8ab8642c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820155185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.3820155185
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.159814100
Short name T557
Test name
Test status
Simulation time 23497320669 ps
CPU time 74.53 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:15:59 PM PDT 24
Peak memory 232572 kb
Host smart-a422f85c-fc07-41a3-bb9c-6d148f61c41c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=159814100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.159814100
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.3086989044
Short name T560
Test name
Test status
Simulation time 737518802 ps
CPU time 3.69 seconds
Started Jul 04 05:14:44 PM PDT 24
Finished Jul 04 05:14:48 PM PDT 24
Peak memory 224304 kb
Host smart-45816569-7eed-4dfa-b2b5-c7e9bebe35c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086989044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.3086989044
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.757038987
Short name T735
Test name
Test status
Simulation time 169563640 ps
CPU time 4.92 seconds
Started Jul 04 05:14:46 PM PDT 24
Finished Jul 04 05:14:51 PM PDT 24
Peak memory 232540 kb
Host smart-4a6df94c-3539-4d0f-bbd8-1b3dcbcb751b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757038987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.757038987
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.239961583
Short name T870
Test name
Test status
Simulation time 1445247015 ps
CPU time 3.6 seconds
Started Jul 04 05:14:49 PM PDT 24
Finished Jul 04 05:14:53 PM PDT 24
Peak memory 218776 kb
Host smart-03c8ef2f-51af-4efe-bf3f-e75b63988501
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=239961583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dire
ct.239961583
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3065062778
Short name T118
Test name
Test status
Simulation time 76334154 ps
CPU time 1.24 seconds
Started Jul 04 05:14:55 PM PDT 24
Finished Jul 04 05:14:56 PM PDT 24
Peak memory 207656 kb
Host smart-b348ff88-2d05-4e65-9f55-d23868571239
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065062778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3065062778
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2581872908
Short name T893
Test name
Test status
Simulation time 1478749454 ps
CPU time 19.27 seconds
Started Jul 04 05:14:46 PM PDT 24
Finished Jul 04 05:15:06 PM PDT 24
Peak memory 216192 kb
Host smart-927f5d87-6467-4dcc-bf3d-c092cf6c3bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581872908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2581872908
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.454544774
Short name T392
Test name
Test status
Simulation time 13413909081 ps
CPU time 8.53 seconds
Started Jul 04 05:14:47 PM PDT 24
Finished Jul 04 05:14:56 PM PDT 24
Peak memory 216300 kb
Host smart-5cdcdff3-a3c5-4b1c-9a83-b4b58c8e823a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454544774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.454544774
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.1968103561
Short name T328
Test name
Test status
Simulation time 82084252 ps
CPU time 0.81 seconds
Started Jul 04 05:14:42 PM PDT 24
Finished Jul 04 05:14:44 PM PDT 24
Peak memory 206024 kb
Host smart-293681f8-5e12-4060-a0d5-0daf6dbe3614
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968103561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.1968103561
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2757825593
Short name T951
Test name
Test status
Simulation time 222863939 ps
CPU time 0.91 seconds
Started Jul 04 05:14:48 PM PDT 24
Finished Jul 04 05:14:49 PM PDT 24
Peak memory 205932 kb
Host smart-415cc906-517f-489f-a293-7bfd77fed4ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757825593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2757825593
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.2758093830
Short name T158
Test name
Test status
Simulation time 54569258 ps
CPU time 2.86 seconds
Started Jul 04 05:14:39 PM PDT 24
Finished Jul 04 05:14:42 PM PDT 24
Peak memory 232956 kb
Host smart-7dca8ac1-e798-4ce0-a5e5-002e5f3027f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758093830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.2758093830
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1905300875
Short name T925
Test name
Test status
Simulation time 15128851 ps
CPU time 0.71 seconds
Started Jul 04 05:14:50 PM PDT 24
Finished Jul 04 05:14:51 PM PDT 24
Peak memory 205416 kb
Host smart-d88fe960-6873-40a4-8886-9578cc7760f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1905300875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1905300875
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.942424675
Short name T810
Test name
Test status
Simulation time 2766817479 ps
CPU time 8.17 seconds
Started Jul 04 05:14:51 PM PDT 24
Finished Jul 04 05:14:59 PM PDT 24
Peak memory 232688 kb
Host smart-7f57e444-55f9-408b-b79e-93f6c263b5c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942424675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.942424675
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.1614239639
Short name T356
Test name
Test status
Simulation time 17112016 ps
CPU time 0.81 seconds
Started Jul 04 05:14:49 PM PDT 24
Finished Jul 04 05:14:50 PM PDT 24
Peak memory 206560 kb
Host smart-2d0d337b-3d58-4524-8aff-86a895665bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614239639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.1614239639
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.960137803
Short name T863
Test name
Test status
Simulation time 46154087383 ps
CPU time 241.85 seconds
Started Jul 04 05:14:49 PM PDT 24
Finished Jul 04 05:18:51 PM PDT 24
Peak memory 256804 kb
Host smart-470182d4-28a2-454b-a72a-2d34f75dc6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960137803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.960137803
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3372836683
Short name T219
Test name
Test status
Simulation time 7735863118 ps
CPU time 118.66 seconds
Started Jul 04 05:14:55 PM PDT 24
Finished Jul 04 05:16:54 PM PDT 24
Peak memory 255400 kb
Host smart-634f7a01-a0e3-45a7-8205-31800cc296dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372836683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3372836683
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.2143520910
Short name T152
Test name
Test status
Simulation time 49977885280 ps
CPU time 210.95 seconds
Started Jul 04 05:14:48 PM PDT 24
Finished Jul 04 05:18:19 PM PDT 24
Peak memory 249300 kb
Host smart-6ce0f237-4b4d-4636-b1c2-51ee27ac8b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143520910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.2143520910
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.82896007
Short name T262
Test name
Test status
Simulation time 6421295102 ps
CPU time 83.88 seconds
Started Jul 04 05:14:50 PM PDT 24
Finished Jul 04 05:16:14 PM PDT 24
Peak memory 273096 kb
Host smart-f589aaa6-f462-4033-8aec-9f42c0923406
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82896007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds.82896007
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.1590315980
Short name T703
Test name
Test status
Simulation time 73851708 ps
CPU time 3.07 seconds
Started Jul 04 05:14:52 PM PDT 24
Finished Jul 04 05:14:55 PM PDT 24
Peak memory 232600 kb
Host smart-3d0318eb-c719-4c23-8a5d-1b714e4af880
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590315980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.1590315980
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4258635396
Short name T734
Test name
Test status
Simulation time 15449444391 ps
CPU time 41.59 seconds
Started Jul 04 05:14:48 PM PDT 24
Finished Jul 04 05:15:30 PM PDT 24
Peak memory 232740 kb
Host smart-9a5b3109-8143-4b3f-ab99-566995453c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258635396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4258635396
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3189201581
Short name T816
Test name
Test status
Simulation time 3507636681 ps
CPU time 8.08 seconds
Started Jul 04 05:14:50 PM PDT 24
Finished Jul 04 05:14:58 PM PDT 24
Peak memory 232732 kb
Host smart-3bb7e3b4-b100-4693-98bf-1c15dabcbadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189201581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3189201581
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2770595017
Short name T621
Test name
Test status
Simulation time 84122555 ps
CPU time 2.16 seconds
Started Jul 04 05:14:50 PM PDT 24
Finished Jul 04 05:14:53 PM PDT 24
Peak memory 224380 kb
Host smart-44f3cad3-f920-4344-a7b4-8f098a217e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770595017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2770595017
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.2019471108
Short name T818
Test name
Test status
Simulation time 690188494 ps
CPU time 8.08 seconds
Started Jul 04 05:14:54 PM PDT 24
Finished Jul 04 05:15:02 PM PDT 24
Peak memory 220252 kb
Host smart-b063b40c-f974-4ec2-874b-c95b201626d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2019471108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.2019471108
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1766459066
Short name T726
Test name
Test status
Simulation time 18137300420 ps
CPU time 186.99 seconds
Started Jul 04 05:14:52 PM PDT 24
Finished Jul 04 05:17:59 PM PDT 24
Peak memory 249184 kb
Host smart-f5b5eace-d7ac-40a8-8ed4-6f92aab79f96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766459066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1766459066
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2015974196
Short name T1004
Test name
Test status
Simulation time 1038292424 ps
CPU time 5.57 seconds
Started Jul 04 05:14:49 PM PDT 24
Finished Jul 04 05:14:55 PM PDT 24
Peak memory 219192 kb
Host smart-f26ede2b-3801-4306-9561-b00e55c9b4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015974196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2015974196
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.3413679282
Short name T67
Test name
Test status
Simulation time 8892970046 ps
CPU time 5.48 seconds
Started Jul 04 05:14:50 PM PDT 24
Finished Jul 04 05:14:56 PM PDT 24
Peak memory 216244 kb
Host smart-cda0a28b-5864-47db-9ba6-3f6e17c8a091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413679282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.3413679282
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.690491138
Short name T956
Test name
Test status
Simulation time 481611270 ps
CPU time 9.71 seconds
Started Jul 04 05:14:49 PM PDT 24
Finished Jul 04 05:14:59 PM PDT 24
Peak memory 216124 kb
Host smart-d582dc9b-7e71-4e9a-bbf8-f7eb298b6f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690491138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.690491138
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.4108374638
Short name T996
Test name
Test status
Simulation time 88539251 ps
CPU time 0.83 seconds
Started Jul 04 05:14:51 PM PDT 24
Finished Jul 04 05:14:52 PM PDT 24
Peak memory 205932 kb
Host smart-549da71a-40d6-4038-a0b7-cf02eb922656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108374638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.4108374638
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1752403290
Short name T634
Test name
Test status
Simulation time 1374099882 ps
CPU time 5.54 seconds
Started Jul 04 05:14:51 PM PDT 24
Finished Jul 04 05:14:57 PM PDT 24
Peak memory 224400 kb
Host smart-ac8f3d78-df25-482d-b897-4219facafad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752403290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1752403290
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.1015990202
Short name T599
Test name
Test status
Simulation time 14235279 ps
CPU time 0.74 seconds
Started Jul 04 05:14:58 PM PDT 24
Finished Jul 04 05:14:59 PM PDT 24
Peak memory 204852 kb
Host smart-84469480-1d7f-4cff-bed0-7c9a1824ef27
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015990202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
1015990202
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3045480431
Short name T479
Test name
Test status
Simulation time 119939665 ps
CPU time 2.68 seconds
Started Jul 04 05:14:58 PM PDT 24
Finished Jul 04 05:15:01 PM PDT 24
Peak memory 224376 kb
Host smart-692bbbd0-d416-4c9f-b84e-1f5254bb6097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045480431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3045480431
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1166717750
Short name T725
Test name
Test status
Simulation time 47216205 ps
CPU time 0.81 seconds
Started Jul 04 05:14:55 PM PDT 24
Finished Jul 04 05:14:56 PM PDT 24
Peak memory 206516 kb
Host smart-8e9ceda6-e1f6-429c-b68b-52f732dd06c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166717750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1166717750
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.54363195
Short name T991
Test name
Test status
Simulation time 2662276693 ps
CPU time 59.03 seconds
Started Jul 04 05:15:00 PM PDT 24
Finished Jul 04 05:15:59 PM PDT 24
Peak memory 264932 kb
Host smart-0c268110-8188-4331-9df5-39e8bba312c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54363195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.54363195
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.1621103813
Short name T408
Test name
Test status
Simulation time 121407303969 ps
CPU time 235.85 seconds
Started Jul 04 05:15:00 PM PDT 24
Finished Jul 04 05:18:56 PM PDT 24
Peak memory 262812 kb
Host smart-1662c05f-2b19-4a78-98d6-3676539d89b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621103813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.1621103813
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.1402136488
Short name T424
Test name
Test status
Simulation time 1855794299 ps
CPU time 15.97 seconds
Started Jul 04 05:14:59 PM PDT 24
Finished Jul 04 05:15:15 PM PDT 24
Peak memory 232620 kb
Host smart-97737bcc-eab5-4f64-b836-595f8fa2ac4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402136488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.1402136488
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.1648273656
Short name T747
Test name
Test status
Simulation time 12054324457 ps
CPU time 44.23 seconds
Started Jul 04 05:14:58 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 240948 kb
Host smart-a7945c84-9c98-4e4b-8301-4446d1686c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648273656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.1648273656
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.790359665
Short name T772
Test name
Test status
Simulation time 703099299 ps
CPU time 5.09 seconds
Started Jul 04 05:14:58 PM PDT 24
Finished Jul 04 05:15:03 PM PDT 24
Peak memory 232564 kb
Host smart-24dd3054-e73b-4ff5-a705-e5a0c68ef5f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790359665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.790359665
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1353711746
Short name T827
Test name
Test status
Simulation time 27612199 ps
CPU time 2.1 seconds
Started Jul 04 05:14:59 PM PDT 24
Finished Jul 04 05:15:02 PM PDT 24
Peak memory 224080 kb
Host smart-96054d42-6181-4fbd-8092-ff0f00604504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353711746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1353711746
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3513523054
Short name T167
Test name
Test status
Simulation time 92944641 ps
CPU time 2.8 seconds
Started Jul 04 05:14:57 PM PDT 24
Finished Jul 04 05:15:00 PM PDT 24
Peak memory 224344 kb
Host smart-6eaf2826-ead0-47a6-8fb8-815ec4212a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513523054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3513523054
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3852340838
Short name T669
Test name
Test status
Simulation time 8050388224 ps
CPU time 10.19 seconds
Started Jul 04 05:14:59 PM PDT 24
Finished Jul 04 05:15:10 PM PDT 24
Peak memory 248772 kb
Host smart-a2a0c70d-0f0f-477b-9488-c20aac97c344
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852340838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3852340838
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.937834873
Short name T429
Test name
Test status
Simulation time 760957732 ps
CPU time 3.52 seconds
Started Jul 04 05:14:57 PM PDT 24
Finished Jul 04 05:15:00 PM PDT 24
Peak memory 218696 kb
Host smart-5eb3e11b-26c5-4cda-ab60-2a031a368a7f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=937834873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dire
ct.937834873
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2788812119
Short name T955
Test name
Test status
Simulation time 49399202 ps
CPU time 1 seconds
Started Jul 04 05:14:58 PM PDT 24
Finished Jul 04 05:14:59 PM PDT 24
Peak memory 206472 kb
Host smart-f86fdd47-52b6-495e-ab10-e75e41aca01e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788812119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2788812119
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.488184243
Short name T559
Test name
Test status
Simulation time 205360623 ps
CPU time 2.3 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:14:58 PM PDT 24
Peak memory 216304 kb
Host smart-2db2dfcb-e153-434e-9e47-4d8901cacc61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=488184243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.488184243
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.3125778914
Short name T547
Test name
Test status
Simulation time 2215835522 ps
CPU time 4.18 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:15:00 PM PDT 24
Peak memory 216204 kb
Host smart-7390f96a-1666-49e2-98f1-6b2d14f7fa49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125778914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.3125778914
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1948167928
Short name T342
Test name
Test status
Simulation time 22240664 ps
CPU time 0.86 seconds
Started Jul 04 05:15:00 PM PDT 24
Finished Jul 04 05:15:02 PM PDT 24
Peak memory 205844 kb
Host smart-8903193b-6d90-49d1-8f10-7fd41119f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948167928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1948167928
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3271350498
Short name T325
Test name
Test status
Simulation time 23305119 ps
CPU time 0.78 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:14:57 PM PDT 24
Peak memory 205900 kb
Host smart-198310d3-e0a1-457c-9f5f-1e43d3837676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271350498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3271350498
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.195023292
Short name T992
Test name
Test status
Simulation time 1750645931 ps
CPU time 5.8 seconds
Started Jul 04 05:14:59 PM PDT 24
Finished Jul 04 05:15:05 PM PDT 24
Peak memory 224444 kb
Host smart-f748a194-e08f-41b5-94c8-ad6b3e460c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195023292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.195023292
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2640926289
Short name T671
Test name
Test status
Simulation time 141640943 ps
CPU time 0.75 seconds
Started Jul 04 05:14:57 PM PDT 24
Finished Jul 04 05:14:58 PM PDT 24
Peak memory 205748 kb
Host smart-27a403c8-b7b2-4d7a-9a71-6bfa2af73c24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640926289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2640926289
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.45086473
Short name T324
Test name
Test status
Simulation time 36818043 ps
CPU time 2.77 seconds
Started Jul 04 05:15:00 PM PDT 24
Finished Jul 04 05:15:03 PM PDT 24
Peak memory 232544 kb
Host smart-9b7bc66d-0913-4f6e-8380-9724f2ba682a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45086473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.45086473
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2035864771
Short name T625
Test name
Test status
Simulation time 18008875 ps
CPU time 0.84 seconds
Started Jul 04 05:15:00 PM PDT 24
Finished Jul 04 05:15:01 PM PDT 24
Peak memory 206504 kb
Host smart-28a7dac6-d208-49b6-ade8-f7eae97b75c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035864771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2035864771
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.1475060516
Short name T397
Test name
Test status
Simulation time 3134104226 ps
CPU time 42.61 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:15:39 PM PDT 24
Peak memory 250664 kb
Host smart-4a5df421-8a07-4b3b-8599-64c4aafda3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475060516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.1475060516
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.3033470945
Short name T583
Test name
Test status
Simulation time 13865500235 ps
CPU time 85.76 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 255636 kb
Host smart-f673c152-da33-42f2-a656-988b8707eb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033470945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.3033470945
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3155319229
Short name T428
Test name
Test status
Simulation time 5924349177 ps
CPU time 55.78 seconds
Started Jul 04 05:15:01 PM PDT 24
Finished Jul 04 05:15:57 PM PDT 24
Peak memory 249456 kb
Host smart-6b89c3af-6c8e-405b-8526-a4c45b360072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155319229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3155319229
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3264075640
Short name T292
Test name
Test status
Simulation time 183116251 ps
CPU time 7.5 seconds
Started Jul 04 05:14:58 PM PDT 24
Finished Jul 04 05:15:06 PM PDT 24
Peak memory 240196 kb
Host smart-b23d986b-f451-45bb-b14c-10234ed4d132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3264075640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3264075640
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3311854117
Short name T805
Test name
Test status
Simulation time 4416800341 ps
CPU time 52.59 seconds
Started Jul 04 05:14:57 PM PDT 24
Finished Jul 04 05:15:50 PM PDT 24
Peak memory 252028 kb
Host smart-1ee092fa-2ac3-4547-9ec1-8d388296c635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311854117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3311854117
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.4033344703
Short name T710
Test name
Test status
Simulation time 32089438 ps
CPU time 2.14 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:14:58 PM PDT 24
Peak memory 224060 kb
Host smart-f411cb85-359d-44b2-b0ba-2775f1cfbf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033344703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.4033344703
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.845478544
Short name T255
Test name
Test status
Simulation time 7046186993 ps
CPU time 24.85 seconds
Started Jul 04 05:15:00 PM PDT 24
Finished Jul 04 05:15:25 PM PDT 24
Peak memory 224468 kb
Host smart-357da37d-2f28-44da-90dd-e389e177db31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=845478544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.845478544
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.325616789
Short name T791
Test name
Test status
Simulation time 5239699631 ps
CPU time 21.59 seconds
Started Jul 04 05:14:59 PM PDT 24
Finished Jul 04 05:15:22 PM PDT 24
Peak memory 224488 kb
Host smart-1dc3a929-ce8b-4853-a564-b53cb7b38d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325616789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.325616789
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.883798172
Short name T758
Test name
Test status
Simulation time 10897634456 ps
CPU time 16.46 seconds
Started Jul 04 05:14:55 PM PDT 24
Finished Jul 04 05:15:12 PM PDT 24
Peak memory 224544 kb
Host smart-76afce30-e082-45b7-b0b2-55fa899dc7e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883798172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.883798172
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1227514838
Short name T405
Test name
Test status
Simulation time 427263553 ps
CPU time 4.17 seconds
Started Jul 04 05:15:01 PM PDT 24
Finished Jul 04 05:15:05 PM PDT 24
Peak memory 222476 kb
Host smart-c05089db-5d6c-4f86-8d7e-60ecd2928a64
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1227514838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1227514838
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.1740364433
Short name T146
Test name
Test status
Simulation time 20475362379 ps
CPU time 184.15 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:18:01 PM PDT 24
Peak memory 264424 kb
Host smart-f8126aff-a5dc-4a7e-9e47-81ce90a0bc23
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1740364433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.1740364433
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.4242752412
Short name T652
Test name
Test status
Simulation time 873410768 ps
CPU time 11.29 seconds
Started Jul 04 05:14:55 PM PDT 24
Finished Jul 04 05:15:07 PM PDT 24
Peak memory 216152 kb
Host smart-73ef9e55-e525-41bc-b625-7d8194a5d77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242752412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.4242752412
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.1747939412
Short name T30
Test name
Test status
Simulation time 10169536524 ps
CPU time 16.12 seconds
Started Jul 04 05:15:02 PM PDT 24
Finished Jul 04 05:15:18 PM PDT 24
Peak memory 216256 kb
Host smart-651aa02f-4e9f-4634-8f17-f0fc28a42c7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747939412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.1747939412
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1390944305
Short name T844
Test name
Test status
Simulation time 384714410 ps
CPU time 1.37 seconds
Started Jul 04 05:14:57 PM PDT 24
Finished Jul 04 05:14:58 PM PDT 24
Peak memory 216136 kb
Host smart-91e7925b-89fa-46fe-acc9-6c8a5a89e548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390944305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1390944305
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.3777652237
Short name T811
Test name
Test status
Simulation time 32715752 ps
CPU time 0.89 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:14:57 PM PDT 24
Peak memory 205892 kb
Host smart-1794ea9f-5ac7-412c-bf47-9ba91afc3c91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777652237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.3777652237
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.2043611737
Short name T928
Test name
Test status
Simulation time 9551530521 ps
CPU time 10.57 seconds
Started Jul 04 05:14:56 PM PDT 24
Finished Jul 04 05:15:07 PM PDT 24
Peak memory 251148 kb
Host smart-09b05cc9-7296-42e1-b7aa-ca078b7fa5d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043611737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.2043611737
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3953101058
Short name T475
Test name
Test status
Simulation time 14115605 ps
CPU time 0.71 seconds
Started Jul 04 05:15:04 PM PDT 24
Finished Jul 04 05:15:05 PM PDT 24
Peak memory 204860 kb
Host smart-9615eb57-9ef5-4127-8cce-d0cc962bf5d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953101058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3953101058
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2034567799
Short name T766
Test name
Test status
Simulation time 785629109 ps
CPU time 2.33 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:08 PM PDT 24
Peak memory 224408 kb
Host smart-64a23b68-cdbd-4740-8c85-d3696f2887a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034567799 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2034567799
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.814473866
Short name T584
Test name
Test status
Simulation time 131726245 ps
CPU time 0.76 seconds
Started Jul 04 05:14:59 PM PDT 24
Finished Jul 04 05:15:00 PM PDT 24
Peak memory 206536 kb
Host smart-3095730a-132c-4ced-8b5c-a882fc5f03ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=814473866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.814473866
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.795864289
Short name T847
Test name
Test status
Simulation time 4507945933 ps
CPU time 42.56 seconds
Started Jul 04 05:15:06 PM PDT 24
Finished Jul 04 05:15:49 PM PDT 24
Peak memory 249560 kb
Host smart-96da341b-01c7-4c72-90af-734181dccc7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795864289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.795864289
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.198234110
Short name T514
Test name
Test status
Simulation time 3555680007 ps
CPU time 7.33 seconds
Started Jul 04 05:15:12 PM PDT 24
Finished Jul 04 05:15:19 PM PDT 24
Peak memory 224456 kb
Host smart-3b7cd21c-a249-4580-ac18-1e6c290d5bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198234110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.198234110
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.1720556838
Short name T814
Test name
Test status
Simulation time 9798030948 ps
CPU time 54.33 seconds
Started Jul 04 05:15:04 PM PDT 24
Finished Jul 04 05:15:59 PM PDT 24
Peak memory 249552 kb
Host smart-48b0f508-3689-45c0-b4cf-e85993696295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720556838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.1720556838
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.1056414996
Short name T581
Test name
Test status
Simulation time 83917935 ps
CPU time 2.59 seconds
Started Jul 04 05:15:07 PM PDT 24
Finished Jul 04 05:15:10 PM PDT 24
Peak memory 232552 kb
Host smart-5227d076-022e-40bb-b493-77d9d69d4f41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056414996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.1056414996
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.2784866047
Short name T501
Test name
Test status
Simulation time 12354044389 ps
CPU time 21.82 seconds
Started Jul 04 05:15:01 PM PDT 24
Finished Jul 04 05:15:24 PM PDT 24
Peak memory 224580 kb
Host smart-8ca7b08f-b54d-4a4a-a06d-f38b9f2bfab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784866047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.2784866047
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3086181257
Short name T266
Test name
Test status
Simulation time 6455338296 ps
CPU time 21.28 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:27 PM PDT 24
Peak memory 234796 kb
Host smart-81fa148c-be7b-43e8-a173-47dc512c4834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3086181257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3086181257
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3870730032
Short name T921
Test name
Test status
Simulation time 8483133458 ps
CPU time 24.47 seconds
Started Jul 04 05:15:03 PM PDT 24
Finished Jul 04 05:15:28 PM PDT 24
Peak memory 240888 kb
Host smart-567633f9-22a6-4bcf-af75-a936c740305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870730032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3870730032
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.249160285
Short name T129
Test name
Test status
Simulation time 255644047 ps
CPU time 4.82 seconds
Started Jul 04 05:15:04 PM PDT 24
Finished Jul 04 05:15:09 PM PDT 24
Peak memory 222652 kb
Host smart-c5b1f798-6f08-481d-8210-ac7742b5e608
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=249160285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.249160285
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.2242676196
Short name T946
Test name
Test status
Simulation time 95877367 ps
CPU time 1 seconds
Started Jul 04 05:15:04 PM PDT 24
Finished Jul 04 05:15:05 PM PDT 24
Peak memory 206732 kb
Host smart-608643b1-b876-4f02-bf5a-4eac30dffd43
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242676196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.2242676196
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.931074983
Short name T861
Test name
Test status
Simulation time 25079566987 ps
CPU time 36.84 seconds
Started Jul 04 05:14:57 PM PDT 24
Finished Jul 04 05:15:34 PM PDT 24
Peak memory 216296 kb
Host smart-069d049d-8dd7-4748-94df-fad547ce08d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931074983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.931074983
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3176007520
Short name T70
Test name
Test status
Simulation time 4482275036 ps
CPU time 15.06 seconds
Started Jul 04 05:15:02 PM PDT 24
Finished Jul 04 05:15:18 PM PDT 24
Peak memory 216264 kb
Host smart-40cb3bce-423d-49cd-b7a0-714bf7ce1c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3176007520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3176007520
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.2390786021
Short name T363
Test name
Test status
Simulation time 68828126 ps
CPU time 0.91 seconds
Started Jul 04 05:15:02 PM PDT 24
Finished Jul 04 05:15:03 PM PDT 24
Peak memory 207288 kb
Host smart-71254b21-4a9c-4f19-b136-7aa846dee3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390786021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.2390786021
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1984694842
Short name T361
Test name
Test status
Simulation time 28020032 ps
CPU time 0.74 seconds
Started Jul 04 05:15:01 PM PDT 24
Finished Jul 04 05:15:02 PM PDT 24
Peak memory 205912 kb
Host smart-307e320e-c684-4650-b376-667482ed6bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984694842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1984694842
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.208981066
Short name T690
Test name
Test status
Simulation time 68601684917 ps
CPU time 21.32 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:27 PM PDT 24
Peak memory 232744 kb
Host smart-41c8fe2e-4af6-4fdb-a668-4024609c4cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208981066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.208981066
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1797272424
Short name T22
Test name
Test status
Simulation time 51056987 ps
CPU time 0.79 seconds
Started Jul 04 05:15:04 PM PDT 24
Finished Jul 04 05:15:05 PM PDT 24
Peak memory 205508 kb
Host smart-88fe27c1-44d2-43ca-98e3-77438cf84ef7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1797272424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1797272424
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.20472786
Short name T910
Test name
Test status
Simulation time 243488305 ps
CPU time 2.88 seconds
Started Jul 04 05:15:04 PM PDT 24
Finished Jul 04 05:15:07 PM PDT 24
Peak memory 224408 kb
Host smart-ae76e4c9-3721-4229-904a-f64ae47b0411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20472786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.20472786
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.167420947
Short name T403
Test name
Test status
Simulation time 15929737 ps
CPU time 0.79 seconds
Started Jul 04 05:15:02 PM PDT 24
Finished Jul 04 05:15:03 PM PDT 24
Peak memory 206532 kb
Host smart-51a39379-e93e-4be6-8b7e-0bb36b3e92db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167420947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.167420947
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.555546639
Short name T933
Test name
Test status
Simulation time 14909182 ps
CPU time 0.77 seconds
Started Jul 04 05:15:11 PM PDT 24
Finished Jul 04 05:15:12 PM PDT 24
Peak memory 215708 kb
Host smart-86a7de33-9ed2-4d64-98fb-d9e583f67161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555546639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.555546639
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.1337939021
Short name T173
Test name
Test status
Simulation time 7724499199 ps
CPU time 102.57 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:16:48 PM PDT 24
Peak memory 240940 kb
Host smart-fb13d8f6-cb06-4530-8521-80b8ae1db41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337939021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.1337939021
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3013514197
Short name T912
Test name
Test status
Simulation time 29288242332 ps
CPU time 107.12 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:16:53 PM PDT 24
Peak memory 251752 kb
Host smart-6bc90e67-61a3-49c7-8440-9905c1c30de5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013514197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3013514197
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.984022028
Short name T914
Test name
Test status
Simulation time 212180198 ps
CPU time 8.97 seconds
Started Jul 04 05:15:02 PM PDT 24
Finished Jul 04 05:15:11 PM PDT 24
Peak memory 241152 kb
Host smart-86fc6bcc-f09c-40aa-8d9e-e7e4d78b0a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984022028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.984022028
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.1916880255
Short name T845
Test name
Test status
Simulation time 3512452527 ps
CPU time 18.21 seconds
Started Jul 04 05:15:06 PM PDT 24
Finished Jul 04 05:15:25 PM PDT 24
Peak memory 239464 kb
Host smart-ee63ba26-bf03-447f-a5b5-e69cdcf53d1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1916880255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.1916880255
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.3335003774
Short name T875
Test name
Test status
Simulation time 124555392 ps
CPU time 3.27 seconds
Started Jul 04 05:15:06 PM PDT 24
Finished Jul 04 05:15:09 PM PDT 24
Peak memory 232520 kb
Host smart-1132e039-c36e-4017-be7f-53cdcc8e628a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335003774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.3335003774
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.821907344
Short name T345
Test name
Test status
Simulation time 9322217762 ps
CPU time 28.03 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:34 PM PDT 24
Peak memory 232708 kb
Host smart-0cbaf9ef-c716-448f-863a-969a07196bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=821907344 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.821907344
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3010743808
Short name T971
Test name
Test status
Simulation time 610893939 ps
CPU time 3.24 seconds
Started Jul 04 05:15:11 PM PDT 24
Finished Jul 04 05:15:15 PM PDT 24
Peak memory 224348 kb
Host smart-dd3be6f7-d983-42dd-9ee3-17903e697d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010743808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3010743808
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.1304048751
Short name T853
Test name
Test status
Simulation time 155158368 ps
CPU time 3.61 seconds
Started Jul 04 05:15:13 PM PDT 24
Finished Jul 04 05:15:17 PM PDT 24
Peak memory 232600 kb
Host smart-d34432a6-3144-43e3-9f85-e035550b8e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304048751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.1304048751
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.1545526477
Short name T732
Test name
Test status
Simulation time 570493816 ps
CPU time 5.41 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:11 PM PDT 24
Peak memory 218988 kb
Host smart-0acddf02-c8b2-4c4a-85c2-75afbac1e258
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1545526477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.1545526477
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1096274953
Short name T488
Test name
Test status
Simulation time 28506405790 ps
CPU time 76.51 seconds
Started Jul 04 05:15:06 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 249204 kb
Host smart-b89429e8-3c07-4cac-bb23-88f5d6a98cba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096274953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1096274953
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2107992390
Short name T383
Test name
Test status
Simulation time 1083819268 ps
CPU time 4.49 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:10 PM PDT 24
Peak memory 218424 kb
Host smart-2113e815-6add-46cc-8d04-e87ae1f12be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107992390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2107992390
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.460239493
Short name T628
Test name
Test status
Simulation time 1270786433 ps
CPU time 6.75 seconds
Started Jul 04 05:15:04 PM PDT 24
Finished Jul 04 05:15:11 PM PDT 24
Peak memory 216196 kb
Host smart-34efbdb5-0280-4de9-9e1c-c68cd65c12ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=460239493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.460239493
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.502413976
Short name T495
Test name
Test status
Simulation time 50162110 ps
CPU time 0.77 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:06 PM PDT 24
Peak memory 205896 kb
Host smart-e355fabf-e8e6-47c1-8267-47a9e233172b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502413976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.502413976
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1017490184
Short name T527
Test name
Test status
Simulation time 136881018 ps
CPU time 0.91 seconds
Started Jul 04 05:15:06 PM PDT 24
Finished Jul 04 05:15:07 PM PDT 24
Peak memory 205868 kb
Host smart-9865838a-0b43-405d-a86d-8ecb072e3f7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017490184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1017490184
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.1446815250
Short name T636
Test name
Test status
Simulation time 655454104 ps
CPU time 4.38 seconds
Started Jul 04 05:15:13 PM PDT 24
Finished Jul 04 05:15:18 PM PDT 24
Peak memory 232520 kb
Host smart-a3af80b4-a3d0-4d79-bbb6-5f8aecb30746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446815250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.1446815250
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.1243741408
Short name T573
Test name
Test status
Simulation time 64930174 ps
CPU time 0.72 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:11 PM PDT 24
Peak memory 205420 kb
Host smart-75d6c67c-e995-4250-bdf1-ecdc9ebe93a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1243741408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
1243741408
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.3834130736
Short name T897
Test name
Test status
Simulation time 198025209 ps
CPU time 2.66 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:13 PM PDT 24
Peak memory 232552 kb
Host smart-00ae150a-af51-42e5-9e63-716a50757f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834130736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.3834130736
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2772963307
Short name T377
Test name
Test status
Simulation time 32983401 ps
CPU time 0.75 seconds
Started Jul 04 05:15:11 PM PDT 24
Finished Jul 04 05:15:12 PM PDT 24
Peak memory 206532 kb
Host smart-9138246e-ddde-481b-b6e6-919093fd275c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772963307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2772963307
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.859457097
Short name T215
Test name
Test status
Simulation time 7712852128 ps
CPU time 35.93 seconds
Started Jul 04 05:15:09 PM PDT 24
Finished Jul 04 05:15:46 PM PDT 24
Peak memory 249212 kb
Host smart-459aa8e1-170f-46b3-8842-dc23cacab7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859457097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.859457097
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4003921383
Short name T23
Test name
Test status
Simulation time 3270575765 ps
CPU time 23.11 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:33 PM PDT 24
Peak memory 224568 kb
Host smart-e010b148-54c7-4c4f-bfe7-784ba63a3c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003921383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4003921383
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.507487661
Short name T308
Test name
Test status
Simulation time 2095271033 ps
CPU time 25.44 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:36 PM PDT 24
Peak memory 217908 kb
Host smart-96555d7c-29d7-475f-a86c-dadd44168977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507487661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idle
.507487661
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3421722918
Short name T997
Test name
Test status
Simulation time 1874614993 ps
CPU time 28.88 seconds
Started Jul 04 05:15:09 PM PDT 24
Finished Jul 04 05:15:38 PM PDT 24
Peak memory 253944 kb
Host smart-8268670f-7f38-4b40-bc02-651721db32d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421722918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3421722918
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.812822074
Short name T257
Test name
Test status
Simulation time 284547118 ps
CPU time 5.95 seconds
Started Jul 04 05:15:12 PM PDT 24
Finished Jul 04 05:15:18 PM PDT 24
Peak memory 224336 kb
Host smart-6b4b38f0-b8dc-48c8-9fb6-6ab8c754277d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812822074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.812822074
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.1086626260
Short name T898
Test name
Test status
Simulation time 6125618954 ps
CPU time 47.03 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:52 PM PDT 24
Peak memory 232740 kb
Host smart-c53200c2-ebd5-4d91-bd26-ed79ef89e442
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086626260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.1086626260
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3896524942
Short name T595
Test name
Test status
Simulation time 13752219744 ps
CPU time 12 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:17 PM PDT 24
Peak memory 232632 kb
Host smart-1131d42e-d29c-4d58-8da5-a5058346a35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896524942 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3896524942
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2348692796
Short name T192
Test name
Test status
Simulation time 910759559 ps
CPU time 2.87 seconds
Started Jul 04 05:15:05 PM PDT 24
Finished Jul 04 05:15:08 PM PDT 24
Peak memory 232636 kb
Host smart-7ea5c038-f94c-4746-8dfc-6a24d32fb142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348692796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2348692796
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.4051984223
Short name T624
Test name
Test status
Simulation time 592703385 ps
CPU time 3.36 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:13 PM PDT 24
Peak memory 220372 kb
Host smart-210b6aa2-e4aa-4be2-a716-09232715f80d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4051984223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.4051984223
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3304748546
Short name T21
Test name
Test status
Simulation time 3057667025 ps
CPU time 25.97 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:36 PM PDT 24
Peak memory 218092 kb
Host smart-f4273778-8248-4ee9-a69c-0829cedac1a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304748546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3304748546
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2736283621
Short name T448
Test name
Test status
Simulation time 1304211954 ps
CPU time 6.5 seconds
Started Jul 04 05:15:06 PM PDT 24
Finished Jul 04 05:15:13 PM PDT 24
Peak memory 216184 kb
Host smart-dcb617a8-964a-4963-8cdc-8bef7c9936a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736283621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2736283621
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.255293573
Short name T905
Test name
Test status
Simulation time 1487432591 ps
CPU time 4.67 seconds
Started Jul 04 05:15:07 PM PDT 24
Finished Jul 04 05:15:12 PM PDT 24
Peak memory 216152 kb
Host smart-1adeca1b-b5b0-4086-9cd5-326c6adcd1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255293573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.255293573
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.539864125
Short name T684
Test name
Test status
Simulation time 926054444 ps
CPU time 2.06 seconds
Started Jul 04 05:15:04 PM PDT 24
Finished Jul 04 05:15:07 PM PDT 24
Peak memory 216132 kb
Host smart-e5103af5-3508-43ce-aa1e-aa7ed0dbc8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539864125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.539864125
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.90846572
Short name T985
Test name
Test status
Simulation time 51491560 ps
CPU time 0.88 seconds
Started Jul 04 05:15:13 PM PDT 24
Finished Jul 04 05:15:14 PM PDT 24
Peak memory 206896 kb
Host smart-45b39cf4-9eeb-4c66-b0c5-0c5c01c85550
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90846572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.90846572
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.2185221521
Short name T908
Test name
Test status
Simulation time 561182324 ps
CPU time 2.65 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:20 PM PDT 24
Peak memory 232540 kb
Host smart-43ec793e-045b-49b0-b7ad-a1e430303567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2185221521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.2185221521
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4171512270
Short name T779
Test name
Test status
Simulation time 58860487 ps
CPU time 0.7 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:12:34 PM PDT 24
Peak memory 205784 kb
Host smart-3f9b4547-f273-4a66-9d11-0dcb06b2e15e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4171512270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
171512270
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3319652992
Short name T550
Test name
Test status
Simulation time 756079072 ps
CPU time 10.3 seconds
Started Jul 04 05:12:32 PM PDT 24
Finished Jul 04 05:12:42 PM PDT 24
Peak memory 232632 kb
Host smart-6ee30a0f-d64e-4f32-bda2-0618b78a0423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319652992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3319652992
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2405294928
Short name T320
Test name
Test status
Simulation time 16206551 ps
CPU time 0.8 seconds
Started Jul 04 05:12:36 PM PDT 24
Finished Jul 04 05:12:37 PM PDT 24
Peak memory 206548 kb
Host smart-2614dfd0-76d4-4eff-af3f-b5dff498550a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405294928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2405294928
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3439155319
Short name T372
Test name
Test status
Simulation time 20176689 ps
CPU time 0.72 seconds
Started Jul 04 05:12:31 PM PDT 24
Finished Jul 04 05:12:32 PM PDT 24
Peak memory 215740 kb
Host smart-5f91b125-c913-4fe3-94a7-fda504d8c657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439155319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3439155319
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.1666202006
Short name T582
Test name
Test status
Simulation time 21429732792 ps
CPU time 243.91 seconds
Started Jul 04 05:12:35 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 265560 kb
Host smart-758ba60b-a4d1-4600-970f-4c2eed808a91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666202006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.1666202006
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2915218445
Short name T467
Test name
Test status
Simulation time 12702710855 ps
CPU time 42.22 seconds
Started Jul 04 05:12:31 PM PDT 24
Finished Jul 04 05:13:13 PM PDT 24
Peak memory 238352 kb
Host smart-f6d13999-524a-45f6-876b-e478f1685147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915218445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2915218445
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.392278311
Short name T935
Test name
Test status
Simulation time 2902868192 ps
CPU time 8.32 seconds
Started Jul 04 05:12:34 PM PDT 24
Finished Jul 04 05:12:42 PM PDT 24
Peak memory 236464 kb
Host smart-98a7a117-164a-4c04-a14c-72802b440511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392278311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.392278311
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1316206232
Short name T645
Test name
Test status
Simulation time 37666118768 ps
CPU time 72.12 seconds
Started Jul 04 05:12:32 PM PDT 24
Finished Jul 04 05:13:44 PM PDT 24
Peak memory 240340 kb
Host smart-b9a60e9e-91d3-4a56-aa3f-4d1de6323279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316206232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1316206232
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1228926042
Short name T718
Test name
Test status
Simulation time 1900028815 ps
CPU time 6.88 seconds
Started Jul 04 05:12:34 PM PDT 24
Finished Jul 04 05:12:41 PM PDT 24
Peak memory 224392 kb
Host smart-7a0942b9-f0c4-4f60-971f-79316a7a79c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228926042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1228926042
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1939499771
Short name T859
Test name
Test status
Simulation time 5693077409 ps
CPU time 22.34 seconds
Started Jul 04 05:12:34 PM PDT 24
Finished Jul 04 05:12:57 PM PDT 24
Peak memory 224500 kb
Host smart-ee740187-b406-40c9-bb3d-168e89e5d260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1939499771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1939499771
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.1741789842
Short name T666
Test name
Test status
Simulation time 5135828428 ps
CPU time 17.27 seconds
Started Jul 04 05:12:32 PM PDT 24
Finished Jul 04 05:12:49 PM PDT 24
Peak memory 232736 kb
Host smart-7db0f245-2d08-4929-a9a6-1ebf3ac8ebbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741789842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.1741789842
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.1921603761
Short name T609
Test name
Test status
Simulation time 1589950072 ps
CPU time 9.34 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:12:42 PM PDT 24
Peak memory 232644 kb
Host smart-c9d31a0f-cfa7-428e-9884-78a5ea76fbfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921603761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.1921603761
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.3268647517
Short name T620
Test name
Test status
Simulation time 8086444146 ps
CPU time 7.93 seconds
Started Jul 04 05:12:31 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 219452 kb
Host smart-4deb7a09-d131-455d-b9f3-44dd25d94a13
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3268647517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.3268647517
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.703977414
Short name T62
Test name
Test status
Simulation time 72608312 ps
CPU time 1.21 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:12:35 PM PDT 24
Peak memory 236552 kb
Host smart-4ce5d207-245b-4deb-af3d-c63f12d10198
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=703977414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.703977414
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.1724345786
Short name T533
Test name
Test status
Simulation time 2018225903 ps
CPU time 19.81 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:12:53 PM PDT 24
Peak memory 219356 kb
Host smart-2d0f5e28-52d0-4fb2-a038-dc540d129427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724345786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.1724345786
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.4065992044
Short name T116
Test name
Test status
Simulation time 1553262557 ps
CPU time 5.97 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 216156 kb
Host smart-ab91a734-eead-4ecf-99e4-0b4ab74bdfb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065992044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.4065992044
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3307245128
Short name T416
Test name
Test status
Simulation time 22107732 ps
CPU time 0.94 seconds
Started Jul 04 05:12:33 PM PDT 24
Finished Jul 04 05:12:35 PM PDT 24
Peak memory 207108 kb
Host smart-b3ab95b9-3a96-4dd8-91f5-9f5d8b7ad9c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307245128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3307245128
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.1441699824
Short name T579
Test name
Test status
Simulation time 12788762 ps
CPU time 0.68 seconds
Started Jul 04 05:12:34 PM PDT 24
Finished Jul 04 05:12:35 PM PDT 24
Peak memory 205560 kb
Host smart-0c3f8862-cbf2-406f-8e50-677629f9bc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441699824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.1441699824
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.2596888548
Short name T880
Test name
Test status
Simulation time 637602776 ps
CPU time 3.99 seconds
Started Jul 04 05:12:35 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 240708 kb
Host smart-8d00c948-7e23-42f9-b849-718ce46b1f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2596888548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.2596888548
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.1488175009
Short name T425
Test name
Test status
Simulation time 22207075 ps
CPU time 0.73 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:18 PM PDT 24
Peak memory 205468 kb
Host smart-9c4df284-1246-417e-a82f-c371fce5ea0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488175009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
1488175009
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.700669617
Short name T631
Test name
Test status
Simulation time 33598747 ps
CPU time 2.41 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:13 PM PDT 24
Peak memory 232644 kb
Host smart-bda7cdde-3d98-495b-9d38-c90a584249c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700669617 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.700669617
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2952708848
Short name T647
Test name
Test status
Simulation time 18172161 ps
CPU time 0.76 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:18 PM PDT 24
Peak memory 205776 kb
Host smart-82534a27-a141-4d03-8fd7-18110ebcc37d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952708848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2952708848
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1853105604
Short name T716
Test name
Test status
Simulation time 2016991539 ps
CPU time 30.55 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:41 PM PDT 24
Peak memory 238128 kb
Host smart-ca18673b-c7c5-4368-ae4a-dd566a36e299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853105604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1853105604
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.1090213596
Short name T480
Test name
Test status
Simulation time 3286947816 ps
CPU time 11.92 seconds
Started Jul 04 05:15:18 PM PDT 24
Finished Jul 04 05:15:31 PM PDT 24
Peak memory 217564 kb
Host smart-af303f3c-8560-4006-894a-2191b3c5c0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090213596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.1090213596
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.815965630
Short name T149
Test name
Test status
Simulation time 34667746939 ps
CPU time 137.16 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:17:36 PM PDT 24
Peak memory 240988 kb
Host smart-c2ded9e0-2f1e-4bc8-94d1-a8b4ecdbb3dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815965630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idle
.815965630
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.4230092108
Short name T724
Test name
Test status
Simulation time 730029835 ps
CPU time 11.59 seconds
Started Jul 04 05:15:09 PM PDT 24
Finished Jul 04 05:15:21 PM PDT 24
Peak memory 240788 kb
Host smart-c520a024-1475-486f-89ca-612fb8ad4980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230092108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.4230092108
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.4145472893
Short name T821
Test name
Test status
Simulation time 25370767142 ps
CPU time 92.96 seconds
Started Jul 04 05:15:16 PM PDT 24
Finished Jul 04 05:16:50 PM PDT 24
Peak memory 255484 kb
Host smart-e2a9ac65-a5af-4b93-bc63-17ba833a6a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145472893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.4145472893
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.13365297
Short name T596
Test name
Test status
Simulation time 5159995717 ps
CPU time 22.82 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:40 PM PDT 24
Peak memory 232664 kb
Host smart-5f9c0b7d-9288-4479-a9dd-ce0e7af6dc37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13365297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.13365297
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.772939282
Short name T4
Test name
Test status
Simulation time 1936649717 ps
CPU time 9 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:19 PM PDT 24
Peak memory 224288 kb
Host smart-0af2ef6e-acde-43d5-a43c-9b90a9664485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=772939282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.772939282
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1304441013
Short name T597
Test name
Test status
Simulation time 316220879 ps
CPU time 4.61 seconds
Started Jul 04 05:15:11 PM PDT 24
Finished Jul 04 05:15:16 PM PDT 24
Peak memory 232604 kb
Host smart-a4acdda3-3e2d-4294-b31e-2f9635d349ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304441013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1304441013
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1665117805
Short name T263
Test name
Test status
Simulation time 72894316759 ps
CPU time 26.47 seconds
Started Jul 04 05:15:11 PM PDT 24
Finished Jul 04 05:15:37 PM PDT 24
Peak memory 237892 kb
Host smart-47a3c2ec-9ce8-4401-aaca-3a802559a815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665117805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1665117805
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.4221189933
Short name T768
Test name
Test status
Simulation time 141395346 ps
CPU time 4.71 seconds
Started Jul 04 05:15:08 PM PDT 24
Finished Jul 04 05:15:13 PM PDT 24
Peak memory 222964 kb
Host smart-11e517c9-65d5-4857-b491-91146b7be88d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4221189933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.4221189933
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.2176082992
Short name T829
Test name
Test status
Simulation time 39698299 ps
CPU time 0.71 seconds
Started Jul 04 05:15:11 PM PDT 24
Finished Jul 04 05:15:12 PM PDT 24
Peak memory 205668 kb
Host smart-bc104a8d-6c8c-41d3-9739-bcdad40148d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176082992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.2176082992
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2604112445
Short name T602
Test name
Test status
Simulation time 1823898008 ps
CPU time 4.01 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:14 PM PDT 24
Peak memory 216140 kb
Host smart-ff173a1c-b605-40f0-95ee-053c1e5d73e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604112445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2604112445
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.1976638341
Short name T601
Test name
Test status
Simulation time 100924198 ps
CPU time 1.32 seconds
Started Jul 04 05:15:09 PM PDT 24
Finished Jul 04 05:15:11 PM PDT 24
Peak memory 207824 kb
Host smart-574b60d2-fb92-4528-a344-40d4ca914f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976638341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.1976638341
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1754141509
Short name T679
Test name
Test status
Simulation time 14071868 ps
CPU time 0.75 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:11 PM PDT 24
Peak memory 205904 kb
Host smart-191c8696-2cad-4442-a200-00971e9864f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754141509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1754141509
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1644886134
Short name T186
Test name
Test status
Simulation time 8816552214 ps
CPU time 31.89 seconds
Started Jul 04 05:15:10 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 249140 kb
Host smart-46453d44-2bfa-41ef-adff-5bec2aa364e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644886134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1644886134
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1346658445
Short name T659
Test name
Test status
Simulation time 14639101 ps
CPU time 0.7 seconds
Started Jul 04 05:15:18 PM PDT 24
Finished Jul 04 05:15:20 PM PDT 24
Peak memory 205472 kb
Host smart-0f541f6b-10d1-4cc3-9014-42d4b419f07e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1346658445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1346658445
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.2000817422
Short name T926
Test name
Test status
Simulation time 81636271 ps
CPU time 2.42 seconds
Started Jul 04 05:15:18 PM PDT 24
Finished Jul 04 05:15:21 PM PDT 24
Peak memory 224360 kb
Host smart-ca9c6f06-bc71-4e56-9d41-959a075bc925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000817422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.2000817422
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1332899273
Short name T949
Test name
Test status
Simulation time 40013202 ps
CPU time 0.81 seconds
Started Jul 04 05:15:16 PM PDT 24
Finished Jul 04 05:15:18 PM PDT 24
Peak memory 206520 kb
Host smart-4d21b628-88eb-4122-8dcd-3343b468d41a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332899273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1332899273
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1599881436
Short name T788
Test name
Test status
Simulation time 3035807348 ps
CPU time 51.18 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:16:09 PM PDT 24
Peak memory 253368 kb
Host smart-f43bb9e9-eceb-4062-9d4a-543d5d2d5a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599881436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1599881436
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.1079594923
Short name T656
Test name
Test status
Simulation time 8938185897 ps
CPU time 65.33 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 257360 kb
Host smart-95d841dd-6a9e-452d-8bd7-0475d93d3423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079594923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.1079594923
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3372887758
Short name T637
Test name
Test status
Simulation time 80548085366 ps
CPU time 138.56 seconds
Started Jul 04 05:15:18 PM PDT 24
Finished Jul 04 05:17:37 PM PDT 24
Peak memory 250836 kb
Host smart-f7044198-18e5-49c6-93b4-f58c00a69b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372887758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3372887758
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1758301969
Short name T293
Test name
Test status
Simulation time 1975618780 ps
CPU time 27.51 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:46 PM PDT 24
Peak memory 224372 kb
Host smart-2a5d1acf-2e3a-4e99-acc6-87a31bf32b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758301969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1758301969
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.1497912939
Short name T230
Test name
Test status
Simulation time 220403205903 ps
CPU time 271.46 seconds
Started Jul 04 05:15:19 PM PDT 24
Finished Jul 04 05:19:51 PM PDT 24
Peak memory 251468 kb
Host smart-3e07f9ca-2cab-4f8b-8bbc-d7917ad97b78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497912939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.1497912939
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.1886162676
Short name T407
Test name
Test status
Simulation time 420464077 ps
CPU time 2.27 seconds
Started Jul 04 05:15:23 PM PDT 24
Finished Jul 04 05:15:25 PM PDT 24
Peak memory 222876 kb
Host smart-c2abcfe5-714d-45b7-ac72-db998ccfa52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886162676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.1886162676
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.1242598474
Short name T558
Test name
Test status
Simulation time 12798605428 ps
CPU time 25.32 seconds
Started Jul 04 05:15:19 PM PDT 24
Finished Jul 04 05:15:45 PM PDT 24
Peak memory 232664 kb
Host smart-4a59734f-d5e9-4307-a4f7-f4223df024ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242598474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.1242598474
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.812849375
Short name T617
Test name
Test status
Simulation time 328434020 ps
CPU time 3.85 seconds
Started Jul 04 05:15:19 PM PDT 24
Finished Jul 04 05:15:23 PM PDT 24
Peak memory 224404 kb
Host smart-ab74e5fb-2120-44f2-98e7-d37bb256e26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812849375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swap
.812849375
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2640001587
Short name T490
Test name
Test status
Simulation time 42181384 ps
CPU time 2.5 seconds
Started Jul 04 05:15:18 PM PDT 24
Finished Jul 04 05:15:21 PM PDT 24
Peak memory 224424 kb
Host smart-1dbfad3e-1eec-4cb3-a96f-9aa8060dc4c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640001587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2640001587
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.880744822
Short name T575
Test name
Test status
Simulation time 185088064 ps
CPU time 4.31 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:21 PM PDT 24
Peak memory 220444 kb
Host smart-76a049ff-fcc5-4cdd-ac9e-dae653a1cf9a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=880744822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dire
ct.880744822
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2558317540
Short name T934
Test name
Test status
Simulation time 19074028410 ps
CPU time 52.77 seconds
Started Jul 04 05:15:16 PM PDT 24
Finished Jul 04 05:16:10 PM PDT 24
Peak memory 249176 kb
Host smart-8d12574a-9ad3-4384-ad5b-aba83c58b164
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558317540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2558317540
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2389003559
Short name T701
Test name
Test status
Simulation time 1539515092 ps
CPU time 16.89 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:35 PM PDT 24
Peak memory 216392 kb
Host smart-d630d5c9-c979-4090-892f-d43a5eaeb9a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389003559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2389003559
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1334943020
Short name T744
Test name
Test status
Simulation time 17104492963 ps
CPU time 12.5 seconds
Started Jul 04 05:15:19 PM PDT 24
Finished Jul 04 05:15:32 PM PDT 24
Peak memory 216268 kb
Host smart-6da12e90-d80c-4595-bbe1-f64be96b74f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1334943020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1334943020
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.3850854481
Short name T691
Test name
Test status
Simulation time 28339298 ps
CPU time 1.36 seconds
Started Jul 04 05:15:20 PM PDT 24
Finished Jul 04 05:15:21 PM PDT 24
Peak memory 216104 kb
Host smart-ba02b5bd-ee2e-4a6d-a88a-7d4bf9bc23c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850854481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.3850854481
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.474082288
Short name T435
Test name
Test status
Simulation time 69557453 ps
CPU time 0.87 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:19 PM PDT 24
Peak memory 205928 kb
Host smart-35542a01-611c-4e60-b619-b4db1281d553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474082288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.474082288
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.2953540978
Short name T686
Test name
Test status
Simulation time 3100282480 ps
CPU time 14.47 seconds
Started Jul 04 05:15:15 PM PDT 24
Finished Jul 04 05:15:30 PM PDT 24
Peak memory 237624 kb
Host smart-4c1b848a-03bb-44ef-aaf3-4aeb9dafc090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953540978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.2953540978
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1876316244
Short name T841
Test name
Test status
Simulation time 26452737 ps
CPU time 0.71 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:25 PM PDT 24
Peak memory 205424 kb
Host smart-21190b3e-cfce-42ab-8a8d-647f189d010d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876316244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1876316244
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.487512201
Short name T155
Test name
Test status
Simulation time 963422268 ps
CPU time 6.12 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:24 PM PDT 24
Peak memory 224376 kb
Host smart-5b329c7c-3312-497c-b03e-f4b13179a600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487512201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.487512201
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.4126823053
Short name T749
Test name
Test status
Simulation time 32656676 ps
CPU time 0.79 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:19 PM PDT 24
Peak memory 205480 kb
Host smart-53eec103-4cd4-43ee-aca2-f0c0f86d77e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126823053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.4126823053
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2911703354
Short name T423
Test name
Test status
Simulation time 134937370048 ps
CPU time 165.09 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:18:03 PM PDT 24
Peak memory 252324 kb
Host smart-d60565c6-0ffb-4642-89b6-0dce19677e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911703354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2911703354
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.1832866647
Short name T707
Test name
Test status
Simulation time 27838566215 ps
CPU time 48 seconds
Started Jul 04 05:15:20 PM PDT 24
Finished Jul 04 05:16:08 PM PDT 24
Peak memory 249184 kb
Host smart-530f5421-4c22-4abe-994d-dd38ddd3f6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832866647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.1832866647
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3548111019
Short name T834
Test name
Test status
Simulation time 8475869464 ps
CPU time 42.93 seconds
Started Jul 04 05:15:18 PM PDT 24
Finished Jul 04 05:16:01 PM PDT 24
Peak memory 235100 kb
Host smart-bf50d322-0494-43c0-8413-7bab902f7e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548111019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3548111019
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.3330631420
Short name T585
Test name
Test status
Simulation time 4852418158 ps
CPU time 16.48 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:35 PM PDT 24
Peak memory 240908 kb
Host smart-f4c3f3eb-13ee-4378-ae2f-279ff2d81a90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330631420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.3330631420
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.431801561
Short name T261
Test name
Test status
Simulation time 17598325061 ps
CPU time 68.4 seconds
Started Jul 04 05:15:16 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 249132 kb
Host smart-bb54b43e-4df0-4ae0-9c6b-c2e037212430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431801561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.431801561
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2536371731
Short name T965
Test name
Test status
Simulation time 1950148635 ps
CPU time 12.19 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:30 PM PDT 24
Peak memory 232664 kb
Host smart-b61f5276-71ba-4aed-90ba-3a114e420135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536371731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2536371731
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.673796301
Short name T288
Test name
Test status
Simulation time 4166219863 ps
CPU time 34.67 seconds
Started Jul 04 05:15:21 PM PDT 24
Finished Jul 04 05:15:56 PM PDT 24
Peak memory 232700 kb
Host smart-9fc4473d-f169-43a1-9e56-9fa00741609e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673796301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.673796301
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3366595934
Short name T990
Test name
Test status
Simulation time 3726405125 ps
CPU time 11.04 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:29 PM PDT 24
Peak memory 238568 kb
Host smart-25249fd7-9bcd-4e77-9133-23d9493ce2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366595934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3366595934
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.297697627
Short name T11
Test name
Test status
Simulation time 2111758889 ps
CPU time 5.57 seconds
Started Jul 04 05:15:16 PM PDT 24
Finished Jul 04 05:15:22 PM PDT 24
Peak memory 232588 kb
Host smart-db65827c-29c6-42c4-81c6-77fe70cf7b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297697627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.297697627
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.2289670330
Short name T566
Test name
Test status
Simulation time 2138948593 ps
CPU time 10.03 seconds
Started Jul 04 05:15:15 PM PDT 24
Finished Jul 04 05:15:25 PM PDT 24
Peak memory 220140 kb
Host smart-84622337-7e58-419b-89e2-86a032b577f8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2289670330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.2289670330
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2067646907
Short name T14
Test name
Test status
Simulation time 24348742042 ps
CPU time 58.85 seconds
Started Jul 04 05:15:23 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 240976 kb
Host smart-23ed2c83-b79f-4726-b789-f5cb9663b730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067646907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2067646907
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.3750311710
Short name T307
Test name
Test status
Simulation time 2833927246 ps
CPU time 24.64 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:43 PM PDT 24
Peak memory 220264 kb
Host smart-42019110-ccaa-434d-984e-51506de9bbc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3750311710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.3750311710
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.113387011
Short name T952
Test name
Test status
Simulation time 12029944451 ps
CPU time 10.53 seconds
Started Jul 04 05:15:19 PM PDT 24
Finished Jul 04 05:15:30 PM PDT 24
Peak memory 216280 kb
Host smart-17ecd6aa-c33b-42d2-aace-e4a4959da00e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113387011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.113387011
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1663535376
Short name T1013
Test name
Test status
Simulation time 28312745 ps
CPU time 1.03 seconds
Started Jul 04 05:15:19 PM PDT 24
Finished Jul 04 05:15:20 PM PDT 24
Peak memory 206940 kb
Host smart-f1e1bb7d-1c93-43d2-8427-f7d49259cc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663535376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1663535376
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.3279325522
Short name T77
Test name
Test status
Simulation time 112340835 ps
CPU time 0.75 seconds
Started Jul 04 05:15:19 PM PDT 24
Finished Jul 04 05:15:20 PM PDT 24
Peak memory 205852 kb
Host smart-3dddeea0-422b-4d28-81da-41bac7e3a40f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279325522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.3279325522
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.297615229
Short name T282
Test name
Test status
Simulation time 1523639814 ps
CPU time 4.33 seconds
Started Jul 04 05:15:17 PM PDT 24
Finished Jul 04 05:15:22 PM PDT 24
Peak memory 224488 kb
Host smart-02546b11-c667-465c-938c-3ed196ad305d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297615229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.297615229
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.724595854
Short name T959
Test name
Test status
Simulation time 32778022 ps
CPU time 0.72 seconds
Started Jul 04 05:15:23 PM PDT 24
Finished Jul 04 05:15:24 PM PDT 24
Peak memory 205784 kb
Host smart-501aeb8c-5f79-43fc-9a0a-3d105f1a5687
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=724595854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.724595854
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3198808692
Short name T578
Test name
Test status
Simulation time 1831626939 ps
CPU time 8.2 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:15:34 PM PDT 24
Peak memory 232656 kb
Host smart-e937af77-03b7-4ee8-8136-f4f56fd9f8b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198808692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3198808692
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1209812613
Short name T333
Test name
Test status
Simulation time 18813582 ps
CPU time 0.79 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:25 PM PDT 24
Peak memory 206536 kb
Host smart-4868a834-cb21-4f29-9285-767250f773b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209812613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1209812613
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.3165049078
Short name T980
Test name
Test status
Simulation time 274980061340 ps
CPU time 235.78 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:19:23 PM PDT 24
Peak memory 264644 kb
Host smart-2cc2abc0-7247-41a3-ad39-c9ce19ff491d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165049078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.3165049078
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.875628166
Short name T563
Test name
Test status
Simulation time 500663320023 ps
CPU time 354.64 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:21:19 PM PDT 24
Peak memory 255652 kb
Host smart-916ee385-7cf6-4162-87dd-2f7fa36db7b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875628166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.875628166
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.888281825
Short name T762
Test name
Test status
Simulation time 1882896401 ps
CPU time 8.71 seconds
Started Jul 04 05:15:27 PM PDT 24
Finished Jul 04 05:15:36 PM PDT 24
Peak memory 232628 kb
Host smart-b49d0ff1-03f3-4744-b548-cdc767d36add
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888281825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.888281825
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.534403294
Short name T238
Test name
Test status
Simulation time 507193137923 ps
CPU time 246.67 seconds
Started Jul 04 05:15:28 PM PDT 24
Finished Jul 04 05:19:35 PM PDT 24
Peak memory 252056 kb
Host smart-11d5364d-93b7-4ad1-9e84-cf08f128d7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534403294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmds
.534403294
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2598234463
Short name T185
Test name
Test status
Simulation time 7924657798 ps
CPU time 11.54 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:36 PM PDT 24
Peak memory 232720 kb
Host smart-562fc14d-d0c3-4dba-bbd7-01827c0601b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598234463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2598234463
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.1825702895
Short name T166
Test name
Test status
Simulation time 6343751498 ps
CPU time 44.23 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:16:09 PM PDT 24
Peak memory 232704 kb
Host smart-85d5e212-e83e-4511-bd8c-dff777f3fa20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825702895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.1825702895
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.9289462
Short name T512
Test name
Test status
Simulation time 2916870158 ps
CPU time 10.04 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:35 PM PDT 24
Peak memory 232664 kb
Host smart-c8f40642-23be-49ec-bbec-b519cfe55ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9289462 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swap.9289462
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.866267312
Short name T850
Test name
Test status
Simulation time 3217714821 ps
CPU time 5.29 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:29 PM PDT 24
Peak memory 227544 kb
Host smart-ceb6063f-29ed-452e-b9e4-cbf7d5042b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866267312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.866267312
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.885002986
Short name T443
Test name
Test status
Simulation time 795544055 ps
CPU time 8.02 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:15:33 PM PDT 24
Peak memory 220400 kb
Host smart-4d21349a-b7f3-4a11-b4cc-5be91ff5a293
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=885002986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.885002986
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.1315419573
Short name T998
Test name
Test status
Simulation time 12606400 ps
CPU time 0.79 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:25 PM PDT 24
Peak memory 205664 kb
Host smart-6ef25fbf-8fd0-414f-9d4a-3fe07afef9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315419573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.1315419573
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1076835230
Short name T592
Test name
Test status
Simulation time 1978919248 ps
CPU time 7.91 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:15:34 PM PDT 24
Peak memory 216164 kb
Host smart-c1a8fa4b-c14c-4d83-ac50-cb1b5eecb416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076835230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1076835230
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.3104216685
Short name T422
Test name
Test status
Simulation time 62351659 ps
CPU time 1.42 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:25 PM PDT 24
Peak memory 216104 kb
Host smart-1eb373e9-f4ca-4fda-9692-59ac6789a96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3104216685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.3104216685
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.17871594
Short name T894
Test name
Test status
Simulation time 35147076 ps
CPU time 0.78 seconds
Started Jul 04 05:15:23 PM PDT 24
Finished Jul 04 05:15:25 PM PDT 24
Peak memory 205940 kb
Host smart-8535fc16-2213-4a92-a0a9-41320142692b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=17871594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.17871594
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.818364451
Short name T1000
Test name
Test status
Simulation time 20295416265 ps
CPU time 23.81 seconds
Started Jul 04 05:15:22 PM PDT 24
Finished Jul 04 05:15:46 PM PDT 24
Peak memory 232744 kb
Host smart-4e1bf52b-8192-4bf4-80f6-d2a147da7ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818364451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.818364451
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.4258838638
Short name T938
Test name
Test status
Simulation time 37700501 ps
CPU time 0.7 seconds
Started Jul 04 05:15:28 PM PDT 24
Finished Jul 04 05:15:29 PM PDT 24
Peak memory 205460 kb
Host smart-76fc9f80-ec16-49e2-91a9-30ec7addfdae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258838638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
4258838638
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3562976767
Short name T193
Test name
Test status
Simulation time 126577670 ps
CPU time 2.3 seconds
Started Jul 04 05:15:28 PM PDT 24
Finished Jul 04 05:15:31 PM PDT 24
Peak memory 224392 kb
Host smart-ada35b65-1863-4f55-9e6d-bdc0bc875dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562976767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3562976767
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1607070272
Short name T769
Test name
Test status
Simulation time 21263600 ps
CPU time 0.88 seconds
Started Jul 04 05:15:23 PM PDT 24
Finished Jul 04 05:15:24 PM PDT 24
Peak memory 206864 kb
Host smart-68098af3-0c9f-4ddd-8c9a-26f1b7382603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607070272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1607070272
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1879536070
Short name T254
Test name
Test status
Simulation time 47132781146 ps
CPU time 176.77 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:18:22 PM PDT 24
Peak memory 249420 kb
Host smart-a3d18e38-250c-46be-a991-b42d1786dd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879536070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1879536070
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.3556972810
Short name T50
Test name
Test status
Simulation time 2717338329 ps
CPU time 58.37 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 250360 kb
Host smart-d15f1f4f-da47-4555-a49d-ffb007bd5e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556972810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.3556972810
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3659700439
Short name T504
Test name
Test status
Simulation time 443296761 ps
CPU time 11.3 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:15:38 PM PDT 24
Peak memory 224780 kb
Host smart-8fc84b53-656c-434e-b4e1-faae6888fd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659700439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3659700439
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.2352916386
Short name T147
Test name
Test status
Simulation time 26075888839 ps
CPU time 47.23 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:16:12 PM PDT 24
Peak memory 232772 kb
Host smart-74c42139-91b7-48d5-b45a-2458a070ef98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352916386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.2352916386
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3077235383
Short name T775
Test name
Test status
Simulation time 4913627385 ps
CPU time 10.78 seconds
Started Jul 04 05:15:28 PM PDT 24
Finished Jul 04 05:15:39 PM PDT 24
Peak memory 224544 kb
Host smart-56c8822e-870c-4f7d-be22-3e4b911f8c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077235383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3077235383
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.195861771
Short name T277
Test name
Test status
Simulation time 8854684652 ps
CPU time 89.67 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:16:55 PM PDT 24
Peak memory 224476 kb
Host smart-d1b38b57-dc26-4d79-8e02-107c9d217585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195861771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.195861771
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.762924085
Short name T197
Test name
Test status
Simulation time 173375606 ps
CPU time 3.53 seconds
Started Jul 04 05:15:28 PM PDT 24
Finished Jul 04 05:15:32 PM PDT 24
Peak memory 224400 kb
Host smart-7789205e-ac1c-47a2-b8cb-2baaa9b5dae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762924085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.762924085
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.653171968
Short name T178
Test name
Test status
Simulation time 360467543 ps
CPU time 3.17 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:15:29 PM PDT 24
Peak memory 232596 kb
Host smart-03876598-6e88-4a10-8f8f-23bafad26e17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653171968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.653171968
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2851898694
Short name T42
Test name
Test status
Simulation time 9015062143 ps
CPU time 18.18 seconds
Started Jul 04 05:15:23 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 219380 kb
Host smart-01c8b945-7f55-4330-8c87-f168e1361c95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2851898694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2851898694
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.785310661
Short name T281
Test name
Test status
Simulation time 11069101136 ps
CPU time 125.73 seconds
Started Jul 04 05:15:27 PM PDT 24
Finished Jul 04 05:17:33 PM PDT 24
Peak memory 255260 kb
Host smart-1a81f047-560c-4aa5-8da2-c73b9d870890
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785310661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stres
s_all.785310661
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1476189877
Short name T876
Test name
Test status
Simulation time 21385423825 ps
CPU time 17.39 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:41 PM PDT 24
Peak memory 216544 kb
Host smart-acbdd46f-b933-4f4c-925e-cdeb93a13301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476189877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1476189877
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1509775096
Short name T438
Test name
Test status
Simulation time 1405831698 ps
CPU time 3.1 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:28 PM PDT 24
Peak memory 216208 kb
Host smart-9615222f-5f40-47d0-8981-2bab20e0f8c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509775096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1509775096
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.2188703904
Short name T867
Test name
Test status
Simulation time 72140285 ps
CPU time 1.19 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:15:27 PM PDT 24
Peak memory 216128 kb
Host smart-79295e07-9734-48e5-96be-acf40135365d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2188703904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.2188703904
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.1948779317
Short name T673
Test name
Test status
Simulation time 37882196 ps
CPU time 0.69 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:15:27 PM PDT 24
Peak memory 205584 kb
Host smart-b32d2499-12db-4125-9d70-7db69c03e4c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948779317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.1948779317
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.977668573
Short name T809
Test name
Test status
Simulation time 297007031 ps
CPU time 5.71 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:30 PM PDT 24
Peak memory 232600 kb
Host smart-9ebfbd02-21f7-40a5-86be-b8856366aa94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977668573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.977668573
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1261750738
Short name T654
Test name
Test status
Simulation time 13594557 ps
CPU time 0.74 seconds
Started Jul 04 05:15:30 PM PDT 24
Finished Jul 04 05:15:31 PM PDT 24
Peak memory 205440 kb
Host smart-bb6595ca-e740-4d7b-b2df-00b000ba23ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261750738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1261750738
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.1717602990
Short name T808
Test name
Test status
Simulation time 147061450 ps
CPU time 3.52 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:15:29 PM PDT 24
Peak memory 232536 kb
Host smart-3731d305-b3f0-453d-aec0-ae8d1928dfb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717602990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.1717602990
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3084734122
Short name T587
Test name
Test status
Simulation time 173977951 ps
CPU time 0.8 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:15:26 PM PDT 24
Peak memory 206528 kb
Host smart-9aa82b46-b70d-4511-8efc-01ffe9a12959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084734122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3084734122
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.2938963591
Short name T632
Test name
Test status
Simulation time 4644568736 ps
CPU time 92.36 seconds
Started Jul 04 05:15:29 PM PDT 24
Finished Jul 04 05:17:02 PM PDT 24
Peak memory 256444 kb
Host smart-8ab11a2a-d8b1-42f6-abc2-6d68714b8fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938963591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.2938963591
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.682074079
Short name T204
Test name
Test status
Simulation time 15181896635 ps
CPU time 129.58 seconds
Started Jul 04 05:15:30 PM PDT 24
Finished Jul 04 05:17:40 PM PDT 24
Peak memory 250296 kb
Host smart-17d5852d-71a6-4abd-a6bb-261c0a9e4cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682074079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idle
.682074079
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2452136705
Short name T568
Test name
Test status
Simulation time 6618814924 ps
CPU time 26.57 seconds
Started Jul 04 05:15:24 PM PDT 24
Finished Jul 04 05:15:51 PM PDT 24
Peak memory 232660 kb
Host smart-3fba4c94-23c2-41e7-b001-07e2e121d036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452136705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2452136705
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.4145534609
Short name T614
Test name
Test status
Simulation time 4758075950 ps
CPU time 69.17 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:16:36 PM PDT 24
Peak memory 255476 kb
Host smart-b28c6460-58b4-4ab9-b3e3-6374fd95aad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145534609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.4145534609
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.215544188
Short name T727
Test name
Test status
Simulation time 1525539234 ps
CPU time 11.27 seconds
Started Jul 04 05:15:23 PM PDT 24
Finished Jul 04 05:15:35 PM PDT 24
Peak memory 232592 kb
Host smart-c8591fdd-60fd-427c-bfed-ee86ed26bc3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215544188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.215544188
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.3208361712
Short name T787
Test name
Test status
Simulation time 218952536 ps
CPU time 2.09 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:15:29 PM PDT 24
Peak memory 224036 kb
Host smart-6a031ed5-0aa2-4c68-b09b-263333849e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208361712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.3208361712
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.2107351408
Short name T542
Test name
Test status
Simulation time 328212948 ps
CPU time 5.32 seconds
Started Jul 04 05:15:22 PM PDT 24
Finished Jul 04 05:15:28 PM PDT 24
Peak memory 232548 kb
Host smart-1728040b-7897-46c3-9473-cfe5fa2becb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2107351408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.2107351408
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1201329251
Short name T640
Test name
Test status
Simulation time 6604197378 ps
CPU time 10.28 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:15:36 PM PDT 24
Peak memory 232688 kb
Host smart-dcd26f7a-eb65-475e-baef-78cea4c4ee15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1201329251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1201329251
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3639443762
Short name T430
Test name
Test status
Simulation time 87083722 ps
CPU time 4.39 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:15:37 PM PDT 24
Peak memory 218680 kb
Host smart-166dd213-ad89-4488-a34e-b73a8979250f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3639443762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3639443762
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.882170118
Short name T730
Test name
Test status
Simulation time 31788294699 ps
CPU time 233.59 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:19:26 PM PDT 24
Peak memory 248896 kb
Host smart-7ba5dad9-4290-4002-9888-3c586d3ca62d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882170118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stres
s_all.882170118
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.4188789755
Short name T995
Test name
Test status
Simulation time 274298433 ps
CPU time 3.25 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:15:29 PM PDT 24
Peak memory 216184 kb
Host smart-2b7ad0cd-5c14-40d0-9d16-06fb02f0ba9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188789755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.4188789755
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.1612335013
Short name T442
Test name
Test status
Simulation time 19405541088 ps
CPU time 12.81 seconds
Started Jul 04 05:15:28 PM PDT 24
Finished Jul 04 05:15:41 PM PDT 24
Peak memory 216384 kb
Host smart-2b984306-b12f-4685-a89b-209a0fff6200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612335013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.1612335013
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2394747134
Short name T717
Test name
Test status
Simulation time 132953511 ps
CPU time 1.2 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:15:27 PM PDT 24
Peak memory 206620 kb
Host smart-5e0bb228-29af-44eb-b2a4-6e1267137008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394747134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2394747134
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2805387982
Short name T348
Test name
Test status
Simulation time 88637512 ps
CPU time 0.75 seconds
Started Jul 04 05:15:26 PM PDT 24
Finished Jul 04 05:15:27 PM PDT 24
Peak memory 205916 kb
Host smart-b829579d-1993-45e2-83a9-b54b5c4cc89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805387982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2805387982
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.1230799897
Short name T24
Test name
Test status
Simulation time 33822245538 ps
CPU time 25.72 seconds
Started Jul 04 05:15:25 PM PDT 24
Finished Jul 04 05:15:51 PM PDT 24
Peak memory 232748 kb
Host smart-ae91485d-b144-4dbd-b112-5628395129c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230799897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.1230799897
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.360964937
Short name T541
Test name
Test status
Simulation time 16824181 ps
CPU time 0.73 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:15:33 PM PDT 24
Peak memory 204880 kb
Host smart-fe71545c-a7c6-4a0b-bc4c-5c7b4ce87106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360964937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.360964937
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3047111971
Short name T456
Test name
Test status
Simulation time 717293019 ps
CPU time 4.75 seconds
Started Jul 04 05:15:30 PM PDT 24
Finished Jul 04 05:15:35 PM PDT 24
Peak memory 224436 kb
Host smart-88345709-6ac0-45ed-a529-484d2702136f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047111971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3047111971
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.941978773
Short name T381
Test name
Test status
Simulation time 21231497 ps
CPU time 0.81 seconds
Started Jul 04 05:15:34 PM PDT 24
Finished Jul 04 05:15:35 PM PDT 24
Peak memory 206828 kb
Host smart-4bf155e6-5cb3-471e-bf7f-99f9cb2966ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941978773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.941978773
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4024320294
Short name T233
Test name
Test status
Simulation time 16121942439 ps
CPU time 35.4 seconds
Started Jul 04 05:15:31 PM PDT 24
Finished Jul 04 05:16:07 PM PDT 24
Peak memory 238584 kb
Host smart-d53f8b6e-e9b7-46e0-adaf-a1b7e850307b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024320294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4024320294
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3245638628
Short name T918
Test name
Test status
Simulation time 11004876534 ps
CPU time 54.05 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:16:26 PM PDT 24
Peak memory 249228 kb
Host smart-813e6fd4-af08-4ee1-8254-d86d51c0b139
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3245638628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3245638628
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.436873621
Short name T412
Test name
Test status
Simulation time 16201363864 ps
CPU time 62.84 seconds
Started Jul 04 05:15:33 PM PDT 24
Finished Jul 04 05:16:36 PM PDT 24
Peak memory 251388 kb
Host smart-706e61b8-6f15-4a7d-b5cf-9b6a79a8cfab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436873621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idle
.436873621
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.3333359258
Short name T337
Test name
Test status
Simulation time 183321963 ps
CPU time 4.84 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:15:37 PM PDT 24
Peak memory 224292 kb
Host smart-97fcfe50-03f9-41d7-9de2-4521dc2bb664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333359258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.3333359258
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.4134827053
Short name T394
Test name
Test status
Simulation time 3123307854 ps
CPU time 28.73 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:16:01 PM PDT 24
Peak memory 234316 kb
Host smart-e55ceabc-0a2c-4a51-b656-a2022135e301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134827053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.4134827053
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.3096775368
Short name T629
Test name
Test status
Simulation time 159918696 ps
CPU time 2.85 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:15:35 PM PDT 24
Peak memory 232540 kb
Host smart-6807e34c-2a80-4cb4-a7c1-84aa0319f16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096775368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.3096775368
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3105654641
Short name T478
Test name
Test status
Simulation time 254536080840 ps
CPU time 142.93 seconds
Started Jul 04 05:15:31 PM PDT 24
Finished Jul 04 05:17:55 PM PDT 24
Peak memory 237608 kb
Host smart-ec13f6ff-d82a-4361-add0-63a321f3dcfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105654641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3105654641
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.2761459015
Short name T187
Test name
Test status
Simulation time 3027047060 ps
CPU time 6.6 seconds
Started Jul 04 05:15:31 PM PDT 24
Finished Jul 04 05:15:38 PM PDT 24
Peak memory 231944 kb
Host smart-f7241a6e-d10c-4102-85cf-08f9b995a75f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761459015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.2761459015
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3595381673
Short name T1011
Test name
Test status
Simulation time 3248289887 ps
CPU time 11.01 seconds
Started Jul 04 05:15:31 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 233768 kb
Host smart-171250de-bbc2-4c88-9cff-08745532aa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595381673 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3595381673
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2031841007
Short name T41
Test name
Test status
Simulation time 2532818820 ps
CPU time 19.91 seconds
Started Jul 04 05:15:33 PM PDT 24
Finished Jul 04 05:15:53 PM PDT 24
Peak memory 220528 kb
Host smart-2460812c-7dc1-41d0-b791-ddb64adf0ae1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2031841007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2031841007
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3351928092
Short name T366
Test name
Test status
Simulation time 10899036879 ps
CPU time 63.57 seconds
Started Jul 04 05:15:31 PM PDT 24
Finished Jul 04 05:16:35 PM PDT 24
Peak memory 265572 kb
Host smart-e21da1fc-cb98-4fda-999e-72c88cce4e1b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351928092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3351928092
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.2274640011
Short name T396
Test name
Test status
Simulation time 31619318352 ps
CPU time 41.6 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 216316 kb
Host smart-8a66c3d1-7597-416c-af63-0b329193349d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274640011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.2274640011
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.2559144298
Short name T489
Test name
Test status
Simulation time 2567501632 ps
CPU time 8.56 seconds
Started Jul 04 05:15:33 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 216288 kb
Host smart-2fe694c7-9f2f-4f74-94f5-2e16572999bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559144298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.2559144298
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.74054461
Short name T764
Test name
Test status
Simulation time 42348243 ps
CPU time 1.32 seconds
Started Jul 04 05:15:31 PM PDT 24
Finished Jul 04 05:15:33 PM PDT 24
Peak memory 216104 kb
Host smart-d9420c5c-772b-479b-9e24-6eb462d2d879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74054461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.74054461
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1289583693
Short name T803
Test name
Test status
Simulation time 134812046 ps
CPU time 1.06 seconds
Started Jul 04 05:15:33 PM PDT 24
Finished Jul 04 05:15:34 PM PDT 24
Peak memory 206936 kb
Host smart-4cd0e3ac-a533-4bb9-9924-de786750cdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289583693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1289583693
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3014557185
Short name T123
Test name
Test status
Simulation time 3666860501 ps
CPU time 8.1 seconds
Started Jul 04 05:15:30 PM PDT 24
Finished Jul 04 05:15:38 PM PDT 24
Peak memory 224528 kb
Host smart-7cb8e228-3926-43bc-8d82-0a84fcf245db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014557185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3014557185
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.935086992
Short name T360
Test name
Test status
Simulation time 14276800 ps
CPU time 0.77 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:15:40 PM PDT 24
Peak memory 205388 kb
Host smart-f1d1d407-1a8c-4419-9696-134af0ecc2ff
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935086992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.935086992
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3588880714
Short name T80
Test name
Test status
Simulation time 758533122 ps
CPU time 9.21 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:15:49 PM PDT 24
Peak memory 224364 kb
Host smart-c93a994a-cf9e-4c06-8884-2ef612513b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588880714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3588880714
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.3879660420
Short name T32
Test name
Test status
Simulation time 16917717 ps
CPU time 0.81 seconds
Started Jul 04 05:15:32 PM PDT 24
Finished Jul 04 05:15:33 PM PDT 24
Peak memory 206516 kb
Host smart-74250a1a-2e50-4a5b-baad-eec3e3e9b050
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3879660420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.3879660420
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3445634840
Short name T160
Test name
Test status
Simulation time 3609651058 ps
CPU time 9.48 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:48 PM PDT 24
Peak memory 224572 kb
Host smart-b732c72b-10a7-420b-818c-2c9e2dc48da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445634840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3445634840
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.1971698210
Short name T824
Test name
Test status
Simulation time 64815399524 ps
CPU time 498.27 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:23:57 PM PDT 24
Peak memory 265588 kb
Host smart-75627e19-6897-4b9e-8703-26d2d811d8a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971698210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.1971698210
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.4086430947
Short name T200
Test name
Test status
Simulation time 36825710809 ps
CPU time 260.35 seconds
Started Jul 04 05:15:40 PM PDT 24
Finished Jul 04 05:20:00 PM PDT 24
Peak memory 254232 kb
Host smart-3c2ae131-d855-49e9-a8ea-44b927ab9363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086430947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.4086430947
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3128644999
Short name T929
Test name
Test status
Simulation time 4147231518 ps
CPU time 13.53 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:15:53 PM PDT 24
Peak memory 224416 kb
Host smart-dcac29fc-6114-4156-a4b5-01a8ff5a6de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128644999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3128644999
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.231650828
Short name T569
Test name
Test status
Simulation time 136025747109 ps
CPU time 243.45 seconds
Started Jul 04 05:15:37 PM PDT 24
Finished Jul 04 05:19:41 PM PDT 24
Peak memory 254528 kb
Host smart-80c02f80-01d4-43a5-b88d-cd5b2b36c7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231650828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmds
.231650828
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.2294221723
Short name T832
Test name
Test status
Simulation time 225455181 ps
CPU time 2.86 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:41 PM PDT 24
Peak memory 224288 kb
Host smart-f0c3dbb6-f505-4d86-a7c3-a067baa03afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2294221723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.2294221723
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1978695400
Short name T874
Test name
Test status
Simulation time 319882153 ps
CPU time 6.65 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:45 PM PDT 24
Peak memory 231360 kb
Host smart-666f94d0-9d73-4eb7-8861-77f7062bbda9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978695400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1978695400
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.472438649
Short name T436
Test name
Test status
Simulation time 5447890095 ps
CPU time 11.26 seconds
Started Jul 04 05:15:41 PM PDT 24
Finished Jul 04 05:15:52 PM PDT 24
Peak memory 224484 kb
Host smart-080e7599-5cda-4d32-9ca3-af412111b452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=472438649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.472438649
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.2257806792
Short name T371
Test name
Test status
Simulation time 112513841 ps
CPU time 2.2 seconds
Started Jul 04 05:15:33 PM PDT 24
Finished Jul 04 05:15:35 PM PDT 24
Peak memory 232288 kb
Host smart-ab0973ba-4dbf-4de4-8b80-3efaef4ceae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257806792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.2257806792
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3469822313
Short name T350
Test name
Test status
Simulation time 2850135160 ps
CPU time 8.38 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:15:47 PM PDT 24
Peak memory 220600 kb
Host smart-1dc29f06-9d66-4061-9d1f-af43550745e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3469822313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3469822313
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.4205033257
Short name T484
Test name
Test status
Simulation time 52788390780 ps
CPU time 114.16 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:17:33 PM PDT 24
Peak memory 249200 kb
Host smart-9acd4934-0723-45f8-a7bb-d0e6dc88bc98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205033257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.4205033257
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3018239039
Short name T312
Test name
Test status
Simulation time 27668684 ps
CPU time 0.73 seconds
Started Jul 04 05:15:33 PM PDT 24
Finished Jul 04 05:15:34 PM PDT 24
Peak memory 205680 kb
Host smart-2a1f6c2e-056e-4e0a-b8ab-b2014997ad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018239039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3018239039
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3685115604
Short name T792
Test name
Test status
Simulation time 3553040624 ps
CPU time 1.52 seconds
Started Jul 04 05:15:31 PM PDT 24
Finished Jul 04 05:15:32 PM PDT 24
Peak memory 207696 kb
Host smart-c50fe59e-df77-469f-922f-9c04bf97469c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685115604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3685115604
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2404469982
Short name T822
Test name
Test status
Simulation time 433092769 ps
CPU time 2.63 seconds
Started Jul 04 05:15:31 PM PDT 24
Finished Jul 04 05:15:34 PM PDT 24
Peak memory 215320 kb
Host smart-ebb1061d-509c-46fc-8a89-4e4836d9ddab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404469982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2404469982
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2667211280
Short name T776
Test name
Test status
Simulation time 79817579 ps
CPU time 0.75 seconds
Started Jul 04 05:15:30 PM PDT 24
Finished Jul 04 05:15:31 PM PDT 24
Peak memory 205916 kb
Host smart-617de2e1-5a1f-491d-bc33-7d898f799b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667211280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2667211280
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.815039961
Short name T336
Test name
Test status
Simulation time 62459447 ps
CPU time 2.02 seconds
Started Jul 04 05:15:36 PM PDT 24
Finished Jul 04 05:15:38 PM PDT 24
Peak memory 223324 kb
Host smart-64162153-b291-4ebb-a825-d19231aca50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=815039961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.815039961
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.4195503237
Short name T322
Test name
Test status
Simulation time 29231195 ps
CPU time 0.72 seconds
Started Jul 04 05:15:40 PM PDT 24
Finished Jul 04 05:15:41 PM PDT 24
Peak memory 205488 kb
Host smart-24047454-19c1-4107-9829-f5c8e7ae17f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195503237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
4195503237
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.2103041220
Short name T760
Test name
Test status
Simulation time 168847288 ps
CPU time 4.07 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:15:44 PM PDT 24
Peak memory 224444 kb
Host smart-1aa74cae-7782-43e2-994d-778d6455be58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103041220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.2103041220
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1054838575
Short name T68
Test name
Test status
Simulation time 151286500 ps
CPU time 0.8 seconds
Started Jul 04 05:15:41 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 206556 kb
Host smart-03c9bdc2-7f25-4543-b47d-c98a057c11bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054838575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1054838575
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2608781846
Short name T206
Test name
Test status
Simulation time 27418303129 ps
CPU time 136.76 seconds
Started Jul 04 05:15:41 PM PDT 24
Finished Jul 04 05:17:58 PM PDT 24
Peak memory 262964 kb
Host smart-beab1e83-d1f8-45d0-aef8-24e80de0fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608781846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2608781846
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2909650419
Short name T276
Test name
Test status
Simulation time 2720206518 ps
CPU time 64.22 seconds
Started Jul 04 05:15:41 PM PDT 24
Finished Jul 04 05:16:45 PM PDT 24
Peak memory 251336 kb
Host smart-6631b021-1941-4188-a0dc-a9e7ee4024ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909650419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2909650419
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3341541085
Short name T159
Test name
Test status
Simulation time 50028503561 ps
CPU time 443.71 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:23:03 PM PDT 24
Peak memory 255900 kb
Host smart-02fe6303-302c-4b45-9664-201c6a24983a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341541085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3341541085
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.3392721274
Short name T329
Test name
Test status
Simulation time 378118136 ps
CPU time 6.42 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:45 PM PDT 24
Peak memory 239576 kb
Host smart-daa3bcdb-3c9d-40c6-a211-1826c3e428f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392721274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.3392721274
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3238973909
Short name T260
Test name
Test status
Simulation time 9890994951 ps
CPU time 87.01 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:17:06 PM PDT 24
Peak memory 249240 kb
Host smart-a5ccad88-c5c8-4b57-93c8-8ad3ee84d523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238973909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3238973909
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.671696507
Short name T616
Test name
Test status
Simulation time 64497344 ps
CPU time 2.41 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:41 PM PDT 24
Peak memory 232540 kb
Host smart-ae6b13f6-8602-402e-b9a7-6f066ed33a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671696507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.671696507
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.3459194832
Short name T846
Test name
Test status
Simulation time 709764573 ps
CPU time 3.71 seconds
Started Jul 04 05:15:40 PM PDT 24
Finished Jul 04 05:15:44 PM PDT 24
Peak memory 232568 kb
Host smart-a6c5f030-d22b-46aa-bfe2-1107fc49f693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459194832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.3459194832
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.3059187279
Short name T658
Test name
Test status
Simulation time 2128971524 ps
CPU time 4.39 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:15:44 PM PDT 24
Peak memory 224420 kb
Host smart-0b433007-6854-4c34-abb8-571aedf1287e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059187279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.3059187279
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.734629993
Short name T470
Test name
Test status
Simulation time 4806311210 ps
CPU time 10.36 seconds
Started Jul 04 05:15:40 PM PDT 24
Finished Jul 04 05:15:51 PM PDT 24
Peak memory 236224 kb
Host smart-9c3cf4ef-c6a9-4686-84ec-55392614083a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734629993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.734629993
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2578970149
Short name T892
Test name
Test status
Simulation time 8913423844 ps
CPU time 6.42 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:15:45 PM PDT 24
Peak memory 220508 kb
Host smart-73659cd5-1532-4cc0-863c-5f2f1961781d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2578970149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2578970149
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1046688025
Short name T920
Test name
Test status
Simulation time 6841569734 ps
CPU time 74.09 seconds
Started Jul 04 05:15:41 PM PDT 24
Finished Jul 04 05:16:55 PM PDT 24
Peak memory 239232 kb
Host smart-48319a46-642e-4f3a-9c2b-a4176f94aca1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1046688025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1046688025
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.916369976
Short name T931
Test name
Test status
Simulation time 108318770154 ps
CPU time 32.75 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:16:12 PM PDT 24
Peak memory 216264 kb
Host smart-630afc70-3f98-4388-87f8-7fbeae1bad73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916369976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.916369976
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.3908320984
Short name T499
Test name
Test status
Simulation time 660578892 ps
CPU time 3.17 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 216132 kb
Host smart-7fd5acf1-ee5f-4f14-81de-3902f1f9ad94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908320984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.3908320984
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.4069183703
Short name T819
Test name
Test status
Simulation time 34539385 ps
CPU time 1.02 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:39 PM PDT 24
Peak memory 206952 kb
Host smart-7dfe9064-9c53-422e-9ab5-3ce95ff7091b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069183703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.4069183703
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.4111555312
Short name T382
Test name
Test status
Simulation time 35584381 ps
CPU time 0.79 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:40 PM PDT 24
Peak memory 205928 kb
Host smart-aecb7d11-d296-4679-8301-7726551dab44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111555312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.4111555312
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3365312657
Short name T537
Test name
Test status
Simulation time 3124743912 ps
CPU time 12.24 seconds
Started Jul 04 05:15:41 PM PDT 24
Finished Jul 04 05:15:54 PM PDT 24
Peak memory 232736 kb
Host smart-789c4c98-fc09-4371-8e26-6932409b6a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365312657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3365312657
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.3823627616
Short name T709
Test name
Test status
Simulation time 43804675 ps
CPU time 0.76 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:15:50 PM PDT 24
Peak memory 204860 kb
Host smart-3b1fb423-6c9f-4474-b57f-d4c5c12ef59d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3823627616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
3823627616
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.775877215
Short name T376
Test name
Test status
Simulation time 12831176049 ps
CPU time 33.68 seconds
Started Jul 04 05:15:45 PM PDT 24
Finished Jul 04 05:16:19 PM PDT 24
Peak memory 232676 kb
Host smart-0f8049a5-e5f8-435c-ba86-d8573aa2f4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775877215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.775877215
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3017915482
Short name T713
Test name
Test status
Simulation time 18679310 ps
CPU time 0.79 seconds
Started Jul 04 05:15:41 PM PDT 24
Finished Jul 04 05:15:42 PM PDT 24
Peak memory 205544 kb
Host smart-8b2a49e1-4c15-4132-8224-385ca4d9b64d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017915482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3017915482
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2062646814
Short name T983
Test name
Test status
Simulation time 3916240895 ps
CPU time 20.41 seconds
Started Jul 04 05:15:50 PM PDT 24
Finished Jul 04 05:16:10 PM PDT 24
Peak memory 241220 kb
Host smart-9ba0be23-3ecf-4925-8335-f674deb68bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062646814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2062646814
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1404608819
Short name T761
Test name
Test status
Simulation time 2919722960 ps
CPU time 56.27 seconds
Started Jul 04 05:15:49 PM PDT 24
Finished Jul 04 05:16:46 PM PDT 24
Peak memory 250100 kb
Host smart-32413fb5-4541-40ba-81b0-71b51dad7076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404608819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1404608819
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1856823181
Short name T519
Test name
Test status
Simulation time 2793635654 ps
CPU time 27.94 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:16:16 PM PDT 24
Peak memory 217432 kb
Host smart-dad5403b-6fea-46d3-9f85-3eaabef85d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856823181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1856823181
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.490487303
Short name T450
Test name
Test status
Simulation time 1521032203 ps
CPU time 4.87 seconds
Started Jul 04 05:15:44 PM PDT 24
Finished Jul 04 05:15:50 PM PDT 24
Peak memory 224440 kb
Host smart-3ca236e0-fde0-4057-b758-38a9a9a297ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490487303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.490487303
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2633522813
Short name T491
Test name
Test status
Simulation time 46674453222 ps
CPU time 164.41 seconds
Started Jul 04 05:15:47 PM PDT 24
Finished Jul 04 05:18:32 PM PDT 24
Peak memory 252052 kb
Host smart-7bab0103-ba2c-4283-9988-537eb72a67e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633522813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2633522813
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.754174270
Short name T357
Test name
Test status
Simulation time 1434219363 ps
CPU time 12.81 seconds
Started Jul 04 05:15:46 PM PDT 24
Finished Jul 04 05:15:59 PM PDT 24
Peak memory 224436 kb
Host smart-b1bf5103-918e-4538-b994-fc0ac47be05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754174270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.754174270
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.3338584677
Short name T367
Test name
Test status
Simulation time 14970976068 ps
CPU time 120.91 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:17:49 PM PDT 24
Peak memory 240248 kb
Host smart-6f679351-263f-43d7-8d97-34db6aa9d835
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338584677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.3338584677
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1066774612
Short name T823
Test name
Test status
Simulation time 1811238662 ps
CPU time 5.1 seconds
Started Jul 04 05:15:46 PM PDT 24
Finished Jul 04 05:15:51 PM PDT 24
Peak memory 232596 kb
Host smart-f30815a1-359a-4618-9081-3a596eae792d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066774612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1066774612
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2604633042
Short name T668
Test name
Test status
Simulation time 4612009442 ps
CPU time 5.01 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:15:44 PM PDT 24
Peak memory 240392 kb
Host smart-902a2bf0-7001-470d-b54e-73ceea37f7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2604633042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2604633042
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.4238555318
Short name T663
Test name
Test status
Simulation time 5894988205 ps
CPU time 8.59 seconds
Started Jul 04 05:15:47 PM PDT 24
Finished Jul 04 05:15:56 PM PDT 24
Peak memory 220180 kb
Host smart-ca65cd75-9f4b-483d-8382-5b7e80565c8b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4238555318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.4238555318
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.337029561
Short name T15
Test name
Test status
Simulation time 306781517 ps
CPU time 1.19 seconds
Started Jul 04 05:15:44 PM PDT 24
Finished Jul 04 05:15:45 PM PDT 24
Peak memory 207108 kb
Host smart-cf3f1292-23c2-46b3-9933-45091e228048
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337029561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.337029561
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4242067826
Short name T866
Test name
Test status
Simulation time 13762368537 ps
CPU time 18.78 seconds
Started Jul 04 05:15:40 PM PDT 24
Finished Jul 04 05:15:59 PM PDT 24
Peak memory 220328 kb
Host smart-afc7974d-f78f-4679-a5d8-3d72af3b97cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242067826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4242067826
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.1942531939
Short name T65
Test name
Test status
Simulation time 12162228509 ps
CPU time 9.44 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:48 PM PDT 24
Peak memory 216272 kb
Host smart-0e2fed9d-7e5f-4e66-9570-9bfffb57cd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942531939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.1942531939
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.3685914547
Short name T702
Test name
Test status
Simulation time 179387339 ps
CPU time 2.6 seconds
Started Jul 04 05:15:38 PM PDT 24
Finished Jul 04 05:15:40 PM PDT 24
Peak memory 216104 kb
Host smart-10ee4b7b-e96b-4fa3-9f75-e39c1b1c13d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685914547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.3685914547
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3180475412
Short name T594
Test name
Test status
Simulation time 67192129 ps
CPU time 0.94 seconds
Started Jul 04 05:15:39 PM PDT 24
Finished Jul 04 05:15:40 PM PDT 24
Peak memory 206964 kb
Host smart-99a5823b-1e0e-40f0-8b9f-1def5f0135b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180475412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3180475412
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3080535931
Short name T712
Test name
Test status
Simulation time 17282899926 ps
CPU time 52.52 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:16:40 PM PDT 24
Peak memory 249124 kb
Host smart-ff79a55b-36f0-4937-ac82-1c7b731eee08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080535931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3080535931
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.1716086989
Short name T506
Test name
Test status
Simulation time 12389068 ps
CPU time 0.73 seconds
Started Jul 04 05:12:39 PM PDT 24
Finished Jul 04 05:12:40 PM PDT 24
Peak memory 205780 kb
Host smart-8725d06c-6ed0-420e-87b5-e54221e7f8f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716086989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.1
716086989
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1151361036
Short name T604
Test name
Test status
Simulation time 834340808 ps
CPU time 7.64 seconds
Started Jul 04 05:12:40 PM PDT 24
Finished Jul 04 05:12:48 PM PDT 24
Peak memory 232588 kb
Host smart-729175a1-af3b-47ee-afdf-8d6f6416bf41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151361036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1151361036
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.3909240133
Short name T655
Test name
Test status
Simulation time 19444286 ps
CPU time 0.78 seconds
Started Jul 04 05:12:34 PM PDT 24
Finished Jul 04 05:12:35 PM PDT 24
Peak memory 206488 kb
Host smart-52a9aa96-04a9-4ceb-aad3-2a6babe09b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909240133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.3909240133
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.556177600
Short name T431
Test name
Test status
Simulation time 219900207708 ps
CPU time 103.13 seconds
Started Jul 04 05:12:39 PM PDT 24
Finished Jul 04 05:14:22 PM PDT 24
Peak memory 240972 kb
Host smart-a208a0fb-4e7d-4ca9-bac3-c786bf01b629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556177600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.556177600
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.3842921895
Short name T402
Test name
Test status
Simulation time 2966568256 ps
CPU time 18.4 seconds
Started Jul 04 05:12:42 PM PDT 24
Finished Jul 04 05:13:01 PM PDT 24
Peak memory 217468 kb
Host smart-0a23983b-3868-4405-a9e9-adf11a630275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842921895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.3842921895
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.1989496443
Short name T211
Test name
Test status
Simulation time 4851191493 ps
CPU time 65.75 seconds
Started Jul 04 05:12:40 PM PDT 24
Finished Jul 04 05:13:46 PM PDT 24
Peak memory 250256 kb
Host smart-57e782dc-230f-4983-b44c-0d5d5beb8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989496443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.1989496443
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2269682539
Short name T773
Test name
Test status
Simulation time 824154029 ps
CPU time 9 seconds
Started Jul 04 05:12:40 PM PDT 24
Finished Jul 04 05:12:49 PM PDT 24
Peak memory 224392 kb
Host smart-993e1209-cdc7-4931-984f-baf46e108845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269682539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2269682539
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.3183259297
Short name T681
Test name
Test status
Simulation time 44044003138 ps
CPU time 290.21 seconds
Started Jul 04 05:12:39 PM PDT 24
Finished Jul 04 05:17:30 PM PDT 24
Peak memory 253084 kb
Host smart-66fdef45-4f4a-471f-99fc-d3949f10622d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183259297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.3183259297
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.3536943142
Short name T269
Test name
Test status
Simulation time 751973760 ps
CPU time 4.6 seconds
Started Jul 04 05:12:39 PM PDT 24
Finished Jul 04 05:12:44 PM PDT 24
Peak memory 224360 kb
Host smart-4967ea0d-2fd5-4ed2-8aac-e786449f78cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536943142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.3536943142
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.620127410
Short name T531
Test name
Test status
Simulation time 433945438 ps
CPU time 5.75 seconds
Started Jul 04 05:12:38 PM PDT 24
Finished Jul 04 05:12:44 PM PDT 24
Peak memory 232640 kb
Host smart-d285f16f-33aa-44da-9285-07749a799964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620127410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.620127410
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.2494533855
Short name T226
Test name
Test status
Simulation time 3876727890 ps
CPU time 13.78 seconds
Started Jul 04 05:12:38 PM PDT 24
Finished Jul 04 05:12:52 PM PDT 24
Peak memory 224504 kb
Host smart-0735e79c-e0a4-445a-8888-44ede3b85c24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494533855 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.2494533855
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1607027745
Short name T646
Test name
Test status
Simulation time 141251298 ps
CPU time 2.65 seconds
Started Jul 04 05:12:40 PM PDT 24
Finished Jul 04 05:12:43 PM PDT 24
Peak memory 232264 kb
Host smart-8a74dd39-18d2-4caa-86d4-9f0cccee7787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607027745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1607027745
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.734027863
Short name T534
Test name
Test status
Simulation time 1122746895 ps
CPU time 8.47 seconds
Started Jul 04 05:12:42 PM PDT 24
Finished Jul 04 05:12:50 PM PDT 24
Peak memory 222020 kb
Host smart-ee885326-0eea-40f8-a845-e2032a4ad752
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=734027863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.734027863
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.4173624677
Short name T61
Test name
Test status
Simulation time 202658093 ps
CPU time 1.17 seconds
Started Jul 04 05:12:37 PM PDT 24
Finished Jul 04 05:12:38 PM PDT 24
Peak memory 236540 kb
Host smart-c9f169a5-0851-4a99-97c4-d944678ed6bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173624677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.4173624677
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.308028323
Short name T144
Test name
Test status
Simulation time 19229055999 ps
CPU time 25.2 seconds
Started Jul 04 05:12:39 PM PDT 24
Finished Jul 04 05:13:04 PM PDT 24
Peak memory 224500 kb
Host smart-3099c332-a4e6-438a-adcb-3ddcfba219c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=308028323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.308028323
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3949798641
Short name T790
Test name
Test status
Simulation time 98766284 ps
CPU time 0.75 seconds
Started Jul 04 05:12:42 PM PDT 24
Finished Jul 04 05:12:43 PM PDT 24
Peak memory 205616 kb
Host smart-2e8899f5-2fbe-4f02-b6a5-7649a7d5618a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949798641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3949798641
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2726950307
Short name T877
Test name
Test status
Simulation time 2338167010 ps
CPU time 5.29 seconds
Started Jul 04 05:12:38 PM PDT 24
Finished Jul 04 05:12:43 PM PDT 24
Peak memory 216244 kb
Host smart-34a25148-9759-44a1-b2fc-510c6b188335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2726950307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2726950307
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2640476310
Short name T873
Test name
Test status
Simulation time 62397151 ps
CPU time 0.92 seconds
Started Jul 04 05:12:38 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 207108 kb
Host smart-e2117aa5-6f12-48d6-82ad-c3504bc20bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640476310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2640476310
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1418733749
Short name T492
Test name
Test status
Simulation time 289834744 ps
CPU time 0.99 seconds
Started Jul 04 05:12:38 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 206276 kb
Host smart-e940f9cb-4739-4130-be22-69c1c371651d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418733749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1418733749
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2375435375
Short name T432
Test name
Test status
Simulation time 2235188324 ps
CPU time 10.56 seconds
Started Jul 04 05:12:42 PM PDT 24
Finished Jul 04 05:12:53 PM PDT 24
Peak memory 232700 kb
Host smart-8acf7ea1-824e-4962-9eac-accf1452cfbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375435375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2375435375
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3930724083
Short name T370
Test name
Test status
Simulation time 12263061 ps
CPU time 0.71 seconds
Started Jul 04 05:15:46 PM PDT 24
Finished Jul 04 05:15:47 PM PDT 24
Peak memory 205788 kb
Host smart-1404b103-e7da-4ecf-825c-461b486b2c21
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930724083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3930724083
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.2800943954
Short name T444
Test name
Test status
Simulation time 105454594 ps
CPU time 3.32 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:15:52 PM PDT 24
Peak memory 232636 kb
Host smart-80df5e0c-6c30-45e6-b2bc-ac4d409f0c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800943954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.2800943954
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2782375070
Short name T626
Test name
Test status
Simulation time 45140037 ps
CPU time 0.76 seconds
Started Jul 04 05:15:44 PM PDT 24
Finished Jul 04 05:15:45 PM PDT 24
Peak memory 206536 kb
Host smart-8af41a5a-272e-40ac-b419-517762679027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782375070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2782375070
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.698506543
Short name T474
Test name
Test status
Simulation time 24485390033 ps
CPU time 88.66 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:17:17 PM PDT 24
Peak memory 249172 kb
Host smart-ef1f63d5-ee41-460f-ac70-39d6a2d6f943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698506543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.698506543
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.1776939379
Short name T207
Test name
Test status
Simulation time 6029987628 ps
CPU time 132.49 seconds
Started Jul 04 05:15:44 PM PDT 24
Finished Jul 04 05:17:57 PM PDT 24
Peak memory 256912 kb
Host smart-bfb4e2b5-4ded-4f2d-a6cc-a3f497623202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1776939379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.1776939379
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2512186594
Short name T71
Test name
Test status
Simulation time 119371714290 ps
CPU time 232.76 seconds
Started Jul 04 05:15:49 PM PDT 24
Finished Jul 04 05:19:42 PM PDT 24
Peak memory 251300 kb
Host smart-e200f099-1f4c-43c9-bb8c-58f9716b3c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512186594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2512186594
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.2040798796
Short name T917
Test name
Test status
Simulation time 245127668 ps
CPU time 3.84 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:15:52 PM PDT 24
Peak memory 232616 kb
Host smart-82947a4c-b6d5-43de-a1b1-890b7a2f8267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040798796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.2040798796
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.450934403
Short name T224
Test name
Test status
Simulation time 1590014345 ps
CPU time 30.09 seconds
Started Jul 04 05:15:45 PM PDT 24
Finished Jul 04 05:16:15 PM PDT 24
Peak memory 237216 kb
Host smart-16c7d780-d618-4ea3-93f1-da74253804d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=450934403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.450934403
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.182782774
Short name T469
Test name
Test status
Simulation time 1109981331 ps
CPU time 5.68 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:15:54 PM PDT 24
Peak memory 224340 kb
Host smart-fdb88621-2661-4746-a924-32b812cbd92c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182782774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.182782774
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.3118607659
Short name T384
Test name
Test status
Simulation time 1774976434 ps
CPU time 8.63 seconds
Started Jul 04 05:15:45 PM PDT 24
Finished Jul 04 05:15:54 PM PDT 24
Peak memory 232528 kb
Host smart-f63b1f58-1d48-4249-87c8-177c845d95a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118607659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.3118607659
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.3625709478
Short name T386
Test name
Test status
Simulation time 1706162134 ps
CPU time 4.32 seconds
Started Jul 04 05:15:51 PM PDT 24
Finished Jul 04 05:15:56 PM PDT 24
Peak memory 232532 kb
Host smart-32011b1f-9f25-4cd5-b03c-5c0e2c0e0c69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625709478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.3625709478
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.3951702049
Short name T639
Test name
Test status
Simulation time 1596395872 ps
CPU time 7.06 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:15:55 PM PDT 24
Peak memory 224392 kb
Host smart-f97d81a1-12e9-4ce4-b098-6d0634aabf6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951702049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.3951702049
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.4073043200
Short name T395
Test name
Test status
Simulation time 2611760144 ps
CPU time 4.91 seconds
Started Jul 04 05:15:46 PM PDT 24
Finished Jul 04 05:15:51 PM PDT 24
Peak memory 220536 kb
Host smart-bc393922-ac0b-4e94-a5b4-1931996a2470
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4073043200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.4073043200
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.966184730
Short name T895
Test name
Test status
Simulation time 40807197005 ps
CPU time 363.7 seconds
Started Jul 04 05:15:44 PM PDT 24
Finished Jul 04 05:21:49 PM PDT 24
Peak memory 256356 kb
Host smart-67eb9fc5-7ce7-47c0-bd9c-4d0f77d2e9e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966184730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stres
s_all.966184730
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3027768772
Short name T305
Test name
Test status
Simulation time 3492663767 ps
CPU time 28.05 seconds
Started Jul 04 05:15:49 PM PDT 24
Finished Jul 04 05:16:18 PM PDT 24
Peak memory 216532 kb
Host smart-3328ae06-0924-4f53-a97f-48a7f5603d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027768772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3027768772
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2103898139
Short name T858
Test name
Test status
Simulation time 16504015 ps
CPU time 0.69 seconds
Started Jul 04 05:15:45 PM PDT 24
Finished Jul 04 05:15:46 PM PDT 24
Peak memory 205652 kb
Host smart-3843681f-5736-490c-85f2-85191794deb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2103898139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2103898139
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.279426208
Short name T319
Test name
Test status
Simulation time 101598490 ps
CPU time 1.9 seconds
Started Jul 04 05:15:44 PM PDT 24
Finished Jul 04 05:15:47 PM PDT 24
Peak memory 216128 kb
Host smart-b7a293dc-9e5e-432a-943e-1722aac68288
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279426208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.279426208
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2193241223
Short name T605
Test name
Test status
Simulation time 15318649 ps
CPU time 0.79 seconds
Started Jul 04 05:15:46 PM PDT 24
Finished Jul 04 05:15:47 PM PDT 24
Peak memory 205920 kb
Host smart-3641b494-e4c7-4d27-a100-e7eeb2b159f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193241223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2193241223
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.4058136632
Short name T667
Test name
Test status
Simulation time 6748556110 ps
CPU time 21.39 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:16:10 PM PDT 24
Peak memory 232484 kb
Host smart-79842326-f3d2-4fa0-a80a-a55c1f3ed633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058136632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.4058136632
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.4128357846
Short name T553
Test name
Test status
Simulation time 22325538 ps
CPU time 0.69 seconds
Started Jul 04 05:15:53 PM PDT 24
Finished Jul 04 05:15:54 PM PDT 24
Peak memory 204840 kb
Host smart-c11a0498-6839-41a0-98c5-621133264ce8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128357846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
4128357846
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2348346112
Short name T528
Test name
Test status
Simulation time 3568571115 ps
CPU time 21.97 seconds
Started Jul 04 05:15:51 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 224548 kb
Host smart-b8496332-a119-4094-be7b-e6991988fbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348346112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2348346112
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.226387654
Short name T924
Test name
Test status
Simulation time 28519262 ps
CPU time 0.75 seconds
Started Jul 04 05:15:45 PM PDT 24
Finished Jul 04 05:15:46 PM PDT 24
Peak memory 205852 kb
Host smart-11ba51a7-295e-4f0d-9b19-e71be092c1e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226387654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.226387654
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4006029048
Short name T239
Test name
Test status
Simulation time 21225695543 ps
CPU time 66.26 seconds
Started Jul 04 05:15:51 PM PDT 24
Finished Jul 04 05:16:57 PM PDT 24
Peak memory 240132 kb
Host smart-7dae3710-a63f-456d-ae76-a0a87944f5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006029048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4006029048
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3821464633
Short name T44
Test name
Test status
Simulation time 11784907387 ps
CPU time 112.7 seconds
Started Jul 04 05:15:54 PM PDT 24
Finished Jul 04 05:17:47 PM PDT 24
Peak memory 269932 kb
Host smart-c16f7c5f-4ccf-4697-92ff-bb8babeaa65d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821464633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3821464633
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1411529597
Short name T785
Test name
Test status
Simulation time 50520513349 ps
CPU time 97.78 seconds
Started Jul 04 05:15:52 PM PDT 24
Finished Jul 04 05:17:31 PM PDT 24
Peak memory 265572 kb
Host smart-8f19d687-fca6-4ab7-b83e-f2a3a1d0be88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411529597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1411529597
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.774620532
Short name T610
Test name
Test status
Simulation time 2569404373 ps
CPU time 36.64 seconds
Started Jul 04 05:15:45 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 224472 kb
Host smart-1be76081-374d-4f36-ba43-5cdcc6e16149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774620532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.774620532
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3327451896
Short name T950
Test name
Test status
Simulation time 9919201473 ps
CPU time 80.92 seconds
Started Jul 04 05:15:50 PM PDT 24
Finished Jul 04 05:17:11 PM PDT 24
Peak memory 249156 kb
Host smart-de7d2300-7550-432d-9e33-04b8dc942fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327451896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3327451896
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3586558180
Short name T272
Test name
Test status
Simulation time 19079189514 ps
CPU time 8.7 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:15:57 PM PDT 24
Peak memory 232788 kb
Host smart-84e806ba-4758-4df5-9219-6cabaa82a862
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3586558180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3586558180
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.2177386980
Short name T316
Test name
Test status
Simulation time 31833675 ps
CPU time 2.03 seconds
Started Jul 04 05:15:51 PM PDT 24
Finished Jul 04 05:15:54 PM PDT 24
Peak memory 224080 kb
Host smart-3940ac29-8346-4b38-b55b-e7616d02dcae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177386980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.2177386980
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.638720307
Short name T196
Test name
Test status
Simulation time 298828570 ps
CPU time 4.57 seconds
Started Jul 04 05:15:45 PM PDT 24
Finished Jul 04 05:15:50 PM PDT 24
Peak memory 224396 kb
Host smart-667d2f9d-0caa-4730-aae0-da34c73453a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638720307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swap
.638720307
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.128711655
Short name T508
Test name
Test status
Simulation time 847761401 ps
CPU time 4.68 seconds
Started Jul 04 05:15:46 PM PDT 24
Finished Jul 04 05:15:51 PM PDT 24
Peak memory 224412 kb
Host smart-c029e9fa-d445-467f-9fa4-03f7739e9a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128711655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.128711655
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3052499888
Short name T977
Test name
Test status
Simulation time 8185149918 ps
CPU time 6.08 seconds
Started Jul 04 05:15:53 PM PDT 24
Finished Jul 04 05:15:59 PM PDT 24
Peak memory 222636 kb
Host smart-1a00cb01-44ff-4cf7-8936-e009b59f3802
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3052499888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3052499888
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.424016881
Short name T916
Test name
Test status
Simulation time 557059569 ps
CPU time 2.5 seconds
Started Jul 04 05:15:50 PM PDT 24
Finished Jul 04 05:15:52 PM PDT 24
Peak memory 219532 kb
Host smart-2202ad07-2ab2-423f-a40d-9caf29df3526
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424016881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stres
s_all.424016881
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2484322869
Short name T433
Test name
Test status
Simulation time 2012854624 ps
CPU time 15.34 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:16:04 PM PDT 24
Peak memory 218972 kb
Host smart-31381d80-757a-4c03-adf0-30b5700d6bcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484322869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2484322869
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.827104971
Short name T937
Test name
Test status
Simulation time 3348638311 ps
CPU time 10.67 seconds
Started Jul 04 05:15:46 PM PDT 24
Finished Jul 04 05:15:57 PM PDT 24
Peak memory 216312 kb
Host smart-a63e29ad-fdc5-4cfd-aa5e-4e2e8f366d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827104971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.827104971
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1516404085
Short name T326
Test name
Test status
Simulation time 14462818 ps
CPU time 0.87 seconds
Started Jul 04 05:15:46 PM PDT 24
Finished Jul 04 05:15:47 PM PDT 24
Peak memory 206600 kb
Host smart-160e905d-7609-46ab-ab51-e6245c21dfc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516404085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1516404085
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3563052624
Short name T638
Test name
Test status
Simulation time 517146834 ps
CPU time 1 seconds
Started Jul 04 05:15:45 PM PDT 24
Finished Jul 04 05:15:46 PM PDT 24
Peak memory 206920 kb
Host smart-1c116de5-a8b6-40ac-9040-9acb42130194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563052624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3563052624
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.1132852315
Short name T332
Test name
Test status
Simulation time 453721748 ps
CPU time 2.22 seconds
Started Jul 04 05:15:48 PM PDT 24
Finished Jul 04 05:15:51 PM PDT 24
Peak memory 223416 kb
Host smart-0524a1eb-f1c5-49e4-bd9d-352b86e478c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132852315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.1132852315
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3910213515
Short name T984
Test name
Test status
Simulation time 52946828 ps
CPU time 0.7 seconds
Started Jul 04 05:15:58 PM PDT 24
Finished Jul 04 05:15:59 PM PDT 24
Peak memory 205844 kb
Host smart-41f2d18d-d815-4d2f-9723-4a85e772b4b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910213515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3910213515
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.2502560297
Short name T975
Test name
Test status
Simulation time 965994807 ps
CPU time 5.03 seconds
Started Jul 04 05:15:52 PM PDT 24
Finished Jul 04 05:15:57 PM PDT 24
Peak memory 232588 kb
Host smart-12d6b21c-3d99-44df-a75d-19c5f5510e2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502560297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.2502560297
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1758452781
Short name T477
Test name
Test status
Simulation time 22989915 ps
CPU time 0.78 seconds
Started Jul 04 05:15:50 PM PDT 24
Finished Jul 04 05:15:51 PM PDT 24
Peak memory 206560 kb
Host smart-77864a68-1f29-44dd-8fa3-d9728189593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758452781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1758452781
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.955575723
Short name T551
Test name
Test status
Simulation time 7786613679 ps
CPU time 25.85 seconds
Started Jul 04 05:15:52 PM PDT 24
Finished Jul 04 05:16:19 PM PDT 24
Peak memory 232712 kb
Host smart-bcd4e490-d18c-4fcb-a9c6-37b411d53d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955575723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.955575723
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.4215734496
Short name T714
Test name
Test status
Simulation time 12740733225 ps
CPU time 40.03 seconds
Started Jul 04 05:15:54 PM PDT 24
Finished Jul 04 05:16:34 PM PDT 24
Peak memory 253080 kb
Host smart-c28b54ec-9f0e-4bb8-a669-808eb14c55d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215734496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.4215734496
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1843887872
Short name T122
Test name
Test status
Simulation time 13208479753 ps
CPU time 42.29 seconds
Started Jul 04 05:15:53 PM PDT 24
Finished Jul 04 05:16:35 PM PDT 24
Peak memory 250892 kb
Host smart-067774c2-8ac9-4ca9-8683-34a4ce175364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843887872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1843887872
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.530146459
Short name T1008
Test name
Test status
Simulation time 14035164870 ps
CPU time 13.5 seconds
Started Jul 04 05:15:52 PM PDT 24
Finished Jul 04 05:16:05 PM PDT 24
Peak memory 224560 kb
Host smart-e5ef41ab-2629-40e6-a352-2878fdb723f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530146459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.530146459
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.692786003
Short name T837
Test name
Test status
Simulation time 15955253350 ps
CPU time 28.46 seconds
Started Jul 04 05:15:51 PM PDT 24
Finished Jul 04 05:16:20 PM PDT 24
Peak memory 232712 kb
Host smart-b10821b7-0f2e-48a7-8551-a0583011c21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692786003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.692786003
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1765015166
Short name T598
Test name
Test status
Simulation time 5503870378 ps
CPU time 9.12 seconds
Started Jul 04 05:15:53 PM PDT 24
Finished Jul 04 05:16:03 PM PDT 24
Peak memory 232656 kb
Host smart-c611dac4-32ca-4fd9-9dfb-4678ca520abf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765015166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1765015166
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3028484743
Short name T721
Test name
Test status
Simulation time 721383274 ps
CPU time 3.58 seconds
Started Jul 04 05:15:53 PM PDT 24
Finished Jul 04 05:15:57 PM PDT 24
Peak memory 224368 kb
Host smart-5ba7f23c-1e7b-487a-b813-527984667357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3028484743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3028484743
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1764861501
Short name T9
Test name
Test status
Simulation time 238345733 ps
CPU time 2.66 seconds
Started Jul 04 05:15:52 PM PDT 24
Finished Jul 04 05:15:56 PM PDT 24
Peak memory 224424 kb
Host smart-37b1b2a3-d878-4d90-8e25-9347e7a27a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764861501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1764861501
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.2206852891
Short name T404
Test name
Test status
Simulation time 1513401467 ps
CPU time 4.16 seconds
Started Jul 04 05:15:52 PM PDT 24
Finished Jul 04 05:15:56 PM PDT 24
Peak memory 219316 kb
Host smart-c71686a0-fcd7-4800-a762-81d753e3e52a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2206852891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.2206852891
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.2034027675
Short name T349
Test name
Test status
Simulation time 3038275329 ps
CPU time 4.84 seconds
Started Jul 04 05:15:51 PM PDT 24
Finished Jul 04 05:15:56 PM PDT 24
Peak memory 216436 kb
Host smart-0eac955c-0383-408f-8fd6-b7a86fcf52a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034027675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.2034027675
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3107533777
Short name T352
Test name
Test status
Simulation time 31235938697 ps
CPU time 12.74 seconds
Started Jul 04 05:15:52 PM PDT 24
Finished Jul 04 05:16:05 PM PDT 24
Peak memory 216220 kb
Host smart-09c581f8-fe55-45aa-8558-11eac70d136a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107533777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3107533777
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.1801678009
Short name T340
Test name
Test status
Simulation time 138118842 ps
CPU time 5.09 seconds
Started Jul 04 05:15:52 PM PDT 24
Finished Jul 04 05:15:57 PM PDT 24
Peak memory 216076 kb
Host smart-95aaebf8-df08-49eb-8fb0-7d617cb15843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801678009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.1801678009
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.2921916811
Short name T494
Test name
Test status
Simulation time 54730828 ps
CPU time 0.77 seconds
Started Jul 04 05:15:53 PM PDT 24
Finished Jul 04 05:15:54 PM PDT 24
Peak memory 205864 kb
Host smart-e7d80530-b197-4fbc-ab38-ad298742e036
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921916811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.2921916811
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1819465059
Short name T253
Test name
Test status
Simulation time 10527826152 ps
CPU time 32.33 seconds
Started Jul 04 05:15:51 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 234732 kb
Host smart-97ea2479-a828-4fbd-a802-58a1bf0fb967
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1819465059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1819465059
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2857347550
Short name T1009
Test name
Test status
Simulation time 12261376 ps
CPU time 0.73 seconds
Started Jul 04 05:15:57 PM PDT 24
Finished Jul 04 05:15:58 PM PDT 24
Peak memory 204904 kb
Host smart-c39964ea-156b-47f4-8440-6844f873b1cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857347550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2857347550
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1142800717
Short name T284
Test name
Test status
Simulation time 1502451004 ps
CPU time 11.26 seconds
Started Jul 04 05:16:05 PM PDT 24
Finished Jul 04 05:16:17 PM PDT 24
Peak memory 224420 kb
Host smart-29b1e6b3-6566-40bb-a7bf-890bfbd1efb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142800717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1142800717
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.360865162
Short name T466
Test name
Test status
Simulation time 22335498 ps
CPU time 0.82 seconds
Started Jul 04 05:16:00 PM PDT 24
Finished Jul 04 05:16:01 PM PDT 24
Peak memory 206552 kb
Host smart-1ad5d6c0-02cd-4364-8d74-5879457a7f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360865162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.360865162
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.1479268241
Short name T240
Test name
Test status
Simulation time 25756977590 ps
CPU time 184.06 seconds
Started Jul 04 05:15:57 PM PDT 24
Finished Jul 04 05:19:01 PM PDT 24
Peak memory 249828 kb
Host smart-ced111c6-80fb-404b-8a7a-2b1e35e4ecc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1479268241 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.1479268241
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2923689317
Short name T259
Test name
Test status
Simulation time 10947493280 ps
CPU time 88.06 seconds
Started Jul 04 05:16:03 PM PDT 24
Finished Jul 04 05:17:31 PM PDT 24
Peak memory 255476 kb
Host smart-013990fa-996c-4219-a2cd-7601f111311c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923689317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2923689317
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1579453625
Short name T922
Test name
Test status
Simulation time 7179619357 ps
CPU time 15.99 seconds
Started Jul 04 05:15:59 PM PDT 24
Finished Jul 04 05:16:15 PM PDT 24
Peak memory 234736 kb
Host smart-64a9388c-637e-4260-b5b8-f43ad5a68c2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579453625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1579453625
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.4089070138
Short name T78
Test name
Test status
Simulation time 1379122553 ps
CPU time 30.22 seconds
Started Jul 04 05:15:58 PM PDT 24
Finished Jul 04 05:16:29 PM PDT 24
Peak memory 239816 kb
Host smart-33351f8d-72a4-4b16-bd21-3971d4047f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089070138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.4089070138
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.3416958447
Short name T826
Test name
Test status
Simulation time 2036882484 ps
CPU time 7.93 seconds
Started Jul 04 05:15:57 PM PDT 24
Finished Jul 04 05:16:06 PM PDT 24
Peak memory 224368 kb
Host smart-70a524e5-fff4-4a70-9298-d6d0efdb3259
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416958447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.3416958447
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.397296532
Short name T736
Test name
Test status
Simulation time 31860186568 ps
CPU time 44.9 seconds
Started Jul 04 05:16:00 PM PDT 24
Finished Jul 04 05:16:45 PM PDT 24
Peak memory 232760 kb
Host smart-320adf92-5684-4085-9879-82683600989f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397296532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.397296532
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2225104614
Short name T46
Test name
Test status
Simulation time 942584846 ps
CPU time 8.06 seconds
Started Jul 04 05:16:00 PM PDT 24
Finished Jul 04 05:16:08 PM PDT 24
Peak memory 232620 kb
Host smart-91c34066-efdb-4bff-b4df-684439ec250e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225104614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2225104614
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1253373286
Short name T741
Test name
Test status
Simulation time 382358314 ps
CPU time 2.4 seconds
Started Jul 04 05:16:01 PM PDT 24
Finished Jul 04 05:16:04 PM PDT 24
Peak memory 223368 kb
Host smart-3c3304ad-d30d-4dd8-82fb-76aca807cda0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253373286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1253373286
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1403547507
Short name T849
Test name
Test status
Simulation time 1764650553 ps
CPU time 7.32 seconds
Started Jul 04 05:16:04 PM PDT 24
Finished Jul 04 05:16:11 PM PDT 24
Peak memory 223144 kb
Host smart-a4bfde7e-8b1b-49f6-b780-38d886914187
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1403547507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1403547507
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.848398729
Short name T886
Test name
Test status
Simulation time 31788760930 ps
CPU time 218.07 seconds
Started Jul 04 05:16:00 PM PDT 24
Finished Jul 04 05:19:38 PM PDT 24
Peak memory 273752 kb
Host smart-9f06983b-450c-48db-ad8b-9e201b916d4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848398729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.848398729
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3422378504
Short name T653
Test name
Test status
Simulation time 5125600665 ps
CPU time 25.94 seconds
Started Jul 04 05:15:59 PM PDT 24
Finished Jul 04 05:16:26 PM PDT 24
Peak memory 216264 kb
Host smart-f12b2f59-8549-47b2-a2ed-b5dee40ed250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422378504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3422378504
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.337550326
Short name T783
Test name
Test status
Simulation time 9195867975 ps
CPU time 13.33 seconds
Started Jul 04 05:15:59 PM PDT 24
Finished Jul 04 05:16:12 PM PDT 24
Peak memory 216272 kb
Host smart-fb095add-2fcf-4bc6-ac66-6b8ad89fc444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337550326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.337550326
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1435307285
Short name T630
Test name
Test status
Simulation time 1068855142 ps
CPU time 5.91 seconds
Started Jul 04 05:15:58 PM PDT 24
Finished Jul 04 05:16:05 PM PDT 24
Peak memory 216088 kb
Host smart-cf758751-13f6-4ac1-90e5-978aef90920c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435307285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1435307285
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.425733543
Short name T576
Test name
Test status
Simulation time 74964982 ps
CPU time 0.86 seconds
Started Jul 04 05:16:00 PM PDT 24
Finished Jul 04 05:16:01 PM PDT 24
Peak memory 205884 kb
Host smart-7aab2a8d-64f6-44ab-9c65-09c084d709d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425733543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.425733543
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.389062772
Short name T878
Test name
Test status
Simulation time 191918241 ps
CPU time 2.82 seconds
Started Jul 04 05:16:00 PM PDT 24
Finished Jul 04 05:16:03 PM PDT 24
Peak memory 224312 kb
Host smart-ca1e8973-9775-42d3-9888-61889b634997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389062772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.389062772
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.2877168563
Short name T731
Test name
Test status
Simulation time 12110607 ps
CPU time 0.72 seconds
Started Jul 04 05:16:07 PM PDT 24
Finished Jul 04 05:16:07 PM PDT 24
Peak memory 205392 kb
Host smart-305f0e91-5449-4436-bd20-bc41c09bc48b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877168563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
2877168563
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.3829406636
Short name T380
Test name
Test status
Simulation time 842879101 ps
CPU time 6.01 seconds
Started Jul 04 05:15:57 PM PDT 24
Finished Jul 04 05:16:04 PM PDT 24
Peak memory 224404 kb
Host smart-74b0084c-04fc-4fe7-a013-3ac775c57218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829406636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.3829406636
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3636802193
Short name T500
Test name
Test status
Simulation time 27245891 ps
CPU time 0.74 seconds
Started Jul 04 05:16:04 PM PDT 24
Finished Jul 04 05:16:05 PM PDT 24
Peak memory 205520 kb
Host smart-4b8d5ec0-40bd-4c13-a18a-c6b635662aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3636802193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3636802193
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.3605308927
Short name T923
Test name
Test status
Simulation time 6101320943 ps
CPU time 21.62 seconds
Started Jul 04 05:16:04 PM PDT 24
Finished Jul 04 05:16:26 PM PDT 24
Peak memory 249332 kb
Host smart-29dcd4a9-ecc8-4390-b7c0-acfccf03e970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605308927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.3605308927
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.1792580585
Short name T969
Test name
Test status
Simulation time 1350431671 ps
CPU time 39.61 seconds
Started Jul 04 05:16:07 PM PDT 24
Finished Jul 04 05:16:47 PM PDT 24
Peak memory 251376 kb
Host smart-85d371b0-aea3-4824-9545-dddebaa9ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792580585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.1792580585
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1906222243
Short name T227
Test name
Test status
Simulation time 39321622970 ps
CPU time 87.07 seconds
Started Jul 04 05:16:08 PM PDT 24
Finished Jul 04 05:17:36 PM PDT 24
Peak memory 257256 kb
Host smart-73f34e23-cca8-4012-86b1-c1d2ecdac1dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906222243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1906222243
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2551221079
Short name T482
Test name
Test status
Simulation time 979906785 ps
CPU time 9.17 seconds
Started Jul 04 05:15:58 PM PDT 24
Finished Jul 04 05:16:07 PM PDT 24
Peak memory 224420 kb
Host smart-e1feb04d-cb3b-4849-b081-665dd3478c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551221079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2551221079
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3418023998
Short name T43
Test name
Test status
Simulation time 10049812661 ps
CPU time 81.58 seconds
Started Jul 04 05:16:00 PM PDT 24
Finished Jul 04 05:17:22 PM PDT 24
Peak memory 240732 kb
Host smart-d44d427b-8eb4-4e49-862b-01a0f852e665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3418023998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3418023998
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.655531191
Short name T723
Test name
Test status
Simulation time 2529929185 ps
CPU time 26.61 seconds
Started Jul 04 05:15:57 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 224532 kb
Host smart-4409976e-67b2-4f6e-aa84-8b2ebd65be3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655531191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.655531191
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.2581994504
Short name T199
Test name
Test status
Simulation time 3827122202 ps
CPU time 30.35 seconds
Started Jul 04 05:15:58 PM PDT 24
Finished Jul 04 05:16:28 PM PDT 24
Peak memory 240592 kb
Host smart-50493909-c79b-4cad-b7f7-9efb006be722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581994504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.2581994504
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.3567180674
Short name T289
Test name
Test status
Simulation time 400703093 ps
CPU time 5.12 seconds
Started Jul 04 05:15:57 PM PDT 24
Finished Jul 04 05:16:03 PM PDT 24
Peak memory 240376 kb
Host smart-649b3110-49d6-4590-abb4-e5f60feb8dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3567180674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.3567180674
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3882134996
Short name T972
Test name
Test status
Simulation time 542849486 ps
CPU time 3.7 seconds
Started Jul 04 05:15:59 PM PDT 24
Finished Jul 04 05:16:03 PM PDT 24
Peak memory 224380 kb
Host smart-87ee9d1d-dbe7-4783-bc84-e1ccd32fb16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882134996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3882134996
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.3430409329
Short name T830
Test name
Test status
Simulation time 291469334 ps
CPU time 4.34 seconds
Started Jul 04 05:16:03 PM PDT 24
Finished Jul 04 05:16:08 PM PDT 24
Peak memory 218600 kb
Host smart-c5cde623-c3d8-42e6-8c0c-4c8675cb3b47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3430409329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.3430409329
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2920124965
Short name T406
Test name
Test status
Simulation time 44886433290 ps
CPU time 241.76 seconds
Started Jul 04 05:16:06 PM PDT 24
Finished Jul 04 05:20:08 PM PDT 24
Peak memory 256232 kb
Host smart-1d7a28ba-fd35-4169-aa3d-8eb5ba7f6a7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920124965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2920124965
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.948030705
Short name T1012
Test name
Test status
Simulation time 3281592876 ps
CPU time 32.3 seconds
Started Jul 04 05:15:58 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 216224 kb
Host smart-6ee15dc9-5b08-4eab-a59c-04d8c46e45b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948030705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.948030705
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2731501713
Short name T69
Test name
Test status
Simulation time 1531706963 ps
CPU time 6.77 seconds
Started Jul 04 05:15:59 PM PDT 24
Finished Jul 04 05:16:06 PM PDT 24
Peak memory 216200 kb
Host smart-49e7c9a1-d1d2-4432-a925-2ece62554ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731501713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2731501713
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.892811785
Short name T804
Test name
Test status
Simulation time 18031375 ps
CPU time 0.82 seconds
Started Jul 04 05:16:01 PM PDT 24
Finished Jul 04 05:16:02 PM PDT 24
Peak memory 205864 kb
Host smart-e064135b-4365-4953-a69f-cc7f7f1471a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892811785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.892811785
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3595958027
Short name T746
Test name
Test status
Simulation time 36443220 ps
CPU time 0.71 seconds
Started Jul 04 05:15:57 PM PDT 24
Finished Jul 04 05:15:58 PM PDT 24
Peak memory 205912 kb
Host smart-0edafa5f-17a7-4136-abf0-75af5c946149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595958027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3595958027
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.3648623953
Short name T838
Test name
Test status
Simulation time 4821110419 ps
CPU time 7.16 seconds
Started Jul 04 05:15:58 PM PDT 24
Finished Jul 04 05:16:05 PM PDT 24
Peak memory 224548 kb
Host smart-caca8d45-f6f4-43d0-ba82-7eb0a953473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648623953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.3648623953
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.346131686
Short name T399
Test name
Test status
Simulation time 27836626 ps
CPU time 0.72 seconds
Started Jul 04 05:16:07 PM PDT 24
Finished Jul 04 05:16:08 PM PDT 24
Peak memory 205776 kb
Host smart-80f7e03e-789a-4cba-87e9-d289b92023d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346131686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.346131686
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3923461235
Short name T79
Test name
Test status
Simulation time 1124638334 ps
CPU time 3.39 seconds
Started Jul 04 05:16:07 PM PDT 24
Finished Jul 04 05:16:10 PM PDT 24
Peak memory 224428 kb
Host smart-c5840b50-c7d4-4efd-a923-bb8bf0e40c32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923461235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3923461235
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1143429383
Short name T979
Test name
Test status
Simulation time 55953828 ps
CPU time 0.76 seconds
Started Jul 04 05:16:09 PM PDT 24
Finished Jul 04 05:16:10 PM PDT 24
Peak memory 206848 kb
Host smart-81765f4d-2511-4e62-896a-ed814e33a4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143429383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1143429383
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3478897215
Short name T943
Test name
Test status
Simulation time 30141679 ps
CPU time 0.82 seconds
Started Jul 04 05:16:07 PM PDT 24
Finished Jul 04 05:16:08 PM PDT 24
Peak memory 215880 kb
Host smart-2a912a0a-ab11-4a00-8fc4-be14589d3a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478897215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3478897215
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.262387231
Short name T234
Test name
Test status
Simulation time 19453615910 ps
CPU time 158.97 seconds
Started Jul 04 05:16:09 PM PDT 24
Finished Jul 04 05:18:48 PM PDT 24
Peak memory 253952 kb
Host smart-d610f48a-7533-43c7-87bf-8908782e673c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262387231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.262387231
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.2669161426
Short name T530
Test name
Test status
Simulation time 104522138631 ps
CPU time 249.99 seconds
Started Jul 04 05:16:08 PM PDT 24
Finished Jul 04 05:20:18 PM PDT 24
Peak memory 265364 kb
Host smart-6ab3724c-b02c-4e24-a98d-b5cf7cc89278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669161426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.2669161426
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.2869463948
Short name T294
Test name
Test status
Simulation time 14470720409 ps
CPU time 50.39 seconds
Started Jul 04 05:16:04 PM PDT 24
Finished Jul 04 05:16:55 PM PDT 24
Peak memory 240080 kb
Host smart-4529f92f-3eb2-496e-b2eb-89314ed7d513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869463948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.2869463948
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.1353911989
Short name T330
Test name
Test status
Simulation time 13998847411 ps
CPU time 13.42 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:16:25 PM PDT 24
Peak memory 240904 kb
Host smart-558d0ec4-381b-487c-8ba5-9d2bf8b22dc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353911989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.1353911989
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.407770459
Short name T170
Test name
Test status
Simulation time 348896330 ps
CPU time 4.56 seconds
Started Jul 04 05:16:08 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 224384 kb
Host smart-982b54fe-c553-4b61-bab2-08a9fd3bda26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407770459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.407770459
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.4195598166
Short name T687
Test name
Test status
Simulation time 30733776991 ps
CPU time 79.77 seconds
Started Jul 04 05:16:09 PM PDT 24
Finished Jul 04 05:17:29 PM PDT 24
Peak memory 232756 kb
Host smart-6ba24043-046b-43b9-ba7a-f540b53e25ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195598166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.4195598166
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.82343696
Short name T174
Test name
Test status
Simulation time 2818652253 ps
CPU time 6.69 seconds
Started Jul 04 05:16:08 PM PDT 24
Finished Jul 04 05:16:15 PM PDT 24
Peak memory 240592 kb
Host smart-74e6b19e-e466-4080-b294-421c824727be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82343696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap.82343696
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.1195909988
Short name T1010
Test name
Test status
Simulation time 4400178325 ps
CPU time 8.74 seconds
Started Jul 04 05:16:06 PM PDT 24
Finished Jul 04 05:16:15 PM PDT 24
Peak memory 232688 kb
Host smart-0480a614-888e-44c0-a95c-f322820cd768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195909988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.1195909988
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.478479003
Short name T750
Test name
Test status
Simulation time 213304955 ps
CPU time 4.16 seconds
Started Jul 04 05:16:05 PM PDT 24
Finished Jul 04 05:16:09 PM PDT 24
Peak memory 224156 kb
Host smart-dc8ea784-436a-4c36-b95a-f99042c7531a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=478479003 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dire
ct.478479003
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.3376204083
Short name T225
Test name
Test status
Simulation time 42538314954 ps
CPU time 195.83 seconds
Started Jul 04 05:16:08 PM PDT 24
Finished Jul 04 05:19:25 PM PDT 24
Peak memory 264008 kb
Host smart-a8759176-d1c9-4796-bb75-12ffd2dac5e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3376204083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.3376204083
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.467873814
Short name T705
Test name
Test status
Simulation time 11526480555 ps
CPU time 22.8 seconds
Started Jul 04 05:16:07 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 216320 kb
Host smart-394f0713-9f65-442a-8ec6-6160633ed729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467873814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.467873814
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2052675196
Short name T748
Test name
Test status
Simulation time 4131500501 ps
CPU time 10.73 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 216216 kb
Host smart-3cc258ea-4bb5-45f7-a68f-9ab28aa35f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052675196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2052675196
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3843324796
Short name T485
Test name
Test status
Simulation time 102474774 ps
CPU time 1.53 seconds
Started Jul 04 05:16:06 PM PDT 24
Finished Jul 04 05:16:08 PM PDT 24
Peak memory 216148 kb
Host smart-88b99d83-71ca-4f37-b12f-ae09f7d799d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843324796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3843324796
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1318846481
Short name T817
Test name
Test status
Simulation time 23513060 ps
CPU time 0.8 seconds
Started Jul 04 05:16:05 PM PDT 24
Finished Jul 04 05:16:06 PM PDT 24
Peak memory 205908 kb
Host smart-d313877c-2f3d-4879-b127-6e4f38076e15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318846481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1318846481
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.2890786063
Short name T678
Test name
Test status
Simulation time 35036183503 ps
CPU time 23.71 seconds
Started Jul 04 05:16:04 PM PDT 24
Finished Jul 04 05:16:28 PM PDT 24
Peak memory 224548 kb
Host smart-d1afc0cf-5107-4cbd-ba92-a85a3b3bef8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890786063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.2890786063
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.309053623
Short name T505
Test name
Test status
Simulation time 53317072 ps
CPU time 0.71 seconds
Started Jul 04 05:16:08 PM PDT 24
Finished Jul 04 05:16:09 PM PDT 24
Peak memory 205376 kb
Host smart-7d475f03-cbf8-4040-a052-d1f3f641981f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309053623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.309053623
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.142666614
Short name T871
Test name
Test status
Simulation time 196693902 ps
CPU time 2.55 seconds
Started Jul 04 05:16:05 PM PDT 24
Finished Jul 04 05:16:07 PM PDT 24
Peak memory 232624 kb
Host smart-6842ef05-e46d-45cc-91c5-0f06afe8eb28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142666614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.142666614
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.916317319
Short name T680
Test name
Test status
Simulation time 42753992 ps
CPU time 0.78 seconds
Started Jul 04 05:16:06 PM PDT 24
Finished Jul 04 05:16:07 PM PDT 24
Peak memory 205504 kb
Host smart-f249ea12-ba19-4372-95d7-fc0e3da87252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916317319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.916317319
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1550887322
Short name T854
Test name
Test status
Simulation time 251535358 ps
CPU time 6.5 seconds
Started Jul 04 05:16:09 PM PDT 24
Finished Jul 04 05:16:16 PM PDT 24
Peak memory 234180 kb
Host smart-84a14d5f-b317-4065-8e04-d953a7bd0fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550887322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1550887322
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.277513681
Short name T662
Test name
Test status
Simulation time 20333631876 ps
CPU time 199.12 seconds
Started Jul 04 05:16:05 PM PDT 24
Finished Jul 04 05:19:24 PM PDT 24
Peak memory 250608 kb
Host smart-4ef2e98d-7af7-4943-8ff6-4bd86f11feba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277513681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.277513681
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.427499865
Short name T535
Test name
Test status
Simulation time 108382101 ps
CPU time 3.19 seconds
Started Jul 04 05:16:05 PM PDT 24
Finished Jul 04 05:16:08 PM PDT 24
Peak memory 224356 kb
Host smart-8d95fd4c-625e-4a7f-8543-633e84b5e812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427499865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.427499865
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.1665506411
Short name T961
Test name
Test status
Simulation time 157840124188 ps
CPU time 139.44 seconds
Started Jul 04 05:16:06 PM PDT 24
Finished Jul 04 05:18:25 PM PDT 24
Peak memory 249724 kb
Host smart-89061bce-6311-4976-a9e4-8c84285f1a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665506411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.1665506411
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2713405652
Short name T513
Test name
Test status
Simulation time 788950821 ps
CPU time 4.74 seconds
Started Jul 04 05:16:07 PM PDT 24
Finished Jul 04 05:16:12 PM PDT 24
Peak memory 219644 kb
Host smart-5dd78542-da91-4d74-8bfc-839271674c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713405652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2713405652
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.70827183
Short name T879
Test name
Test status
Simulation time 780070304 ps
CPU time 7.2 seconds
Started Jul 04 05:16:05 PM PDT 24
Finished Jul 04 05:16:12 PM PDT 24
Peak memory 232680 kb
Host smart-166f859a-e36c-43ed-842a-7862624c9823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=70827183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.70827183
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3076382880
Short name T648
Test name
Test status
Simulation time 369547636 ps
CPU time 2.94 seconds
Started Jul 04 05:16:07 PM PDT 24
Finished Jul 04 05:16:11 PM PDT 24
Peak memory 224396 kb
Host smart-eee1505d-3f6c-4152-af68-e9ec5ad7d565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076382880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3076382880
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.945035919
Short name T903
Test name
Test status
Simulation time 16482139891 ps
CPU time 24.28 seconds
Started Jul 04 05:16:09 PM PDT 24
Finished Jul 04 05:16:34 PM PDT 24
Peak memory 232716 kb
Host smart-b4ebcf80-ccad-40af-b05b-cf9563c9820f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945035919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.945035919
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.1738131183
Short name T672
Test name
Test status
Simulation time 1221338751 ps
CPU time 7.43 seconds
Started Jul 04 05:16:06 PM PDT 24
Finished Jul 04 05:16:14 PM PDT 24
Peak memory 218688 kb
Host smart-c15aab1c-8144-443b-98c3-a92c9ece1569
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1738131183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.1738131183
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.1830421709
Short name T552
Test name
Test status
Simulation time 2634561453 ps
CPU time 15.93 seconds
Started Jul 04 05:16:06 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 219232 kb
Host smart-b25df28d-3d93-4a2b-b1ce-2ae61f33126c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830421709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.1830421709
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.174937693
Short name T567
Test name
Test status
Simulation time 300399456 ps
CPU time 1.33 seconds
Started Jul 04 05:16:04 PM PDT 24
Finished Jul 04 05:16:06 PM PDT 24
Peak memory 207852 kb
Host smart-1037ae78-e3b4-4e35-9d71-feff1a094edd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174937693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.174937693
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2275311857
Short name T835
Test name
Test status
Simulation time 127652346 ps
CPU time 1.09 seconds
Started Jul 04 05:16:09 PM PDT 24
Finished Jul 04 05:16:10 PM PDT 24
Peak memory 207956 kb
Host smart-c89e3b28-fe5b-4263-a8be-dac21852ad50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275311857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2275311857
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.448686755
Short name T441
Test name
Test status
Simulation time 147710815 ps
CPU time 0.88 seconds
Started Jul 04 05:16:08 PM PDT 24
Finished Jul 04 05:16:09 PM PDT 24
Peak memory 205816 kb
Host smart-babcc553-8e49-4e63-ba0f-fcd9f913c63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448686755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.448686755
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1790941401
Short name T986
Test name
Test status
Simulation time 742384235 ps
CPU time 7.48 seconds
Started Jul 04 05:16:03 PM PDT 24
Finished Jul 04 05:16:11 PM PDT 24
Peak memory 232600 kb
Host smart-2cec1641-79f6-4732-b32e-89367db8ce7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790941401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1790941401
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.3016013249
Short name T763
Test name
Test status
Simulation time 45760670 ps
CPU time 0.72 seconds
Started Jul 04 05:16:15 PM PDT 24
Finished Jul 04 05:16:16 PM PDT 24
Peak memory 205416 kb
Host smart-1cfef0f5-2b38-4181-b5fe-0803d8bf043f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3016013249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
3016013249
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1797433089
Short name T194
Test name
Test status
Simulation time 54322892 ps
CPU time 2.49 seconds
Started Jul 04 05:16:14 PM PDT 24
Finished Jul 04 05:16:17 PM PDT 24
Peak memory 224328 kb
Host smart-eaa858c2-dc51-4b38-b5e6-7d5b86ffbeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797433089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1797433089
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.1372039149
Short name T978
Test name
Test status
Simulation time 340571944 ps
CPU time 0.79 seconds
Started Jul 04 05:16:12 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 206552 kb
Host smart-6eb0c746-9b66-4595-aeb9-84bba6a4918d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372039149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.1372039149
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2666073625
Short name T882
Test name
Test status
Simulation time 31751969945 ps
CPU time 50.53 seconds
Started Jul 04 05:16:13 PM PDT 24
Finished Jul 04 05:17:04 PM PDT 24
Peak memory 250132 kb
Host smart-019a005b-87f9-4e75-9c94-f1a7eca3d44c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666073625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2666073625
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.4069700214
Short name T471
Test name
Test status
Simulation time 5510257477 ps
CPU time 36.49 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:16:48 PM PDT 24
Peak memory 224544 kb
Host smart-7b7d8a62-d888-49aa-9a2a-03841653eb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069700214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.4069700214
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.3801456278
Short name T302
Test name
Test status
Simulation time 8603220204 ps
CPU time 53.86 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:17:06 PM PDT 24
Peak memory 249204 kb
Host smart-f9acba9c-a3ed-4bd4-8a96-5000353ff97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801456278 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.3801456278
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1595727260
Short name T299
Test name
Test status
Simulation time 1963473348 ps
CPU time 10.48 seconds
Started Jul 04 05:16:14 PM PDT 24
Finished Jul 04 05:16:25 PM PDT 24
Peak memory 224308 kb
Host smart-91c39ac1-5e30-46ca-88cd-714b46f7876f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595727260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1595727260
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2914188644
Short name T708
Test name
Test status
Simulation time 6791405895 ps
CPU time 17.99 seconds
Started Jul 04 05:16:15 PM PDT 24
Finished Jul 04 05:16:33 PM PDT 24
Peak memory 224516 kb
Host smart-70c17d4e-6b2f-4769-bf42-eed730a3e7ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914188644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2914188644
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.189086446
Short name T390
Test name
Test status
Simulation time 206224084 ps
CPU time 2.33 seconds
Started Jul 04 05:16:15 PM PDT 24
Finished Jul 04 05:16:17 PM PDT 24
Peak memory 222936 kb
Host smart-2c7a3f5e-496b-46a1-980a-ca3c7c197b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189086446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.189086446
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.55401652
Short name T452
Test name
Test status
Simulation time 364706003 ps
CPU time 5.56 seconds
Started Jul 04 05:16:15 PM PDT 24
Finished Jul 04 05:16:21 PM PDT 24
Peak memory 224456 kb
Host smart-ab64e73d-ce0a-4324-b06a-270d749c3295
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55401652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.55401652
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.1268197838
Short name T198
Test name
Test status
Simulation time 197880044 ps
CPU time 2.74 seconds
Started Jul 04 05:16:15 PM PDT 24
Finished Jul 04 05:16:19 PM PDT 24
Peak memory 232564 kb
Host smart-afdbfd60-f310-4f92-81ce-3a7881b9ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268197838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.1268197838
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1676895022
Short name T273
Test name
Test status
Simulation time 1113029529 ps
CPU time 5.92 seconds
Started Jul 04 05:16:12 PM PDT 24
Finished Jul 04 05:16:18 PM PDT 24
Peak memory 224348 kb
Host smart-103811c3-e9cc-4248-9dbb-1cb216bd7602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676895022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1676895022
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.347046915
Short name T754
Test name
Test status
Simulation time 1799733385 ps
CPU time 15.44 seconds
Started Jul 04 05:16:16 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 222124 kb
Host smart-2bad336e-b625-4e63-b81e-ef39ecdc1a8a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=347046915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dire
ct.347046915
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.641801897
Short name T142
Test name
Test status
Simulation time 186774295 ps
CPU time 0.98 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 207532 kb
Host smart-fa99edbb-c443-44c2-bc7a-1f2c58045ceb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=641801897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stres
s_all.641801897
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.1432856301
Short name T335
Test name
Test status
Simulation time 640924970 ps
CPU time 3.24 seconds
Started Jul 04 05:16:12 PM PDT 24
Finished Jul 04 05:16:16 PM PDT 24
Peak memory 216124 kb
Host smart-3f5dff05-c853-4911-944c-c66df6439e9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432856301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.1432856301
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1686659625
Short name T353
Test name
Test status
Simulation time 71527921 ps
CPU time 0.71 seconds
Started Jul 04 05:16:12 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 205596 kb
Host smart-c53bec50-3376-4997-89a6-75ebbe109cb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686659625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1686659625
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.2442090629
Short name T649
Test name
Test status
Simulation time 99918587 ps
CPU time 3.76 seconds
Started Jul 04 05:16:13 PM PDT 24
Finished Jul 04 05:16:16 PM PDT 24
Peak memory 216060 kb
Host smart-8961f370-83b8-40ce-a83e-e59600abacf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442090629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.2442090629
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.679302178
Short name T462
Test name
Test status
Simulation time 15605590 ps
CPU time 0.72 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:16:12 PM PDT 24
Peak memory 205936 kb
Host smart-9c7133e5-73de-4dcc-a979-48eb5370e2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679302178 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.679302178
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4115411960
Short name T49
Test name
Test status
Simulation time 743821056 ps
CPU time 4.25 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:16:16 PM PDT 24
Peak memory 224388 kb
Host smart-729b4875-2ed4-49f6-bb09-74c96a61320b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4115411960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4115411960
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2245718588
Short name T545
Test name
Test status
Simulation time 65685196 ps
CPU time 0.72 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 205480 kb
Host smart-a04d0bfb-65aa-4132-90d5-caf10f9b7263
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245718588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2245718588
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1417486810
Short name T464
Test name
Test status
Simulation time 2878799518 ps
CPU time 8.21 seconds
Started Jul 04 05:16:12 PM PDT 24
Finished Jul 04 05:16:20 PM PDT 24
Peak memory 232704 kb
Host smart-0bf470c0-a7b0-4f6c-819d-4aa75549a242
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417486810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1417486810
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.435602810
Short name T321
Test name
Test status
Simulation time 37915044 ps
CPU time 0.77 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:16:12 PM PDT 24
Peak memory 206844 kb
Host smart-f02fbaea-cda8-4edc-adbe-b2c4c3694243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435602810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.435602810
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.562010447
Short name T177
Test name
Test status
Simulation time 47889995696 ps
CPU time 124.53 seconds
Started Jul 04 05:16:12 PM PDT 24
Finished Jul 04 05:18:16 PM PDT 24
Peak memory 250904 kb
Host smart-62cc63db-67ef-4fbc-b40e-713060e11185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562010447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.562010447
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.4082683516
Short name T795
Test name
Test status
Simulation time 11796310550 ps
CPU time 71.47 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:17:23 PM PDT 24
Peak memory 265516 kb
Host smart-28908ff9-46d8-494f-9aa1-1ee4f2e0fab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082683516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.4082683516
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1559423900
Short name T529
Test name
Test status
Simulation time 645809350 ps
CPU time 17.65 seconds
Started Jul 04 05:16:13 PM PDT 24
Finished Jul 04 05:16:30 PM PDT 24
Peak memory 233604 kb
Host smart-c6c1f88f-d87d-41e8-8e96-8cea3303164c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559423900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1559423900
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.2238060852
Short name T37
Test name
Test status
Simulation time 260712676884 ps
CPU time 202.66 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:19:34 PM PDT 24
Peak memory 253980 kb
Host smart-47fad3db-32dc-413c-925f-26439424e4b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238060852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.2238060852
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3766963256
Short name T1002
Test name
Test status
Simulation time 1120646740 ps
CPU time 2.37 seconds
Started Jul 04 05:16:13 PM PDT 24
Finished Jul 04 05:16:16 PM PDT 24
Peak memory 222912 kb
Host smart-84514275-166a-497f-9dc5-34c96210a797
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766963256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3766963256
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.4248889122
Short name T181
Test name
Test status
Simulation time 15166910315 ps
CPU time 23.64 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:16:35 PM PDT 24
Peak memory 232744 kb
Host smart-7c5e3886-44a3-4765-9fb3-cecd83d0101c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248889122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.4248889122
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3986314692
Short name T913
Test name
Test status
Simulation time 4279086098 ps
CPU time 9.3 seconds
Started Jul 04 05:16:11 PM PDT 24
Finished Jul 04 05:16:21 PM PDT 24
Peak memory 240648 kb
Host smart-4a9e1080-0b6b-4210-98ce-5d20a2e7e264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986314692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3986314692
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2368193591
Short name T561
Test name
Test status
Simulation time 982998652 ps
CPU time 2.71 seconds
Started Jul 04 05:16:16 PM PDT 24
Finished Jul 04 05:16:19 PM PDT 24
Peak memory 224436 kb
Host smart-ef1e36ab-a5cf-4941-8329-7374ec3733c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368193591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2368193591
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.1592248412
Short name T738
Test name
Test status
Simulation time 319895657 ps
CPU time 3.29 seconds
Started Jul 04 05:16:12 PM PDT 24
Finished Jul 04 05:16:15 PM PDT 24
Peak memory 223080 kb
Host smart-75253517-55b5-40f0-be4e-37945bf1580d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1592248412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.1592248412
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.492151141
Short name T359
Test name
Test status
Simulation time 214985282 ps
CPU time 1.08 seconds
Started Jul 04 05:16:17 PM PDT 24
Finished Jul 04 05:16:18 PM PDT 24
Peak memory 207556 kb
Host smart-f9ac13ff-8dd0-4234-97ad-ffae63fec4bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492151141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stres
s_all.492151141
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.768076757
Short name T517
Test name
Test status
Simulation time 228758273 ps
CPU time 2.12 seconds
Started Jul 04 05:16:14 PM PDT 24
Finished Jul 04 05:16:16 PM PDT 24
Peak memory 216116 kb
Host smart-82b2f4b4-4907-487f-87f9-3d81c08aa238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=768076757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.768076757
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.4175844235
Short name T745
Test name
Test status
Simulation time 774926867 ps
CPU time 1.41 seconds
Started Jul 04 05:16:10 PM PDT 24
Finished Jul 04 05:16:12 PM PDT 24
Peak memory 207852 kb
Host smart-38f27bf0-67fb-4573-9933-a88636ecfef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175844235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.4175844235
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3562303400
Short name T782
Test name
Test status
Simulation time 14601384 ps
CPU time 0.95 seconds
Started Jul 04 05:16:13 PM PDT 24
Finished Jul 04 05:16:14 PM PDT 24
Peak memory 207072 kb
Host smart-b7c8ae2c-3cb4-42e3-b020-40662c4a7736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562303400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3562303400
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2165894044
Short name T771
Test name
Test status
Simulation time 52022457 ps
CPU time 0.86 seconds
Started Jul 04 05:16:10 PM PDT 24
Finished Jul 04 05:16:11 PM PDT 24
Peak memory 205908 kb
Host smart-f9c113a4-096b-4375-847e-81ce9bea52e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165894044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2165894044
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.1187854149
Short name T393
Test name
Test status
Simulation time 198163558 ps
CPU time 2.59 seconds
Started Jul 04 05:16:10 PM PDT 24
Finished Jul 04 05:16:13 PM PDT 24
Peak memory 224440 kb
Host smart-b5a4e613-dc3f-442b-88f0-b41925ee4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187854149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.1187854149
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.1704494154
Short name T719
Test name
Test status
Simulation time 25397503 ps
CPU time 0.71 seconds
Started Jul 04 05:16:21 PM PDT 24
Finished Jul 04 05:16:22 PM PDT 24
Peak memory 204848 kb
Host smart-168ac075-ddcd-4c93-a5e2-80e5989b4c06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704494154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
1704494154
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3559425935
Short name T54
Test name
Test status
Simulation time 69166760 ps
CPU time 3.26 seconds
Started Jul 04 05:16:23 PM PDT 24
Finished Jul 04 05:16:27 PM PDT 24
Peak memory 232644 kb
Host smart-04d57ebc-a42f-42a3-b5fc-f709f4dc7e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559425935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3559425935
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2078509529
Short name T927
Test name
Test status
Simulation time 87905783 ps
CPU time 0.84 seconds
Started Jul 04 05:16:24 PM PDT 24
Finished Jul 04 05:16:25 PM PDT 24
Peak memory 206876 kb
Host smart-19314813-c59b-4dd8-a5bc-c0d0b3f1be38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078509529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2078509529
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1298674374
Short name T38
Test name
Test status
Simulation time 45205209990 ps
CPU time 172.38 seconds
Started Jul 04 05:16:20 PM PDT 24
Finished Jul 04 05:19:12 PM PDT 24
Peak memory 266512 kb
Host smart-948fc6d0-51a7-4580-9d9e-6d69796c962f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1298674374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1298674374
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.626601067
Short name T989
Test name
Test status
Simulation time 4290136189 ps
CPU time 90.35 seconds
Started Jul 04 05:16:21 PM PDT 24
Finished Jul 04 05:17:51 PM PDT 24
Peak memory 264856 kb
Host smart-942042b0-597e-49d1-95a9-04bd202a02b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626601067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.626601067
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3113378797
Short name T521
Test name
Test status
Simulation time 2790888162 ps
CPU time 12.82 seconds
Started Jul 04 05:16:23 PM PDT 24
Finished Jul 04 05:16:36 PM PDT 24
Peak memory 249092 kb
Host smart-5551b4c0-169f-45b5-9ece-1c9d2984d3e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113378797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3113378797
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2824710880
Short name T607
Test name
Test status
Simulation time 188863073 ps
CPU time 3.96 seconds
Started Jul 04 05:16:18 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 224396 kb
Host smart-cffae1f2-61f8-4b9e-8d52-428f28f06f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824710880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2824710880
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.282610808
Short name T777
Test name
Test status
Simulation time 490935932 ps
CPU time 10.61 seconds
Started Jul 04 05:16:23 PM PDT 24
Finished Jul 04 05:16:34 PM PDT 24
Peak memory 239328 kb
Host smart-4bf0a30a-7eda-40ec-8854-cedd85349fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282610808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.282610808
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.3444617551
Short name T682
Test name
Test status
Simulation time 5448480242 ps
CPU time 17.69 seconds
Started Jul 04 05:16:21 PM PDT 24
Finished Jul 04 05:16:39 PM PDT 24
Peak memory 232736 kb
Host smart-8d271a50-6c75-432c-9091-d16a7b10ddb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444617551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.3444617551
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.1418094314
Short name T865
Test name
Test status
Simulation time 2022906653 ps
CPU time 9.05 seconds
Started Jul 04 05:16:21 PM PDT 24
Finished Jul 04 05:16:31 PM PDT 24
Peak memory 224428 kb
Host smart-7294fa9e-4093-46b5-b358-db606e41c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418094314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.1418094314
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.75993960
Short name T497
Test name
Test status
Simulation time 6805810078 ps
CPU time 13.47 seconds
Started Jul 04 05:16:20 PM PDT 24
Finished Jul 04 05:16:34 PM PDT 24
Peak memory 219644 kb
Host smart-45b3c92e-cff2-4124-9335-aff1486296e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=75993960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_direc
t.75993960
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.959340223
Short name T143
Test name
Test status
Simulation time 51478009098 ps
CPU time 156.16 seconds
Started Jul 04 05:16:21 PM PDT 24
Finished Jul 04 05:18:57 PM PDT 24
Peak memory 257320 kb
Host smart-afb9c603-177e-4d2f-a387-40766a70c1bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959340223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.959340223
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.2994909668
Short name T344
Test name
Test status
Simulation time 17021068 ps
CPU time 0.73 seconds
Started Jul 04 05:16:24 PM PDT 24
Finished Jul 04 05:16:25 PM PDT 24
Peak memory 205652 kb
Host smart-efccdf72-5535-4735-ab10-c22574705154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994909668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.2994909668
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3421354291
Short name T728
Test name
Test status
Simulation time 959551192 ps
CPU time 6.54 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:28 PM PDT 24
Peak memory 216204 kb
Host smart-6b2e8566-e227-4190-85f8-0287a03c8104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421354291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3421354291
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2112044396
Short name T774
Test name
Test status
Simulation time 41059263 ps
CPU time 1.01 seconds
Started Jul 04 05:16:23 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 207020 kb
Host smart-33b62b1e-d97f-451a-be45-a620278c31b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2112044396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2112044396
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.1249077290
Short name T391
Test name
Test status
Simulation time 90194141 ps
CPU time 0.97 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:23 PM PDT 24
Peak memory 206952 kb
Host smart-0bbffc9a-a4af-4d14-85ad-7784acbdd3df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1249077290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.1249077290
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.3920451524
Short name T121
Test name
Test status
Simulation time 205247337 ps
CPU time 3.24 seconds
Started Jul 04 05:16:22 PM PDT 24
Finished Jul 04 05:16:26 PM PDT 24
Peak memory 232596 kb
Host smart-110429cc-2b33-4da8-a48f-8ed06a828c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920451524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.3920451524
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.4082893320
Short name T851
Test name
Test status
Simulation time 50380518 ps
CPU time 0.71 seconds
Started Jul 04 05:12:50 PM PDT 24
Finished Jul 04 05:12:51 PM PDT 24
Peak memory 205784 kb
Host smart-1f97ca85-7b68-4fad-9a99-3da703b8029a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4082893320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.4
082893320
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2276267730
Short name T453
Test name
Test status
Simulation time 117490187 ps
CPU time 2.64 seconds
Started Jul 04 05:12:38 PM PDT 24
Finished Jul 04 05:12:41 PM PDT 24
Peak memory 232332 kb
Host smart-d85d2891-da0b-46af-9f3d-e8f83dd8cd37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276267730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2276267730
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2722293021
Short name T117
Test name
Test status
Simulation time 21905437 ps
CPU time 0.77 seconds
Started Jul 04 05:12:38 PM PDT 24
Finished Jul 04 05:12:39 PM PDT 24
Peak memory 206560 kb
Host smart-5c79cb6a-5ac6-44d1-9204-d745aff7ef8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722293021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2722293021
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.755550090
Short name T693
Test name
Test status
Simulation time 31236408777 ps
CPU time 36.18 seconds
Started Jul 04 05:12:49 PM PDT 24
Finished Jul 04 05:13:26 PM PDT 24
Peak memory 240832 kb
Host smart-28600ef1-8115-4794-9f14-1a2b5cc31b9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=755550090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.755550090
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.4076939563
Short name T188
Test name
Test status
Simulation time 42831742987 ps
CPU time 360.99 seconds
Started Jul 04 05:12:49 PM PDT 24
Finished Jul 04 05:18:50 PM PDT 24
Peak memory 257368 kb
Host smart-d28a38f2-0d3f-4a9f-a33d-c69c341ff632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4076939563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.4076939563
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2581327953
Short name T988
Test name
Test status
Simulation time 22562906239 ps
CPU time 215.2 seconds
Started Jul 04 05:12:50 PM PDT 24
Finished Jul 04 05:16:25 PM PDT 24
Peak memory 256776 kb
Host smart-0e94c39b-eb68-4084-b898-42bc913de970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581327953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2581327953
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3718614923
Short name T831
Test name
Test status
Simulation time 123266518 ps
CPU time 3.41 seconds
Started Jul 04 05:12:49 PM PDT 24
Finished Jul 04 05:12:52 PM PDT 24
Peak memory 224440 kb
Host smart-6a597683-dba1-4436-9712-eabf2a24a027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718614923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3718614923
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3227822936
Short name T737
Test name
Test status
Simulation time 84526589115 ps
CPU time 102.12 seconds
Started Jul 04 05:12:52 PM PDT 24
Finished Jul 04 05:14:34 PM PDT 24
Peak memory 240708 kb
Host smart-25cc91a8-7038-4629-8b03-139c1c073a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227822936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3227822936
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.2968171702
Short name T982
Test name
Test status
Simulation time 359906480 ps
CPU time 3.18 seconds
Started Jul 04 05:12:42 PM PDT 24
Finished Jul 04 05:12:45 PM PDT 24
Peak memory 224368 kb
Host smart-f20a183d-8970-4024-8bf3-ef5921ddb087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968171702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.2968171702
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1393468645
Short name T195
Test name
Test status
Simulation time 406691006 ps
CPU time 9.39 seconds
Started Jul 04 05:12:42 PM PDT 24
Finished Jul 04 05:12:51 PM PDT 24
Peak memory 233676 kb
Host smart-fed57108-841e-4b98-92cc-3b74ec267837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393468645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1393468645
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4260128639
Short name T208
Test name
Test status
Simulation time 2493652806 ps
CPU time 5.25 seconds
Started Jul 04 05:12:38 PM PDT 24
Finished Jul 04 05:12:44 PM PDT 24
Peak memory 224528 kb
Host smart-ea8f8700-b9fe-4f2e-9b92-7b9c8122b8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260128639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4260128639
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.74671932
Short name T836
Test name
Test status
Simulation time 22313978203 ps
CPU time 35.7 seconds
Started Jul 04 05:12:39 PM PDT 24
Finished Jul 04 05:13:16 PM PDT 24
Peak memory 238956 kb
Host smart-f7e7b69e-3493-4f5f-a7bd-cff210e269c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74671932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.74671932
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3507951040
Short name T896
Test name
Test status
Simulation time 12711925109 ps
CPU time 18.46 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 222060 kb
Host smart-2032ec25-0aff-4efe-971d-c504adfe11b4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3507951040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3507951040
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2266130705
Short name T280
Test name
Test status
Simulation time 147983854036 ps
CPU time 215.32 seconds
Started Jul 04 05:12:48 PM PDT 24
Finished Jul 04 05:16:24 PM PDT 24
Peak memory 265516 kb
Host smart-daeadaa2-c8ca-422e-a590-5501388170b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266130705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2266130705
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.764197213
Short name T301
Test name
Test status
Simulation time 5404793632 ps
CPU time 20.16 seconds
Started Jul 04 05:12:37 PM PDT 24
Finished Jul 04 05:12:58 PM PDT 24
Peak memory 220192 kb
Host smart-de7e5535-abe9-46ab-96d3-25e8995cb9bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764197213 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.764197213
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3163523293
Short name T354
Test name
Test status
Simulation time 15761144340 ps
CPU time 25.03 seconds
Started Jul 04 05:12:42 PM PDT 24
Finished Jul 04 05:13:07 PM PDT 24
Peak memory 216288 kb
Host smart-4c84b309-6a10-4818-954f-f2c114cba1bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163523293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3163523293
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.3691883680
Short name T902
Test name
Test status
Simulation time 618409214 ps
CPU time 1.49 seconds
Started Jul 04 05:12:39 PM PDT 24
Finished Jul 04 05:12:41 PM PDT 24
Peak memory 216132 kb
Host smart-79f2daf0-38e8-49d8-b5e7-059d707765b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691883680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.3691883680
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1472555073
Short name T967
Test name
Test status
Simulation time 18336402 ps
CPU time 0.74 seconds
Started Jul 04 05:12:39 PM PDT 24
Finished Jul 04 05:12:40 PM PDT 24
Peak memory 205884 kb
Host smart-884e1362-57f6-46e7-8364-c5e24b4c1d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472555073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1472555073
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.305605689
Short name T974
Test name
Test status
Simulation time 6248807785 ps
CPU time 20.33 seconds
Started Jul 04 05:12:39 PM PDT 24
Finished Jul 04 05:13:00 PM PDT 24
Peak memory 232768 kb
Host smart-aabd409a-8321-4468-8ff1-8a2b762d7da9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305605689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.305605689
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2951563700
Short name T445
Test name
Test status
Simulation time 16206670 ps
CPU time 0.73 seconds
Started Jul 04 05:13:08 PM PDT 24
Finished Jul 04 05:13:09 PM PDT 24
Peak memory 205768 kb
Host smart-48a8312a-8aac-4375-80b0-544df271595f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951563700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
951563700
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.3276661431
Short name T286
Test name
Test status
Simulation time 71620137 ps
CPU time 2.76 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:54 PM PDT 24
Peak memory 232580 kb
Host smart-c1be3e51-fa52-4167-b749-097f1f7515ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276661431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.3276661431
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2304170507
Short name T932
Test name
Test status
Simulation time 171696519 ps
CPU time 0.84 seconds
Started Jul 04 05:12:49 PM PDT 24
Finished Jul 04 05:12:51 PM PDT 24
Peak memory 206536 kb
Host smart-094a1e85-c3dd-4308-8635-edd1428e8ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304170507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2304170507
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1942001327
Short name T608
Test name
Test status
Simulation time 37061634254 ps
CPU time 130.16 seconds
Started Jul 04 05:12:50 PM PDT 24
Finished Jul 04 05:15:01 PM PDT 24
Peak memory 251936 kb
Host smart-08fc0941-e6a6-49f7-8e21-9922109a6421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942001327 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1942001327
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3771385047
Short name T825
Test name
Test status
Simulation time 43075912376 ps
CPU time 270.84 seconds
Started Jul 04 05:12:52 PM PDT 24
Finished Jul 04 05:17:23 PM PDT 24
Peak memory 257144 kb
Host smart-62afc4ec-5806-4b7f-99d5-ee1f4fb7ab3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771385047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3771385047
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.510911469
Short name T665
Test name
Test status
Simulation time 4903830764 ps
CPU time 45.77 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:13:37 PM PDT 24
Peak memory 240584 kb
Host smart-cc729104-1920-4140-bdcf-f7b3ade5bc10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510911469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle.
510911469
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1138900317
Short name T752
Test name
Test status
Simulation time 1195951606 ps
CPU time 11.42 seconds
Started Jul 04 05:12:54 PM PDT 24
Finished Jul 04 05:13:06 PM PDT 24
Peak memory 249052 kb
Host smart-dffc2c8e-d628-46b5-ba6c-c5d2daa46d20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138900317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1138900317
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.2460902805
Short name T210
Test name
Test status
Simulation time 162446364627 ps
CPU time 509.56 seconds
Started Jul 04 05:12:53 PM PDT 24
Finished Jul 04 05:21:23 PM PDT 24
Peak memory 251176 kb
Host smart-dba2592c-95e1-4f99-90c2-d0889c589f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460902805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.2460902805
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1588534044
Short name T696
Test name
Test status
Simulation time 6223472277 ps
CPU time 15.48 seconds
Started Jul 04 05:12:52 PM PDT 24
Finished Jul 04 05:13:07 PM PDT 24
Peak memory 224492 kb
Host smart-841f8cab-341e-4231-905e-0eb487f203bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588534044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1588534044
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.291628990
Short name T812
Test name
Test status
Simulation time 4275530383 ps
CPU time 13.21 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:13:05 PM PDT 24
Peak memory 224348 kb
Host smart-61d45f44-a1d4-4aaa-91c5-d5390fc29f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291628990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.291628990
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.4080372892
Short name T820
Test name
Test status
Simulation time 7753472900 ps
CPU time 7.32 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:58 PM PDT 24
Peak memory 232688 kb
Host smart-1f2ff1b0-1b9f-423d-8a29-2ba95baccd51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080372892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.4080372892
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.1259580569
Short name T856
Test name
Test status
Simulation time 171046650 ps
CPU time 3.29 seconds
Started Jul 04 05:12:53 PM PDT 24
Finished Jul 04 05:12:57 PM PDT 24
Peak memory 232512 kb
Host smart-6e1372ab-bc5a-4566-bc14-7f0ac054d7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259580569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.1259580569
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.2086494879
Short name T341
Test name
Test status
Simulation time 1070845317 ps
CPU time 5.78 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:58 PM PDT 24
Peak memory 219244 kb
Host smart-4f1484ec-cc21-4344-b6a3-c54aeed5ab38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2086494879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.2086494879
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.218897906
Short name T12
Test name
Test status
Simulation time 29759834051 ps
CPU time 47.06 seconds
Started Jul 04 05:12:50 PM PDT 24
Finished Jul 04 05:13:38 PM PDT 24
Peak memory 219808 kb
Host smart-c02c8bab-f09d-4a9b-b0bf-e929581707af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=218897906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.218897906
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.1680419463
Short name T460
Test name
Test status
Simulation time 2862781717 ps
CPU time 19.45 seconds
Started Jul 04 05:12:50 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 216320 kb
Host smart-b1d9b6c2-46ee-40ce-b2e5-954c585131bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680419463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.1680419463
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3775028404
Short name T346
Test name
Test status
Simulation time 4121083884 ps
CPU time 6.06 seconds
Started Jul 04 05:12:50 PM PDT 24
Finished Jul 04 05:12:56 PM PDT 24
Peak memory 216316 kb
Host smart-9578a92a-f8e1-49da-af2a-d81a0b738b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775028404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3775028404
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1314366668
Short name T692
Test name
Test status
Simulation time 45371472 ps
CPU time 0.98 seconds
Started Jul 04 05:12:51 PM PDT 24
Finished Jul 04 05:12:53 PM PDT 24
Peak memory 206452 kb
Host smart-4571d048-7e68-4e53-b06e-b0acbf408464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314366668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1314366668
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.3397776585
Short name T331
Test name
Test status
Simulation time 416195228 ps
CPU time 0.83 seconds
Started Jul 04 05:12:50 PM PDT 24
Finished Jul 04 05:12:52 PM PDT 24
Peak memory 205888 kb
Host smart-2786a9d8-9593-4f98-96ab-d303cd0417ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397776585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.3397776585
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1070223206
Short name T161
Test name
Test status
Simulation time 375650817 ps
CPU time 2.47 seconds
Started Jul 04 05:12:52 PM PDT 24
Finished Jul 04 05:12:55 PM PDT 24
Peak memory 224360 kb
Host smart-6bdc39ea-513b-4de0-821c-50d1d4824e76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070223206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1070223206
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3333083838
Short name T664
Test name
Test status
Simulation time 121715816 ps
CPU time 0.75 seconds
Started Jul 04 05:13:04 PM PDT 24
Finished Jul 04 05:13:05 PM PDT 24
Peak memory 205460 kb
Host smart-45621aa8-34cc-4529-b91f-407beba16e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333083838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
333083838
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2114551609
Short name T459
Test name
Test status
Simulation time 60879901 ps
CPU time 2.62 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 224332 kb
Host smart-e328e8fe-dddb-42f7-a99e-4956ebd238ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114551609 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2114551609
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.3817402124
Short name T670
Test name
Test status
Simulation time 13310676 ps
CPU time 0.75 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:07 PM PDT 24
Peak memory 206876 kb
Host smart-90efd652-ad24-49db-87f8-20b0acce7f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817402124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.3817402124
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.1848620503
Short name T904
Test name
Test status
Simulation time 20965299270 ps
CPU time 80.43 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:14:28 PM PDT 24
Peak memory 255364 kb
Host smart-81a29387-ab96-48ed-8069-97795b1dfefe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848620503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.1848620503
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.3121681465
Short name T124
Test name
Test status
Simulation time 4616855432 ps
CPU time 78.12 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:14:26 PM PDT 24
Peak memory 256804 kb
Host smart-aa9c76e5-3071-49f9-895a-457d480aa652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121681465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.3121681465
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.361586264
Short name T34
Test name
Test status
Simulation time 10157122776 ps
CPU time 81.49 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:14:29 PM PDT 24
Peak memory 256156 kb
Host smart-162f725b-ee5d-4717-a68c-ab9a4e9789f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361586264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.
361586264
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.4021858122
Short name T298
Test name
Test status
Simulation time 838140700 ps
CPU time 9.29 seconds
Started Jul 04 05:13:03 PM PDT 24
Finished Jul 04 05:13:13 PM PDT 24
Peak memory 250396 kb
Host smart-7e314da1-4a6c-497e-9051-5332212a379d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021858122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.4021858122
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3553470852
Short name T228
Test name
Test status
Simulation time 53402451335 ps
CPU time 189.92 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:16:17 PM PDT 24
Peak memory 248852 kb
Host smart-1ef6bc99-619c-4b4c-8fff-f17bb72d70ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553470852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3553470852
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.345219230
Short name T957
Test name
Test status
Simulation time 1570384098 ps
CPU time 9.4 seconds
Started Jul 04 05:13:08 PM PDT 24
Finished Jul 04 05:13:18 PM PDT 24
Peak memory 232588 kb
Host smart-fd61b6c1-eb53-4417-bcf9-efa5e6a5d19a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345219230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.345219230
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.936264078
Short name T869
Test name
Test status
Simulation time 23222020478 ps
CPU time 62.43 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:14:07 PM PDT 24
Peak memory 224440 kb
Host smart-5ab52d5d-e2cc-4fe6-a290-271d480b33c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936264078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.936264078
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3955569388
Short name T220
Test name
Test status
Simulation time 12555436702 ps
CPU time 13.51 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:21 PM PDT 24
Peak memory 239920 kb
Host smart-d601e098-59bf-49b4-a0e3-f7dd608ad5dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955569388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3955569388
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2371533854
Short name T930
Test name
Test status
Simulation time 2443152604 ps
CPU time 9.27 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:16 PM PDT 24
Peak memory 232688 kb
Host smart-f16e3cfc-ff29-43e4-aea3-1a7a770c3dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371533854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2371533854
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1018340312
Short name T465
Test name
Test status
Simulation time 8982028937 ps
CPU time 9.16 seconds
Started Jul 04 05:13:04 PM PDT 24
Finished Jul 04 05:13:13 PM PDT 24
Peak memory 222828 kb
Host smart-0e8206c2-acf0-4929-b60c-1d4cb95d3383
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1018340312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1018340312
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.739015585
Short name T52
Test name
Test status
Simulation time 104074177849 ps
CPU time 470.99 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:20:59 PM PDT 24
Peak memory 285144 kb
Host smart-3c02d421-7491-4fc2-9fe5-d094402334b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739015585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.739015585
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.596091033
Short name T694
Test name
Test status
Simulation time 2327131349 ps
CPU time 6.93 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:15 PM PDT 24
Peak memory 216268 kb
Host smart-8730e23b-cec0-4180-a86e-64c25d8b820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=596091033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.596091033
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.3725669132
Short name T509
Test name
Test status
Simulation time 5611737501 ps
CPU time 4.5 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:12 PM PDT 24
Peak memory 216316 kb
Host smart-6f492658-fd75-4dd7-84fb-a20c71c92322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725669132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.3725669132
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1401821754
Short name T309
Test name
Test status
Simulation time 65484215 ps
CPU time 1.04 seconds
Started Jul 04 05:13:03 PM PDT 24
Finished Jul 04 05:13:04 PM PDT 24
Peak memory 206800 kb
Host smart-24b8d192-b1af-40dd-b962-af33b483495f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401821754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1401821754
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.2586052032
Short name T532
Test name
Test status
Simulation time 52123741 ps
CPU time 0.82 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:07 PM PDT 24
Peak memory 205936 kb
Host smart-7c6b77de-2fc4-44b8-9553-c561fe0577e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586052032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.2586052032
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.3172376862
Short name T518
Test name
Test status
Simulation time 274352392 ps
CPU time 2.88 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:11 PM PDT 24
Peak memory 224396 kb
Host smart-feb1fed0-9483-4229-b22a-8bd9184daccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172376862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.3172376862
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2542019301
Short name T369
Test name
Test status
Simulation time 20191463 ps
CPU time 0.68 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:36 PM PDT 24
Peak memory 205416 kb
Host smart-98d604be-9aec-4ef8-b79f-1491bf041465
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542019301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
542019301
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.3382684921
Short name T285
Test name
Test status
Simulation time 1723558266 ps
CPU time 19.35 seconds
Started Jul 04 05:13:08 PM PDT 24
Finished Jul 04 05:13:28 PM PDT 24
Peak memory 232552 kb
Host smart-3b403c59-f092-4769-85fe-bcd8b5677416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382684921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.3382684921
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1721688177
Short name T323
Test name
Test status
Simulation time 56624778 ps
CPU time 0.77 seconds
Started Jul 04 05:13:04 PM PDT 24
Finished Jul 04 05:13:05 PM PDT 24
Peak memory 206856 kb
Host smart-31c8903b-e2c9-445c-a3c1-158569acbf56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721688177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1721688177
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3786859405
Short name T611
Test name
Test status
Simulation time 9511774149 ps
CPU time 53.48 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:14:01 PM PDT 24
Peak memory 252436 kb
Host smart-29b4400f-3a1e-4b74-a639-457f7abd1fc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786859405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3786859405
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.2211212817
Short name T881
Test name
Test status
Simulation time 49336296134 ps
CPU time 243.87 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:17:10 PM PDT 24
Peak memory 251336 kb
Host smart-541c563f-f1e2-4f76-85e5-3f9b2fe0dad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211212817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.2211212817
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.2118617956
Short name T493
Test name
Test status
Simulation time 14321920436 ps
CPU time 80.18 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:14:56 PM PDT 24
Peak memory 257392 kb
Host smart-91648817-a15d-4773-bc06-7dd4c527a243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118617956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.2118617956
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.4169428434
Short name T852
Test name
Test status
Simulation time 16490418510 ps
CPU time 25.32 seconds
Started Jul 04 05:13:04 PM PDT 24
Finished Jul 04 05:13:30 PM PDT 24
Peak memory 232700 kb
Host smart-11f1b54c-e32c-4b03-91e2-e99c3e579a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169428434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.4169428434
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.3595396742
Short name T796
Test name
Test status
Simulation time 6330880415 ps
CPU time 43.61 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:52 PM PDT 24
Peak memory 224584 kb
Host smart-798b4445-9c8f-4c89-a1ff-c9231cc56efc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3595396742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.3595396742
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3790552523
Short name T660
Test name
Test status
Simulation time 99115458 ps
CPU time 2.21 seconds
Started Jul 04 05:13:08 PM PDT 24
Finished Jul 04 05:13:11 PM PDT 24
Peak memory 224024 kb
Host smart-61ae5ff8-ef2e-4f40-92f9-86f1c56ef511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790552523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3790552523
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3724949819
Short name T507
Test name
Test status
Simulation time 5434827229 ps
CPU time 34.01 seconds
Started Jul 04 05:13:05 PM PDT 24
Finished Jul 04 05:13:40 PM PDT 24
Peak memory 224488 kb
Host smart-cbe25286-5728-4b02-89ad-2f49bd969f3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3724949819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3724949819
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3601677469
Short name T633
Test name
Test status
Simulation time 662295657 ps
CPU time 5.02 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:11 PM PDT 24
Peak memory 232548 kb
Host smart-fdf72ed3-4e78-4dba-ab81-43f7c7b4d7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601677469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3601677469
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.1769710672
Short name T739
Test name
Test status
Simulation time 234370724 ps
CPU time 2.85 seconds
Started Jul 04 05:13:03 PM PDT 24
Finished Jul 04 05:13:06 PM PDT 24
Peak memory 232580 kb
Host smart-8073d047-7e52-4fd2-a9bc-372ad2ec2755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769710672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.1769710672
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.1866738127
Short name T899
Test name
Test status
Simulation time 485043423 ps
CPU time 5.92 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:14 PM PDT 24
Peak memory 220024 kb
Host smart-8db98bd5-120a-4115-9388-411559a17ff4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1866738127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.1866738127
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2579543545
Short name T222
Test name
Test status
Simulation time 64532905101 ps
CPU time 313.92 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:18:50 PM PDT 24
Peak memory 272104 kb
Host smart-2de3fd39-cced-4c97-88c8-7dfdbe96f3ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579543545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2579543545
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.1199168073
Short name T722
Test name
Test status
Simulation time 16162099892 ps
CPU time 39.34 seconds
Started Jul 04 05:13:06 PM PDT 24
Finished Jul 04 05:13:47 PM PDT 24
Peak memory 217864 kb
Host smart-e4f928e8-80df-4efa-a398-98ddecde91ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199168073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.1199168073
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.2154417575
Short name T364
Test name
Test status
Simulation time 1372390937 ps
CPU time 4.34 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:13 PM PDT 24
Peak memory 216256 kb
Host smart-6c1b0d14-452a-4ace-8f79-489adcb1e185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154417575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.2154417575
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.266173518
Short name T454
Test name
Test status
Simulation time 26528568 ps
CPU time 0.96 seconds
Started Jul 04 05:13:08 PM PDT 24
Finished Jul 04 05:13:10 PM PDT 24
Peak memory 206976 kb
Host smart-37b92044-d7a1-4614-a1f6-3e8ecad01719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266173518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.266173518
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1282704095
Short name T389
Test name
Test status
Simulation time 106609503 ps
CPU time 0.71 seconds
Started Jul 04 05:13:07 PM PDT 24
Finished Jul 04 05:13:09 PM PDT 24
Peak memory 205912 kb
Host smart-bf682e8c-eb1c-4bc6-ac97-8981e251a670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1282704095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1282704095
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.363979107
Short name T472
Test name
Test status
Simulation time 3815055099 ps
CPU time 8.89 seconds
Started Jul 04 05:13:08 PM PDT 24
Finished Jul 04 05:13:17 PM PDT 24
Peak memory 232720 kb
Host smart-acfd22bb-25f2-47ae-b27d-8639432519dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363979107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.363979107
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.977277798
Short name T379
Test name
Test status
Simulation time 18156299 ps
CPU time 0.74 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:36 PM PDT 24
Peak memory 204868 kb
Host smart-7936f237-0a94-4b95-9c07-77814fcb4367
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977277798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.977277798
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.653855552
Short name T862
Test name
Test status
Simulation time 923058042 ps
CPU time 4.42 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:41 PM PDT 24
Peak memory 223956 kb
Host smart-b40ba9e1-8cbf-4cee-811d-896b53ec0186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653855552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.653855552
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.3181458596
Short name T374
Test name
Test status
Simulation time 79060685 ps
CPU time 0.83 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:37 PM PDT 24
Peak memory 206472 kb
Host smart-a6a01cc6-fbec-4ebb-8d11-742d777c5c1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181458596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.3181458596
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.536168240
Short name T498
Test name
Test status
Simulation time 12398924 ps
CPU time 0.76 seconds
Started Jul 04 05:13:34 PM PDT 24
Finished Jul 04 05:13:35 PM PDT 24
Peak memory 215740 kb
Host smart-964c790a-a394-497f-b1c6-26899de49a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536168240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.536168240
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.1969416484
Short name T190
Test name
Test status
Simulation time 7230877906 ps
CPU time 97.85 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:15:14 PM PDT 24
Peak memory 254020 kb
Host smart-b3e79781-4786-4cc9-8a94-9a27f14976d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969416484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.1969416484
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2422397392
Short name T264
Test name
Test status
Simulation time 66612268280 ps
CPU time 98.01 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:15:16 PM PDT 24
Peak memory 257328 kb
Host smart-9625d429-5e34-47d0-9256-18e741cd0215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422397392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2422397392
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.796656475
Short name T434
Test name
Test status
Simulation time 152325347 ps
CPU time 2.49 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:39 PM PDT 24
Peak memory 224376 kb
Host smart-39cb6583-0bd4-469f-ab99-e22df65da4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796656475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.796656475
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.4241758665
Short name T235
Test name
Test status
Simulation time 6074723140 ps
CPU time 38.68 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:14:14 PM PDT 24
Peak memory 253736 kb
Host smart-a7caecd6-69fb-4f48-9f91-2be6e95e6844
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241758665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.4241758665
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2914410365
Short name T591
Test name
Test status
Simulation time 1065877203 ps
CPU time 6.66 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:43 PM PDT 24
Peak memory 224392 kb
Host smart-2d7b9caf-2b68-4daa-a27b-d40e7b894da4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914410365 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2914410365
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2537450682
Short name T606
Test name
Test status
Simulation time 2451608886 ps
CPU time 27.49 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:14:04 PM PDT 24
Peak memory 238492 kb
Host smart-012dacfe-9a85-4f28-b5ca-2f28655aedeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537450682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2537450682
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.3578649367
Short name T888
Test name
Test status
Simulation time 15739823739 ps
CPU time 11.43 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:49 PM PDT 24
Peak memory 232664 kb
Host smart-92668754-f0ee-4e29-8ba5-9c338e914e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578649367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.3578649367
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.522986469
Short name T919
Test name
Test status
Simulation time 5203731330 ps
CPU time 8.96 seconds
Started Jul 04 05:13:35 PM PDT 24
Finished Jul 04 05:13:44 PM PDT 24
Peak memory 232736 kb
Host smart-db0f8564-e5e7-4ab8-993c-7c74a56339ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522986469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.522986469
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3923153998
Short name T740
Test name
Test status
Simulation time 318394129 ps
CPU time 4.87 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:13:41 PM PDT 24
Peak memory 222380 kb
Host smart-2b3c3314-a106-4fa2-ac8c-dbad9a0033e2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3923153998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3923153998
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2847242796
Short name T53
Test name
Test status
Simulation time 137612376431 ps
CPU time 752.33 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:26:10 PM PDT 24
Peak memory 273688 kb
Host smart-eee5633b-dc79-4e30-9d7d-9c4fdeffee72
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847242796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2847242796
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3525811034
Short name T426
Test name
Test status
Simulation time 56151505 ps
CPU time 0.72 seconds
Started Jul 04 05:13:34 PM PDT 24
Finished Jul 04 05:13:35 PM PDT 24
Peak memory 205648 kb
Host smart-6361def3-2796-4999-934d-ff513b948f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525811034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3525811034
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1757942507
Short name T958
Test name
Test status
Simulation time 1171054013 ps
CPU time 5.78 seconds
Started Jul 04 05:13:37 PM PDT 24
Finished Jul 04 05:13:43 PM PDT 24
Peak memory 216128 kb
Host smart-2e16620d-3efe-43da-9062-51c790df0ce6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757942507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1757942507
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.1021839065
Short name T947
Test name
Test status
Simulation time 16017300 ps
CPU time 0.8 seconds
Started Jul 04 05:13:33 PM PDT 24
Finished Jul 04 05:13:34 PM PDT 24
Peak memory 205944 kb
Host smart-bffdc3bf-db64-452c-88d6-cd720c2e09b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021839065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.1021839065
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.604138391
Short name T759
Test name
Test status
Simulation time 140583156 ps
CPU time 0.83 seconds
Started Jul 04 05:13:33 PM PDT 24
Finished Jul 04 05:13:34 PM PDT 24
Peak memory 205888 kb
Host smart-aee69cdb-00b0-4d37-a972-2f94d169bdbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604138391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.604138391
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3335926670
Short name T1005
Test name
Test status
Simulation time 9060512300 ps
CPU time 29.63 seconds
Started Jul 04 05:13:36 PM PDT 24
Finished Jul 04 05:14:07 PM PDT 24
Peak memory 240300 kb
Host smart-a55e80d8-81a8-4f3c-b675-23f566360e82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335926670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3335926670
Directory /workspace/9.spi_device_upload/latest
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