Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2493494	1			T1	1		T2	1225		T3	4172
all_values[1]	2493494	1			T1	1		T2	1225		T3	4172
all_values[2]	2493494	1			T1	1		T2	1225		T3	4172
all_values[3]	2493494	1			T1	1		T2	1225		T3	4172
all_values[4]	2493494	1			T1	1		T2	1225		T3	4172
all_values[5]	2493494	1			T1	1		T2	1225		T3	4172
all_values[6]	2493494	1			T1	1		T2	1225		T3	4172
all_values[7]	2493494	1			T1	1		T2	1225		T3	4172

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18949801

1

T1

8

T2

9800

T3

33376

auto[1]

998151

1

T19

33

T20

96

T21

54

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19921992

1

T1

8

T2

9800

T3

33376

auto[1]

25960

1

T12

210

T18

108

T27

61

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2300644	1			T1	1		T2	1225		T3	4172
all_values[0]	auto[0]	auto[1]	11281	1			T12	93		T18	106		T27	33
all_values[0]	auto[1]	auto[0]	180487	1			T19	2		T20	7		T29	5
all_values[0]	auto[1]	auto[1]	1082	1			T19	3		T20	8		T21	5
all_values[1]	auto[0]	auto[0]	2360726	1			T1	1		T2	1225		T3	4172
all_values[1]	auto[0]	auto[1]	7950	1			T12	93		T18	2		T27	14
all_values[1]	auto[1]	auto[0]	124425	1			T19	3		T20	4		T21	4
all_values[1]	auto[1]	auto[1]	393	1			T19	3		T20	14		T21	5
all_values[2]	auto[0]	auto[0]	2376509	1			T1	1		T2	1225		T3	4172
all_values[2]	auto[0]	auto[1]	3072	1			T12	24		T27	14		T34	85
all_values[2]	auto[1]	auto[0]	113519	1			T20	2		T21	3		T22	4
all_values[2]	auto[1]	auto[1]	394	1			T20	5		T21	1		T22	2
all_values[3]	auto[0]	auto[0]	2220415	1			T1	1		T2	1225		T3	4172
all_values[3]	auto[0]	auto[1]	182	1			T19	3		T20	4		T29	3
all_values[3]	auto[1]	auto[0]	272710	1			T19	3		T20	6		T21	8
all_values[3]	auto[1]	auto[1]	187	1			T19	1		T20	6		T21	3
all_values[4]	auto[0]	auto[0]	2420009	1			T1	1		T2	1225		T3	4172
all_values[4]	auto[0]	auto[1]	192	1			T19	1		T20	3		T21	4
all_values[4]	auto[1]	auto[0]	73126	1			T19	2		T20	3		T21	6
all_values[4]	auto[1]	auto[1]	167	1			T20	7		T22	2		T29	1
all_values[5]	auto[0]	auto[0]	2408886	1			T1	1		T2	1225		T3	4172
all_values[5]	auto[0]	auto[1]	172	1			T19	1		T20	6		T21	3
all_values[5]	auto[1]	auto[0]	84265	1			T19	2		T20	5		T21	5
all_values[5]	auto[1]	auto[1]	171	1			T19	2		T20	5		T21	1
all_values[6]	auto[0]	auto[0]	2416306	1			T1	1		T2	1225		T3	4172
all_values[6]	auto[0]	auto[1]	176	1			T19	1		T20	3		T22	2
all_values[6]	auto[1]	auto[0]	76842	1			T19	2		T20	5		T21	5
all_values[6]	auto[1]	auto[1]	170	1			T19	3		T20	7		T21	3
all_values[7]	auto[0]	auto[0]	2423104	1			T1	1		T2	1225		T3	4172
all_values[7]	auto[0]	auto[1]	177	1			T20	3		T21	5		T22	3
all_values[7]	auto[1]	auto[0]	70019	1			T19	3		T20	3		T21	4
all_values[7]	auto[1]	auto[1]	194	1			T19	4		T20	9		T21	1