Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	35062	1			T3	80		T4	110		T6	223
auto[SpiFlashAddrCfg]	7733	1			T3	35		T6	46		T12	46
auto[SpiFlashAddr3b]	9392	1			T3	28		T4	10		T6	50
auto[SpiFlashAddr4b]	7515	1			T3	26		T6	48		T12	60

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33370

1

T3

85

T4

120

T6

120

auto[1]

26332

1

T3

84

T6

247

T12

296

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32441

1

T3

94

T4

2

T6

188

auto[1]

27261

1

T3

75

T4

118

T6

179

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	39832	1			T3	102		T4	116		T6	261
values[1]	1102	1			T3	2		T6	2		T12	3
values[2]	1472	1			T6	5		T8	2		T12	6
values[3]	1526	1			T3	7		T6	9		T12	22
values[4]	1454	1			T3	3		T6	11		T12	10
values[5]	1383	1			T3	4		T6	10		T12	4
values[6]	1416	1			T3	7		T6	9		T12	2
values[7]	1449	1			T3	6		T4	2		T6	8
values[8]	10068	1			T3	38		T4	2		T6	52

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31280

1

T3

169

T4

120

T6

367

auto[1]

28422

1

T16

4

T18

381

T37

151

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

56467

1

T3

165

T4

120

T6

350

write

3235

1

T3

4

T6

17

T12

20

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19401

1

T3

65

T4

10

T6

117

valids[0x1]

40301

1

T3

104

T4

110

T6

250

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1570	1			T3	4		T6	8		T12	6
internal_process_ops[0x5a]	1603	1			T3	4		T6	6		T12	10
internal_process_ops[0x05]	21130	1			T3	51		T4	110		T6	153
internal_process_ops[0x35]	1584	1			T3	3		T6	3		T12	9
internal_process_ops[0x15]	1608	1			T3	1		T6	12		T12	12
internal_process_ops[0x03]	1110	1			T3	3		T6	10		T12	7
internal_process_ops[0x0b]	1037	1			T3	5		T6	6		T12	6
internal_process_ops[0x3b]	1069	1			T3	2		T4	2		T6	6
internal_process_ops[0x6b]	1065	1			T3	4		T6	8		T12	10
internal_process_ops[0xbb]	1073	1			T3	2		T6	10		T12	10
internal_process_ops[0xeb]	1063	1			T3	9		T6	5		T8	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58101

1

T3

168

T4

120

T6

361

auto[1]

1601

1

T3

1

T6

6

T12

11

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

57432

1

T3

162

T4

114

T6

354

auto[1]

2270

1

T3

7

T4

6

T6

13

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10264

1

T3

39

T4

110

T6

57

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6840

1

T3

40

T6

164

T12

200

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2010

1

T3

14

T6

20

T12

14

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1893

1

T3

19

T6

26

T12

28

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2505

1

T3

12

T4

10

T6

17

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2305

1

T3

15

T6

22

T12

35

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2030

1

T3

16

T6

15

T12

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1828

1

T3

10

T6

29

T12

28

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

101

1

T3

1

T6

1

T12

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

118

1

T6

1

T12

4

T38

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

105

1

T27

2

T44

2

T19

3

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

79

1

T12

1

T45

2

T46

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

135

1

T3

2

T12

1

T27

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

103

1

T12

3

T27

1

T19

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

80

1

T27

1

T48

2

T22

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

94

1

T38

5

T47

2

T19

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

128

1

T6

8

T27

2

T19

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

97

1

T3

1

T6

1

T44

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

86

1

T12

1

T27

2

T38

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

84

1

T6

2

T38

1

T44

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

105

1

T12

4

T39

1

T19

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

98

1

T12

1

T27

1

T159

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

76

1

T6

2

T12

1

T38

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

116

1

T6

2

T12

2

T38

1

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10064

1

T18

147

T37

46

T43

20

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

7100

1

T18

93

T37

23

T43

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1481

1

T16

3

T18

16

T37

13

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1493

1

T18

24

T37

12

T43

6

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1888

1

T16

1

T18

37

T37

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1879

1

T18

19

T37

14

T43

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1439

1

T18

10

T37

7

T43

5

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1448

1

T18

14

T37

10

T43

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

97

1

T37

1

T160

1

T161

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

97

1

T34

3

T162

3

T163

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

108

1

T18

2

T160

1

T164

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

89

1

T18

1

T37

2

T34

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

94

1

T34

1

T162

2

T163

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

130

1

T18

1

T37

2

T43

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

117

1

T18

2

T34

1

T162

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

103

1

T18

2

T160

9

T164

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

107

1

T37

1

T160

1

T161

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

99

1

T37

1

T162

1

T160

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

103

1

T34

4

T160

2

T164

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

111

1

T18

4

T37

1

T161

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

96

1

T18

8

T34

2

T162

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

84

1

T43

2

T34

2

T160

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

96

1

T37

2

T43

2

T162

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

99

1

T18

1

T34

2

T162

2

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3889	1			T3	24		T4	6		T6	46
auto[0]	values[0]	valids[0x1]	16187	1			T3	78		T4	110		T6	215
auto[0]	values[1]	valids[0x1]	542	1			T3	2		T6	2		T12	3
auto[0]	values[2]	valids[0x0]	542	1			T6	4		T8	2		T12	5
auto[0]	values[2]	valids[0x1]	317	1			T6	1		T12	1		T27	2
auto[0]	values[3]	valids[0x0]	590	1			T3	6		T6	7		T12	20
auto[0]	values[3]	valids[0x1]	271	1			T3	1		T6	2		T12	2
auto[0]	values[4]	valids[0x0]	533	1			T3	2		T6	8		T12	5
auto[0]	values[4]	valids[0x1]	300	1			T3	1		T6	3		T12	5
auto[0]	values[5]	valids[0x0]	483	1			T3	3		T6	7		T12	4
auto[0]	values[5]	valids[0x1]	264	1			T3	1		T6	3		T27	1
auto[0]	values[6]	valids[0x0]	522	1			T3	3		T6	7		T12	1
auto[0]	values[6]	valids[0x1]	265	1			T3	4		T6	2		T12	1
auto[0]	values[7]	valids[0x0]	507	1			T3	2		T4	2		T6	5
auto[0]	values[7]	valids[0x1]	307	1			T3	4		T6	3		T12	4
auto[0]	values[8]	valids[0x0]	3702	1			T3	25		T4	2		T6	33
auto[0]	values[8]	valids[0x1]	2059	1			T3	13		T6	19		T12	29
auto[1]	values[0]	valids[0x0]	3874	1			T18	51		T37	37		T43	19
auto[1]	values[0]	valids[0x1]	15882	1			T18	226		T37	58		T43	21
auto[1]	values[1]	valids[0x1]	560	1			T18	4		T37	2		T43	5
auto[1]	values[2]	valids[0x0]	344	1			T18	5		T43	2		T34	7
auto[1]	values[2]	valids[0x1]	269	1			T18	6		T34	4		T162	2
auto[1]	values[3]	valids[0x0]	399	1			T18	1		T37	2		T43	3
auto[1]	values[3]	valids[0x1]	266	1			T18	4		T37	3		T43	1
auto[1]	values[4]	valids[0x0]	388	1			T16	3		T18	4		T37	3
auto[1]	values[4]	valids[0x1]	233	1			T18	6		T34	1		T162	2
auto[1]	values[5]	valids[0x0]	367	1			T18	8		T37	1		T43	3
auto[1]	values[5]	valids[0x1]	269	1			T18	4		T37	3		T41	2
auto[1]	values[6]	valids[0x0]	373	1			T18	4		T34	1		T162	3
auto[1]	values[6]	valids[0x1]	256	1			T18	2		T37	4		T34	3
auto[1]	values[7]	valids[0x0]	375	1			T18	6		T37	3		T43	4
auto[1]	values[7]	valids[0x1]	260	1			T18	3		T37	4		T34	4
auto[1]	values[8]	valids[0x0]	2513	1			T18	38		T37	21		T43	15
auto[1]	values[8]	valids[0x1]	1794	1			T16	1		T18	9		T37	10