Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3234648

1

T3

3604

T4

269

T6

14947

auto[1]

30601

1

T3

49

T4

108

T6

147

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

835240

1

T3

38

T4

13

T6

64

auto[1]

2430009

1

T3

3615

T4

364

T6

15030

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	556060	1			T3	5		T4	377		T6	263
auto[524288:1048575]	368062	1			T3	288		T6	563		T7	811
auto[1048576:1572863]	383043	1			T3	2		T6	3000		T7	387
auto[1572864:2097151]	385751	1			T3	14		T6	699		T12	268
auto[2097152:2621439]	367961	1			T3	17		T6	3077		T7	2458
auto[2621440:3145727]	406802	1			T3	1339		T6	2405		T7	945
auto[3145728:3670015]	391398	1			T3	1986		T6	4224		T12	1123
auto[3670016:4194303]	406172	1			T3	2		T6	863		T7	142

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2463899

1

T3

3643

T4

371

T6

15087

auto[1]

801350

1

T3

10

T4

6

T6

7

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2790497

1

T3

2304

T4

377

T6

6492

auto[1]

474752

1

T3

1349

T6

8602

T12

793

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	159335	1			T3	2		T4	7		T6	4
auto[0]	auto[0]	auto[0:524287]	auto[1]	338503	1			T3	1		T4	262		T6	257
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	79356	1			T3	5		T6	8		T7	811
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	237014	1			T3	277		T6	519		T12	1694
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	90617	1			T3	2		T6	7		T7	387
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	229335	1			T6	2993		T12	1116		T13	1757
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	97147	1			T3	1		T6	4		T12	3
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	217541	1			T6	682		T12	260		T13	2120
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	84290	1			T6	6		T7	2458		T12	1
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	238575	1			T6	101		T12	1456		T13	1758
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	114399	1			T3	7		T6	1		T7	945
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	209167	1			T3	2		T12	3411		T18	53
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	93038	1			T3	3		T6	4		T12	12
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	237438	1			T3	1982		T6	1508		T12	1046
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	102500	1			T6	6		T7	142		T12	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	237439	1			T6	259		T18	1028		T27	128
auto[0]	auto[1]	auto[0:524287]	auto[0]	4705	1			T3	1		T6	1		T12	4
auto[0]	auto[1]	auto[0:524287]	auto[1]	48638	1			T12	128		T34	128		T162	388
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	1000	1			T12	1		T18	3		T27	3
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	47986	1			T18	2		T27	5		T37	256
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	732	1			T18	1		T27	2		T37	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	58963	1			T27	1		T43	1616		T34	4767
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	968	1			T3	2		T12	5		T18	2
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	66552	1			T3	1		T18	513		T27	258
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	686	1			T3	1		T6	1		T37	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	38883	1			T3	1		T6	2956		T37	2189
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	956	1			T3	6		T6	3		T12	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	77824	1			T3	1307		T6	2401		T12	641
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	527	1			T3	1		T6	3		T27	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	57244	1			T6	2707		T27	1887		T37	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1290	1			T6	3		T12	1		T37	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	62000	1			T3	2		T6	513		T162	256
auto[1]	auto[0]	auto[0:524287]	auto[0]	434	1			T3	1		T4	6		T6	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	3961	1			T4	102		T12	56		T37	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	402	1			T3	1		T6	4		T12	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	2060	1			T3	5		T6	32		T12	7
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	368	1			T12	1		T37	1		T38	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2508	1			T12	32		T38	15		T34	11
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	358	1			T6	1		T18	3		T38	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2531	1			T6	12		T18	16		T38	19
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	451	1			T6	1		T12	1		T18	7
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	4416	1			T6	12		T12	29		T18	55
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	346	1			T3	2		T27	1		T38	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1796	1			T3	13		T27	1		T38	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	384	1			T12	3		T37	2		T43	10
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2342	1			T12	62		T37	1		T34	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	332	1			T6	3		T18	1		T37	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2114	1			T6	67		T18	9		T37	1
auto[1]	auto[1]	auto[0:524287]	auto[0]	73	1			T162	1		T163	2		T161	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	411	1			T162	49		T163	8		T161	22
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	66	1			T18	2		T22	1		T196	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	178	1			T18	39		T22	2		T196	22
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	58	1			T27	1		T177	3		T30	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	462	1			T27	5		T217	3		T203	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	100	1			T3	1		T18	1		T27	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	554	1			T3	9		T18	2		T27	22
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	54	1			T3	1		T37	1		T22	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	606	1			T3	14		T22	46		T152	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	120	1			T3	1		T12	1		T18	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	2194	1			T3	1		T12	8		T18	19
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	78	1			T6	2		T37	1		T160	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	347	1			T160	1		T60	18		T31	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	70	1			T6	1		T44	2		T152	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	427	1			T6	11		T152	34		T210	21

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1971156	1			T3	2281		T4	265		T6	6355
auto[0]	auto[0]	auto[1]	794538	1			T3	1		T4	4		T6	4
auto[0]	auto[1]	auto[0]	462770	1			T3	1320		T6	8585		T12	784
auto[0]	auto[1]	auto[1]	6184	1			T3	2		T6	3		T27	2
auto[1]	auto[0]	auto[0]	24274	1			T3	18		T4	106		T6	133
auto[1]	auto[0]	auto[1]	529	1			T3	4		T4	2		T12	1
auto[1]	auto[1]	auto[0]	5699	1			T3	24		T6	14		T12	9
auto[1]	auto[1]	auto[1]	99	1			T3	3		T18	1		T27	1