Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2493494	1			T1	1		T2	1225		T3	4172
all_pins[1]	2493494	1			T1	1		T2	1225		T3	4172
all_pins[2]	2493494	1			T1	1		T2	1225		T3	4172
all_pins[3]	2493494	1			T1	1		T2	1225		T3	4172
all_pins[4]	2493494	1			T1	1		T2	1225		T3	4172
all_pins[5]	2493494	1			T1	1		T2	1225		T3	4172
all_pins[6]	2493494	1			T1	1		T2	1225		T3	4172
all_pins[7]	2493494	1			T1	1		T2	1225		T3	4172

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19867246	1			T1	8		T2	9800		T3	33376
values[0x1]	80706	1			T19	16		T20	61		T21	19
transitions[0x0=>0x1]	79187	1			T19	10		T20	27		T21	15
transitions[0x1=>0x0]	79206	1			T19	10		T20	27		T21	15

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2492329	1			T1	1		T2	1225		T3	4172
all_pins[0]	values[0x1]	1165	1			T19	3		T20	8		T21	5
all_pins[0]	transitions[0x0=>0x1]	882	1			T19	2		T20	1		T21	2
all_pins[0]	transitions[0x1=>0x0]	130	1			T19	2		T20	7		T21	2
all_pins[1]	values[0x0]	2493081	1			T1	1		T2	1225		T3	4172
all_pins[1]	values[0x1]	413	1			T19	3		T20	14		T21	5
all_pins[1]	transitions[0x0=>0x1]	317	1			T19	3		T20	9		T21	5
all_pins[1]	transitions[0x1=>0x0]	314	1			T21	1		T30	2		T31	1
all_pins[2]	values[0x0]	2493084	1			T1	1		T2	1225		T3	4172
all_pins[2]	values[0x1]	410	1			T20	5		T21	1		T22	2
all_pins[2]	transitions[0x0=>0x1]	361	1			T20	2		T21	1		T29	1
all_pins[2]	transitions[0x1=>0x0]	138	1			T19	1		T20	3		T21	3
all_pins[3]	values[0x0]	2493307	1			T1	1		T2	1225		T3	4172
all_pins[3]	values[0x1]	187	1			T19	1		T20	6		T21	3
all_pins[3]	transitions[0x0=>0x1]	142	1			T19	1		T20	2		T21	3
all_pins[3]	transitions[0x1=>0x0]	122	1			T20	3		T29	1		T30	4
all_pins[4]	values[0x0]	2493327	1			T1	1		T2	1225		T3	4172
all_pins[4]	values[0x1]	167	1			T20	7		T22	2		T29	1
all_pins[4]	transitions[0x0=>0x1]	128	1			T20	4		T22	2		T29	1
all_pins[4]	transitions[0x1=>0x0]	1551	1			T19	2		T20	2		T21	1
all_pins[5]	values[0x0]	2491904	1			T1	1		T2	1225		T3	4172
all_pins[5]	values[0x1]	1590	1			T19	2		T20	5		T21	1
all_pins[5]	transitions[0x0=>0x1]	697	1			T19	1		T20	2		T21	1
all_pins[5]	transitions[0x1=>0x0]	75687	1			T19	2		T20	4		T21	3
all_pins[6]	values[0x0]	2416914	1			T1	1		T2	1225		T3	4172
all_pins[6]	values[0x1]	76580	1			T19	3		T20	7		T21	3
all_pins[6]	transitions[0x0=>0x1]	76524	1			T20	2		T21	2		T29	1
all_pins[6]	transitions[0x1=>0x0]	138	1			T19	1		T20	4		T30	9
all_pins[7]	values[0x0]	2493300	1			T1	1		T2	1225		T3	4172
all_pins[7]	values[0x1]	194	1			T19	4		T20	9		T21	1
all_pins[7]	transitions[0x0=>0x1]	136	1			T19	3		T20	5		T21	1
all_pins[7]	transitions[0x1=>0x0]	1126	1			T19	2		T20	4		T21	5