Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

17694

1

T3

85

T4

120

T6

120

auto[1]

13586

1

T3

84

T6

247

T12

296

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4154	1			T6	39		T7	4		T12	124
values[1]	4140	1			T4	120		T6	29		T8	2
values[2]	5228	1			T3	56		T6	20		T12	121
values[3]	3140	1			T3	36		T6	40		T12	20
values[4]	3829	1			T3	37		T6	65		T27	20
values[5]	3565	1			T3	20		T6	20		T12	40
values[6]	3770	1			T6	50		T12	50		T38	40
values[7]	3454	1			T3	20		T6	104		T12	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4298	1			T6	119		T12	20		T38	25
values[1]	3119	1			T13	4		T27	23		T38	25
values[2]	4563	1			T3	20		T6	123		T12	73
values[3]	4094	1			T3	37		T6	20		T7	4
values[4]	3457	1			T3	56		T4	120		T12	40
values[5]	3604	1			T3	36		T6	40		T12	20
values[6]	4556	1			T6	65		T12	194		T27	42
values[7]	3589	1			T3	20		T12	28		T38	84

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	208	1			T196	17		T159	13		T174	11
auto[0]	values[0]	values[1]	148	1			T44	13		T80	13		T145	19
auto[0]	values[0]	values[2]	472	1			T6	13		T22	16		T80	9
auto[0]	values[0]	values[3]	197	1			T7	4		T159	14		T152	8
auto[0]	values[0]	values[4]	202	1			T155	18		T218	18		T116	35
auto[0]	values[0]	values[5]	221	1			T44	10		T19	11		T48	6
auto[0]	values[0]	values[6]	416	1			T12	35		T48	12		T22	46
auto[0]	values[0]	values[7]	214	1			T152	21		T31	16		T145	10
auto[0]	values[1]	values[0]	248	1			T6	10		T80	9		T176	11
auto[0]	values[1]	values[1]	144	1			T159	16		T152	12		T157	2
auto[0]	values[1]	values[2]	340	1			T38	46		T39	10		T19	14
auto[0]	values[1]	values[3]	238	1			T8	2		T12	9		T102	8
auto[0]	values[1]	values[4]	434	1			T4	120		T12	9		T17	8
auto[0]	values[1]	values[5]	201	1			T203	20		T219	7		T220	24
auto[0]	values[1]	values[6]	529	1			T19	8		T48	8		T22	9
auto[0]	values[1]	values[7]	161	1			T48	13		T80	14		T31	12
auto[0]	values[2]	values[0]	356	1			T6	12		T44	15		T199	12
auto[0]	values[2]	values[1]	345	1			T38	7		T83	10		T60	14
auto[0]	values[2]	values[2]	556	1			T12	7		T27	20		T48	9
auto[0]	values[2]	values[3]	424	1			T44	11		T29	14		T194	14
auto[0]	values[2]	values[4]	355	1			T3	29		T12	12		T60	52
auto[0]	values[2]	values[5]	312	1			T60	34		T151	2		T176	12
auto[0]	values[2]	values[6]	402	1			T27	12		T19	14		T22	7
auto[0]	values[2]	values[7]	262	1			T3	5		T12	19		T38	6
auto[0]	values[3]	values[0]	393	1			T6	15		T196	10		T192	8
auto[0]	values[3]	values[1]	217	1			T13	4		T159	11		T30	11
auto[0]	values[3]	values[2]	136	1			T44	12		T178	4		T203	13
auto[0]	values[3]	values[3]	223	1			T6	11		T152	8		T145	15
auto[0]	values[3]	values[4]	100	1			T27	9		T213	14		T117	14
auto[0]	values[3]	values[5]	250	1			T3	11		T12	10		T38	11
auto[0]	values[3]	values[6]	243	1			T27	13		T81	22		T19	14
auto[0]	values[3]	values[7]	162	1			T196	9		T80	11		T30	14
auto[0]	values[4]	values[0]	368	1			T22	13		T189	78		T174	16
auto[0]	values[4]	values[1]	236	1			T201	6		T221	12		T193	15
auto[0]	values[4]	values[2]	406	1			T222	69		T31	17		T203	12
auto[0]	values[4]	values[3]	281	1			T3	13		T27	11		T44	12
auto[0]	values[4]	values[4]	216	1			T208	8		T199	25		T152	10
auto[0]	values[4]	values[5]	271	1			T6	9		T196	36		T223	2
auto[0]	values[4]	values[6]	214	1			T6	7		T152	12		T145	13
auto[0]	values[4]	values[7]	411	1			T19	17		T174	10		T203	12
auto[0]	values[5]	values[0]	329	1			T12	10		T38	22		T196	13
auto[0]	values[5]	values[1]	211	1			T27	11		T31	10		T224	10
auto[0]	values[5]	values[2]	370	1			T3	11		T189	14		T117	72
auto[0]	values[5]	values[3]	300	1			T209	2		T31	8		T194	17
auto[0]	values[5]	values[4]	168	1			T19	14		T174	14		T225	14
auto[0]	values[5]	values[5]	219	1			T6	10		T199	41		T80	15
auto[0]	values[5]	values[6]	242	1			T12	11		T226	10		T116	26
auto[0]	values[5]	values[7]	196	1			T214	10		T80	13		T31	7
auto[0]	values[6]	values[0]	362	1			T6	12		T101	74		T44	10
auto[0]	values[6]	values[1]	186	1			T44	15		T60	10		T116	9
auto[0]	values[6]	values[2]	151	1			T61	11		T30	9		T176	17
auto[0]	values[6]	values[3]	524	1			T30	21		T227	12		T195	123
auto[0]	values[6]	values[4]	262	1			T74	36		T22	9		T159	11
auto[0]	values[6]	values[5]	233	1			T159	21		T174	12		T31	12
auto[0]	values[6]	values[6]	134	1			T12	40		T228	18		T229	18
auto[0]	values[6]	values[7]	437	1			T38	12		T39	13		T22	130
auto[0]	values[7]	values[0]	238	1			T80	16		T30	13		T221	10
auto[0]	values[7]	values[1]	144	1			T48	10		T196	17		T145	14
auto[0]	values[7]	values[2]	319	1			T6	14		T61	12		T196	24
auto[0]	values[7]	values[3]	208	1			T12	6		T60	10		T189	21
auto[0]	values[7]	values[4]	157	1			T3	16		T48	14		T74	10
auto[0]	values[7]	values[5]	326	1			T44	9		T60	10		T230	4
auto[0]	values[7]	values[6]	269	1			T6	7		T74	12		T189	25
auto[0]	values[7]	values[7]	197	1			T174	9		T203	9		T176	13
auto[1]	values[0]	values[0]	116	1			T196	9		T159	7		T174	9
auto[1]	values[0]	values[1]	182	1			T44	7		T80	7		T145	9
auto[1]	values[0]	values[2]	331	1			T6	26		T22	4		T80	11
auto[1]	values[0]	values[3]	186	1			T159	6		T152	47		T80	8
auto[1]	values[0]	values[4]	126	1			T116	2		T193	12		T231	9
auto[1]	values[0]	values[5]	415	1			T44	10		T19	9		T48	50
auto[1]	values[0]	values[6]	422	1			T12	89		T48	10		T22	12
auto[1]	values[0]	values[7]	298	1			T152	4		T31	5		T145	140
auto[1]	values[1]	values[0]	94	1			T6	19		T80	11		T176	9
auto[1]	values[1]	values[1]	179	1			T159	9		T152	8		T31	9
auto[1]	values[1]	values[2]	336	1			T38	8		T39	10		T19	15
auto[1]	values[1]	values[3]	150	1			T12	60		T193	7		T232	4
auto[1]	values[1]	values[4]	337	1			T12	11		T19	13		T196	9
auto[1]	values[1]	values[5]	150	1			T203	53		T219	13		T150	11
auto[1]	values[1]	values[6]	424	1			T19	12		T48	65		T22	12
auto[1]	values[1]	values[7]	175	1			T48	7		T156	18		T80	6
auto[1]	values[2]	values[0]	186	1			T6	8		T44	5		T199	8
auto[1]	values[2]	values[1]	149	1			T38	18		T60	6		T194	7
auto[1]	values[2]	values[2]	341	1			T12	66		T27	50		T48	11
auto[1]	values[2]	values[3]	213	1			T44	9		T29	12		T194	6
auto[1]	values[2]	values[4]	331	1			T3	7		T12	8		T60	11
auto[1]	values[2]	values[5]	263	1			T60	10		T176	8		T117	10
auto[1]	values[2]	values[6]	563	1			T27	10		T45	6		T19	8
auto[1]	values[2]	values[7]	170	1			T3	15		T12	9		T38	38
auto[1]	values[3]	values[0]	392	1			T6	5		T196	10		T233	5
auto[1]	values[3]	values[1]	212	1			T159	9		T30	11		T189	12
auto[1]	values[3]	values[2]	100	1			T44	8		T203	11		T234	8
auto[1]	values[3]	values[3]	148	1			T6	9		T152	20		T145	5
auto[1]	values[3]	values[4]	79	1			T27	11		T117	6		T35	7
auto[1]	values[3]	values[5]	147	1			T3	25		T12	10		T38	11
auto[1]	values[3]	values[6]	198	1			T27	7		T19	11		T22	86
auto[1]	values[3]	values[7]	140	1			T196	11		T80	9		T30	6
auto[1]	values[4]	values[0]	340	1			T46	14		T22	101		T189	10
auto[1]	values[4]	values[1]	249	1			T82	24		T221	50		T193	5
auto[1]	values[4]	values[2]	145	1			T31	3		T203	8		T194	11
auto[1]	values[4]	values[3]	190	1			T3	24		T27	9		T44	8
auto[1]	values[4]	values[4]	206	1			T199	15		T152	10		T203	6
auto[1]	values[4]	values[5]	74	1			T6	11		T196	6		T235	9
auto[1]	values[4]	values[6]	109	1			T6	38		T152	8		T145	16
auto[1]	values[4]	values[7]	113	1			T19	3		T174	10		T203	8
auto[1]	values[5]	values[0]	205	1			T12	10		T38	3		T196	7
auto[1]	values[5]	values[1]	185	1			T27	12		T31	11		T236	13
auto[1]	values[5]	values[2]	207	1			T3	9		T189	6		T117	24
auto[1]	values[5]	values[3]	351	1			T31	12		T194	3		T176	7
auto[1]	values[5]	values[4]	211	1			T19	6		T174	6		T202	77
auto[1]	values[5]	values[5]	85	1			T6	10		T199	3		T80	5
auto[1]	values[5]	values[6]	137	1			T12	9		T116	11		T125	3
auto[1]	values[5]	values[7]	149	1			T80	7		T31	16		T183	16
auto[1]	values[6]	values[0]	242	1			T6	38		T44	10		T48	10
auto[1]	values[6]	values[1]	188	1			T44	5		T60	29		T116	11
auto[1]	values[6]	values[2]	134	1			T61	9		T30	17		T176	23
auto[1]	values[6]	values[3]	217	1			T30	19		T195	42		T237	76
auto[1]	values[6]	values[4]	123	1			T74	1		T22	20		T159	18
auto[1]	values[6]	values[5]	208	1			T159	11		T174	8		T31	8
auto[1]	values[6]	values[6]	55	1			T12	10		T238	10		T239	8
auto[1]	values[6]	values[7]	314	1			T38	28		T39	10		T22	13
auto[1]	values[7]	values[0]	221	1			T80	4		T30	8		T221	10
auto[1]	values[7]	values[1]	144	1			T48	10		T196	10		T145	6
auto[1]	values[7]	values[2]	219	1			T6	70		T61	8		T196	9
auto[1]	values[7]	values[3]	244	1			T12	14		T60	10		T189	14
auto[1]	values[7]	values[4]	150	1			T3	4		T48	6		T74	10
auto[1]	values[7]	values[5]	229	1			T44	11		T60	49		T31	17
auto[1]	values[7]	values[6]	199	1			T6	13		T74	9		T189	3
auto[1]	values[7]	values[7]	190	1			T47	20		T240	8		T174	11