Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	419	1			T3	3		T6	4		T12	5
auto[ReadAddrCrossIntoMailbox]	323	1			T3	4		T6	3		T12	4
auto[ReadAddrCrossOutOfMailbox]	324	1			T3	1		T6	2		T12	9
auto[ReadAddrCrossAllMailbox]	244	1			T3	1		T12	4		T27	1
auto[ReadAddrOutsideMailbox]	3544	1			T3	16		T4	2		T6	36

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2408

1

T3

12

T4

1

T6

30

auto[1]

2446

1

T3

13

T4

1

T6

15

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	850	1			T3	3		T6	10		T12	7
read_ops[0x0b]	779	1			T3	5		T6	6		T12	6
read_ops[0x3b]	786	1			T3	2		T4	2		T6	6
read_ops[0x6b]	809	1			T3	4		T6	8		T12	10
read_ops[0xbb]	812	1			T3	2		T6	10		T12	10
read_ops[0xeb]	818	1			T3	9		T6	5		T8	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T3	1		T22	1		T196	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	41	1			T27	1		T22	1		T196	2
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T12	1		T159	1		T174	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T44	1		T22	2		T29	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	34	1			T6	1		T12	1		T159	3
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	29	1			T44	1		T19	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T27	1		T48	1		T152	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	26	1			T74	1		T30	1		T194	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	312	1			T3	1		T6	8		T12	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	297	1			T3	1		T6	1		T12	3
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	38	1			T12	1		T38	1		T19	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T3	1		T27	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T27	1		T38	1		T60	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T6	1		T12	1		T38	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T12	1		T19	1		T22	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T12	1		T196	1		T159	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T189	1		T31	1		T116	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T48	2		T194	2		T237	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	285	1			T3	2		T6	4		T12	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	289	1			T3	2		T6	1		T27	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T6	1		T27	1		T19	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	42	1			T6	1		T44	1		T209	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T12	1		T199	1		T196	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T3	1		T44	1		T48	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T152	1		T31	3		T203	2
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	32	1			T12	1		T19	1		T196	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T12	1		T48	1		T199	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T12	1		T44	1		T19	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T4	1		T6	2		T12	3
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	299	1			T3	1		T4	1		T6	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T6	1		T27	1		T38	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	38	1			T44	1		T60	1		T159	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T19	1		T48	1		T74	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	36	1			T44	1		T30	1		T31	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	26	1			T27	2		T152	1		T80	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	15	1			T203	1		T145	1		T194	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T12	1		T29	1		T189	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T159	1		T145	1		T231	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	292	1			T3	3		T6	4		T12	6
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	306	1			T3	1		T6	3		T12	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	41	1			T6	1		T12	1		T152	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T74	1		T22	3		T159	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T3	1		T6	2		T27	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T44	1		T74	1		T80	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T3	1		T6	1		T12	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T12	1		T27	2		T38	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	31	1			T196	1		T159	1		T31	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	23	1			T74	1		T22	1		T80	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	291	1			T6	3		T27	1		T101	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	284	1			T6	3		T12	7		T38	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T3	1		T12	2		T74	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T12	1		T48	1		T196	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T3	1		T12	1		T27	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T3	1		T44	3		T48	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T12	3		T19	1		T22	2
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	16	1			T44	2		T19	1		T29	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	21	1			T19	1		T48	1		T159	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	27	1			T3	1		T12	1		T44	2
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	306	1			T3	1		T6	2		T8	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	313	1			T3	4		T6	3		T8	1