Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3391	1			T3	77		T6	45		T8	2
values[1]	4127	1			T6	49		T12	93		T17	8
values[2]	3841	1			T3	56		T4	120		T6	20
values[3]	4722	1			T6	20		T12	40		T27	23
values[4]	3580	1			T6	84		T12	20		T38	25
values[5]	4064	1			T3	36		T6	39		T7	4
values[6]	3680	1			T6	90		T12	20		T27	20
values[7]	3875	1			T6	20		T12	79		T27	42

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4132	1			T6	59		T12	20		T27	70
values[1]	4387	1			T3	77		T6	49		T12	69
values[2]	4304	1			T3	36		T6	115		T7	4
values[3]	4137	1			T6	104		T12	20		T27	20
values[4]	3667	1			T3	56		T12	53		T13	4
values[5]	3299	1			T4	120		T12	73		T27	23
values[6]	3914	1			T6	20		T12	71		T17	8
values[7]	3440	1			T6	20		T8	2		T12	48

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30491

1

T3

168

T4

120

T6

361

auto[1]

789

1

T3

1

T6

6

T12

11

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	300	1			T19	28		T199	17		T194	18
auto[0]	values[0]	values[1]	534	1			T3	56		T12	67		T48	20
auto[0]	values[0]	values[2]	624	1			T6	43		T12	20		T38	42
auto[0]	values[0]	values[3]	454	1			T38	25		T44	19		T19	20
auto[0]	values[0]	values[4]	521	1			T3	20		T159	20		T189	21
auto[0]	values[0]	values[5]	272	1			T48	17		T196	30		T80	20
auto[0]	values[0]	values[6]	345	1			T27	19		T60	20		T176	19
auto[0]	values[0]	values[7]	244	1			T8	2		T152	23		T31	21
auto[0]	values[1]	values[0]	369	1			T189	30		T31	44		T203	24
auto[0]	values[1]	values[1]	567	1			T6	47		T27	20		T22	19
auto[0]	values[1]	values[2]	499	1			T196	20		T241	4		T193	20
auto[0]	values[1]	values[3]	780	1			T38	49		T22	58		T199	24
auto[0]	values[1]	values[4]	353	1			T22	20		T80	20		T176	20
auto[0]	values[1]	values[5]	422	1			T12	72		T44	20		T31	20
auto[0]	values[1]	values[6]	469	1			T17	8		T48	22		T145	70
auto[0]	values[1]	values[7]	570	1			T12	20		T194	20		T176	19
auto[0]	values[2]	values[0]	488	1			T187	10		T30	22		T145	20
auto[0]	values[2]	values[1]	526	1			T3	20		T189	20		T242	18
auto[0]	values[2]	values[2]	375	1			T45	4		T82	24		T217	25
auto[0]	values[2]	values[3]	324	1			T6	20		T60	20		T193	40
auto[0]	values[2]	values[4]	377	1			T3	36		T12	53		T215	12
auto[0]	values[2]	values[5]	677	1			T4	120		T60	63		T189	29
auto[0]	values[2]	values[6]	640	1			T19	20		T196	31		T152	20
auto[0]	values[2]	values[7]	352	1			T159	29		T80	19		T174	20
auto[0]	values[3]	values[0]	403	1			T6	19		T19	19		T48	20
auto[0]	values[3]	values[1]	910	1			T44	38		T60	39		T22	138
auto[0]	values[3]	values[2]	698	1			T12	20		T226	10		T199	44
auto[0]	values[3]	values[3]	443	1			T208	8		T48	55		T194	20
auto[0]	values[3]	values[4]	482	1			T196	19		T152	20		T176	18
auto[0]	values[3]	values[5]	449	1			T27	23		T102	8		T44	40
auto[0]	values[3]	values[6]	445	1			T12	20		T77	27		T46	12
auto[0]	values[3]	values[7]	780	1			T214	10		T196	26		T29	24
auto[0]	values[4]	values[0]	708	1			T240	6		T151	2		T30	43
auto[0]	values[4]	values[1]	212	1			T145	27		T185	17		T193	37
auto[0]	values[4]	values[2]	441	1			T12	20		T196	25		T152	26
auto[0]	values[4]	values[3]	468	1			T6	84		T22	29		T159	17
auto[0]	values[4]	values[4]	587	1			T60	59		T231	20		T242	19
auto[0]	values[4]	values[5]	328	1			T38	25		T44	20		T152	54
auto[0]	values[4]	values[6]	331	1			T47	18		T48	25		T199	20
auto[0]	values[4]	values[7]	404	1			T39	23		T243	16		T244	4
auto[0]	values[5]	values[0]	693	1			T6	39		T12	17		T27	49
auto[0]	values[5]	values[1]	680	1			T30	18		T174	40		T145	20
auto[0]	values[5]	values[2]	542	1			T3	36		T7	4		T12	50
auto[0]	values[5]	values[3]	560	1			T38	39		T230	4		T22	110
auto[0]	values[5]	values[4]	330	1			T13	4		T61	19		T219	21
auto[0]	values[5]	values[5]	272	1			T199	32		T31	23		T176	38
auto[0]	values[5]	values[6]	554	1			T44	20		T159	70		T152	20
auto[0]	values[5]	values[7]	322	1			T48	72		T237	88		T245	45
auto[0]	values[6]	values[0]	604	1			T201	6		T60	55		T152	28
auto[0]	values[6]	values[1]	369	1			T31	23		T203	20		T176	19
auto[0]	values[6]	values[2]	543	1			T6	69		T61	20		T60	44
auto[0]	values[6]	values[3]	446	1			T12	18		T27	20		T38	21
auto[0]	values[6]	values[4]	549	1			T74	34		T203	23		T176	20
auto[0]	values[6]	values[5]	401	1			T209	2		T80	20		T31	20
auto[0]	values[6]	values[6]	372	1			T74	21		T30	20		T31	20
auto[0]	values[6]	values[7]	290	1			T6	20		T39	20		T194	17
auto[0]	values[7]	values[0]	457	1			T27	20		T176	17		T195	119
auto[0]	values[7]	values[1]	479	1			T27	22		T44	20		T196	20
auto[0]	values[7]	values[2]	460	1			T19	20		T22	114		T178	4
auto[0]	values[7]	values[3]	560	1			T101	74		T22	122		T159	20
auto[0]	values[7]	values[4]	385	1			T83	10		T19	20		T31	67
auto[0]	values[7]	values[5]	386	1			T30	20		T174	18		T207	16
auto[0]	values[7]	values[6]	664	1			T6	20		T12	49		T19	20
auto[0]	values[7]	values[7]	402	1			T12	27		T152	20		T125	20
auto[1]	values[0]	values[0]	10	1			T19	1		T199	3		T194	2
auto[1]	values[0]	values[1]	14	1			T3	1		T12	2		T30	2
auto[1]	values[0]	values[2]	17	1			T6	2		T38	2		T31	1
auto[1]	values[0]	values[3]	10	1			T44	1		T174	1		T203	1
auto[1]	values[0]	values[4]	21	1			T189	1		T234	2		T246	3
auto[1]	values[0]	values[5]	9	1			T48	3		T247	2		T238	2
auto[1]	values[0]	values[6]	9	1			T27	1		T176	1		T248	3
auto[1]	values[0]	values[7]	7	1			T152	1		T249	1		T250	2
auto[1]	values[1]	values[0]	9	1			T189	5		T203	1		T193	2
auto[1]	values[1]	values[1]	16	1			T6	2		T22	1		T203	1
auto[1]	values[1]	values[2]	4	1			T235	1		T205	2		T251	1
auto[1]	values[1]	values[3]	24	1			T38	5		T152	1		T156	4
auto[1]	values[1]	values[4]	8	1			T179	2		T202	1		T249	1
auto[1]	values[1]	values[5]	12	1			T12	1		T193	1		T200	1
auto[1]	values[1]	values[6]	12	1			T145	2		T252	2		T253	1
auto[1]	values[1]	values[7]	13	1			T176	1		T200	3		T179	1
auto[1]	values[2]	values[0]	15	1			T117	1		T183	2		T205	1
auto[1]	values[2]	values[1]	12	1			T242	2		T254	4		T255	2
auto[1]	values[2]	values[2]	15	1			T45	2		T217	2		T31	1
auto[1]	values[2]	values[3]	4	1			T251	2		T256	1		T257	1
auto[1]	values[2]	values[4]	1	1			T258	1		-	-		-	-
auto[1]	values[2]	values[5]	23	1			T189	1		T203	2		T116	1
auto[1]	values[2]	values[6]	4	1			T196	1		T80	1		T31	1
auto[1]	values[2]	values[7]	8	1			T80	1		T31	2		T117	1
auto[1]	values[3]	values[0]	14	1			T6	1		T19	3		T22	1
auto[1]	values[3]	values[1]	15	1			T44	2		T22	5		T255	1
auto[1]	values[3]	values[2]	24	1			T174	2		T116	2		T117	1
auto[1]	values[3]	values[3]	7	1			T48	1		T235	3		T253	1
auto[1]	values[3]	values[4]	14	1			T196	1		T176	2		T221	2
auto[1]	values[3]	values[5]	4	1			T145	1		T254	1		T253	1
auto[1]	values[3]	values[6]	12	1			T46	2		T196	1		T159	1
auto[1]	values[3]	values[7]	22	1			T196	1		T29	2		T189	2
auto[1]	values[4]	values[0]	20	1			T240	2		T30	3		T31	1
auto[1]	values[4]	values[1]	10	1			T145	1		T185	3		T193	3
auto[1]	values[4]	values[2]	21	1			T196	1		T152	2		T30	1
auto[1]	values[4]	values[3]	15	1			T159	3		T116	1		T185	2
auto[1]	values[4]	values[4]	11	1			T242	1		T254	2		T259	4
auto[1]	values[4]	values[5]	8	1			T152	1		T80	2		T117	2
auto[1]	values[4]	values[6]	10	1			T47	2		T48	1		T80	1
auto[1]	values[4]	values[7]	6	1			T243	2		T251	2		T260	2
auto[1]	values[5]	values[0]	13	1			T12	3		T27	1		T145	3
auto[1]	values[5]	values[1]	22	1			T30	2		T195	1		T186	1
auto[1]	values[5]	values[2]	17	1			T196	2		T203	4		T194	2
auto[1]	values[5]	values[3]	14	1			T38	1		T196	2		T261	2
auto[1]	values[5]	values[4]	7	1			T61	1		T234	1		T181	1
auto[1]	values[5]	values[5]	10	1			T199	1		T31	2		T176	2
auto[1]	values[5]	values[6]	23	1			T194	3		T237	3		T221	1
auto[1]	values[5]	values[7]	5	1			T48	1		T237	1		T202	2
auto[1]	values[6]	values[0]	18	1			T152	1		T80	1		T35	1
auto[1]	values[6]	values[1]	9	1			T31	1		T176	1		T186	1
auto[1]	values[6]	values[2]	17	1			T6	1		T80	1		T248	1
auto[1]	values[6]	values[3]	8	1			T12	2		T38	1		T204	2
auto[1]	values[6]	values[4]	15	1			T74	3		T203	1		T233	2
auto[1]	values[6]	values[5]	21	1			T221	1		T35	1		T183	4
auto[1]	values[6]	values[6]	10	1			T194	2		T231	5		T191	1
auto[1]	values[6]	values[7]	8	1			T194	3		T246	3		T262	1
auto[1]	values[7]	values[0]	11	1			T176	3		T195	2		T246	1
auto[1]	values[7]	values[1]	12	1			T176	2		T116	5		T231	1
auto[1]	values[7]	values[2]	7	1			T237	1		T246	1		T238	4
auto[1]	values[7]	values[3]	20	1			T22	1		T159	5		T174	2
auto[1]	values[7]	values[4]	6	1			T31	1		T200	1		T252	1
auto[1]	values[7]	values[5]	5	1			T174	2		T186	1		T254	1
auto[1]	values[7]	values[6]	14	1			T12	2		T263	4		T264	2
auto[1]	values[7]	values[7]	7	1			T12	1		T265	4		T232	1