Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	759	1			T19	7		T20	17		T21	11
all_values[1]	759	1			T19	7		T20	17		T21	11
all_values[2]	759	1			T19	7		T20	17		T21	11
all_values[3]	759	1			T19	7		T20	17		T21	11
all_values[4]	759	1			T19	7		T20	17		T21	11
all_values[5]	759	1			T19	7		T20	17		T21	11
all_values[6]	759	1			T19	7		T20	17		T21	11
all_values[7]	759	1			T19	7		T20	17		T21	11

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3190

1

T19

30

T20

50

T21

43

auto[1]

2882

1

T19

26

T20

86

T21

45

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2410

1

T19

18

T20

30

T21

39

auto[1]

3662

1

T19

38

T20

106

T21

49

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3440

1

T19

27

T20

64

T21

56

auto[1]

2632

1

T19

29

T20

72

T21

32

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	153	1			T20	3		T22	2		T30	6
all_values[0]	auto[0]	auto[0]	auto[1]	74	1			T19	1		T21	3		T30	2
all_values[0]	auto[0]	auto[1]	auto[0]	109	1			T20	1		T29	1		T30	7
all_values[0]	auto[0]	auto[1]	auto[1]	81	1			T19	1		T20	5		T22	1
all_values[0]	auto[1]	auto[0]	auto[1]	191	1			T19	3		T20	3		T21	2
all_values[0]	auto[1]	auto[1]	auto[1]	151	1			T19	2		T20	5		T21	6
all_values[1]	auto[0]	auto[0]	auto[0]	137	1			T20	1		T21	2		T30	3
all_values[1]	auto[0]	auto[0]	auto[1]	64	1			T22	1		T30	1		T33	2
all_values[1]	auto[0]	auto[1]	auto[0]	143	1			T19	2		T21	2		T29	1
all_values[1]	auto[0]	auto[1]	auto[1]	81	1			T20	7		T21	3		T22	2
all_values[1]	auto[1]	auto[0]	auto[1]	169	1			T19	3		T20	2		T21	2
all_values[1]	auto[1]	auto[1]	auto[1]	165	1			T19	2		T20	7		T21	2
all_values[2]	auto[0]	auto[0]	auto[0]	163	1			T19	3		T20	1		T22	2
all_values[2]	auto[0]	auto[0]	auto[1]	79	1			T19	2		T20	2		T21	3
all_values[2]	auto[0]	auto[1]	auto[0]	109	1			T21	3		T30	4		T31	2
all_values[2]	auto[0]	auto[1]	auto[1]	83	1			T20	3		T22	1		T29	1
all_values[2]	auto[1]	auto[0]	auto[1]	162	1			T19	2		T20	8		T21	3
all_values[2]	auto[1]	auto[1]	auto[1]	163	1			T20	3		T21	2		T22	1
all_values[3]	auto[0]	auto[0]	auto[0]	151	1			T19	1		T20	1		T21	1
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T19	1		T29	2		T30	2
all_values[3]	auto[0]	auto[1]	auto[0]	136	1			T19	1		T20	5		T21	5
all_values[3]	auto[0]	auto[1]	auto[1]	69	1			T19	1		T20	2		T21	2
all_values[3]	auto[1]	auto[0]	auto[1]	178	1			T19	1		T20	5		T21	2
all_values[3]	auto[1]	auto[1]	auto[1]	152	1			T19	2		T20	4		T21	1
all_values[4]	auto[0]	auto[0]	auto[0]	154	1			T19	3		T20	2		T21	2
all_values[4]	auto[0]	auto[0]	auto[1]	74	1			T19	1		T20	2		T21	2
all_values[4]	auto[0]	auto[1]	auto[0]	137	1			T19	1		T20	2		T21	5
all_values[4]	auto[0]	auto[1]	auto[1]	79	1			T20	3		T22	1		T30	5
all_values[4]	auto[1]	auto[0]	auto[1]	179	1			T19	2		T20	1		T21	1
all_values[4]	auto[1]	auto[1]	auto[1]	136	1			T20	7		T21	1		T29	1
all_values[5]	auto[0]	auto[0]	auto[0]	218	1			T19	3		T20	3		T21	4
all_values[5]	auto[0]	auto[1]	auto[0]	198	1			T19	1		T20	3		T21	3
all_values[5]	auto[1]	auto[0]	auto[1]	174	1			T20	6		T21	3		T30	4
all_values[5]	auto[1]	auto[1]	auto[1]	169	1			T19	3		T20	5		T21	1
all_values[6]	auto[0]	auto[0]	auto[0]	170	1			T20	3		T21	6		T22	2
all_values[6]	auto[0]	auto[0]	auto[1]	70	1			T20	1		T22	1		T29	1
all_values[6]	auto[0]	auto[1]	auto[0]	145	1			T19	1		T20	2		T21	2
all_values[6]	auto[0]	auto[1]	auto[1]	70	1			T19	1		T20	5		T21	2
all_values[6]	auto[1]	auto[0]	auto[1]	161	1			T19	2		T20	1		T22	1
all_values[6]	auto[1]	auto[1]	auto[1]	143	1			T19	3		T20	5		T21	1
all_values[7]	auto[0]	auto[0]	auto[0]	157	1			T19	2		T20	2		T21	2
all_values[7]	auto[0]	auto[0]	auto[1]	70	1			T20	2		T21	2		T22	2
all_values[7]	auto[0]	auto[1]	auto[0]	130	1			T20	1		T21	2		T22	1
all_values[7]	auto[0]	auto[1]	auto[1]	63	1			T19	1		T20	2		T30	5
all_values[7]	auto[1]	auto[0]	auto[1]	169	1			T20	1		T21	3		T29	3
all_values[7]	auto[1]	auto[1]	auto[1]	170	1			T19	4		T20	9		T21	2

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal