Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1673

1

T2

11

T12

6

T14

4

auto[1]

1670

1

T2

11

T12

6

T14

10

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1821

1

T2

22

T12

6

T26

2

auto[1]

1522

1

T12

6

T14

14

T15

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2622

1

T2

12

T12

9

T14

14

auto[1]

721

1

T2

10

T12

3

T26

1

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	693	1			T2	4		T12	2		T14	3
valid[1]	671	1			T2	3		T12	1		T14	5
valid[2]	664	1			T2	6		T12	1		T14	3
valid[3]	643	1			T2	5		T12	4		T15	2
valid[4]	672	1			T2	4		T12	4		T14	3

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	109	1			T12	1		T27	1		T37	2
auto[0]	auto[0]	valid[0]	auto[1]	146	1			T12	1		T24	3		T75	1
auto[0]	auto[0]	valid[1]	auto[0]	107	1			T2	2		T28	1		T39	1
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T14	1		T15	1		T24	1
auto[0]	auto[0]	valid[2]	auto[0]	117	1			T2	1		T28	2		T37	2
auto[0]	auto[0]	valid[2]	auto[1]	148	1			T14	1		T24	1		T76	2
auto[0]	auto[0]	valid[3]	auto[0]	102	1			T2	1		T12	1		T18	2
auto[0]	auto[0]	valid[3]	auto[1]	144	1			T12	2		T15	1		T24	1
auto[0]	auto[0]	valid[4]	auto[0]	109	1			T34	4		T279	2		T74	2
auto[0]	auto[0]	valid[4]	auto[1]	161	1			T14	2		T24	1		T39	1
auto[0]	auto[1]	valid[0]	auto[0]	119	1			T2	1		T18	1		T27	1
auto[0]	auto[1]	valid[0]	auto[1]	156	1			T14	3		T24	2		T25	2
auto[0]	auto[1]	valid[1]	auto[0]	96	1			T2	1		T26	1		T18	1
auto[0]	auto[1]	valid[1]	auto[1]	174	1			T14	4		T24	1		T25	2
auto[0]	auto[1]	valid[2]	auto[0]	105	1			T2	3		T18	2		T37	1
auto[0]	auto[1]	valid[2]	auto[1]	150	1			T12	1		T14	2		T15	1
auto[0]	auto[1]	valid[3]	auto[0]	96	1			T2	1		T12	1		T18	1
auto[0]	auto[1]	valid[3]	auto[1]	156	1			T15	1		T24	1		T75	1
auto[0]	auto[1]	valid[4]	auto[0]	140	1			T2	2		T18	1		T37	4
auto[0]	auto[1]	valid[4]	auto[1]	128	1			T12	2		T14	1		T24	1
auto[1]	auto[0]	valid[0]	auto[0]	83	1			T2	2		T28	1		T49	1
auto[1]	auto[0]	valid[1]	auto[0]	71	1			T37	1		T34	1		T279	1
auto[1]	auto[0]	valid[2]	auto[0]	69	1			T2	1		T37	1		T39	1
auto[1]	auto[0]	valid[3]	auto[0]	82	1			T2	2		T28	1		T37	1
auto[1]	auto[0]	valid[4]	auto[0]	66	1			T2	2		T12	1		T49	3
auto[1]	auto[1]	valid[0]	auto[0]	80	1			T2	1		T18	1		T27	1
auto[1]	auto[1]	valid[1]	auto[0]	64	1			T12	1		T37	1		T49	1
auto[1]	auto[1]	valid[2]	auto[0]	75	1			T2	1		T39	2		T19	1
auto[1]	auto[1]	valid[3]	auto[0]	63	1			T2	1		T26	1		T39	1
auto[1]	auto[1]	valid[4]	auto[0]	68	1			T12	1		T39	2		T49	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal