Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47878

1

T2

511

T12

187

T26

127

auto[1]

16124

1

T12

45

T14

14

T15

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46418

1

T2

330

T12

153

T14

14

auto[1]

17584

1

T2

181

T12

79

T26

47

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	33018	1			T2	257		T12	127		T14	14
others[1]	5437	1			T2	43		T12	22		T26	15
others[2]	5382	1			T2	45		T12	18		T26	17
others[3]	5971	1			T2	48		T12	21		T26	13
interest[1]	3507	1			T2	31		T12	10		T26	9
interest[4]	21636	1			T2	158		T12	81		T14	14
interest[64]	10687	1			T2	87		T12	34		T26	32

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15565	1			T2	168		T12	56		T26	39
auto[0]	auto[0]	others[1]	2568	1			T2	26		T12	10		T26	6
auto[0]	auto[0]	others[2]	2586	1			T2	28		T12	9		T26	11
auto[0]	auto[0]	others[3]	2795	1			T2	31		T12	10		T26	6
auto[0]	auto[0]	interest[1]	1671	1			T2	18		T12	4		T26	6
auto[0]	auto[0]	interest[4]	10114	1			T2	109		T12	39		T26	32
auto[0]	auto[0]	interest[64]	5109	1			T2	59		T12	19		T26	12
auto[0]	auto[1]	others[0]	8426	1			T12	28		T14	14		T15	4
auto[0]	auto[1]	others[1]	1364	1			T12	5		T26	7		T28	3
auto[0]	auto[1]	others[2]	1313	1			T12	2		T26	4		T28	3
auto[0]	auto[1]	others[3]	1496	1			T12	4		T26	5		T28	5
auto[0]	auto[1]	interest[1]	868	1			T12	2		T26	2		T28	2
auto[0]	auto[1]	interest[4]	5657	1			T12	22		T14	14		T15	4
auto[0]	auto[1]	interest[64]	2657	1			T12	4		T26	11		T28	7
auto[1]	auto[0]	others[0]	9027	1			T2	89		T12	43		T26	31
auto[1]	auto[0]	others[1]	1505	1			T2	17		T12	7		T26	2
auto[1]	auto[0]	others[2]	1483	1			T2	17		T12	7		T26	2
auto[1]	auto[0]	others[3]	1680	1			T2	17		T12	7		T26	2
auto[1]	auto[0]	interest[1]	968	1			T2	13		T12	4		T26	1
auto[1]	auto[0]	interest[4]	5865	1			T2	49		T12	20		T26	19
auto[1]	auto[0]	interest[64]	2921	1			T2	28		T12	11		T26	9

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal