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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.98 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1129
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T71 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1097955854 Jul 05 04:29:17 PM PDT 24 Jul 05 04:29:26 PM PDT 24 47925604 ps
T96 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1205616180 Jul 05 04:29:13 PM PDT 24 Jul 05 04:29:25 PM PDT 24 189222792 ps
T107 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3638551930 Jul 05 04:29:13 PM PDT 24 Jul 05 04:29:23 PM PDT 24 31216537 ps
T95 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1622103245 Jul 05 04:29:19 PM PDT 24 Jul 05 04:29:30 PM PDT 24 151016276 ps
T1024 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4169068410 Jul 05 04:29:15 PM PDT 24 Jul 05 04:29:25 PM PDT 24 118015941 ps
T1025 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.382338205 Jul 05 04:28:59 PM PDT 24 Jul 05 04:29:19 PM PDT 24 14223585 ps
T1026 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1447313430 Jul 05 04:29:08 PM PDT 24 Jul 05 04:29:54 PM PDT 24 7193422610 ps
T1027 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2701565613 Jul 05 04:29:22 PM PDT 24 Jul 05 04:29:37 PM PDT 24 816777864 ps
T1028 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2039070282 Jul 05 04:28:59 PM PDT 24 Jul 05 04:29:12 PM PDT 24 392619185 ps
T1029 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3845442925 Jul 05 04:29:04 PM PDT 24 Jul 05 04:29:13 PM PDT 24 16598780 ps
T1030 /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2854574781 Jul 05 04:29:16 PM PDT 24 Jul 05 04:29:25 PM PDT 24 40597396 ps
T168 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2147232826 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:25 PM PDT 24 4039345933 ps
T1031 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1488849673 Jul 05 04:29:13 PM PDT 24 Jul 05 04:29:23 PM PDT 24 95726400 ps
T1032 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.987650097 Jul 05 04:29:15 PM PDT 24 Jul 05 04:29:27 PM PDT 24 464082343 ps
T1033 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4136425815 Jul 05 04:29:10 PM PDT 24 Jul 05 04:29:20 PM PDT 24 15632868 ps
T89 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2935521603 Jul 05 04:29:10 PM PDT 24 Jul 05 04:29:24 PM PDT 24 205900330 ps
T171 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.816296561 Jul 05 04:29:12 PM PDT 24 Jul 05 04:29:35 PM PDT 24 1090593565 ps
T90 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3764862273 Jul 05 04:29:16 PM PDT 24 Jul 05 04:29:27 PM PDT 24 299693682 ps
T1034 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2223099428 Jul 05 04:29:10 PM PDT 24 Jul 05 04:29:21 PM PDT 24 44416320 ps
T92 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3600629196 Jul 05 04:29:06 PM PDT 24 Jul 05 04:29:19 PM PDT 24 319226217 ps
T1035 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1381461089 Jul 05 04:29:20 PM PDT 24 Jul 05 04:29:30 PM PDT 24 87929444 ps
T72 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.753965805 Jul 05 04:28:58 PM PDT 24 Jul 05 04:29:09 PM PDT 24 60124232 ps
T1036 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3954028896 Jul 05 04:29:00 PM PDT 24 Jul 05 04:29:13 PM PDT 24 1040226282 ps
T1037 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.557358885 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:17 PM PDT 24 145021492 ps
T1038 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.916830802 Jul 05 04:29:09 PM PDT 24 Jul 05 04:29:20 PM PDT 24 57735061 ps
T1039 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.211788309 Jul 05 04:29:20 PM PDT 24 Jul 05 04:29:30 PM PDT 24 26207880 ps
T1040 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2057641247 Jul 05 04:29:14 PM PDT 24 Jul 05 04:29:26 PM PDT 24 840624147 ps
T1041 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.232891242 Jul 05 04:29:30 PM PDT 24 Jul 05 04:29:38 PM PDT 24 15558710 ps
T1042 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4141146227 Jul 05 04:29:24 PM PDT 24 Jul 05 04:29:33 PM PDT 24 41055210 ps
T1043 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2837362963 Jul 05 04:29:11 PM PDT 24 Jul 05 04:29:20 PM PDT 24 73960388 ps
T1044 /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1906880546 Jul 05 04:29:12 PM PDT 24 Jul 05 04:29:22 PM PDT 24 17998714 ps
T1045 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1626899091 Jul 05 04:29:24 PM PDT 24 Jul 05 04:29:33 PM PDT 24 16646222 ps
T1046 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3978710161 Jul 05 04:29:05 PM PDT 24 Jul 05 04:29:14 PM PDT 24 42287428 ps
T169 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1536602592 Jul 05 04:29:17 PM PDT 24 Jul 05 04:29:42 PM PDT 24 194187569 ps
T172 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2626044170 Jul 05 04:29:01 PM PDT 24 Jul 05 04:29:18 PM PDT 24 1572639958 ps
T1047 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3451067962 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:12 PM PDT 24 21268214 ps
T108 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2418430985 Jul 05 04:29:00 PM PDT 24 Jul 05 04:29:11 PM PDT 24 165575041 ps
T1048 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2030785917 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:13 PM PDT 24 286708987 ps
T166 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2892784109 Jul 05 04:29:04 PM PDT 24 Jul 05 04:29:28 PM PDT 24 677654619 ps
T99 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3098779346 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:14 PM PDT 24 231394346 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2329182495 Jul 05 04:28:59 PM PDT 24 Jul 05 04:29:11 PM PDT 24 593261486 ps
T1050 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4195192684 Jul 05 04:28:58 PM PDT 24 Jul 05 04:29:09 PM PDT 24 214180378 ps
T115 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2549282223 Jul 05 04:28:59 PM PDT 24 Jul 05 04:29:30 PM PDT 24 1453429731 ps
T1051 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1701792385 Jul 05 04:29:00 PM PDT 24 Jul 05 04:29:12 PM PDT 24 46212168 ps
T109 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3754360054 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:18 PM PDT 24 109522256 ps
T1052 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.894098446 Jul 05 04:29:17 PM PDT 24 Jul 05 04:29:26 PM PDT 24 15434343 ps
T1053 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1175179480 Jul 05 04:29:06 PM PDT 24 Jul 05 04:29:16 PM PDT 24 34594238 ps
T1054 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.672929649 Jul 05 04:29:00 PM PDT 24 Jul 05 04:29:11 PM PDT 24 138474164 ps
T110 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3150557629 Jul 05 04:29:14 PM PDT 24 Jul 05 04:29:24 PM PDT 24 141438299 ps
T167 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1005742693 Jul 05 04:28:58 PM PDT 24 Jul 05 04:29:22 PM PDT 24 564931770 ps
T1055 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2038844905 Jul 05 04:29:13 PM PDT 24 Jul 05 04:29:23 PM PDT 24 256865038 ps
T1056 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.67273576 Jul 05 04:29:18 PM PDT 24 Jul 05 04:29:30 PM PDT 24 148140815 ps
T1057 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3117911889 Jul 05 04:29:12 PM PDT 24 Jul 05 04:29:22 PM PDT 24 40005825 ps
T1058 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3006464513 Jul 05 04:29:17 PM PDT 24 Jul 05 04:29:25 PM PDT 24 14008217 ps
T111 /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1064451857 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:38 PM PDT 24 6089923231 ps
T112 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3751612547 Jul 05 04:29:19 PM PDT 24 Jul 05 04:29:30 PM PDT 24 44274532 ps
T1059 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4273466472 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:17 PM PDT 24 45223664 ps
T1060 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3244064696 Jul 05 04:29:12 PM PDT 24 Jul 05 04:29:27 PM PDT 24 388536634 ps
T1061 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4062717424 Jul 05 04:29:23 PM PDT 24 Jul 05 04:29:36 PM PDT 24 166046853 ps
T1062 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2947690208 Jul 05 04:28:57 PM PDT 24 Jul 05 04:29:08 PM PDT 24 55678517 ps
T1063 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3985889445 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:18 PM PDT 24 92391256 ps
T1064 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1160089187 Jul 05 04:29:34 PM PDT 24 Jul 05 04:29:40 PM PDT 24 30828608 ps
T1065 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3944275113 Jul 05 04:29:35 PM PDT 24 Jul 05 04:29:41 PM PDT 24 47197690 ps
T1066 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.630811935 Jul 05 04:29:24 PM PDT 24 Jul 05 04:29:34 PM PDT 24 25881603 ps
T1067 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2203341765 Jul 05 04:29:30 PM PDT 24 Jul 05 04:29:37 PM PDT 24 40126148 ps
T1068 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2169364237 Jul 05 04:29:18 PM PDT 24 Jul 05 04:29:28 PM PDT 24 14706753 ps
T1069 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2799403311 Jul 05 04:29:19 PM PDT 24 Jul 05 04:29:41 PM PDT 24 207615567 ps
T1070 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1486038601 Jul 05 04:29:16 PM PDT 24 Jul 05 04:29:26 PM PDT 24 55485375 ps
T1071 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2380090606 Jul 05 04:28:58 PM PDT 24 Jul 05 04:29:11 PM PDT 24 184120453 ps
T1072 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.955800646 Jul 05 04:28:56 PM PDT 24 Jul 05 04:29:39 PM PDT 24 10410773888 ps
T1073 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.39443931 Jul 05 04:28:56 PM PDT 24 Jul 05 04:29:06 PM PDT 24 26058117 ps
T1074 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4030583964 Jul 05 04:29:17 PM PDT 24 Jul 05 04:29:25 PM PDT 24 19334411 ps
T1075 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2336014460 Jul 05 04:29:21 PM PDT 24 Jul 05 04:29:31 PM PDT 24 151411803 ps
T173 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1754159933 Jul 05 04:29:06 PM PDT 24 Jul 05 04:29:28 PM PDT 24 744325297 ps
T1076 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.249640288 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:18 PM PDT 24 250622626 ps
T1077 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.545966045 Jul 05 04:29:16 PM PDT 24 Jul 05 04:29:27 PM PDT 24 124761492 ps
T1078 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.210159154 Jul 05 04:29:03 PM PDT 24 Jul 05 04:29:15 PM PDT 24 139928008 ps
T1079 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.683308429 Jul 05 04:29:04 PM PDT 24 Jul 05 04:29:15 PM PDT 24 148379222 ps
T1080 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.223393014 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:17 PM PDT 24 59679136 ps
T1081 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1037376411 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:15 PM PDT 24 596070699 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3190119495 Jul 05 04:29:04 PM PDT 24 Jul 05 04:29:13 PM PDT 24 16154844 ps
T1083 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2960032728 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:20 PM PDT 24 487246459 ps
T1084 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3919279612 Jul 05 04:29:20 PM PDT 24 Jul 05 04:29:29 PM PDT 24 20652562 ps
T1085 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3121809180 Jul 05 04:29:20 PM PDT 24 Jul 05 04:29:31 PM PDT 24 356444199 ps
T1086 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2285054422 Jul 05 04:29:08 PM PDT 24 Jul 05 04:29:31 PM PDT 24 1096201548 ps
T1087 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2359435493 Jul 05 04:28:53 PM PDT 24 Jul 05 04:29:04 PM PDT 24 29703845 ps
T1088 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1301878937 Jul 05 04:29:14 PM PDT 24 Jul 05 04:29:23 PM PDT 24 16536076 ps
T1089 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.357024963 Jul 05 04:29:10 PM PDT 24 Jul 05 04:29:21 PM PDT 24 67949676 ps
T1090 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3671168545 Jul 05 04:28:58 PM PDT 24 Jul 05 04:29:09 PM PDT 24 26934297 ps
T1091 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.935284298 Jul 05 04:29:05 PM PDT 24 Jul 05 04:29:15 PM PDT 24 69176011 ps
T1092 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2860639872 Jul 05 04:29:01 PM PDT 24 Jul 05 04:29:13 PM PDT 24 18084475 ps
T1093 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1154135512 Jul 05 04:29:19 PM PDT 24 Jul 05 04:29:31 PM PDT 24 308680155 ps
T1094 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1756242028 Jul 05 04:29:06 PM PDT 24 Jul 05 04:29:16 PM PDT 24 16530789 ps
T1095 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2537961903 Jul 05 04:29:06 PM PDT 24 Jul 05 04:29:18 PM PDT 24 100385586 ps
T1096 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2181369531 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:13 PM PDT 24 319944323 ps
T1097 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.937266649 Jul 05 04:28:58 PM PDT 24 Jul 05 04:29:11 PM PDT 24 165688727 ps
T1098 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1298886585 Jul 05 04:29:24 PM PDT 24 Jul 05 04:29:35 PM PDT 24 92930797 ps
T1099 /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1803010509 Jul 05 04:29:24 PM PDT 24 Jul 05 04:29:45 PM PDT 24 214578543 ps
T1100 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3138727735 Jul 05 04:29:36 PM PDT 24 Jul 05 04:29:44 PM PDT 24 530478248 ps
T1101 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1616555850 Jul 05 04:29:01 PM PDT 24 Jul 05 04:29:13 PM PDT 24 86197844 ps
T1102 /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4014096534 Jul 05 04:29:22 PM PDT 24 Jul 05 04:29:32 PM PDT 24 12263936 ps
T1103 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1635758060 Jul 05 04:29:23 PM PDT 24 Jul 05 04:29:34 PM PDT 24 106710228 ps
T1104 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4134811542 Jul 05 04:29:04 PM PDT 24 Jul 05 04:29:15 PM PDT 24 168641175 ps
T1105 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.607923888 Jul 05 04:29:06 PM PDT 24 Jul 05 04:29:18 PM PDT 24 109809913 ps
T1106 /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4233828661 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:21 PM PDT 24 143043314 ps
T1107 /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1210798352 Jul 05 04:29:05 PM PDT 24 Jul 05 04:29:15 PM PDT 24 41520953 ps
T1108 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1178294785 Jul 05 04:29:15 PM PDT 24 Jul 05 04:29:24 PM PDT 24 29371421 ps
T1109 /workspace/coverage/cover_reg_top/41.spi_device_intr_test.385308520 Jul 05 04:29:22 PM PDT 24 Jul 05 04:29:32 PM PDT 24 24632543 ps
T1110 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3869204179 Jul 05 04:29:11 PM PDT 24 Jul 05 04:29:23 PM PDT 24 350029393 ps
T1111 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.67897633 Jul 05 04:29:10 PM PDT 24 Jul 05 04:29:35 PM PDT 24 4648054360 ps
T1112 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.427796338 Jul 05 04:29:17 PM PDT 24 Jul 05 04:29:27 PM PDT 24 52249657 ps
T1113 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.880742850 Jul 05 04:29:24 PM PDT 24 Jul 05 04:29:34 PM PDT 24 19054637 ps
T1114 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3899087621 Jul 05 04:29:08 PM PDT 24 Jul 05 04:29:25 PM PDT 24 4349377032 ps
T73 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3358591367 Jul 05 04:29:06 PM PDT 24 Jul 05 04:29:16 PM PDT 24 20054435 ps
T1115 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3525491399 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:19 PM PDT 24 413115899 ps
T1116 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.151872480 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:18 PM PDT 24 108305008 ps
T1117 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3316363635 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:17 PM PDT 24 11770899 ps
T1118 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3006605570 Jul 05 04:29:09 PM PDT 24 Jul 05 04:29:19 PM PDT 24 45460987 ps
T1119 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2168897488 Jul 05 04:29:21 PM PDT 24 Jul 05 04:29:38 PM PDT 24 537611058 ps
T1120 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2023175305 Jul 05 04:28:54 PM PDT 24 Jul 05 04:29:10 PM PDT 24 105605155 ps
T1121 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.908778033 Jul 05 04:29:07 PM PDT 24 Jul 05 04:29:17 PM PDT 24 29572995 ps
T1122 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3819266988 Jul 05 04:29:12 PM PDT 24 Jul 05 04:29:24 PM PDT 24 110842108 ps
T1123 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2370820173 Jul 05 04:28:58 PM PDT 24 Jul 05 04:29:10 PM PDT 24 517888552 ps
T1124 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1306110167 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:11 PM PDT 24 22398240 ps
T1125 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1899742240 Jul 05 04:29:01 PM PDT 24 Jul 05 04:29:13 PM PDT 24 112543500 ps
T1126 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.869633425 Jul 05 04:29:00 PM PDT 24 Jul 05 04:29:10 PM PDT 24 98985428 ps
T1127 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.457971457 Jul 05 04:28:51 PM PDT 24 Jul 05 04:29:13 PM PDT 24 216101668 ps
T1128 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3943755779 Jul 05 04:29:28 PM PDT 24 Jul 05 04:29:37 PM PDT 24 31120614 ps
T1129 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3649421295 Jul 05 04:29:02 PM PDT 24 Jul 05 04:29:31 PM PDT 24 4805330046 ps

Test location /workspace/coverage/default/18.spi_device_flash_all.4190936518
Short name T6
Test name
Test status
Simulation time 4955845051 ps
CPU time 87.76 seconds
Started Jul 05 06:08:28 PM PDT 24
Finished Jul 05 06:09:56 PM PDT 24
Peak memory 255908 kb
Host smart-c4c788b1-5072-4ad8-81d7-f876651560ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190936518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.4190936518
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.3224953911
Short name T26
Test name
Test status
Simulation time 945357718 ps
CPU time 9.56 seconds
Started Jul 05 06:10:18 PM PDT 24
Finished Jul 05 06:10:28 PM PDT 24
Peak memory 219404 kb
Host smart-049cc1b9-a9d2-4e4e-9b2b-e1c7a52094d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3224953911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.3224953911
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.2249146309
Short name T31
Test name
Test status
Simulation time 253201041044 ps
CPU time 663.83 seconds
Started Jul 05 06:07:59 PM PDT 24
Finished Jul 05 06:19:05 PM PDT 24
Peak memory 284776 kb
Host smart-67821553-0872-4ff9-9111-6e9dd47b84cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249146309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.2249146309
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.2581583197
Short name T34
Test name
Test status
Simulation time 92575462490 ps
CPU time 265.07 seconds
Started Jul 05 06:08:10 PM PDT 24
Finished Jul 05 06:12:36 PM PDT 24
Peak memory 265488 kb
Host smart-ac70cc26-71e7-486d-a74b-89d9ecb98744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581583197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.2581583197
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.2458721930
Short name T84
Test name
Test status
Simulation time 2873470728 ps
CPU time 15.34 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:32 PM PDT 24
Peak memory 217428 kb
Host smart-a417a509-96c1-4356-85ac-984a5bd83ed3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458721930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.2458721930
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.1219010203
Short name T22
Test name
Test status
Simulation time 69124284241 ps
CPU time 411.81 seconds
Started Jul 05 06:10:32 PM PDT 24
Finished Jul 05 06:17:25 PM PDT 24
Peak memory 296368 kb
Host smart-da8297b6-6a54-422a-b384-a4b488236e35
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219010203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.1219010203
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.305382722
Short name T66
Test name
Test status
Simulation time 17525545 ps
CPU time 0.73 seconds
Started Jul 05 06:07:07 PM PDT 24
Finished Jul 05 06:07:08 PM PDT 24
Peak memory 216092 kb
Host smart-c29b2633-7662-4ce8-aaac-bd1895ac847e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305382722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.305382722
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3971289560
Short name T37
Test name
Test status
Simulation time 24254264534 ps
CPU time 225.73 seconds
Started Jul 05 06:08:50 PM PDT 24
Finished Jul 05 06:12:36 PM PDT 24
Peak memory 249020 kb
Host smart-b7e9683b-87e9-47ed-abae-96ba6c1a1b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971289560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3971289560
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3040698741
Short name T12
Test name
Test status
Simulation time 22743500722 ps
CPU time 175.8 seconds
Started Jul 05 06:08:05 PM PDT 24
Finished Jul 05 06:11:01 PM PDT 24
Peak memory 262748 kb
Host smart-5de2247d-a2ba-4981-9078-da2456a4c811
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040698741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3040698741
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3438340916
Short name T203
Test name
Test status
Simulation time 30673572229 ps
CPU time 211.47 seconds
Started Jul 05 06:08:56 PM PDT 24
Finished Jul 05 06:12:28 PM PDT 24
Peak memory 255824 kb
Host smart-35a89007-3923-4922-9552-6cc29c6dbe26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438340916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3438340916
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.1672843341
Short name T85
Test name
Test status
Simulation time 403665834 ps
CPU time 4.53 seconds
Started Jul 05 04:29:03 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 215884 kb
Host smart-8e51b81a-bdbf-4833-8ace-68b0376a7310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672843341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
1672843341
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2974787330
Short name T10
Test name
Test status
Simulation time 326713033 ps
CPU time 1.14 seconds
Started Jul 05 06:07:28 PM PDT 24
Finished Jul 05 06:07:30 PM PDT 24
Peak memory 236848 kb
Host smart-96512a04-a285-4492-a498-526609a048a3
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974787330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2974787330
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.964360731
Short name T221
Test name
Test status
Simulation time 148934088781 ps
CPU time 800.05 seconds
Started Jul 05 06:07:56 PM PDT 24
Finished Jul 05 06:21:17 PM PDT 24
Peak memory 270644 kb
Host smart-d623c0ab-92e0-40f9-8376-63268692f608
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964360731 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stress
_all.964360731
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2837509234
Short name T78
Test name
Test status
Simulation time 168441980 ps
CPU time 4.57 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:08:49 PM PDT 24
Peak memory 224460 kb
Host smart-ae1773cf-b565-4b4f-a3e1-2de6a929a3fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837509234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2837509234
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.2828228893
Short name T116
Test name
Test status
Simulation time 18085751630 ps
CPU time 231.53 seconds
Started Jul 05 06:10:33 PM PDT 24
Finished Jul 05 06:14:25 PM PDT 24
Peak memory 271200 kb
Host smart-a8e08ed4-0fc8-42a8-8f17-33c73a3d7efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2828228893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idl
e.2828228893
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.700443729
Short name T30
Test name
Test status
Simulation time 133746836920 ps
CPU time 670.29 seconds
Started Jul 05 06:10:16 PM PDT 24
Finished Jul 05 06:21:27 PM PDT 24
Peak memory 249236 kb
Host smart-a8f1efa9-5e88-4164-8efd-212528a82c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700443729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.700443729
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.933917323
Short name T48
Test name
Test status
Simulation time 755149110701 ps
CPU time 415.37 seconds
Started Jul 05 06:09:38 PM PDT 24
Finished Jul 05 06:16:34 PM PDT 24
Peak memory 264764 kb
Host smart-6d7e1ea8-bc50-417b-989f-e04c1153445a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933917323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idle
.933917323
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2980052289
Short name T105
Test name
Test status
Simulation time 779826594 ps
CPU time 16.27 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:33 PM PDT 24
Peak memory 215540 kb
Host smart-c1cfeb11-1272-4a1f-8123-42537c0d7645
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980052289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2980052289
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.3408568257
Short name T152
Test name
Test status
Simulation time 20611390339 ps
CPU time 151.87 seconds
Started Jul 05 06:07:16 PM PDT 24
Finished Jul 05 06:09:48 PM PDT 24
Peak memory 254164 kb
Host smart-5dd5c9d2-3c88-4773-8731-ed2c1d01483f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408568257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.3408568257
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.136660788
Short name T194
Test name
Test status
Simulation time 76353555065 ps
CPU time 519.92 seconds
Started Jul 05 06:07:17 PM PDT 24
Finished Jul 05 06:15:57 PM PDT 24
Peak memory 254992 kb
Host smart-ba5cc0bb-015a-4c69-b6ee-4cd1b2fabcdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136660788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds.
136660788
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3784802922
Short name T145
Test name
Test status
Simulation time 104218622142 ps
CPU time 499.47 seconds
Started Jul 05 06:08:54 PM PDT 24
Finished Jul 05 06:17:14 PM PDT 24
Peak memory 288040 kb
Host smart-aeb5b9b5-974f-4189-b2c2-9b6670bcf31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784802922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3784802922
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3728043428
Short name T176
Test name
Test status
Simulation time 45234325173 ps
CPU time 358.66 seconds
Started Jul 05 06:08:28 PM PDT 24
Finished Jul 05 06:14:27 PM PDT 24
Peak memory 265488 kb
Host smart-f379b720-1976-4d6f-adb7-db65fdf0c58f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728043428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3728043428
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3111581164
Short name T254
Test name
Test status
Simulation time 223099064680 ps
CPU time 494.86 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:17:32 PM PDT 24
Peak memory 271092 kb
Host smart-02e92831-9901-4924-af56-17227e4b3dc0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111581164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3111581164
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.2931707527
Short name T687
Test name
Test status
Simulation time 47362321467 ps
CPU time 503.27 seconds
Started Jul 05 06:10:14 PM PDT 24
Finished Jul 05 06:18:38 PM PDT 24
Peak memory 280396 kb
Host smart-f319bbc9-f298-48a6-9a64-eab4628eb127
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931707527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.2931707527
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.3862188226
Short name T9
Test name
Test status
Simulation time 14476628 ps
CPU time 0.77 seconds
Started Jul 05 06:07:56 PM PDT 24
Finished Jul 05 06:07:58 PM PDT 24
Peak memory 205536 kb
Host smart-aa85aa25-0978-4d78-ae8d-bdbdb2a58cac
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862188226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
3862188226
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.544358960
Short name T251
Test name
Test status
Simulation time 126403998709 ps
CPU time 335.96 seconds
Started Jul 05 06:07:33 PM PDT 24
Finished Jul 05 06:13:09 PM PDT 24
Peak memory 265328 kb
Host smart-72e15568-ba31-4aa4-a571-28282d106949
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544358960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stress
_all.544358960
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.3902455511
Short name T2
Test name
Test status
Simulation time 6604567923 ps
CPU time 32.13 seconds
Started Jul 05 06:07:26 PM PDT 24
Finished Jul 05 06:07:59 PM PDT 24
Peak memory 216668 kb
Host smart-44c7717d-8a40-4aea-a2d1-3d2634c71459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902455511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.3902455511
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.2892784109
Short name T166
Test name
Test status
Simulation time 677654619 ps
CPU time 15.5 seconds
Started Jul 05 04:29:04 PM PDT 24
Finished Jul 05 04:29:28 PM PDT 24
Peak memory 215664 kb
Host smart-6d3a4998-8807-4b36-8e28-b937a72732b4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892784109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.2892784109
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2160251390
Short name T80
Test name
Test status
Simulation time 238434954253 ps
CPU time 292.32 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:13:32 PM PDT 24
Peak memory 269384 kb
Host smart-fccf728e-3ac8-41f4-ba4e-1c51d0661a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160251390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2160251390
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.1718906713
Short name T185
Test name
Test status
Simulation time 34386325523 ps
CPU time 193.2 seconds
Started Jul 05 06:08:10 PM PDT 24
Finished Jul 05 06:11:24 PM PDT 24
Peak memory 250864 kb
Host smart-1e449d89-71ee-4ef4-84f1-b57a450dba80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1718906713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.1718906713
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3556576602
Short name T271
Test name
Test status
Simulation time 3889093020 ps
CPU time 53.93 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:09:15 PM PDT 24
Peak memory 240496 kb
Host smart-281d3c2b-fe6d-4f0e-9da3-da86909b1417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556576602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3556576602
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.894718367
Short name T266
Test name
Test status
Simulation time 716510657 ps
CPU time 7.16 seconds
Started Jul 05 06:08:50 PM PDT 24
Finished Jul 05 06:08:57 PM PDT 24
Peak memory 236648 kb
Host smart-907208a0-f4ae-46b5-9121-e5b80ea71064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894718367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.894718367
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.2407005418
Short name T50
Test name
Test status
Simulation time 205187271914 ps
CPU time 265.96 seconds
Started Jul 05 06:07:33 PM PDT 24
Finished Jul 05 06:12:00 PM PDT 24
Peak memory 256912 kb
Host smart-511c4930-8dd6-4b22-86d2-68dc62da6809
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407005418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.2407005418
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.3600629196
Short name T92
Test name
Test status
Simulation time 319226217 ps
CPU time 4.15 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:19 PM PDT 24
Peak memory 215904 kb
Host smart-24717ec5-e9de-461d-889a-5174db6c3e51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3600629196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
3600629196
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1754159933
Short name T173
Test name
Test status
Simulation time 744325297 ps
CPU time 11.76 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:28 PM PDT 24
Peak memory 216052 kb
Host smart-9b0b69e7-a0cc-4aba-aa08-403511a32f8c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754159933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1754159933
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.2441915110
Short name T750
Test name
Test status
Simulation time 116551919241 ps
CPU time 567.87 seconds
Started Jul 05 06:07:26 PM PDT 24
Finished Jul 05 06:16:54 PM PDT 24
Peak memory 272860 kb
Host smart-732aa0db-7e5e-4e62-87c5-e573f5d97fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441915110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.2441915110
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1927612806
Short name T238
Test name
Test status
Simulation time 32590715140 ps
CPU time 204.96 seconds
Started Jul 05 06:08:23 PM PDT 24
Finished Jul 05 06:11:49 PM PDT 24
Peak memory 260136 kb
Host smart-dcb804fd-3cc6-4c86-be14-74fd2db69389
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927612806 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1927612806
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.3893751308
Short name T691
Test name
Test status
Simulation time 22098060385 ps
CPU time 184.13 seconds
Started Jul 05 06:08:59 PM PDT 24
Finished Jul 05 06:12:04 PM PDT 24
Peak memory 254784 kb
Host smart-4dbf3673-d9ab-4965-a45a-1141e7746902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893751308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.3893751308
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.1035065657
Short name T255
Test name
Test status
Simulation time 5117297790 ps
CPU time 101.23 seconds
Started Jul 05 06:09:35 PM PDT 24
Finished Jul 05 06:11:17 PM PDT 24
Peak memory 262148 kb
Host smart-751b0ef3-13ed-4538-b8e4-796faceea669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035065657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.1035065657
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.3694080593
Short name T170
Test name
Test status
Simulation time 2457603700 ps
CPU time 14.34 seconds
Started Jul 05 04:28:50 PM PDT 24
Finished Jul 05 04:29:14 PM PDT 24
Peak memory 215952 kb
Host smart-b78a143c-649b-4192-b111-ea6eedf1228a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694080593 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.3694080593
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/13.spi_device_intercept.2651869426
Short name T192
Test name
Test status
Simulation time 1106358181 ps
CPU time 12.89 seconds
Started Jul 05 06:07:57 PM PDT 24
Finished Jul 05 06:08:11 PM PDT 24
Peak memory 232728 kb
Host smart-87ea1ed4-7803-4e02-bcc0-fb42eeb17bb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651869426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.2651869426
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.4160013892
Short name T258
Test name
Test status
Simulation time 12567341131 ps
CPU time 66.92 seconds
Started Jul 05 06:09:39 PM PDT 24
Finished Jul 05 06:10:46 PM PDT 24
Peak memory 256944 kb
Host smart-621ea14a-f0fb-4ef5-8b58-845d95fbf70f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160013892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.4160013892
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.1631728691
Short name T240
Test name
Test status
Simulation time 1479394076 ps
CPU time 2.71 seconds
Started Jul 05 06:07:11 PM PDT 24
Finished Jul 05 06:07:14 PM PDT 24
Peak memory 224492 kb
Host smart-6439f02e-a9d3-4a8d-968f-7b3c3ff74cdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631728691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.1631728691
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.1872375039
Short name T65
Test name
Test status
Simulation time 76076829 ps
CPU time 2.32 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:19 PM PDT 24
Peak memory 215860 kb
Host smart-9eb13b66-146a-464d-951d-db37e81777a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1872375039 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.1
872375039
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.3063091204
Short name T139
Test name
Test status
Simulation time 886565011 ps
CPU time 5.68 seconds
Started Jul 05 06:08:02 PM PDT 24
Finished Jul 05 06:08:09 PM PDT 24
Peak memory 222632 kb
Host smart-485156b5-4507-445d-9aa6-b82a9107f567
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3063091204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.3063091204
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1097955854
Short name T71
Test name
Test status
Simulation time 47925604 ps
CPU time 0.92 seconds
Started Jul 05 04:29:17 PM PDT 24
Finished Jul 05 04:29:26 PM PDT 24
Peak memory 207096 kb
Host smart-343c6fee-5210-4ab5-a7f8-4ddd8adf24da
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097955854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1097955854
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3899087621
Short name T1114
Test name
Test status
Simulation time 4349377032 ps
CPU time 7.73 seconds
Started Jul 05 04:29:08 PM PDT 24
Finished Jul 05 04:29:25 PM PDT 24
Peak memory 215656 kb
Host smart-026d3fab-4831-43ed-836b-d1361fc9c135
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899087621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3899087621
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.955800646
Short name T1072
Test name
Test status
Simulation time 10410773888 ps
CPU time 33.46 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:29:39 PM PDT 24
Peak memory 215708 kb
Host smart-85034aad-bd09-4200-a0df-a47693cb5e26
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955800646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.955800646
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.672929649
Short name T1054
Test name
Test status
Simulation time 138474164 ps
CPU time 1.78 seconds
Started Jul 05 04:29:00 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 216760 kb
Host smart-52eb614b-a84b-468f-a76e-b14bd73184ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672929649 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.672929649
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.935284298
Short name T1091
Test name
Test status
Simulation time 69176011 ps
CPU time 2.04 seconds
Started Jul 05 04:29:05 PM PDT 24
Finished Jul 05 04:29:15 PM PDT 24
Peak memory 207368 kb
Host smart-e67b889d-f0e3-4e8f-83d7-18220c0e1fab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935284298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.935284298
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.2860639872
Short name T1092
Test name
Test status
Simulation time 18084475 ps
CPU time 0.77 seconds
Started Jul 05 04:29:01 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 204156 kb
Host smart-36ebd846-0f42-4c2b-ab2a-82834fe6d3f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860639872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.2
860639872
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.3638551930
Short name T107
Test name
Test status
Simulation time 31216537 ps
CPU time 1.27 seconds
Started Jul 05 04:29:13 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 215620 kb
Host smart-551dbee5-3f52-4406-9537-79bc133b0561
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3638551930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.3638551930
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.2282077584
Short name T1008
Test name
Test status
Simulation time 35439068 ps
CPU time 0.65 seconds
Started Jul 05 04:28:52 PM PDT 24
Finished Jul 05 04:29:02 PM PDT 24
Peak memory 204324 kb
Host smart-76f38ffe-258a-400b-a79f-d2047c274cab
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282077584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.2282077584
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1899742240
Short name T1125
Test name
Test status
Simulation time 112543500 ps
CPU time 3.06 seconds
Started Jul 05 04:29:01 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 215544 kb
Host smart-43698ee6-ac06-489b-b649-9b5d0a45c4fe
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899742240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1899742240
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.2359435493
Short name T1087
Test name
Test status
Simulation time 29703845 ps
CPU time 1.8 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 215792 kb
Host smart-bc814544-35dc-4ff1-b1c9-e637149b5df5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359435493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.2
359435493
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.1064451857
Short name T111
Test name
Test status
Simulation time 6089923231 ps
CPU time 21.86 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:38 PM PDT 24
Peak memory 215640 kb
Host smart-7daf0d53-f9c1-4dc0-94e4-b585dcda4176
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064451857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.1064451857
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2677355347
Short name T114
Test name
Test status
Simulation time 1071117058 ps
CPU time 30 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:47 PM PDT 24
Peak memory 215464 kb
Host smart-d91be0cb-a2fc-4c6a-87bc-3fba8d722746
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677355347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2677355347
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.753965805
Short name T72
Test name
Test status
Simulation time 60124232 ps
CPU time 1.17 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:09 PM PDT 24
Peak memory 207308 kb
Host smart-b8992ea5-128d-4b37-a069-b6ad24c81bc3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753965805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_hw_reset.753965805
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.427796338
Short name T1112
Test name
Test status
Simulation time 52249657 ps
CPU time 2.08 seconds
Started Jul 05 04:29:17 PM PDT 24
Finished Jul 05 04:29:27 PM PDT 24
Peak memory 216684 kb
Host smart-fbc5b638-dd4b-4899-9883-ca63f9ffa36d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427796338 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.427796338
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3150557629
Short name T110
Test name
Test status
Simulation time 141438299 ps
CPU time 1.28 seconds
Started Jul 05 04:29:14 PM PDT 24
Finished Jul 05 04:29:24 PM PDT 24
Peak memory 207440 kb
Host smart-ab042644-6cba-4d34-96c9-71ce478b97cd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3150557629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
150557629
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.3316363635
Short name T1117
Test name
Test status
Simulation time 11770899 ps
CPU time 0.69 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 204164 kb
Host smart-ac1969e0-2f0a-417c-916e-1439e73ffbb6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316363635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.3
316363635
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.2947690208
Short name T1062
Test name
Test status
Simulation time 55678517 ps
CPU time 1.3 seconds
Started Jul 05 04:28:57 PM PDT 24
Finished Jul 05 04:29:08 PM PDT 24
Peak memory 215672 kb
Host smart-0cd77f7f-ff54-480d-903b-eed5429adca1
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2947690208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi
_device_mem_partial_access.2947690208
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.3117911889
Short name T1057
Test name
Test status
Simulation time 40005825 ps
CPU time 0.65 seconds
Started Jul 05 04:29:12 PM PDT 24
Finished Jul 05 04:29:22 PM PDT 24
Peak memory 203980 kb
Host smart-d20322e4-4c5a-483b-8fbc-4b316c1fe1a6
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3117911889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_me
m_walk.3117911889
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.210159154
Short name T1078
Test name
Test status
Simulation time 139928008 ps
CPU time 2.86 seconds
Started Jul 05 04:29:03 PM PDT 24
Finished Jul 05 04:29:15 PM PDT 24
Peak memory 215652 kb
Host smart-c3ad149e-ea27-4c4e-a0ad-123702ff4e32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=210159154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sp
i_device_same_csr_outstanding.210159154
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.4118804399
Short name T93
Test name
Test status
Simulation time 60603776 ps
CPU time 1.89 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:29:10 PM PDT 24
Peak memory 215888 kb
Host smart-d752dbbd-4394-43a5-aa04-853f1e50ceb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118804399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.4
118804399
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.3360692134
Short name T144
Test name
Test status
Simulation time 219297191 ps
CPU time 1.7 seconds
Started Jul 05 04:28:54 PM PDT 24
Finished Jul 05 04:29:04 PM PDT 24
Peak memory 216708 kb
Host smart-c3eafca3-f493-472a-9489-d6250d8ef38b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360692134 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.3360692134
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.2418430985
Short name T108
Test name
Test status
Simulation time 165575041 ps
CPU time 1.91 seconds
Started Jul 05 04:29:00 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 215540 kb
Host smart-2424286d-5285-4341-b1ee-cf5153bd0cee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418430985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
2418430985
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.4014096534
Short name T1102
Test name
Test status
Simulation time 12263936 ps
CPU time 0.75 seconds
Started Jul 05 04:29:22 PM PDT 24
Finished Jul 05 04:29:32 PM PDT 24
Peak memory 204112 kb
Host smart-f734187b-17a9-4251-8662-010b073fb729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4014096534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
4014096534
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.937266649
Short name T1097
Test name
Test status
Simulation time 165688727 ps
CPU time 2.84 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 215588 kb
Host smart-985eb4e2-35c5-4794-ba3a-bfeff30f006a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937266649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.s
pi_device_same_csr_outstanding.937266649
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.2580134687
Short name T142
Test name
Test status
Simulation time 1386555592 ps
CPU time 23.98 seconds
Started Jul 05 04:29:04 PM PDT 24
Finished Jul 05 04:29:37 PM PDT 24
Peak memory 215688 kb
Host smart-e6c9aef1-0443-4392-94df-a5040c0fc458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2580134687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_devic
e_tl_intg_err.2580134687
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.1616555850
Short name T1101
Test name
Test status
Simulation time 86197844 ps
CPU time 2.66 seconds
Started Jul 05 04:29:01 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 216900 kb
Host smart-94196955-bbd9-4e08-96aa-a5f9351dabd0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1616555850 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.1616555850
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.2285996790
Short name T1022
Test name
Test status
Simulation time 74042554 ps
CPU time 1.32 seconds
Started Jul 05 04:29:03 PM PDT 24
Finished Jul 05 04:29:14 PM PDT 24
Peak memory 215632 kb
Host smart-0c6ff1e2-66b4-4f40-ab3f-a80fcf31cb38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285996790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
2285996790
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.869633425
Short name T1126
Test name
Test status
Simulation time 98985428 ps
CPU time 0.66 seconds
Started Jul 05 04:29:00 PM PDT 24
Finished Jul 05 04:29:10 PM PDT 24
Peak memory 204476 kb
Host smart-5b6ee7ea-ec46-4c5f-ba8f-3fdb572e454f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869633425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.869633425
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1701792385
Short name T1051
Test name
Test status
Simulation time 46212168 ps
CPU time 2.71 seconds
Started Jul 05 04:29:00 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 215676 kb
Host smart-aa26c53d-c373-42ed-b709-79a67cd9a322
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701792385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1701792385
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3098779346
Short name T99
Test name
Test status
Simulation time 231394346 ps
CPU time 3.79 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:14 PM PDT 24
Peak memory 215892 kb
Host smart-5fe7d516-03e3-44f2-80f9-d5f19f9bcd7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3098779346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3098779346
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1005742693
Short name T167
Test name
Test status
Simulation time 564931770 ps
CPU time 14.75 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:22 PM PDT 24
Peak memory 215660 kb
Host smart-79e4ea19-0d9a-41c4-849d-8c8a543ba49e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005742693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1005742693
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1488849673
Short name T1031
Test name
Test status
Simulation time 95726400 ps
CPU time 1.77 seconds
Started Jul 05 04:29:13 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 216780 kb
Host smart-6bbdcc71-5175-4bc6-bc4c-65c3d30a5be0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488849673 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1488849673
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.545966045
Short name T1077
Test name
Test status
Simulation time 124761492 ps
CPU time 2.33 seconds
Started Jul 05 04:29:16 PM PDT 24
Finished Jul 05 04:29:27 PM PDT 24
Peak memory 215580 kb
Host smart-9fba3fe5-9a91-4f55-b065-61abc9f10339
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545966045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.545966045
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.908778033
Short name T1121
Test name
Test status
Simulation time 29572995 ps
CPU time 0.71 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 204160 kb
Host smart-609be2dc-3165-489c-b608-b6ea29fbc095
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=908778033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.908778033
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1154135512
Short name T1093
Test name
Test status
Simulation time 308680155 ps
CPU time 3.89 seconds
Started Jul 05 04:29:19 PM PDT 24
Finished Jul 05 04:29:31 PM PDT 24
Peak memory 215556 kb
Host smart-54d29bac-bfff-4d49-b7ec-3bffed8816f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154135512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1154135512
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2030785917
Short name T1048
Test name
Test status
Simulation time 286708987 ps
CPU time 2.14 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 216912 kb
Host smart-417719b7-f16b-4eb0-86fa-cd42e3d81f21
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2030785917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2030785917
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.816296561
Short name T171
Test name
Test status
Simulation time 1090593565 ps
CPU time 13.64 seconds
Started Jul 05 04:29:12 PM PDT 24
Finished Jul 05 04:29:35 PM PDT 24
Peak memory 216256 kb
Host smart-a69732a3-839d-4ab9-b173-f3bb38cf1883
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=816296561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.816296561
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.982168383
Short name T98
Test name
Test status
Simulation time 484341673 ps
CPU time 3.38 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 218304 kb
Host smart-0d82f8d4-258e-4e3c-b815-e27b1935f680
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982168383 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.982168383
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.3525491399
Short name T1115
Test name
Test status
Simulation time 413115899 ps
CPU time 2.46 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:19 PM PDT 24
Peak memory 215564 kb
Host smart-a5175f4a-9c66-4bb6-ab41-d5c85fa53ad5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525491399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
3525491399
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3845442925
Short name T1029
Test name
Test status
Simulation time 16598780 ps
CPU time 0.65 seconds
Started Jul 05 04:29:04 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 204068 kb
Host smart-0600ac1e-ecf3-48a5-9717-3d04aeb20cb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845442925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3845442925
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.1037376411
Short name T1081
Test name
Test status
Simulation time 596070699 ps
CPU time 3.96 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:15 PM PDT 24
Peak memory 215628 kb
Host smart-99b75c89-aae4-4fd2-958b-2aba499d7bd1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037376411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.1037376411
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2038844905
Short name T1055
Test name
Test status
Simulation time 256865038 ps
CPU time 1.85 seconds
Started Jul 05 04:29:13 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 215760 kb
Host smart-1d40743c-0335-4968-9982-c9c49fb20afa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038844905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2038844905
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3333847515
Short name T86
Test name
Test status
Simulation time 1135085976 ps
CPU time 23.17 seconds
Started Jul 05 04:29:01 PM PDT 24
Finished Jul 05 04:29:33 PM PDT 24
Peak memory 215632 kb
Host smart-c57d4c4c-a71c-40e0-9373-9f295252968b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333847515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3333847515
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.544140518
Short name T97
Test name
Test status
Simulation time 526118315 ps
CPU time 3.44 seconds
Started Jul 05 04:29:17 PM PDT 24
Finished Jul 05 04:29:28 PM PDT 24
Peak memory 217572 kb
Host smart-28321a12-eb13-4e94-a8c3-acfab6fb1a11
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544140518 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.544140518
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3451067962
Short name T1047
Test name
Test status
Simulation time 21268214 ps
CPU time 1.27 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 215984 kb
Host smart-029f5f46-2f43-43bb-a5f6-4ebf8dc66087
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451067962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3451067962
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.3919279612
Short name T1084
Test name
Test status
Simulation time 20652562 ps
CPU time 0.7 seconds
Started Jul 05 04:29:20 PM PDT 24
Finished Jul 05 04:29:29 PM PDT 24
Peak memory 204436 kb
Host smart-734d2da2-47e1-47c3-9c2f-7b35a178831d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919279612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
3919279612
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.987650097
Short name T1032
Test name
Test status
Simulation time 464082343 ps
CPU time 3.6 seconds
Started Jul 05 04:29:15 PM PDT 24
Finished Jul 05 04:29:27 PM PDT 24
Peak memory 215628 kb
Host smart-1c3c0116-7401-4c83-9f01-d7105a285407
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=987650097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.s
pi_device_same_csr_outstanding.987650097
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.510851258
Short name T165
Test name
Test status
Simulation time 389983536 ps
CPU time 6.32 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 215632 kb
Host smart-94728a17-d55f-4b7a-9371-a88c267eb0cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510851258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.510851258
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1298886585
Short name T1098
Test name
Test status
Simulation time 92930797 ps
CPU time 2.44 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:29:35 PM PDT 24
Peak memory 217116 kb
Host smart-9154a479-45a5-43db-b17c-76d2b75f6d9d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298886585 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1298886585
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2370820173
Short name T1123
Test name
Test status
Simulation time 517888552 ps
CPU time 2 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:10 PM PDT 24
Peak memory 215548 kb
Host smart-71a07e38-c665-4b36-b7e1-19525e469055
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2370820173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2370820173
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.1537617043
Short name T1012
Test name
Test status
Simulation time 52253140 ps
CPU time 0.73 seconds
Started Jul 05 04:29:15 PM PDT 24
Finished Jul 05 04:29:24 PM PDT 24
Peak memory 204468 kb
Host smart-1be0b0b7-1209-41b4-8000-f06c0d4b16a4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537617043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
1537617043
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.916830802
Short name T1038
Test name
Test status
Simulation time 57735061 ps
CPU time 1.92 seconds
Started Jul 05 04:29:09 PM PDT 24
Finished Jul 05 04:29:20 PM PDT 24
Peak memory 215708 kb
Host smart-958648a7-aee1-494f-aa1f-6c7bb8f5c1d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=916830802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.s
pi_device_same_csr_outstanding.916830802
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.4062717424
Short name T1061
Test name
Test status
Simulation time 166046853 ps
CPU time 3.81 seconds
Started Jul 05 04:29:23 PM PDT 24
Finished Jul 05 04:29:36 PM PDT 24
Peak memory 215872 kb
Host smart-00cd7cf7-7bfe-447c-9cf0-dd9f78260fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4062717424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
4062717424
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.2023175305
Short name T1120
Test name
Test status
Simulation time 105605155 ps
CPU time 6.72 seconds
Started Jul 05 04:28:54 PM PDT 24
Finished Jul 05 04:29:10 PM PDT 24
Peak memory 215636 kb
Host smart-6f186f70-4dca-4a33-a334-4ffeadbf7175
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023175305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_devic
e_tl_intg_err.2023175305
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.1205616180
Short name T96
Test name
Test status
Simulation time 189222792 ps
CPU time 3.3 seconds
Started Jul 05 04:29:13 PM PDT 24
Finished Jul 05 04:29:25 PM PDT 24
Peak memory 217952 kb
Host smart-8ef40583-92a5-4966-99af-27d924b561aa
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205616180 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.1205616180
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.2701565613
Short name T1027
Test name
Test status
Simulation time 816777864 ps
CPU time 2.14 seconds
Started Jul 05 04:29:22 PM PDT 24
Finished Jul 05 04:29:37 PM PDT 24
Peak memory 215620 kb
Host smart-fd8be40f-e09e-42f5-9f0b-8e8ceed6fd91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2701565613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
2701565613
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.3888847693
Short name T1019
Test name
Test status
Simulation time 37561268 ps
CPU time 0.68 seconds
Started Jul 05 04:29:19 PM PDT 24
Finished Jul 05 04:29:28 PM PDT 24
Peak memory 204080 kb
Host smart-f49f4fcb-bc1e-4ab4-a6e1-bb5782b5e1c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888847693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.
3888847693
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.67273576
Short name T1056
Test name
Test status
Simulation time 148140815 ps
CPU time 3.17 seconds
Started Jul 05 04:29:18 PM PDT 24
Finished Jul 05 04:29:30 PM PDT 24
Peak memory 215712 kb
Host smart-0738ac8f-5d6c-48df-b045-026349c3761a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67273576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sp
i_device_same_csr_outstanding.67273576
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.299016110
Short name T64
Test name
Test status
Simulation time 72344069 ps
CPU time 1.89 seconds
Started Jul 05 04:29:20 PM PDT 24
Finished Jul 05 04:29:31 PM PDT 24
Peak memory 216072 kb
Host smart-24f64bb9-79e3-4766-afe1-0f249364acbb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299016110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.299016110
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3671168545
Short name T1090
Test name
Test status
Simulation time 26934297 ps
CPU time 1.61 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:09 PM PDT 24
Peak memory 215724 kb
Host smart-2529aed0-bf32-44cb-97f6-b14d8f85b3dc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671168545 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3671168545
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3751612547
Short name T112
Test name
Test status
Simulation time 44274532 ps
CPU time 2.34 seconds
Started Jul 05 04:29:19 PM PDT 24
Finished Jul 05 04:29:30 PM PDT 24
Peak memory 215624 kb
Host smart-7397a16e-df61-445e-9422-c36c5ca94505
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751612547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3751612547
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.4249245081
Short name T1013
Test name
Test status
Simulation time 34883263 ps
CPU time 0.72 seconds
Started Jul 05 04:29:21 PM PDT 24
Finished Jul 05 04:29:31 PM PDT 24
Peak memory 204860 kb
Host smart-844d800d-dea2-4c4d-9fd1-f6ad68e5eb06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249245081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
4249245081
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.1498113044
Short name T133
Test name
Test status
Simulation time 214277484 ps
CPU time 4.26 seconds
Started Jul 05 04:29:12 PM PDT 24
Finished Jul 05 04:29:26 PM PDT 24
Peak memory 215672 kb
Host smart-1e19f24e-618f-4683-9dc2-01c8004a8f59
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498113044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.1498113044
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.3138727735
Short name T1100
Test name
Test status
Simulation time 530478248 ps
CPU time 3.74 seconds
Started Jul 05 04:29:36 PM PDT 24
Finished Jul 05 04:29:44 PM PDT 24
Peak memory 215996 kb
Host smart-c31fada6-f916-4395-a134-93b07e766028
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138727735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
3138727735
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.1803010509
Short name T1099
Test name
Test status
Simulation time 214578543 ps
CPU time 11.89 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:29:45 PM PDT 24
Peak memory 215732 kb
Host smart-1e10173e-2823-4841-aa7b-9704c6f780cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803010509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.1803010509
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1622103245
Short name T95
Test name
Test status
Simulation time 151016276 ps
CPU time 2.57 seconds
Started Jul 05 04:29:19 PM PDT 24
Finished Jul 05 04:29:30 PM PDT 24
Peak memory 216732 kb
Host smart-e8bc1837-afa7-42d0-a048-0870cd8b148c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622103245 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1622103245
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.683308429
Short name T1079
Test name
Test status
Simulation time 148379222 ps
CPU time 2.4 seconds
Started Jul 05 04:29:04 PM PDT 24
Finished Jul 05 04:29:15 PM PDT 24
Peak memory 215488 kb
Host smart-171a525e-a80d-4398-bff3-f254c517f523
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683308429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.683308429
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2595033762
Short name T1021
Test name
Test status
Simulation time 44350062 ps
CPU time 0.7 seconds
Started Jul 05 04:29:20 PM PDT 24
Finished Jul 05 04:29:29 PM PDT 24
Peak memory 204112 kb
Host smart-6875674b-ee55-4f0f-a931-21436eeca012
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2595033762 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2595033762
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2574257223
Short name T130
Test name
Test status
Simulation time 108065606 ps
CPU time 2.76 seconds
Started Jul 05 04:29:05 PM PDT 24
Finished Jul 05 04:29:16 PM PDT 24
Peak memory 215900 kb
Host smart-d1699c45-ce74-49bd-a5d4-967b215e36e7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574257223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2574257223
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.4262067604
Short name T88
Test name
Test status
Simulation time 1732911675 ps
CPU time 3.72 seconds
Started Jul 05 04:29:15 PM PDT 24
Finished Jul 05 04:29:27 PM PDT 24
Peak memory 215800 kb
Host smart-5923522d-1680-49a9-8828-266ae3acb259
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262067604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
4262067604
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.1536602592
Short name T169
Test name
Test status
Simulation time 194187569 ps
CPU time 11.38 seconds
Started Jul 05 04:29:17 PM PDT 24
Finished Jul 05 04:29:42 PM PDT 24
Peak memory 215580 kb
Host smart-c673544e-a551-4f9a-846e-79054e17a2df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536602592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.1536602592
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2182815033
Short name T100
Test name
Test status
Simulation time 156571800 ps
CPU time 1.49 seconds
Started Jul 05 04:29:23 PM PDT 24
Finished Jul 05 04:29:33 PM PDT 24
Peak memory 215888 kb
Host smart-15c3789a-a79e-4066-a08c-e923be0fc6e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182815033 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2182815033
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.3869204179
Short name T1110
Test name
Test status
Simulation time 350029393 ps
CPU time 2.01 seconds
Started Jul 05 04:29:11 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 215604 kb
Host smart-9e1c84cd-a583-4356-86f9-7f2c56e878b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869204179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
3869204179
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1906880546
Short name T1044
Test name
Test status
Simulation time 17998714 ps
CPU time 0.82 seconds
Started Jul 05 04:29:12 PM PDT 24
Finished Jul 05 04:29:22 PM PDT 24
Peak memory 203612 kb
Host smart-9d1b2b0d-8044-41b4-9547-ce2bafeaa8e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1906880546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1906880546
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.1486038601
Short name T1070
Test name
Test status
Simulation time 55485375 ps
CPU time 1.69 seconds
Started Jul 05 04:29:16 PM PDT 24
Finished Jul 05 04:29:26 PM PDT 24
Peak memory 215992 kb
Host smart-903ca598-dbda-4d0f-8cf3-5e4fa945bfc4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486038601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.1486038601
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1262902621
Short name T91
Test name
Test status
Simulation time 35098472 ps
CPU time 2.2 seconds
Started Jul 05 04:29:21 PM PDT 24
Finished Jul 05 04:29:32 PM PDT 24
Peak memory 216024 kb
Host smart-df7b50be-3ce7-4ec1-ba94-ed9dd1afb026
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262902621 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1262902621
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.628548288
Short name T106
Test name
Test status
Simulation time 1377697735 ps
CPU time 10.74 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 207336 kb
Host smart-cf0feaa4-4849-493f-bd50-6d735cc968d3
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628548288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.628548288
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3358591367
Short name T73
Test name
Test status
Simulation time 20054435 ps
CPU time 1.1 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:16 PM PDT 24
Peak memory 207360 kb
Host smart-fea72c5c-ad8d-44d1-bfe8-c121f7c6aefa
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358591367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3358591367
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2039070282
Short name T1028
Test name
Test status
Simulation time 392619185 ps
CPU time 2.86 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 218380 kb
Host smart-ce36d39c-2ec4-4bfe-a721-d175b66a2ee9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2039070282 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2039070282
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.3754360054
Short name T109
Test name
Test status
Simulation time 109522256 ps
CPU time 1.29 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 215568 kb
Host smart-0488b155-4d86-433a-abe4-df251ebfd5a6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754360054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.3
754360054
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.2642733107
Short name T1011
Test name
Test status
Simulation time 12986642 ps
CPU time 0.68 seconds
Started Jul 05 04:29:05 PM PDT 24
Finished Jul 05 04:29:14 PM PDT 24
Peak memory 204484 kb
Host smart-7eed0c59-2b21-4fb1-881e-15d8e5b75eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2642733107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.2
642733107
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2181369531
Short name T1096
Test name
Test status
Simulation time 319944323 ps
CPU time 1.32 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 215664 kb
Host smart-793dc1f5-a774-4a99-91f5-9674b41e40bd
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181369531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2181369531
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.3519917410
Short name T1016
Test name
Test status
Simulation time 41318330 ps
CPU time 0.65 seconds
Started Jul 05 04:29:14 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 204004 kb
Host smart-b0998ce7-66de-427b-8cc3-649e20ad9734
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519917410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.3519917410
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3142949318
Short name T143
Test name
Test status
Simulation time 557968979 ps
CPU time 3 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:05 PM PDT 24
Peak memory 215620 kb
Host smart-2bc6f60e-00f1-4354-b51e-824042f7b9f3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142949318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3142949318
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1635758060
Short name T1103
Test name
Test status
Simulation time 106710228 ps
CPU time 2.06 seconds
Started Jul 05 04:29:23 PM PDT 24
Finished Jul 05 04:29:34 PM PDT 24
Peak memory 215928 kb
Host smart-dad0ff93-5f66-43c4-989a-e2a6c49a9bfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635758060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
635758060
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3649421295
Short name T1129
Test name
Test status
Simulation time 4805330046 ps
CPU time 19.47 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:31 PM PDT 24
Peak memory 216116 kb
Host smart-1cec8808-b520-4bea-abd1-8f1746c9f7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649421295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3649421295
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.223393014
Short name T1080
Test name
Test status
Simulation time 59679136 ps
CPU time 0.68 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 204152 kb
Host smart-02428995-204d-4ed2-a701-872e3a23517e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223393014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.223393014
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2169364237
Short name T1068
Test name
Test status
Simulation time 14706753 ps
CPU time 0.76 seconds
Started Jul 05 04:29:18 PM PDT 24
Finished Jul 05 04:29:28 PM PDT 24
Peak memory 204120 kb
Host smart-e63fdafe-6dac-4a62-a0e4-a1ce35374f0e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169364237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2169364237
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.3944275113
Short name T1065
Test name
Test status
Simulation time 47197690 ps
CPU time 0.69 seconds
Started Jul 05 04:29:35 PM PDT 24
Finished Jul 05 04:29:41 PM PDT 24
Peak memory 204124 kb
Host smart-6859a8e9-cfaf-40d8-8a48-ca9d6f8c8532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3944275113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
3944275113
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.1175179480
Short name T1053
Test name
Test status
Simulation time 34594238 ps
CPU time 0.79 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:16 PM PDT 24
Peak memory 204104 kb
Host smart-8b468cd8-7318-4059-8d3c-2019da3c80b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175179480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
1175179480
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.2837362963
Short name T1043
Test name
Test status
Simulation time 73960388 ps
CPU time 0.75 seconds
Started Jul 05 04:29:11 PM PDT 24
Finished Jul 05 04:29:20 PM PDT 24
Peak memory 204188 kb
Host smart-83bb6396-456b-4bba-adb4-1243f632a250
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2837362963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
2837362963
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.1684516248
Short name T1009
Test name
Test status
Simulation time 19225001 ps
CPU time 0.74 seconds
Started Jul 05 04:29:19 PM PDT 24
Finished Jul 05 04:29:29 PM PDT 24
Peak memory 204420 kb
Host smart-abb8c7e8-4084-4999-8d7c-9ad84b30700e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1684516248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
1684516248
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2203341765
Short name T1067
Test name
Test status
Simulation time 40126148 ps
CPU time 0.74 seconds
Started Jul 05 04:29:30 PM PDT 24
Finished Jul 05 04:29:37 PM PDT 24
Peak memory 204492 kb
Host smart-c0de28fe-8c4d-40aa-b2da-14f9282c134f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203341765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2203341765
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3978710161
Short name T1046
Test name
Test status
Simulation time 42287428 ps
CPU time 0.69 seconds
Started Jul 05 04:29:05 PM PDT 24
Finished Jul 05 04:29:14 PM PDT 24
Peak memory 204172 kb
Host smart-1efba8ea-5f86-4285-9d2c-a99410bd3ab4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978710161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3978710161
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.4273466472
Short name T1059
Test name
Test status
Simulation time 45223664 ps
CPU time 0.69 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 204188 kb
Host smart-2dbbe448-15d3-4533-be55-1043dd731299
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273466472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
4273466472
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.232891242
Short name T1041
Test name
Test status
Simulation time 15558710 ps
CPU time 0.7 seconds
Started Jul 05 04:29:30 PM PDT 24
Finished Jul 05 04:29:38 PM PDT 24
Peak memory 204444 kb
Host smart-c95815b8-96cb-4d4e-92ad-0def2fb45069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232891242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.232891242
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.1661939272
Short name T104
Test name
Test status
Simulation time 1608129094 ps
CPU time 16.03 seconds
Started Jul 05 04:29:25 PM PDT 24
Finished Jul 05 04:29:50 PM PDT 24
Peak memory 215540 kb
Host smart-481dc33a-b4cf-4128-bb61-4bd0ab7ca3d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1661939272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.1661939272
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.2549282223
Short name T115
Test name
Test status
Simulation time 1453429731 ps
CPU time 21.59 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:29:30 PM PDT 24
Peak memory 207416 kb
Host smart-14bfe095-b74e-4493-80e7-7685929d6b46
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549282223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.2549282223
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.249640288
Short name T1076
Test name
Test status
Simulation time 250622626 ps
CPU time 1.2 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 207332 kb
Host smart-3a03468c-77ee-4fbd-b625-91b54abde4f4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249640288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr
_hw_reset.249640288
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2057641247
Short name T1040
Test name
Test status
Simulation time 840624147 ps
CPU time 3.58 seconds
Started Jul 05 04:29:14 PM PDT 24
Finished Jul 05 04:29:26 PM PDT 24
Peak memory 218388 kb
Host smart-ec3cd2c2-36b1-4677-b828-c4825641ddfe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057641247 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2057641247
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3244064696
Short name T1060
Test name
Test status
Simulation time 388536634 ps
CPU time 2.27 seconds
Started Jul 05 04:29:12 PM PDT 24
Finished Jul 05 04:29:27 PM PDT 24
Peak memory 215532 kb
Host smart-b8325868-79c2-495e-9ec2-1429f2d6afff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244064696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
244064696
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.3924940032
Short name T1010
Test name
Test status
Simulation time 37243805 ps
CPU time 0.67 seconds
Started Jul 05 04:29:10 PM PDT 24
Finished Jul 05 04:29:19 PM PDT 24
Peak memory 204160 kb
Host smart-7c7136d1-1514-42d3-8565-4ab262ac4f2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3924940032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.3
924940032
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.2181547631
Short name T103
Test name
Test status
Simulation time 283315304 ps
CPU time 2.23 seconds
Started Jul 05 04:29:20 PM PDT 24
Finished Jul 05 04:29:31 PM PDT 24
Peak memory 215636 kb
Host smart-e8809c23-2d45-41be-b99c-606aa1d8dbda
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181547631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.2181547631
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.4136425815
Short name T1033
Test name
Test status
Simulation time 15632868 ps
CPU time 0.64 seconds
Started Jul 05 04:29:10 PM PDT 24
Finished Jul 05 04:29:20 PM PDT 24
Peak memory 203992 kb
Host smart-96e38ef0-9bce-4651-9a86-f8e9c167540a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136425815 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.4136425815
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.4169068410
Short name T1024
Test name
Test status
Simulation time 118015941 ps
CPU time 1.78 seconds
Started Jul 05 04:29:15 PM PDT 24
Finished Jul 05 04:29:25 PM PDT 24
Peak memory 215524 kb
Host smart-848a19d4-676c-484c-844d-8e9c85e07f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169068410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.4169068410
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.4233828661
Short name T1106
Test name
Test status
Simulation time 143043314 ps
CPU time 4.68 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:21 PM PDT 24
Peak memory 215868 kb
Host smart-9777ce6f-64bd-4d8c-b851-e8d93157292d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4233828661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.4
233828661
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.457971457
Short name T1127
Test name
Test status
Simulation time 216101668 ps
CPU time 12.66 seconds
Started Jul 05 04:28:51 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 215596 kb
Host smart-64e7d20c-7cdc-4364-8af3-3fa5c9a9045e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457971457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.457971457
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1178294785
Short name T1108
Test name
Test status
Simulation time 29371421 ps
CPU time 0.74 seconds
Started Jul 05 04:29:15 PM PDT 24
Finished Jul 05 04:29:24 PM PDT 24
Peak memory 204396 kb
Host smart-b01faf09-65c2-41ae-b0bb-d5cd956b714d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178294785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1178294785
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.630811935
Short name T1066
Test name
Test status
Simulation time 25881603 ps
CPU time 0.74 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:29:34 PM PDT 24
Peak memory 204160 kb
Host smart-e30d3658-1b86-4c14-993f-07edc395433c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630811935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.630811935
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3943755779
Short name T1128
Test name
Test status
Simulation time 31120614 ps
CPU time 0.82 seconds
Started Jul 05 04:29:28 PM PDT 24
Finished Jul 05 04:29:37 PM PDT 24
Peak memory 204172 kb
Host smart-0ccf4a24-4173-473f-b4c3-fb88a63634f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943755779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3943755779
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.211788309
Short name T1039
Test name
Test status
Simulation time 26207880 ps
CPU time 0.74 seconds
Started Jul 05 04:29:20 PM PDT 24
Finished Jul 05 04:29:30 PM PDT 24
Peak memory 204164 kb
Host smart-2df6f27d-3149-4edd-8109-ef4a46b117e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211788309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.211788309
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.4030583964
Short name T1074
Test name
Test status
Simulation time 19334411 ps
CPU time 0.7 seconds
Started Jul 05 04:29:17 PM PDT 24
Finished Jul 05 04:29:25 PM PDT 24
Peak memory 204200 kb
Host smart-97f318bf-3e1c-49e6-89a0-ba607af2140f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030583964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
4030583964
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.4141146227
Short name T1042
Test name
Test status
Simulation time 41055210 ps
CPU time 0.73 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:29:33 PM PDT 24
Peak memory 204176 kb
Host smart-94a88daa-1d66-4fc0-94f3-7c6f3d69e967
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141146227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
4141146227
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.2336014460
Short name T1075
Test name
Test status
Simulation time 151411803 ps
CPU time 0.68 seconds
Started Jul 05 04:29:21 PM PDT 24
Finished Jul 05 04:29:31 PM PDT 24
Peak memory 204472 kb
Host smart-41381c67-c3e9-408c-a766-cfc161044ab2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336014460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
2336014460
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2854574781
Short name T1030
Test name
Test status
Simulation time 40597396 ps
CPU time 0.67 seconds
Started Jul 05 04:29:16 PM PDT 24
Finished Jul 05 04:29:25 PM PDT 24
Peak memory 204164 kb
Host smart-b9f8c702-4ebb-4eda-9760-c0c05a56bb74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854574781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2854574781
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.880742850
Short name T1113
Test name
Test status
Simulation time 19054637 ps
CPU time 0.77 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:29:34 PM PDT 24
Peak memory 204476 kb
Host smart-8bd612a9-587b-43cd-9e86-4c9372d20ce9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=880742850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.880742850
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.1160089187
Short name T1064
Test name
Test status
Simulation time 30828608 ps
CPU time 0.75 seconds
Started Jul 05 04:29:34 PM PDT 24
Finished Jul 05 04:29:40 PM PDT 24
Peak memory 204488 kb
Host smart-f2be1028-708e-4cba-a241-18ad3aa876f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160089187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
1160089187
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.67897633
Short name T1111
Test name
Test status
Simulation time 4648054360 ps
CPU time 15.32 seconds
Started Jul 05 04:29:10 PM PDT 24
Finished Jul 05 04:29:35 PM PDT 24
Peak memory 207504 kb
Host smart-9ceead5a-1f84-453a-8767-8dd2e600e0d3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67897633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_
aliasing.67897633
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.1447313430
Short name T1026
Test name
Test status
Simulation time 7193422610 ps
CPU time 36.19 seconds
Started Jul 05 04:29:08 PM PDT 24
Finished Jul 05 04:29:54 PM PDT 24
Peak memory 207508 kb
Host smart-d5a10142-1af8-40fd-acd6-bd5bb18db1ae
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1447313430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.1447313430
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.1306110167
Short name T1124
Test name
Test status
Simulation time 22398240 ps
CPU time 0.94 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 207112 kb
Host smart-6c478894-3988-4ee9-9aa1-6bbe693cd818
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306110167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.1306110167
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2960032728
Short name T1083
Test name
Test status
Simulation time 487246459 ps
CPU time 3.69 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:20 PM PDT 24
Peak memory 218100 kb
Host smart-7387f3ee-50d2-40a3-aa17-fac3ff443b95
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960032728 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2960032728
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.14798088
Short name T113
Test name
Test status
Simulation time 35516202 ps
CPU time 1.22 seconds
Started Jul 05 04:29:02 PM PDT 24
Finished Jul 05 04:29:12 PM PDT 24
Peak memory 215680 kb
Host smart-0196b540-603d-4ab2-be39-b60a0e7a458d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14798088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.14798088
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3190119495
Short name T1082
Test name
Test status
Simulation time 16154844 ps
CPU time 0.72 seconds
Started Jul 05 04:29:04 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 204460 kb
Host smart-6446a524-3c95-4851-9247-1d57af994a0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3190119495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
190119495
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.3121809180
Short name T1085
Test name
Test status
Simulation time 356444199 ps
CPU time 1.34 seconds
Started Jul 05 04:29:20 PM PDT 24
Finished Jul 05 04:29:31 PM PDT 24
Peak memory 215652 kb
Host smart-a19741e6-8b23-44c7-98dc-db65e465972a
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121809180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.3121809180
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.1381461089
Short name T1035
Test name
Test status
Simulation time 87929444 ps
CPU time 0.66 seconds
Started Jul 05 04:29:20 PM PDT 24
Finished Jul 05 04:29:30 PM PDT 24
Peak memory 204316 kb
Host smart-74374061-f084-4ba7-b4dc-ac4d4780e801
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381461089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.1381461089
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2223099428
Short name T1034
Test name
Test status
Simulation time 44416320 ps
CPU time 1.68 seconds
Started Jul 05 04:29:10 PM PDT 24
Finished Jul 05 04:29:21 PM PDT 24
Peak memory 207516 kb
Host smart-34e70588-6748-40a8-b5f5-915d6737509b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223099428 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2223099428
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.2329182495
Short name T1049
Test name
Test status
Simulation time 593261486 ps
CPU time 2.29 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 216828 kb
Host smart-2f2180c3-d86e-4df9-b9fe-be5ebfeb4a69
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329182495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.2
329182495
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2147232826
Short name T168
Test name
Test status
Simulation time 4039345933 ps
CPU time 22.8 seconds
Started Jul 05 04:28:53 PM PDT 24
Finished Jul 05 04:29:25 PM PDT 24
Peak memory 216420 kb
Host smart-e714c973-cc98-4a45-bfe8-288590db92a9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2147232826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2147232826
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.3656189148
Short name T1015
Test name
Test status
Simulation time 29643526 ps
CPU time 0.7 seconds
Started Jul 05 04:29:17 PM PDT 24
Finished Jul 05 04:29:26 PM PDT 24
Peak memory 204156 kb
Host smart-fbb16638-3674-459c-8c98-bb87b8e18984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3656189148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
3656189148
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.385308520
Short name T1109
Test name
Test status
Simulation time 24632543 ps
CPU time 0.74 seconds
Started Jul 05 04:29:22 PM PDT 24
Finished Jul 05 04:29:32 PM PDT 24
Peak memory 204112 kb
Host smart-abcad03c-97f0-4061-aec4-bd6f6f13d1e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385308520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.385308520
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.3006464513
Short name T1058
Test name
Test status
Simulation time 14008217 ps
CPU time 0.69 seconds
Started Jul 05 04:29:17 PM PDT 24
Finished Jul 05 04:29:25 PM PDT 24
Peak memory 204480 kb
Host smart-1fdac78b-7145-4e42-8783-90ebc08d426c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006464513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
3006464513
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.557358885
Short name T1037
Test name
Test status
Simulation time 145021492 ps
CPU time 0.72 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:17 PM PDT 24
Peak memory 204492 kb
Host smart-8c125e6d-d8fd-4f96-870f-22f6b256d83d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557358885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.557358885
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.686308986
Short name T1020
Test name
Test status
Simulation time 23225253 ps
CPU time 0.74 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:29:34 PM PDT 24
Peak memory 204480 kb
Host smart-eb7bd072-8e66-41f9-a7e4-cd9043f6273e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686308986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.686308986
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.1301878937
Short name T1088
Test name
Test status
Simulation time 16536076 ps
CPU time 0.76 seconds
Started Jul 05 04:29:14 PM PDT 24
Finished Jul 05 04:29:23 PM PDT 24
Peak memory 204140 kb
Host smart-3e5b4d1e-91bc-4f13-893f-4b351be95857
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301878937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
1301878937
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.1541691817
Short name T1014
Test name
Test status
Simulation time 27746565 ps
CPU time 0.77 seconds
Started Jul 05 04:29:27 PM PDT 24
Finished Jul 05 04:29:36 PM PDT 24
Peak memory 204436 kb
Host smart-b0f87542-f3ce-4f5a-adf7-8f0aa7e4bb67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541691817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
1541691817
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2825008971
Short name T1017
Test name
Test status
Simulation time 58814114 ps
CPU time 0.77 seconds
Started Jul 05 04:29:48 PM PDT 24
Finished Jul 05 04:29:51 PM PDT 24
Peak memory 204164 kb
Host smart-2a314dc5-af9d-4b8e-97fb-2375a1eabe82
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825008971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2825008971
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.894098446
Short name T1052
Test name
Test status
Simulation time 15434343 ps
CPU time 0.72 seconds
Started Jul 05 04:29:17 PM PDT 24
Finished Jul 05 04:29:26 PM PDT 24
Peak memory 204152 kb
Host smart-02984a70-f678-40b6-9d49-ef53c367e53b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894098446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.894098446
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.1626899091
Short name T1045
Test name
Test status
Simulation time 16646222 ps
CPU time 0.71 seconds
Started Jul 05 04:29:24 PM PDT 24
Finished Jul 05 04:29:33 PM PDT 24
Peak memory 204168 kb
Host smart-c90ac965-81c7-45c9-b087-08f305f21e9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626899091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
1626899091
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.176437792
Short name T63
Test name
Test status
Simulation time 583722112 ps
CPU time 3.53 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:20 PM PDT 24
Peak memory 218588 kb
Host smart-0ab3e18f-372e-4f0c-9a5f-7beeb84f0bdb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176437792 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.176437792
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.357024963
Short name T1089
Test name
Test status
Simulation time 67949676 ps
CPU time 1.26 seconds
Started Jul 05 04:29:10 PM PDT 24
Finished Jul 05 04:29:21 PM PDT 24
Peak memory 215648 kb
Host smart-195dfe8a-b44d-4105-b738-5e08a86495e5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357024963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.357024963
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.382338205
Short name T1025
Test name
Test status
Simulation time 14223585 ps
CPU time 0.72 seconds
Started Jul 05 04:28:59 PM PDT 24
Finished Jul 05 04:29:19 PM PDT 24
Peak memory 204496 kb
Host smart-d4225eeb-158c-47d6-b5ed-ef76ab29ebb2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382338205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.382338205
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.3954028896
Short name T1036
Test name
Test status
Simulation time 1040226282 ps
CPU time 4.12 seconds
Started Jul 05 04:29:00 PM PDT 24
Finished Jul 05 04:29:13 PM PDT 24
Peak memory 215632 kb
Host smart-e23ac48d-5e9e-4e47-ba2e-b5d03f5e4f47
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3954028896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.3954028896
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.2168897488
Short name T1119
Test name
Test status
Simulation time 537611058 ps
CPU time 7.11 seconds
Started Jul 05 04:29:21 PM PDT 24
Finished Jul 05 04:29:38 PM PDT 24
Peak memory 216308 kb
Host smart-74c3995b-6b2e-4c94-b2b2-ae4c22e0fc22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168897488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.2168897488
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.3965179198
Short name T94
Test name
Test status
Simulation time 166739230 ps
CPU time 3.55 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 217508 kb
Host smart-dfea6df6-7b58-41eb-9e79-4916dce237b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965179198 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.3965179198
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4134811542
Short name T1104
Test name
Test status
Simulation time 168641175 ps
CPU time 2.07 seconds
Started Jul 05 04:29:04 PM PDT 24
Finished Jul 05 04:29:15 PM PDT 24
Peak memory 216008 kb
Host smart-f9bdaebb-1776-473c-8fb4-6d7cce279a7a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134811542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
134811542
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.1756242028
Short name T1094
Test name
Test status
Simulation time 16530789 ps
CPU time 0.71 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:16 PM PDT 24
Peak memory 204152 kb
Host smart-cec4a5f5-f5fc-47f4-ac9c-f095ae9fcd58
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756242028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.1
756242028
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.369813768
Short name T131
Test name
Test status
Simulation time 93383726 ps
CPU time 1.72 seconds
Started Jul 05 04:29:17 PM PDT 24
Finished Jul 05 04:29:28 PM PDT 24
Peak memory 207444 kb
Host smart-b79e2b28-de66-471f-8118-1eebc14919f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=369813768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sp
i_device_same_csr_outstanding.369813768
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2380090606
Short name T1071
Test name
Test status
Simulation time 184120453 ps
CPU time 3.04 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:11 PM PDT 24
Peak memory 216900 kb
Host smart-347f1eb1-744b-4700-8894-68ea418cc4ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380090606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
380090606
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.2626044170
Short name T172
Test name
Test status
Simulation time 1572639958 ps
CPU time 7.51 seconds
Started Jul 05 04:29:01 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 215812 kb
Host smart-a6a63d78-edc7-44c1-8572-10ce4b76320a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626044170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.2626044170
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.2537961903
Short name T1095
Test name
Test status
Simulation time 100385586 ps
CPU time 2.68 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 217916 kb
Host smart-8dd94fd7-e59e-4012-af31-91b7aee984f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2537961903 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.2537961903
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.3006605570
Short name T1118
Test name
Test status
Simulation time 45460987 ps
CPU time 1.46 seconds
Started Jul 05 04:29:09 PM PDT 24
Finished Jul 05 04:29:19 PM PDT 24
Peak memory 207424 kb
Host smart-71aff4c4-4839-4477-87fe-5d638aa98a95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006605570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.3
006605570
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.3543383362
Short name T1023
Test name
Test status
Simulation time 217374307 ps
CPU time 0.74 seconds
Started Jul 05 04:29:10 PM PDT 24
Finished Jul 05 04:29:20 PM PDT 24
Peak memory 204172 kb
Host smart-b3a9b45a-3a7e-4d54-b425-79a2f1bfa5b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3543383362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.3
543383362
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.3985889445
Short name T1063
Test name
Test status
Simulation time 92391256 ps
CPU time 1.7 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 207468 kb
Host smart-2794a156-70de-46ad-a228-81a6743e5548
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985889445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.3985889445
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.2935521603
Short name T89
Test name
Test status
Simulation time 205900330 ps
CPU time 4.44 seconds
Started Jul 05 04:29:10 PM PDT 24
Finished Jul 05 04:29:24 PM PDT 24
Peak memory 215796 kb
Host smart-32c78348-feda-4746-a00a-1ba36cd20918
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935521603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.2
935521603
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.2799403311
Short name T1069
Test name
Test status
Simulation time 207615567 ps
CPU time 12.48 seconds
Started Jul 05 04:29:19 PM PDT 24
Finished Jul 05 04:29:41 PM PDT 24
Peak memory 215592 kb
Host smart-468670b3-12af-4423-9c14-e8dae01a2221
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2799403311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.2799403311
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.368616968
Short name T141
Test name
Test status
Simulation time 102834592 ps
CPU time 2.6 seconds
Started Jul 05 04:29:12 PM PDT 24
Finished Jul 05 04:29:24 PM PDT 24
Peak memory 218232 kb
Host smart-1e2fc785-cf93-4d0d-ba75-7c3d3df02cf4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368616968 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.368616968
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.1210798352
Short name T1107
Test name
Test status
Simulation time 41520953 ps
CPU time 1.42 seconds
Started Jul 05 04:29:05 PM PDT 24
Finished Jul 05 04:29:15 PM PDT 24
Peak memory 207364 kb
Host smart-238dd067-8490-4846-a8c0-1770166c0d19
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210798352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.1
210798352
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.39443931
Short name T1073
Test name
Test status
Simulation time 26058117 ps
CPU time 0.76 seconds
Started Jul 05 04:28:56 PM PDT 24
Finished Jul 05 04:29:06 PM PDT 24
Peak memory 204484 kb
Host smart-3e9f0e92-fb91-40b8-8f9e-f6b7cbf13d81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39443931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.39443931
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.3554104922
Short name T132
Test name
Test status
Simulation time 92256256 ps
CPU time 1.64 seconds
Started Jul 05 04:29:09 PM PDT 24
Finished Jul 05 04:29:21 PM PDT 24
Peak memory 215588 kb
Host smart-d87eaf6a-60e3-46f7-812c-21178d2ac458
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554104922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.3554104922
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3764862273
Short name T90
Test name
Test status
Simulation time 299693682 ps
CPU time 1.94 seconds
Started Jul 05 04:29:16 PM PDT 24
Finished Jul 05 04:29:27 PM PDT 24
Peak memory 215864 kb
Host smart-4382dc84-ea7e-4df5-a2e1-40f22175f293
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764862273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
764862273
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2332407854
Short name T87
Test name
Test status
Simulation time 1479652909 ps
CPU time 7.78 seconds
Started Jul 05 04:29:01 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 215920 kb
Host smart-4fd8d55c-aa5c-48ea-ab0e-bb249f47d959
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2332407854 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2332407854
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.4195192684
Short name T1050
Test name
Test status
Simulation time 214180378 ps
CPU time 1.77 seconds
Started Jul 05 04:28:58 PM PDT 24
Finished Jul 05 04:29:09 PM PDT 24
Peak memory 216748 kb
Host smart-9c407da8-191d-48e8-ad34-dacbdd4177ac
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195192684 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.4195192684
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.607923888
Short name T1105
Test name
Test status
Simulation time 109809913 ps
CPU time 2.6 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 215624 kb
Host smart-9fef3847-b7f5-44fb-b19b-e59a8c7aee03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607923888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.607923888
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.1339175638
Short name T1018
Test name
Test status
Simulation time 17956825 ps
CPU time 0.76 seconds
Started Jul 05 04:29:06 PM PDT 24
Finished Jul 05 04:29:16 PM PDT 24
Peak memory 204508 kb
Host smart-4d8e4b34-b6f2-4927-b577-67af0c2a183c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339175638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.1
339175638
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.3819266988
Short name T1122
Test name
Test status
Simulation time 110842108 ps
CPU time 3.01 seconds
Started Jul 05 04:29:12 PM PDT 24
Finished Jul 05 04:29:24 PM PDT 24
Peak memory 215672 kb
Host smart-c591b14e-742f-46c7-b7ba-fa71bc71b71b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3819266988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.3819266988
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.151872480
Short name T1116
Test name
Test status
Simulation time 108305008 ps
CPU time 1.65 seconds
Started Jul 05 04:29:07 PM PDT 24
Finished Jul 05 04:29:18 PM PDT 24
Peak memory 215772 kb
Host smart-5ddead8b-8382-48ca-a466-faa3d86d90ab
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151872480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.151872480
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.2285054422
Short name T1086
Test name
Test status
Simulation time 1096201548 ps
CPU time 13.61 seconds
Started Jul 05 04:29:08 PM PDT 24
Finished Jul 05 04:29:31 PM PDT 24
Peak memory 215780 kb
Host smart-a2993513-5cf2-46e9-96db-da8d6c4f3bb2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285054422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.2285054422
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3384783860
Short name T662
Test name
Test status
Simulation time 18860890 ps
CPU time 0.78 seconds
Started Jul 05 06:07:18 PM PDT 24
Finished Jul 05 06:07:19 PM PDT 24
Peak memory 204940 kb
Host smart-325b19d0-c7e2-4740-9fda-790e2791b133
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384783860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
384783860
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.1083756586
Short name T681
Test name
Test status
Simulation time 100425481 ps
CPU time 4.16 seconds
Started Jul 05 06:07:12 PM PDT 24
Finished Jul 05 06:07:17 PM PDT 24
Peak memory 232632 kb
Host smart-16e2208a-3764-4f11-b3ef-10ad65c070b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083756586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.1083756586
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.408722911
Short name T337
Test name
Test status
Simulation time 26757206 ps
CPU time 0.74 seconds
Started Jul 05 06:07:08 PM PDT 24
Finished Jul 05 06:07:09 PM PDT 24
Peak memory 206604 kb
Host smart-b93fe161-c0d8-4c94-bdea-7e461136f516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408722911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.408722911
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.1823149864
Short name T199
Test name
Test status
Simulation time 33158589266 ps
CPU time 224.93 seconds
Started Jul 05 06:07:21 PM PDT 24
Finished Jul 05 06:11:06 PM PDT 24
Peak memory 249368 kb
Host smart-1cff8e92-64f5-4758-a7fc-9ef4aabac024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823149864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.1823149864
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.924393791
Short name T200
Test name
Test status
Simulation time 74022920763 ps
CPU time 109.45 seconds
Started Jul 05 06:07:19 PM PDT 24
Finished Jul 05 06:09:09 PM PDT 24
Peak memory 265848 kb
Host smart-95e84244-fb9c-4efe-98d8-14a502512394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924393791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.924393791
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.1014649751
Short name T974
Test name
Test status
Simulation time 1839838767 ps
CPU time 28.15 seconds
Started Jul 05 06:07:13 PM PDT 24
Finished Jul 05 06:07:41 PM PDT 24
Peak memory 249076 kb
Host smart-638dbc10-ebfd-4d38-805c-7ae141f524b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014649751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.1014649751
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.3485400772
Short name T231
Test name
Test status
Simulation time 73563189141 ps
CPU time 170.13 seconds
Started Jul 05 06:07:16 PM PDT 24
Finished Jul 05 06:10:07 PM PDT 24
Peak memory 266056 kb
Host smart-942e8c12-d126-4abf-9252-58700d17c453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485400772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds
.3485400772
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.2751412121
Short name T516
Test name
Test status
Simulation time 13016065089 ps
CPU time 27.08 seconds
Started Jul 05 06:07:09 PM PDT 24
Finished Jul 05 06:07:36 PM PDT 24
Peak memory 232780 kb
Host smart-49bd069f-2c3e-497d-9c7f-20ef64f83083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751412121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.2751412121
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.198446827
Short name T657
Test name
Test status
Simulation time 5714286098 ps
CPU time 26.74 seconds
Started Jul 05 06:07:14 PM PDT 24
Finished Jul 05 06:07:41 PM PDT 24
Peak memory 233828 kb
Host smart-0e489dad-c8ba-4a54-a013-7e223ec08935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=198446827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.198446827
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3543497441
Short name T774
Test name
Test status
Simulation time 1486814565 ps
CPU time 4.76 seconds
Started Jul 05 06:07:14 PM PDT 24
Finished Jul 05 06:07:19 PM PDT 24
Peak memory 240908 kb
Host smart-b23272eb-2154-4eef-80a8-653a41f3c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543497441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3543497441
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.3981318760
Short name T590
Test name
Test status
Simulation time 432047549 ps
CPU time 4.06 seconds
Started Jul 05 06:07:14 PM PDT 24
Finished Jul 05 06:07:19 PM PDT 24
Peak memory 220448 kb
Host smart-bd342c71-6c5e-4ce3-8ae7-5512751d1c3a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3981318760 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.3981318760
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.1539387899
Short name T67
Test name
Test status
Simulation time 165803240 ps
CPU time 1.06 seconds
Started Jul 05 06:07:17 PM PDT 24
Finished Jul 05 06:07:18 PM PDT 24
Peak memory 236524 kb
Host smart-27a15a04-cf0f-4c0c-9f1f-a181403c1989
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539387899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.1539387899
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.3938785229
Short name T862
Test name
Test status
Simulation time 2060746044 ps
CPU time 40.66 seconds
Started Jul 05 06:07:16 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 249168 kb
Host smart-f3800442-16b7-438d-80dd-4750325ea58c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3938785229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.3938785229
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.4087063247
Short name T972
Test name
Test status
Simulation time 36645935741 ps
CPU time 22.65 seconds
Started Jul 05 06:07:12 PM PDT 24
Finished Jul 05 06:07:35 PM PDT 24
Peak memory 220044 kb
Host smart-0ddf818a-c2f9-4256-91f3-e7babae5c255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4087063247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.4087063247
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.1922874837
Short name T932
Test name
Test status
Simulation time 26717682930 ps
CPU time 9.16 seconds
Started Jul 05 06:07:09 PM PDT 24
Finished Jul 05 06:07:18 PM PDT 24
Peak memory 216400 kb
Host smart-269eeb15-b927-4052-83dc-ffd0d539c710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922874837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.1922874837
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.539034067
Short name T877
Test name
Test status
Simulation time 2005066729 ps
CPU time 3.21 seconds
Started Jul 05 06:07:11 PM PDT 24
Finished Jul 05 06:07:15 PM PDT 24
Peak memory 216264 kb
Host smart-7ac58257-8f28-4095-9602-45cfdae0c9b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539034067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.539034067
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.781358525
Short name T724
Test name
Test status
Simulation time 478205199 ps
CPU time 0.8 seconds
Started Jul 05 06:07:08 PM PDT 24
Finished Jul 05 06:07:09 PM PDT 24
Peak memory 205924 kb
Host smart-f84ec705-55d8-43b2-b3c7-116d664e3477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781358525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.781358525
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.3880299853
Short name T424
Test name
Test status
Simulation time 1404149459 ps
CPU time 6.35 seconds
Started Jul 05 06:07:16 PM PDT 24
Finished Jul 05 06:07:23 PM PDT 24
Peak memory 224476 kb
Host smart-e4dbef90-4df2-4df8-89f9-c401b17bc32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880299853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.3880299853
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.3922077820
Short name T818
Test name
Test status
Simulation time 11725889 ps
CPU time 0.72 seconds
Started Jul 05 06:07:25 PM PDT 24
Finished Jul 05 06:07:26 PM PDT 24
Peak memory 205852 kb
Host smart-3d18e127-71c4-4034-9ae2-01d1a28da1da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922077820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.3
922077820
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.2050319848
Short name T223
Test name
Test status
Simulation time 340004768 ps
CPU time 5.02 seconds
Started Jul 05 06:07:22 PM PDT 24
Finished Jul 05 06:07:28 PM PDT 24
Peak memory 232684 kb
Host smart-f0a33136-8bae-4daf-9301-72d26c8b6588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2050319848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.2050319848
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4092785426
Short name T909
Test name
Test status
Simulation time 18747915 ps
CPU time 0.78 seconds
Started Jul 05 06:07:12 PM PDT 24
Finished Jul 05 06:07:14 PM PDT 24
Peak memory 206624 kb
Host smart-68fc047b-195c-400d-b05b-8e42adf71c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092785426 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4092785426
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1220287872
Short name T713
Test name
Test status
Simulation time 43377217061 ps
CPU time 57.03 seconds
Started Jul 05 06:07:28 PM PDT 24
Finished Jul 05 06:08:26 PM PDT 24
Peak memory 249236 kb
Host smart-a0bc0d38-b017-48ee-a547-5ac8d37994f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220287872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1220287872
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.3504315496
Short name T690
Test name
Test status
Simulation time 2323817400 ps
CPU time 15.79 seconds
Started Jul 05 06:07:25 PM PDT 24
Finished Jul 05 06:07:42 PM PDT 24
Peak memory 221856 kb
Host smart-db855d73-1b55-403d-9ab5-cde09161f6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504315496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle
.3504315496
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.1783295650
Short name T272
Test name
Test status
Simulation time 6937263178 ps
CPU time 7.58 seconds
Started Jul 05 06:07:17 PM PDT 24
Finished Jul 05 06:07:25 PM PDT 24
Peak memory 224616 kb
Host smart-467839c5-a375-4fde-ba27-f61827dc0e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783295650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.1783295650
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_intercept.3857277715
Short name T749
Test name
Test status
Simulation time 3339158363 ps
CPU time 13.68 seconds
Started Jul 05 06:07:17 PM PDT 24
Finished Jul 05 06:07:31 PM PDT 24
Peak memory 224580 kb
Host smart-5f24ffaf-d77f-46c0-9d7d-d12bbec801e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857277715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.3857277715
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.349133256
Short name T157
Test name
Test status
Simulation time 1503684761 ps
CPU time 3.67 seconds
Started Jul 05 06:07:17 PM PDT 24
Finished Jul 05 06:07:21 PM PDT 24
Peak memory 224444 kb
Host smart-0b943f73-b9c7-4ef3-94ec-c7771779c142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349133256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.349133256
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2589426444
Short name T491
Test name
Test status
Simulation time 654757051 ps
CPU time 3.24 seconds
Started Jul 05 06:07:23 PM PDT 24
Finished Jul 05 06:07:26 PM PDT 24
Peak memory 232628 kb
Host smart-a658864d-cd53-42d5-9409-8ca1affad404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589426444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2589426444
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4180912872
Short name T198
Test name
Test status
Simulation time 5067417001 ps
CPU time 12.25 seconds
Started Jul 05 06:07:15 PM PDT 24
Finished Jul 05 06:07:28 PM PDT 24
Peak memory 232784 kb
Host smart-2f16e3f5-f5f2-456a-8799-92ed2a324e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4180912872 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4180912872
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.3905032228
Short name T381
Test name
Test status
Simulation time 1155214493 ps
CPU time 9.64 seconds
Started Jul 05 06:07:27 PM PDT 24
Finished Jul 05 06:07:37 PM PDT 24
Peak memory 219280 kb
Host smart-cc5a73d3-d546-406b-bb1e-62f1299ca3ba
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3905032228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_dire
ct.3905032228
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1882392951
Short name T69
Test name
Test status
Simulation time 358967830 ps
CPU time 1.15 seconds
Started Jul 05 06:07:24 PM PDT 24
Finished Jul 05 06:07:25 PM PDT 24
Peak memory 236132 kb
Host smart-81107ff8-33a9-4091-b815-4126d3d301ed
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882392951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1882392951
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.583036111
Short name T893
Test name
Test status
Simulation time 7667495411 ps
CPU time 115.77 seconds
Started Jul 05 06:07:36 PM PDT 24
Finished Jul 05 06:09:32 PM PDT 24
Peak memory 253480 kb
Host smart-cd3d6eb1-026e-4706-8a3f-9357e775e4b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=583036111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.583036111
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.391516345
Short name T902
Test name
Test status
Simulation time 6213361913 ps
CPU time 38.63 seconds
Started Jul 05 06:07:16 PM PDT 24
Finished Jul 05 06:07:55 PM PDT 24
Peak memory 216416 kb
Host smart-9e50ed1a-bf7e-407e-a378-01b808a661f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391516345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.391516345
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1219903416
Short name T941
Test name
Test status
Simulation time 43753950 ps
CPU time 0.93 seconds
Started Jul 05 06:07:16 PM PDT 24
Finished Jul 05 06:07:17 PM PDT 24
Peak memory 206044 kb
Host smart-458ff1fa-ca8c-49c1-8f4c-7ca7b2bc9870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219903416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1219903416
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3354537422
Short name T434
Test name
Test status
Simulation time 835745090 ps
CPU time 12.26 seconds
Started Jul 05 06:19:39 PM PDT 24
Finished Jul 05 06:19:52 PM PDT 24
Peak memory 216188 kb
Host smart-ea1aeeac-721a-4eb9-a6af-53e84ced97bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354537422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3354537422
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3770105303
Short name T460
Test name
Test status
Simulation time 53681976 ps
CPU time 0.73 seconds
Started Jul 05 06:07:13 PM PDT 24
Finished Jul 05 06:07:14 PM PDT 24
Peak memory 206016 kb
Host smart-f7707cc2-7c81-44dd-a832-33a3717eb96b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770105303 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3770105303
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.1247963988
Short name T993
Test name
Test status
Simulation time 3698682765 ps
CPU time 13.38 seconds
Started Jul 05 06:07:18 PM PDT 24
Finished Jul 05 06:07:31 PM PDT 24
Peak memory 232740 kb
Host smart-10724c5c-de21-4b89-a593-c099d6c0ddce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247963988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.1247963988
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.1756738697
Short name T547
Test name
Test status
Simulation time 12285114 ps
CPU time 0.75 seconds
Started Jul 05 06:08:00 PM PDT 24
Finished Jul 05 06:08:02 PM PDT 24
Peak memory 204940 kb
Host smart-a653ec7d-5b91-476c-847f-b2ee9299c403
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1756738697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
1756738697
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1585329436
Short name T452
Test name
Test status
Simulation time 7679920016 ps
CPU time 34.7 seconds
Started Jul 05 06:07:51 PM PDT 24
Finished Jul 05 06:08:26 PM PDT 24
Peak memory 232716 kb
Host smart-de20d1a4-446b-43c9-8477-f1d12eecbded
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1585329436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1585329436
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2029771477
Short name T542
Test name
Test status
Simulation time 19617114 ps
CPU time 0.79 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 206632 kb
Host smart-264abe65-27fb-469f-a2d0-16cda84b9909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029771477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2029771477
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2289659399
Short name T661
Test name
Test status
Simulation time 33416192662 ps
CPU time 221.42 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:11:37 PM PDT 24
Peak memory 249408 kb
Host smart-ff3d6419-625e-4a95-aba4-e349f57ef088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289659399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2289659399
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.879639328
Short name T824
Test name
Test status
Simulation time 98473265220 ps
CPU time 242.25 seconds
Started Jul 05 06:07:53 PM PDT 24
Finished Jul 05 06:11:57 PM PDT 24
Peak memory 250232 kb
Host smart-d48e6d2d-62dd-4239-b86d-8e646cc511b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879639328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.879639328
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.699391309
Short name T495
Test name
Test status
Simulation time 6552923252 ps
CPU time 55.69 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:56 PM PDT 24
Peak memory 241032 kb
Host smart-c36497d9-8a67-4b97-b366-cbd02a767deb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699391309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idle
.699391309
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.874823757
Short name T962
Test name
Test status
Simulation time 87177987 ps
CPU time 5.67 seconds
Started Jul 05 06:07:49 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 224444 kb
Host smart-24e0bfad-1dd7-4968-9999-a0690ead8703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874823757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.874823757
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.771620332
Short name T558
Test name
Test status
Simulation time 2385301464 ps
CPU time 13.93 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:08:09 PM PDT 24
Peak memory 248148 kb
Host smart-f33f5655-9c8f-4afa-9013-9d590b18ead5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771620332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmds
.771620332
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.929083552
Short name T526
Test name
Test status
Simulation time 31036186 ps
CPU time 2.29 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:02 PM PDT 24
Peak memory 232724 kb
Host smart-b9ef7d00-c983-4287-b23e-421cd5252461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929083552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.929083552
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.1352145034
Short name T856
Test name
Test status
Simulation time 2832772042 ps
CPU time 8.75 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:08 PM PDT 24
Peak memory 239632 kb
Host smart-a1769db2-3ae5-4bb4-85ac-ebb549ded96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352145034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.1352145034
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.1619351367
Short name T470
Test name
Test status
Simulation time 33498159 ps
CPU time 2.61 seconds
Started Jul 05 06:07:50 PM PDT 24
Finished Jul 05 06:07:53 PM PDT 24
Peak memory 232392 kb
Host smart-6f6bfc0f-27aa-46e1-bf3c-dd7938f6ef55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619351367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.1619351367
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.2276172469
Short name T579
Test name
Test status
Simulation time 4079078577 ps
CPU time 12.97 seconds
Started Jul 05 06:07:53 PM PDT 24
Finished Jul 05 06:08:07 PM PDT 24
Peak memory 232764 kb
Host smart-29090338-10fc-4094-ad5c-e06472195f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276172469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.2276172469
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.436512048
Short name T438
Test name
Test status
Simulation time 700988494 ps
CPU time 4.47 seconds
Started Jul 05 06:07:59 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 222684 kb
Host smart-e9848716-56a5-43a9-9530-054ed82dd98c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=436512048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dire
ct.436512048
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.3843617050
Short name T658
Test name
Test status
Simulation time 9757478220 ps
CPU time 53.78 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:08:49 PM PDT 24
Peak memory 256632 kb
Host smart-8ae3d96d-d172-4d80-9d22-065d05742f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843617050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.3843617050
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.2035386920
Short name T403
Test name
Test status
Simulation time 7157940935 ps
CPU time 19.24 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:08:11 PM PDT 24
Peak memory 216316 kb
Host smart-2790bee8-c60d-49e8-a8c7-d031090472ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035386920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.2035386920
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.1116802058
Short name T956
Test name
Test status
Simulation time 657900930 ps
CPU time 2.91 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 216076 kb
Host smart-ff941645-d73c-43eb-88c3-395c537503b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116802058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.1116802058
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.1099058589
Short name T380
Test name
Test status
Simulation time 235456813 ps
CPU time 0.86 seconds
Started Jul 05 06:07:55 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 205976 kb
Host smart-ed72d7b5-dab0-4822-8050-30e54a497695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099058589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.1099058589
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2381078030
Short name T755
Test name
Test status
Simulation time 84841165 ps
CPU time 0.88 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:07:53 PM PDT 24
Peak memory 205980 kb
Host smart-fd87850b-fbe4-4cdc-81ba-b38a5caeee5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2381078030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2381078030
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.2754596169
Short name T685
Test name
Test status
Simulation time 43999270 ps
CPU time 2.54 seconds
Started Jul 05 06:07:57 PM PDT 24
Finished Jul 05 06:08:01 PM PDT 24
Peak memory 232328 kb
Host smart-5a1d1e07-bfcb-4e6e-99a6-1a7c6424de2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754596169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.2754596169
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3614237228
Short name T220
Test name
Test status
Simulation time 81949436 ps
CPU time 2.95 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:02 PM PDT 24
Peak memory 232652 kb
Host smart-7fd320de-f3e7-4dfa-a8b6-1b0703d96520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614237228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3614237228
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3046927931
Short name T808
Test name
Test status
Simulation time 16334961 ps
CPU time 0.76 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:01 PM PDT 24
Peak memory 205584 kb
Host smart-ec7a0d03-bbc4-49a1-8947-a410f16bb656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046927931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3046927931
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3999353473
Short name T60
Test name
Test status
Simulation time 9519740629 ps
CPU time 96.6 seconds
Started Jul 05 06:07:59 PM PDT 24
Finished Jul 05 06:09:37 PM PDT 24
Peak memory 249192 kb
Host smart-9d2538ed-c701-43af-81f1-b36827069b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999353473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3999353473
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.1665369376
Short name T933
Test name
Test status
Simulation time 6669523976 ps
CPU time 17.24 seconds
Started Jul 05 06:07:59 PM PDT 24
Finished Jul 05 06:08:18 PM PDT 24
Peak memory 224480 kb
Host smart-0f90efe0-3326-4e24-97e9-4e662af53761
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665369376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.1665369376
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1906757103
Short name T743
Test name
Test status
Simulation time 41017058639 ps
CPU time 32.62 seconds
Started Jul 05 06:08:03 PM PDT 24
Finished Jul 05 06:08:36 PM PDT 24
Peak memory 232828 kb
Host smart-37487679-4e16-4cd9-a082-5e98b67ee4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1906757103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1906757103
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3677609542
Short name T273
Test name
Test status
Simulation time 126497045 ps
CPU time 4.5 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:04 PM PDT 24
Peak memory 236560 kb
Host smart-4a61fde8-bcac-4a0e-86c9-1df2f2c8655c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677609542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3677609542
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3861791162
Short name T860
Test name
Test status
Simulation time 19308301618 ps
CPU time 113.58 seconds
Started Jul 05 06:08:00 PM PDT 24
Finished Jul 05 06:09:55 PM PDT 24
Peak memory 257784 kb
Host smart-fd59e991-9b57-4eea-831c-307c6dece384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861791162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3861791162
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.954010482
Short name T847
Test name
Test status
Simulation time 5115667542 ps
CPU time 12.22 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:15 PM PDT 24
Peak memory 232780 kb
Host smart-476eacb2-a31f-491d-8efb-e42c35210dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954010482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.954010482
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.791053965
Short name T786
Test name
Test status
Simulation time 3675324349 ps
CPU time 17.47 seconds
Started Jul 05 06:08:00 PM PDT 24
Finished Jul 05 06:08:19 PM PDT 24
Peak memory 224588 kb
Host smart-face9d87-387d-4a22-8c17-4904b3c901e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791053965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.791053965
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1964464518
Short name T263
Test name
Test status
Simulation time 32729919377 ps
CPU time 31.02 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:33 PM PDT 24
Peak memory 240368 kb
Host smart-9d72f700-fa36-4905-a37a-b1ee2c73b5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964464518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1964464518
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3664004439
Short name T745
Test name
Test status
Simulation time 2318820099 ps
CPU time 6.87 seconds
Started Jul 05 06:07:57 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 232700 kb
Host smart-1251b296-cdbb-4f31-8feb-c9bf85b4ea1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664004439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3664004439
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3392166999
Short name T761
Test name
Test status
Simulation time 294669881 ps
CPU time 3.37 seconds
Started Jul 05 06:08:00 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 220216 kb
Host smart-9e29b5bb-e38f-4a85-a36b-07f821b597ef
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3392166999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3392166999
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.1516078257
Short name T182
Test name
Test status
Simulation time 10315296258 ps
CPU time 120.9 seconds
Started Jul 05 06:08:06 PM PDT 24
Finished Jul 05 06:10:07 PM PDT 24
Peak memory 268868 kb
Host smart-10c28ab6-e508-4b61-b222-bec47d72ed48
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516078257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.1516078257
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1075352764
Short name T279
Test name
Test status
Simulation time 27818185466 ps
CPU time 35.5 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:37 PM PDT 24
Peak memory 216336 kb
Host smart-6a3122c4-6f3a-491a-b178-bb6666b5cbd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075352764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1075352764
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.360765148
Short name T483
Test name
Test status
Simulation time 3413747382 ps
CPU time 12.79 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:12 PM PDT 24
Peak memory 216336 kb
Host smart-a6ab14a4-1dc8-4a7b-a9fe-9a9a18fecd66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360765148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.360765148
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.2904403507
Short name T377
Test name
Test status
Simulation time 35752200 ps
CPU time 0.8 seconds
Started Jul 05 06:07:55 PM PDT 24
Finished Jul 05 06:07:58 PM PDT 24
Peak memory 205988 kb
Host smart-b62e9ca2-17b3-4377-b101-a126c4acd409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904403507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.2904403507
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1801263518
Short name T357
Test name
Test status
Simulation time 349399843 ps
CPU time 0.93 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:03 PM PDT 24
Peak memory 207024 kb
Host smart-97aa3dfb-f339-4b21-a683-af8ed976052c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801263518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1801263518
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.169699519
Short name T379
Test name
Test status
Simulation time 6893241961 ps
CPU time 11.41 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:11 PM PDT 24
Peak memory 224496 kb
Host smart-8edea5d6-dd38-4be1-b9b7-bf52d87e3c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169699519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.169699519
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.507701282
Short name T553
Test name
Test status
Simulation time 55082167 ps
CPU time 0.73 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:08:39 PM PDT 24
Peak memory 205852 kb
Host smart-62241b85-38e0-4fb6-ae67-37fde2c9d4c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507701282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.507701282
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.177785685
Short name T475
Test name
Test status
Simulation time 3931939448 ps
CPU time 8.62 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:11 PM PDT 24
Peak memory 224572 kb
Host smart-77e739ba-cd10-4d4b-b0a3-03ac1ab60131
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=177785685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.177785685
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.2980074689
Short name T335
Test name
Test status
Simulation time 76253516 ps
CPU time 0.79 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:03 PM PDT 24
Peak memory 206632 kb
Host smart-1c1538b8-4b3d-4b8a-bd94-d6394381409e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2980074689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.2980074689
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.1092483633
Short name T370
Test name
Test status
Simulation time 19685902 ps
CPU time 0.77 seconds
Started Jul 05 06:07:57 PM PDT 24
Finished Jul 05 06:07:59 PM PDT 24
Peak memory 215776 kb
Host smart-c179c765-1610-4dbe-b797-c0af83e849d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092483633 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.1092483633
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.158298788
Short name T926
Test name
Test status
Simulation time 24819830245 ps
CPU time 48.17 seconds
Started Jul 05 06:08:07 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 256616 kb
Host smart-df98afb9-ae97-4414-b01d-d2d4961fcf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158298788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idle
.158298788
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3230630028
Short name T997
Test name
Test status
Simulation time 98757098 ps
CPU time 3.82 seconds
Started Jul 05 06:08:06 PM PDT 24
Finished Jul 05 06:08:10 PM PDT 24
Peak memory 224444 kb
Host smart-a6b774f8-5fe4-4e10-ac98-26104fa0dabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230630028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3230630028
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_intercept.4039813077
Short name T679
Test name
Test status
Simulation time 4270841286 ps
CPU time 23.14 seconds
Started Jul 05 06:08:02 PM PDT 24
Finished Jul 05 06:08:26 PM PDT 24
Peak memory 229020 kb
Host smart-1f154ff7-431e-4cb8-979f-18fcbb963ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039813077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.4039813077
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.935861531
Short name T426
Test name
Test status
Simulation time 3286259547 ps
CPU time 24.09 seconds
Started Jul 05 06:07:56 PM PDT 24
Finished Jul 05 06:08:22 PM PDT 24
Peak memory 234516 kb
Host smart-925efe2a-772d-41fa-9f52-82f039d53e45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935861531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.935861531
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.971351244
Short name T710
Test name
Test status
Simulation time 927725502 ps
CPU time 8.51 seconds
Started Jul 05 06:07:59 PM PDT 24
Finished Jul 05 06:08:09 PM PDT 24
Peak memory 224476 kb
Host smart-6a869d9b-49e6-4ac5-b45e-f2968b174376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971351244 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swap
.971351244
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.4163852688
Short name T432
Test name
Test status
Simulation time 30240517 ps
CPU time 2.61 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 232384 kb
Host smart-f2f916c4-3c65-4f1c-b1e1-a48113b8cfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163852688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.4163852688
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.1703754474
Short name T204
Test name
Test status
Simulation time 40082405635 ps
CPU time 479.68 seconds
Started Jul 05 06:08:05 PM PDT 24
Finished Jul 05 06:16:05 PM PDT 24
Peak memory 282056 kb
Host smart-6b04deae-5915-4673-96be-e33e0483b12f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703754474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.1703754474
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2676594501
Short name T900
Test name
Test status
Simulation time 767406671 ps
CPU time 3.96 seconds
Started Jul 05 06:07:59 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 216364 kb
Host smart-7a92ef89-4253-46df-9f4a-66c08317c490
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2676594501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2676594501
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.531282230
Short name T310
Test name
Test status
Simulation time 1247062402 ps
CPU time 4.12 seconds
Started Jul 05 06:08:03 PM PDT 24
Finished Jul 05 06:08:08 PM PDT 24
Peak memory 216188 kb
Host smart-cb6c27bd-e34a-4b25-b0fa-0853d52de7e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531282230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.531282230
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.645661817
Short name T525
Test name
Test status
Simulation time 38041010 ps
CPU time 0.94 seconds
Started Jul 05 06:08:02 PM PDT 24
Finished Jul 05 06:08:04 PM PDT 24
Peak memory 207768 kb
Host smart-d5c656cf-719d-4cf5-906b-6dfab95c96a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645661817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.645661817
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2972544705
Short name T977
Test name
Test status
Simulation time 38488092 ps
CPU time 0.77 seconds
Started Jul 05 06:08:04 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 205940 kb
Host smart-a9c19424-de79-4ffd-9b6d-af49c48b69a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972544705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2972544705
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.283052747
Short name T716
Test name
Test status
Simulation time 508930435 ps
CPU time 6.92 seconds
Started Jul 05 06:08:06 PM PDT 24
Finished Jul 05 06:08:13 PM PDT 24
Peak memory 232660 kb
Host smart-25bc5617-6712-4c1d-8767-75e70ae6b923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=283052747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.283052747
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.1408138999
Short name T387
Test name
Test status
Simulation time 13934431 ps
CPU time 0.7 seconds
Started Jul 05 06:08:07 PM PDT 24
Finished Jul 05 06:08:08 PM PDT 24
Peak memory 205540 kb
Host smart-5d8d0aaa-004c-43a9-9ee5-4a180d931046
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408138999 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
1408138999
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2119394830
Short name T783
Test name
Test status
Simulation time 408298870 ps
CPU time 6.69 seconds
Started Jul 05 06:08:07 PM PDT 24
Finished Jul 05 06:08:14 PM PDT 24
Peak memory 224504 kb
Host smart-8bf90c48-638a-4e64-8578-b97591fa721f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119394830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2119394830
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.2927259630
Short name T326
Test name
Test status
Simulation time 286166734 ps
CPU time 0.79 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:00 PM PDT 24
Peak memory 206584 kb
Host smart-1c757787-ce33-4841-a580-dee37e5ccc13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927259630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.2927259630
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.1446777656
Short name T245
Test name
Test status
Simulation time 6299580212 ps
CPU time 24.98 seconds
Started Jul 05 06:08:09 PM PDT 24
Finished Jul 05 06:08:34 PM PDT 24
Peak memory 249224 kb
Host smart-0b819fd5-bb17-445d-8293-efcc77868b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1446777656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.1446777656
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.2836875162
Short name T780
Test name
Test status
Simulation time 27618197085 ps
CPU time 70.45 seconds
Started Jul 05 06:08:13 PM PDT 24
Finished Jul 05 06:09:24 PM PDT 24
Peak memory 232904 kb
Host smart-c11c4c4e-5ca7-4150-a4ec-f4b9076fdb3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836875162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.2836875162
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3511433892
Short name T74
Test name
Test status
Simulation time 13885360517 ps
CPU time 43.37 seconds
Started Jul 05 06:08:33 PM PDT 24
Finished Jul 05 06:09:17 PM PDT 24
Peak memory 240684 kb
Host smart-83fac7c6-8778-444e-b0dd-b7d2b8ad511b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511433892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3511433892
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.2029346376
Short name T270
Test name
Test status
Simulation time 2673311296 ps
CPU time 32.52 seconds
Started Jul 05 06:08:06 PM PDT 24
Finished Jul 05 06:08:39 PM PDT 24
Peak memory 239584 kb
Host smart-cfd000c4-434e-4eaf-b925-36e00ae876c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029346376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.2029346376
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.2311924935
Short name T233
Test name
Test status
Simulation time 25289838765 ps
CPU time 155.18 seconds
Started Jul 05 06:08:07 PM PDT 24
Finished Jul 05 06:10:42 PM PDT 24
Peak memory 249216 kb
Host smart-a8c16e6d-d21c-4036-9300-b3adbca1902a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311924935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.2311924935
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.3116730103
Short name T456
Test name
Test status
Simulation time 4472200835 ps
CPU time 24.53 seconds
Started Jul 05 06:07:59 PM PDT 24
Finished Jul 05 06:08:25 PM PDT 24
Peak memory 236532 kb
Host smart-b2067caf-37ad-4d62-a0e5-a870850abaee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116730103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.3116730103
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.2556355157
Short name T247
Test name
Test status
Simulation time 5940605562 ps
CPU time 22.3 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:25 PM PDT 24
Peak memory 241004 kb
Host smart-a389e9dd-729e-4738-a3dd-c498a358b287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556355157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.2556355157
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2693663461
Short name T81
Test name
Test status
Simulation time 2717281628 ps
CPU time 14.35 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:14 PM PDT 24
Peak memory 224652 kb
Host smart-a8ef0937-c7d3-4d1c-bfac-da8a0e3adca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693663461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2693663461
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.119846210
Short name T40
Test name
Test status
Simulation time 90238319 ps
CPU time 3.27 seconds
Started Jul 05 06:08:06 PM PDT 24
Finished Jul 05 06:08:10 PM PDT 24
Peak memory 222788 kb
Host smart-f5d96392-0bbd-47e6-8550-8395813d79b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=119846210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dire
ct.119846210
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.3382440097
Short name T416
Test name
Test status
Simulation time 56331298 ps
CPU time 1.05 seconds
Started Jul 05 06:08:13 PM PDT 24
Finished Jul 05 06:08:14 PM PDT 24
Peak memory 207144 kb
Host smart-639531a7-8a9a-4f40-9a78-528bbe6e21cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382440097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.3382440097
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1352698457
Short name T567
Test name
Test status
Simulation time 1323665195 ps
CPU time 9.59 seconds
Started Jul 05 06:07:57 PM PDT 24
Finished Jul 05 06:08:08 PM PDT 24
Peak memory 216580 kb
Host smart-edc62a0a-d9f7-4105-b046-1bf4a84fa926
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352698457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1352698457
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1755324251
Short name T307
Test name
Test status
Simulation time 5341649465 ps
CPU time 8.47 seconds
Started Jul 05 06:08:06 PM PDT 24
Finished Jul 05 06:08:15 PM PDT 24
Peak memory 216320 kb
Host smart-de593509-12a4-4285-a7ca-c5beb7a1923e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755324251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1755324251
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1504642541
Short name T881
Test name
Test status
Simulation time 223143779 ps
CPU time 1.21 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:03 PM PDT 24
Peak memory 208052 kb
Host smart-c9c7ca43-4ba5-4a8b-9021-8ba1663456f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504642541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1504642541
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1276240186
Short name T996
Test name
Test status
Simulation time 83743809 ps
CPU time 0.83 seconds
Started Jul 05 06:08:00 PM PDT 24
Finished Jul 05 06:08:02 PM PDT 24
Peak memory 205972 kb
Host smart-9ca6d38a-71e9-4366-822f-46d8377cc58a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276240186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1276240186
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.173150450
Short name T398
Test name
Test status
Simulation time 1804121243 ps
CPU time 2.34 seconds
Started Jul 05 06:08:01 PM PDT 24
Finished Jul 05 06:08:04 PM PDT 24
Peak memory 224408 kb
Host smart-00a761fb-fbec-4af2-9c01-8241c90f57d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173150450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.173150450
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2925127534
Short name T683
Test name
Test status
Simulation time 13679005 ps
CPU time 0.71 seconds
Started Jul 05 06:08:15 PM PDT 24
Finished Jul 05 06:08:16 PM PDT 24
Peak memory 205456 kb
Host smart-6a8becdc-2373-4b86-9832-4f9182e690e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2925127534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2925127534
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3711014360
Short name T980
Test name
Test status
Simulation time 1006983866 ps
CPU time 10.7 seconds
Started Jul 05 06:08:08 PM PDT 24
Finished Jul 05 06:08:19 PM PDT 24
Peak memory 224520 kb
Host smart-9692d754-5911-45c3-a8ee-bb7412573df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3711014360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3711014360
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.398721962
Short name T945
Test name
Test status
Simulation time 13990748 ps
CPU time 0.86 seconds
Started Jul 05 06:08:06 PM PDT 24
Finished Jul 05 06:08:08 PM PDT 24
Peak memory 206640 kb
Host smart-2703252d-926b-4d2e-9220-e10fd5e66fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=398721962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.398721962
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.483074371
Short name T625
Test name
Test status
Simulation time 19183245988 ps
CPU time 104.16 seconds
Started Jul 05 06:08:12 PM PDT 24
Finished Jul 05 06:09:57 PM PDT 24
Peak memory 256496 kb
Host smart-c999acd8-c3ba-4102-bc7e-f1c44d49c6c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483074371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.483074371
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.1378197630
Short name T869
Test name
Test status
Simulation time 245799820 ps
CPU time 4 seconds
Started Jul 05 06:08:05 PM PDT 24
Finished Jul 05 06:08:10 PM PDT 24
Peak memory 232716 kb
Host smart-70c771d8-257f-4553-ae98-fec770aae4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1378197630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.1378197630
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.776189993
Short name T789
Test name
Test status
Simulation time 30918764610 ps
CPU time 143.21 seconds
Started Jul 05 06:08:10 PM PDT 24
Finished Jul 05 06:10:33 PM PDT 24
Peak memory 256928 kb
Host smart-cec2b8be-6cdc-466c-bdec-04c96f2adfb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776189993 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.776189993
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.3128631526
Short name T469
Test name
Test status
Simulation time 1311084194 ps
CPU time 14.68 seconds
Started Jul 05 06:08:05 PM PDT 24
Finished Jul 05 06:08:20 PM PDT 24
Peak memory 232728 kb
Host smart-de15010f-153e-4b30-99f5-8c892dc69b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128631526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.3128631526
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.197791544
Short name T331
Test name
Test status
Simulation time 1225674381 ps
CPU time 9.03 seconds
Started Jul 05 06:08:08 PM PDT 24
Finished Jul 05 06:08:17 PM PDT 24
Peak memory 238784 kb
Host smart-5920d9a6-75ed-4a21-9ad6-46a87c76dc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197791544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.197791544
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.419079711
Short name T940
Test name
Test status
Simulation time 681881154 ps
CPU time 9.91 seconds
Started Jul 05 06:08:10 PM PDT 24
Finished Jul 05 06:08:20 PM PDT 24
Peak memory 227096 kb
Host smart-e00726a0-a6e5-4c02-893a-97e5004493d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=419079711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swap
.419079711
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.684472202
Short name T635
Test name
Test status
Simulation time 61323966148 ps
CPU time 27.09 seconds
Started Jul 05 06:08:13 PM PDT 24
Finished Jul 05 06:08:41 PM PDT 24
Peak memory 233820 kb
Host smart-c403a775-3831-4d6a-9f9a-c2deb7151e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684472202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.684472202
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.716037787
Short name T741
Test name
Test status
Simulation time 908619148 ps
CPU time 4.16 seconds
Started Jul 05 06:08:13 PM PDT 24
Finished Jul 05 06:08:17 PM PDT 24
Peak memory 218724 kb
Host smart-cc3ed2cc-c2db-4d36-84c8-0edb097f3986
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=716037787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.716037787
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.515101171
Short name T127
Test name
Test status
Simulation time 17689550854 ps
CPU time 168.04 seconds
Started Jul 05 06:08:11 PM PDT 24
Finished Jul 05 06:11:00 PM PDT 24
Peak memory 271772 kb
Host smart-718c5e4f-a156-4d97-acdb-b7a138a5b5aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515101171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stres
s_all.515101171
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.911481080
Short name T465
Test name
Test status
Simulation time 746254926 ps
CPU time 7.55 seconds
Started Jul 05 06:08:03 PM PDT 24
Finished Jul 05 06:08:12 PM PDT 24
Peak memory 216608 kb
Host smart-ea754af9-974e-49a7-af68-94191e742ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911481080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.911481080
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.2996321677
Short name T440
Test name
Test status
Simulation time 1048277087 ps
CPU time 2.55 seconds
Started Jul 05 06:08:02 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 216040 kb
Host smart-092e00ce-8141-46d2-af39-c6ff6b5d105e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996321677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.2996321677
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2639577254
Short name T540
Test name
Test status
Simulation time 56549104 ps
CPU time 1.21 seconds
Started Jul 05 06:08:05 PM PDT 24
Finished Jul 05 06:08:06 PM PDT 24
Peak memory 207940 kb
Host smart-3d8d3226-31d5-4780-afb6-334d0479136d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639577254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2639577254
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.3233331759
Short name T413
Test name
Test status
Simulation time 121563370 ps
CPU time 0.8 seconds
Started Jul 05 06:08:08 PM PDT 24
Finished Jul 05 06:08:09 PM PDT 24
Peak memory 205996 kb
Host smart-bc173fd9-f2da-4677-8a9c-4c9bc45c0191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233331759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.3233331759
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.3522113756
Short name T17
Test name
Test status
Simulation time 1546093684 ps
CPU time 5.6 seconds
Started Jul 05 06:08:06 PM PDT 24
Finished Jul 05 06:08:12 PM PDT 24
Peak memory 224448 kb
Host smart-1adba7a4-59c1-4ddd-93a7-31e18dc61f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522113756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.3522113756
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2180972590
Short name T296
Test name
Test status
Simulation time 27781704 ps
CPU time 0.78 seconds
Started Jul 05 06:08:13 PM PDT 24
Finished Jul 05 06:08:14 PM PDT 24
Peak memory 205540 kb
Host smart-27f385d5-d712-44b4-9fee-bf5666f707ad
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180972590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2180972590
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2987810475
Short name T659
Test name
Test status
Simulation time 295608755 ps
CPU time 3.08 seconds
Started Jul 05 06:08:14 PM PDT 24
Finished Jul 05 06:08:18 PM PDT 24
Peak memory 224476 kb
Host smart-3926e569-54c8-4902-8b5a-85fed0337c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987810475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2987810475
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3303985308
Short name T532
Test name
Test status
Simulation time 44460720 ps
CPU time 0.76 seconds
Started Jul 05 06:08:20 PM PDT 24
Finished Jul 05 06:08:21 PM PDT 24
Peak memory 206604 kb
Host smart-47a4b316-64d8-45fc-bc08-cbffce747072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303985308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3303985308
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.1743433618
Short name T514
Test name
Test status
Simulation time 70805803559 ps
CPU time 148.88 seconds
Started Jul 05 06:08:15 PM PDT 24
Finished Jul 05 06:10:44 PM PDT 24
Peak memory 252136 kb
Host smart-839205fe-6dbc-463f-a390-99c51748a869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743433618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.1743433618
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2783298464
Short name T354
Test name
Test status
Simulation time 88005040230 ps
CPU time 144.15 seconds
Started Jul 05 06:08:16 PM PDT 24
Finished Jul 05 06:10:41 PM PDT 24
Peak memory 251636 kb
Host smart-60ef4930-dcaa-4687-a80c-ae5ab3511ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783298464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2783298464
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.225789809
Short name T834
Test name
Test status
Simulation time 210078185306 ps
CPU time 494.07 seconds
Started Jul 05 06:08:18 PM PDT 24
Finished Jul 05 06:16:33 PM PDT 24
Peak memory 255152 kb
Host smart-72061936-4bc2-47cd-8d5d-6e09c80951bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225789809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idle
.225789809
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3322766132
Short name T311
Test name
Test status
Simulation time 992789790 ps
CPU time 6.25 seconds
Started Jul 05 06:08:16 PM PDT 24
Finished Jul 05 06:08:22 PM PDT 24
Peak memory 232688 kb
Host smart-127a74f7-c441-4ce2-a71e-4b2e5f0faccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322766132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3322766132
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.1984048782
Short name T53
Test name
Test status
Simulation time 175734833378 ps
CPU time 331.26 seconds
Started Jul 05 06:08:17 PM PDT 24
Finished Jul 05 06:13:49 PM PDT 24
Peak memory 256796 kb
Host smart-b277f12c-af91-468d-80ef-4d0d91966ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984048782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.1984048782
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.3460496848
Short name T836
Test name
Test status
Simulation time 3100758539 ps
CPU time 24.49 seconds
Started Jul 05 06:08:14 PM PDT 24
Finished Jul 05 06:08:39 PM PDT 24
Peak memory 224560 kb
Host smart-23094909-ae3b-4ae9-840f-fec40c306d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460496848 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.3460496848
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.3614076597
Short name T858
Test name
Test status
Simulation time 578765273 ps
CPU time 5.67 seconds
Started Jul 05 06:08:17 PM PDT 24
Finished Jul 05 06:08:23 PM PDT 24
Peak memory 224460 kb
Host smart-3b40112a-5066-4850-9b55-26e5061a51a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3614076597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.3614076597
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1948823372
Short name T773
Test name
Test status
Simulation time 19341865014 ps
CPU time 13.33 seconds
Started Jul 05 06:08:15 PM PDT 24
Finished Jul 05 06:08:28 PM PDT 24
Peak memory 232756 kb
Host smart-54e5878c-4834-41bd-a9c4-bf3a3c26a226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948823372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1948823372
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.152799979
Short name T628
Test name
Test status
Simulation time 23289255210 ps
CPU time 21.47 seconds
Started Jul 05 06:08:19 PM PDT 24
Finished Jul 05 06:08:40 PM PDT 24
Peak memory 240744 kb
Host smart-7acb3f54-5791-4380-9afc-b226dfdb7b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152799979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.152799979
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.1732326732
Short name T611
Test name
Test status
Simulation time 2954113698 ps
CPU time 15.04 seconds
Started Jul 05 06:08:15 PM PDT 24
Finished Jul 05 06:08:31 PM PDT 24
Peak memory 220964 kb
Host smart-1275196a-442a-4e32-b54d-773d7e3391ce
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1732326732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.1732326732
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.547483062
Short name T711
Test name
Test status
Simulation time 54887024 ps
CPU time 0.94 seconds
Started Jul 05 06:08:14 PM PDT 24
Finished Jul 05 06:08:15 PM PDT 24
Peak memory 207596 kb
Host smart-df43d5e5-e661-4212-8871-95b223ff599b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547483062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stres
s_all.547483062
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.1461609701
Short name T545
Test name
Test status
Simulation time 34953143 ps
CPU time 0.7 seconds
Started Jul 05 06:08:17 PM PDT 24
Finished Jul 05 06:08:18 PM PDT 24
Peak memory 205740 kb
Host smart-e0302294-9f66-4e64-a6b2-a98a87103f2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461609701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.1461609701
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.4293760286
Short name T341
Test name
Test status
Simulation time 12938983111 ps
CPU time 9.65 seconds
Started Jul 05 06:08:15 PM PDT 24
Finished Jul 05 06:08:25 PM PDT 24
Peak memory 216332 kb
Host smart-3c8074e4-0b5b-458c-9559-103a3087f014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293760286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.4293760286
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.3922253172
Short name T537
Test name
Test status
Simulation time 156342901 ps
CPU time 1.14 seconds
Started Jul 05 06:08:15 PM PDT 24
Finished Jul 05 06:08:16 PM PDT 24
Peak memory 207908 kb
Host smart-7f047aa7-e361-4e3c-82e2-447d78d7fccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922253172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.3922253172
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.2184356698
Short name T415
Test name
Test status
Simulation time 13537834 ps
CPU time 0.68 seconds
Started Jul 05 06:08:12 PM PDT 24
Finished Jul 05 06:08:13 PM PDT 24
Peak memory 205624 kb
Host smart-3bb654d1-104c-44be-8e60-5242a59ddd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184356698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.2184356698
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.2673618240
Short name T102
Test name
Test status
Simulation time 403902377 ps
CPU time 4.43 seconds
Started Jul 05 06:08:13 PM PDT 24
Finished Jul 05 06:08:18 PM PDT 24
Peak memory 232660 kb
Host smart-240ef375-9e66-4b2f-b8c8-56fcdca2bd69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673618240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.2673618240
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.2562121113
Short name T462
Test name
Test status
Simulation time 39742827 ps
CPU time 0.73 seconds
Started Jul 05 06:08:24 PM PDT 24
Finished Jul 05 06:08:25 PM PDT 24
Peak memory 205504 kb
Host smart-39923b06-ea48-42c4-ac90-629b15a80797
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562121113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
2562121113
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.2474829535
Short name T313
Test name
Test status
Simulation time 29514604 ps
CPU time 2.2 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:08:24 PM PDT 24
Peak memory 224508 kb
Host smart-67a62393-f391-4b1d-ba98-6b09dcd2ca54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474829535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.2474829535
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.2811514235
Short name T827
Test name
Test status
Simulation time 71024282 ps
CPU time 0.75 seconds
Started Jul 05 06:08:12 PM PDT 24
Finished Jul 05 06:08:13 PM PDT 24
Peak memory 206948 kb
Host smart-8417f2a3-6c3f-4286-9bd8-9556b4c42348
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811514235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.2811514235
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3875343560
Short name T898
Test name
Test status
Simulation time 66239281208 ps
CPU time 128.25 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:10:29 PM PDT 24
Peak memory 241028 kb
Host smart-48a5b491-d398-4650-b30f-a6016446ab76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875343560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3875343560
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4145498896
Short name T418
Test name
Test status
Simulation time 7924795214 ps
CPU time 135.49 seconds
Started Jul 05 06:08:20 PM PDT 24
Finished Jul 05 06:10:36 PM PDT 24
Peak memory 257440 kb
Host smart-d694597c-1425-421e-9567-62ed8760ba02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145498896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4145498896
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.3233670578
Short name T648
Test name
Test status
Simulation time 7751962309 ps
CPU time 114.46 seconds
Started Jul 05 06:08:23 PM PDT 24
Finished Jul 05 06:10:18 PM PDT 24
Peak memory 255352 kb
Host smart-320b98e3-65c4-4c7b-86ec-8b720051b97e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233670578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.3233670578
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3129358126
Short name T994
Test name
Test status
Simulation time 148975269 ps
CPU time 2.9 seconds
Started Jul 05 06:08:24 PM PDT 24
Finished Jul 05 06:08:27 PM PDT 24
Peak memory 232652 kb
Host smart-4d27f127-5ef4-4177-ada9-bb2a5a296fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129358126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3129358126
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2256467961
Short name T179
Test name
Test status
Simulation time 135803298042 ps
CPU time 476.66 seconds
Started Jul 05 06:08:20 PM PDT 24
Finished Jul 05 06:16:18 PM PDT 24
Peak memory 269012 kb
Host smart-5933fa06-c07f-4125-84d9-0d55d24b58ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256467961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2256467961
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.1914560618
Short name T688
Test name
Test status
Simulation time 6551826483 ps
CPU time 16.14 seconds
Started Jul 05 06:08:23 PM PDT 24
Finished Jul 05 06:08:40 PM PDT 24
Peak memory 224644 kb
Host smart-23ac374b-9813-4e18-96f9-da21a2de471f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914560618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.1914560618
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2361413670
Short name T664
Test name
Test status
Simulation time 23753956663 ps
CPU time 16.43 seconds
Started Jul 05 06:08:18 PM PDT 24
Finished Jul 05 06:08:34 PM PDT 24
Peak memory 224552 kb
Host smart-5a888623-a41d-4ad9-b183-a3ee6ad7b676
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361413670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2361413670
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.2945533738
Short name T243
Test name
Test status
Simulation time 5038435782 ps
CPU time 10.01 seconds
Started Jul 05 06:08:24 PM PDT 24
Finished Jul 05 06:08:35 PM PDT 24
Peak memory 232800 kb
Host smart-8622ab7d-a1ae-4cdc-abe3-64833031e9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945533738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.2945533738
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.1787099845
Short name T717
Test name
Test status
Simulation time 61217794136 ps
CPU time 17.3 seconds
Started Jul 05 06:08:20 PM PDT 24
Finished Jul 05 06:08:38 PM PDT 24
Peak memory 232800 kb
Host smart-6a47e43d-7b56-42ae-bec9-6dfe49b217f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787099845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.1787099845
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.1660859296
Short name T531
Test name
Test status
Simulation time 749813522 ps
CPU time 8.07 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:08:29 PM PDT 24
Peak memory 218748 kb
Host smart-d0fbfab4-dd62-4b74-8f71-414559ae1c30
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1660859296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.1660859296
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.416917669
Short name T21
Test name
Test status
Simulation time 60261186330 ps
CPU time 63.01 seconds
Started Jul 05 06:08:20 PM PDT 24
Finished Jul 05 06:09:23 PM PDT 24
Peak memory 232856 kb
Host smart-9081b415-1d5a-48aa-a5fb-5025cba7d71a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416917669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stres
s_all.416917669
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2681739284
Short name T399
Test name
Test status
Simulation time 15431561688 ps
CPU time 10.14 seconds
Started Jul 05 06:08:23 PM PDT 24
Finished Jul 05 06:08:34 PM PDT 24
Peak memory 217600 kb
Host smart-d5debaf6-d5e6-4a25-b380-94a54d3a9a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681739284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2681739284
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.1937132268
Short name T474
Test name
Test status
Simulation time 1868327719 ps
CPU time 2.91 seconds
Started Jul 05 06:08:23 PM PDT 24
Finished Jul 05 06:08:27 PM PDT 24
Peak memory 207036 kb
Host smart-b0b4c618-37e9-4abc-b850-5c6e3825b6f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1937132268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.1937132268
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.3652276521
Short name T453
Test name
Test status
Simulation time 188236190 ps
CPU time 1.6 seconds
Started Jul 05 06:08:22 PM PDT 24
Finished Jul 05 06:08:24 PM PDT 24
Peak memory 216200 kb
Host smart-c8a4e8e4-45af-4e15-a6a4-ee529498b794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652276521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.3652276521
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.828295176
Short name T875
Test name
Test status
Simulation time 34682763 ps
CPU time 0.8 seconds
Started Jul 05 06:08:23 PM PDT 24
Finished Jul 05 06:08:25 PM PDT 24
Peak memory 205980 kb
Host smart-2437b5ef-59dd-4c94-9d2b-f1e1277ff2f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828295176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.828295176
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.719788422
Short name T913
Test name
Test status
Simulation time 4339774568 ps
CPU time 8.94 seconds
Started Jul 05 06:08:22 PM PDT 24
Finished Jul 05 06:08:32 PM PDT 24
Peak memory 224604 kb
Host smart-f073d86b-2f0d-449c-85a5-488087270448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719788422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.719788422
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2142283082
Short name T297
Test name
Test status
Simulation time 22804957 ps
CPU time 0.71 seconds
Started Jul 05 06:08:22 PM PDT 24
Finished Jul 05 06:08:24 PM PDT 24
Peak memory 204940 kb
Host smart-3ea8c205-4ad8-4b2d-bd22-7f71d78f86e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142283082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2142283082
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2079408805
Short name T889
Test name
Test status
Simulation time 2620848827 ps
CPU time 4.67 seconds
Started Jul 05 06:08:24 PM PDT 24
Finished Jul 05 06:08:29 PM PDT 24
Peak memory 224648 kb
Host smart-08638c54-13e3-4bb6-aa36-238b78885b5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079408805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2079408805
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1629750227
Short name T315
Test name
Test status
Simulation time 51263884 ps
CPU time 0.76 seconds
Started Jul 05 06:08:22 PM PDT 24
Finished Jul 05 06:08:23 PM PDT 24
Peak memory 206644 kb
Host smart-2d5ba620-4ec3-492e-90a6-95b5ff704727
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629750227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1629750227
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.1101478027
Short name T957
Test name
Test status
Simulation time 10344515742 ps
CPU time 57.17 seconds
Started Jul 05 06:08:22 PM PDT 24
Finished Jul 05 06:09:20 PM PDT 24
Peak memory 249164 kb
Host smart-63115e9e-e6aa-4be9-94c5-249d1eceecae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101478027 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.1101478027
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.547817789
Short name T444
Test name
Test status
Simulation time 1628115528 ps
CPU time 27.68 seconds
Started Jul 05 06:08:22 PM PDT 24
Finished Jul 05 06:08:50 PM PDT 24
Peak memory 224632 kb
Host smart-4c5c73bd-e07e-4ba2-a3d8-43572e35ac69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547817789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.547817789
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2243883452
Short name T174
Test name
Test status
Simulation time 110525280414 ps
CPU time 391.31 seconds
Started Jul 05 06:08:23 PM PDT 24
Finished Jul 05 06:14:55 PM PDT 24
Peak memory 264764 kb
Host smart-bfe098c6-4895-4799-af0e-c1c59a594bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243883452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2243883452
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.610198491
Short name T848
Test name
Test status
Simulation time 524300051 ps
CPU time 7.31 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:08:28 PM PDT 24
Peak memory 232732 kb
Host smart-d83d995d-8886-4485-8583-510b57c01bec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610198491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.610198491
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.3868566315
Short name T574
Test name
Test status
Simulation time 2005374149 ps
CPU time 14.71 seconds
Started Jul 05 06:08:19 PM PDT 24
Finished Jul 05 06:08:34 PM PDT 24
Peak memory 249292 kb
Host smart-dbe76de0-8d1e-4a7b-9bed-d0a08a270ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868566315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.3868566315
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1058040006
Short name T455
Test name
Test status
Simulation time 2527731455 ps
CPU time 10.16 seconds
Started Jul 05 06:08:22 PM PDT 24
Finished Jul 05 06:08:33 PM PDT 24
Peak memory 232844 kb
Host smart-76e721f0-0d7a-48a2-9be8-1c329e3b7658
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058040006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1058040006
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2905487544
Short name T151
Test name
Test status
Simulation time 1676552966 ps
CPU time 3.07 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:08:25 PM PDT 24
Peak memory 224440 kb
Host smart-b6bae40e-4ba3-4758-8baf-6bedca5f2cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905487544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2905487544
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.2331437708
Short name T419
Test name
Test status
Simulation time 1299368218 ps
CPU time 7.74 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:08:30 PM PDT 24
Peak memory 223036 kb
Host smart-fa8389e7-058f-4929-b380-f86f8fe76b53
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2331437708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.2331437708
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1531389779
Short name T720
Test name
Test status
Simulation time 3880318925 ps
CPU time 59.13 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:09:20 PM PDT 24
Peak memory 239308 kb
Host smart-9f9e3909-f9bb-463e-9ebb-f0c3df261eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531389779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1531389779
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.1488475180
Short name T822
Test name
Test status
Simulation time 436193776 ps
CPU time 2.33 seconds
Started Jul 05 06:08:18 PM PDT 24
Finished Jul 05 06:08:21 PM PDT 24
Peak memory 216228 kb
Host smart-c367e081-883c-4cc2-840e-370eb9127121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488475180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.1488475180
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.1399506658
Short name T825
Test name
Test status
Simulation time 371795296 ps
CPU time 2.75 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:08:24 PM PDT 24
Peak memory 216196 kb
Host smart-58029409-c3a6-4d54-93c7-09363be88dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1399506658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.1399506658
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2729276493
Short name T645
Test name
Test status
Simulation time 499025544 ps
CPU time 4.75 seconds
Started Jul 05 06:08:22 PM PDT 24
Finished Jul 05 06:08:27 PM PDT 24
Peak memory 216208 kb
Host smart-d34a5279-1d6b-4d58-94cf-bec4334a6790
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729276493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2729276493
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.3534889587
Short name T575
Test name
Test status
Simulation time 12751228 ps
CPU time 0.7 seconds
Started Jul 05 06:08:22 PM PDT 24
Finished Jul 05 06:08:23 PM PDT 24
Peak memory 205664 kb
Host smart-e3070998-83e2-4b0e-8d45-e567ece53cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534889587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.3534889587
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1701535700
Short name T348
Test name
Test status
Simulation time 1688544697 ps
CPU time 5.93 seconds
Started Jul 05 06:08:21 PM PDT 24
Finished Jul 05 06:08:28 PM PDT 24
Peak memory 232736 kb
Host smart-ea70c6ee-7855-4978-9657-0f745eed891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701535700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1701535700
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.4273259742
Short name T333
Test name
Test status
Simulation time 12046880 ps
CPU time 0.69 seconds
Started Jul 05 06:08:30 PM PDT 24
Finished Jul 05 06:08:30 PM PDT 24
Peak memory 205476 kb
Host smart-f14df3d3-e30a-4e29-8701-396ab69d354b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273259742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
4273259742
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.2344607453
Short name T904
Test name
Test status
Simulation time 547699770 ps
CPU time 8.69 seconds
Started Jul 05 06:08:28 PM PDT 24
Finished Jul 05 06:08:37 PM PDT 24
Peak memory 233612 kb
Host smart-e9e80d9e-7d59-4f40-abd9-f1767ebf62df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344607453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.2344607453
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.2445328243
Short name T5
Test name
Test status
Simulation time 16701480 ps
CPU time 0.77 seconds
Started Jul 05 06:08:30 PM PDT 24
Finished Jul 05 06:08:31 PM PDT 24
Peak memory 206612 kb
Host smart-ce3b187b-c725-47eb-9f41-308ce890a8b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445328243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.2445328243
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3969075345
Short name T260
Test name
Test status
Simulation time 132115443830 ps
CPU time 250.04 seconds
Started Jul 05 06:08:27 PM PDT 24
Finished Jul 05 06:12:37 PM PDT 24
Peak memory 273788 kb
Host smart-5014ba37-294b-4c42-810e-9299481bd4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969075345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3969075345
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.1077491734
Short name T852
Test name
Test status
Simulation time 43416548749 ps
CPU time 163.36 seconds
Started Jul 05 06:08:27 PM PDT 24
Finished Jul 05 06:11:11 PM PDT 24
Peak memory 265380 kb
Host smart-8f3a9f80-ba13-46c9-b7ad-d2e938a0fd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077491734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.1077491734
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.523459194
Short name T784
Test name
Test status
Simulation time 4243855484 ps
CPU time 9.36 seconds
Started Jul 05 06:08:28 PM PDT 24
Finished Jul 05 06:08:38 PM PDT 24
Peak memory 224528 kb
Host smart-787c044b-e7b7-496a-9fe6-c4b8ed6898e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=523459194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.523459194
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_intercept.494057042
Short name T952
Test name
Test status
Simulation time 360064220 ps
CPU time 4.53 seconds
Started Jul 05 06:08:30 PM PDT 24
Finished Jul 05 06:08:35 PM PDT 24
Peak memory 232652 kb
Host smart-3fcac61d-c14a-4e6a-b679-7921905777b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494057042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.494057042
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.3942101069
Short name T938
Test name
Test status
Simulation time 60316475 ps
CPU time 2.41 seconds
Started Jul 05 06:08:27 PM PDT 24
Finished Jul 05 06:08:30 PM PDT 24
Peak memory 232344 kb
Host smart-237ff3a0-11a0-4fdb-b720-89caf50a1b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942101069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.3942101069
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.4097000930
Short name T803
Test name
Test status
Simulation time 710840255 ps
CPU time 5.74 seconds
Started Jul 05 06:08:31 PM PDT 24
Finished Jul 05 06:08:37 PM PDT 24
Peak memory 232636 kb
Host smart-c1f494f8-476d-47dc-8d9e-5795e11bbca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097000930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.4097000930
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.975327249
Short name T705
Test name
Test status
Simulation time 756844990 ps
CPU time 2.78 seconds
Started Jul 05 06:08:30 PM PDT 24
Finished Jul 05 06:08:33 PM PDT 24
Peak memory 224524 kb
Host smart-9288c303-6999-4d5b-bfd0-2621925577fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975327249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.975327249
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.2788443558
Short name T428
Test name
Test status
Simulation time 4501777884 ps
CPU time 7.38 seconds
Started Jul 05 06:08:28 PM PDT 24
Finished Jul 05 06:08:36 PM PDT 24
Peak memory 223148 kb
Host smart-4f7d66a7-7fea-4313-96b8-09d7407cf345
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2788443558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.2788443558
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1150661865
Short name T490
Test name
Test status
Simulation time 300042938 ps
CPU time 1.14 seconds
Started Jul 05 06:08:28 PM PDT 24
Finished Jul 05 06:08:30 PM PDT 24
Peak memory 206816 kb
Host smart-6f872217-5c97-4038-9ec2-5224a904be27
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1150661865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1150661865
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.1743518049
Short name T276
Test name
Test status
Simulation time 1918048955 ps
CPU time 27.78 seconds
Started Jul 05 06:08:30 PM PDT 24
Finished Jul 05 06:08:58 PM PDT 24
Peak memory 220092 kb
Host smart-9590a15e-7ab6-498f-958b-02a8ba279290
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1743518049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.1743518049
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.221633191
Short name T643
Test name
Test status
Simulation time 5291190328 ps
CPU time 4.99 seconds
Started Jul 05 06:08:29 PM PDT 24
Finished Jul 05 06:08:35 PM PDT 24
Peak memory 216332 kb
Host smart-5896c9a0-05cd-40b4-8aa9-255ae0ceb4a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221633191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.221633191
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3942050015
Short name T946
Test name
Test status
Simulation time 11258914 ps
CPU time 0.69 seconds
Started Jul 05 06:08:28 PM PDT 24
Finished Jul 05 06:08:29 PM PDT 24
Peak memory 205648 kb
Host smart-a9d70582-8bd2-47ba-8824-ca5a07ee7421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942050015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3942050015
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4069941666
Short name T639
Test name
Test status
Simulation time 15770030 ps
CPU time 0.73 seconds
Started Jul 05 06:08:28 PM PDT 24
Finished Jul 05 06:08:29 PM PDT 24
Peak memory 205920 kb
Host smart-01fb054f-e9ea-4704-b0f9-741455a08589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069941666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4069941666
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.1390598053
Short name T853
Test name
Test status
Simulation time 24282794190 ps
CPU time 18.75 seconds
Started Jul 05 06:08:33 PM PDT 24
Finished Jul 05 06:08:52 PM PDT 24
Peak memory 232780 kb
Host smart-37759934-1bb0-4e1c-9aeb-3a06acf83bb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390598053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.1390598053
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.1574356778
Short name T999
Test name
Test status
Simulation time 13832305 ps
CPU time 0.71 seconds
Started Jul 05 06:08:36 PM PDT 24
Finished Jul 05 06:08:38 PM PDT 24
Peak memory 204960 kb
Host smart-46b7e20d-8a89-43ec-9636-8bfda3aceea5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574356778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
1574356778
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.762249645
Short name T592
Test name
Test status
Simulation time 2105553355 ps
CPU time 7.82 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:08:47 PM PDT 24
Peak memory 232716 kb
Host smart-5f307550-6943-455b-bc56-a353889c8134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=762249645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.762249645
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.880264458
Short name T140
Test name
Test status
Simulation time 47942772 ps
CPU time 0.72 seconds
Started Jul 05 06:08:29 PM PDT 24
Finished Jul 05 06:08:30 PM PDT 24
Peak memory 206840 kb
Host smart-7cc18af3-302b-488d-a737-6abe2fbb1975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880264458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.880264458
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.554714540
Short name T764
Test name
Test status
Simulation time 8293994327 ps
CPU time 54.48 seconds
Started Jul 05 06:08:36 PM PDT 24
Finished Jul 05 06:09:31 PM PDT 24
Peak memory 241020 kb
Host smart-58424c48-8545-4032-9e3a-26151eee4cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554714540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.554714540
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.1079355747
Short name T966
Test name
Test status
Simulation time 27874423425 ps
CPU time 55.3 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:09:34 PM PDT 24
Peak memory 256848 kb
Host smart-ca831108-eb5c-4d10-aa9e-aa75462c8637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079355747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.1079355747
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.3864447983
Short name T816
Test name
Test status
Simulation time 7736612763 ps
CPU time 137.58 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:10:56 PM PDT 24
Peak memory 273256 kb
Host smart-0f92496a-d8ca-4b1e-8ede-bbac4e74524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3864447983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.3864447983
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1561744049
Short name T870
Test name
Test status
Simulation time 2519068140 ps
CPU time 37.5 seconds
Started Jul 05 06:08:41 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 232812 kb
Host smart-15c11545-6317-48bc-bec3-72c28dd4723e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561744049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1561744049
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.3707170908
Short name T466
Test name
Test status
Simulation time 11025523164 ps
CPU time 85.27 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:10:05 PM PDT 24
Peak memory 249176 kb
Host smart-39e32811-bb9b-4540-a7fa-8a954f8cd1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707170908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.3707170908
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2163908708
Short name T533
Test name
Test status
Simulation time 1376559443 ps
CPU time 4.93 seconds
Started Jul 05 06:08:36 PM PDT 24
Finished Jul 05 06:08:42 PM PDT 24
Peak memory 224420 kb
Host smart-dc5a75df-5fa6-48c1-b344-1a63943952dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163908708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2163908708
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3621765367
Short name T706
Test name
Test status
Simulation time 877786000 ps
CPU time 11.91 seconds
Started Jul 05 06:08:43 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 240608 kb
Host smart-51357678-adf9-410c-ac12-8108a1eecfae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621765367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3621765367
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.479120439
Short name T156
Test name
Test status
Simulation time 11235342489 ps
CPU time 30.02 seconds
Started Jul 05 06:08:41 PM PDT 24
Finished Jul 05 06:09:11 PM PDT 24
Peak memory 238132 kb
Host smart-df33ea7b-7828-428b-b867-794fb17b9272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479120439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swap
.479120439
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.3990874613
Short name T797
Test name
Test status
Simulation time 10325142529 ps
CPU time 16.43 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 232700 kb
Host smart-8d05e49b-6208-4ba5-947d-810a59579f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990874613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.3990874613
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.1664301757
Short name T726
Test name
Test status
Simulation time 976884958 ps
CPU time 5.17 seconds
Started Jul 05 06:08:34 PM PDT 24
Finished Jul 05 06:08:40 PM PDT 24
Peak memory 220280 kb
Host smart-407a58eb-b1fe-4550-b886-248f199ab8fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1664301757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.1664301757
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1532829007
Short name T865
Test name
Test status
Simulation time 358254341689 ps
CPU time 766.04 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:21:26 PM PDT 24
Peak memory 273856 kb
Host smart-55bbf9eb-eb11-4432-a3c6-9c0e32df3b6d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532829007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1532829007
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.2006081551
Short name T366
Test name
Test status
Simulation time 999625373 ps
CPU time 7.83 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:08:48 PM PDT 24
Peak memory 216200 kb
Host smart-ec0aff0a-9e0f-44f7-9786-6107a007892f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006081551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.2006081551
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1860193792
Short name T907
Test name
Test status
Simulation time 432277687 ps
CPU time 3.41 seconds
Started Jul 05 06:08:35 PM PDT 24
Finished Jul 05 06:08:39 PM PDT 24
Peak memory 216116 kb
Host smart-e726fd1c-2f85-4931-9731-eb679602ecb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860193792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1860193792
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3041670339
Short name T560
Test name
Test status
Simulation time 230560191 ps
CPU time 2.16 seconds
Started Jul 05 06:08:33 PM PDT 24
Finished Jul 05 06:08:36 PM PDT 24
Peak memory 216196 kb
Host smart-658cfa07-f249-48c5-b3a0-23348b99a070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041670339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3041670339
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.2624760955
Short name T888
Test name
Test status
Simulation time 65819003 ps
CPU time 0.79 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:08:40 PM PDT 24
Peak memory 206000 kb
Host smart-ae77bd4e-367c-4732-8911-9175c1ba036f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2624760955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.2624760955
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.2710398314
Short name T987
Test name
Test status
Simulation time 3790020805 ps
CPU time 13.36 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:08:52 PM PDT 24
Peak memory 240932 kb
Host smart-b3037af4-f3c8-40ec-a1de-81d03061096a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710398314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.2710398314
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.911251420
Short name T649
Test name
Test status
Simulation time 24810185 ps
CPU time 0.72 seconds
Started Jul 05 06:07:33 PM PDT 24
Finished Jul 05 06:07:35 PM PDT 24
Peak memory 205504 kb
Host smart-90406a08-ae13-4b74-93db-59e3c9078bfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=911251420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.911251420
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.1662866271
Short name T371
Test name
Test status
Simulation time 6629570274 ps
CPU time 12.71 seconds
Started Jul 05 06:07:26 PM PDT 24
Finished Jul 05 06:07:40 PM PDT 24
Peak memory 224532 kb
Host smart-cb37fd6d-acf9-48c0-8d3d-61bd0f0494cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662866271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.1662866271
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.1701320291
Short name T924
Test name
Test status
Simulation time 37329241 ps
CPU time 0.83 seconds
Started Jul 05 06:07:25 PM PDT 24
Finished Jul 05 06:07:26 PM PDT 24
Peak memory 206640 kb
Host smart-0e84747e-7ccb-41fa-aff1-f99766426d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701320291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.1701320291
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2256293226
Short name T3
Test name
Test status
Simulation time 29844464652 ps
CPU time 218.09 seconds
Started Jul 05 06:07:27 PM PDT 24
Finished Jul 05 06:11:06 PM PDT 24
Peak memory 252320 kb
Host smart-e444bf14-cbf5-43cd-92d9-1aad498110c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256293226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2256293226
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.3528502812
Short name T210
Test name
Test status
Simulation time 172890598832 ps
CPU time 248.01 seconds
Started Jul 05 06:07:28 PM PDT 24
Finished Jul 05 06:11:37 PM PDT 24
Peak memory 266052 kb
Host smart-4342b4cd-96a0-4fbe-a899-135f6d6f8908
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528502812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.3528502812
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.90290523
Short name T36
Test name
Test status
Simulation time 95831359595 ps
CPU time 189.74 seconds
Started Jul 05 06:07:29 PM PDT 24
Finished Jul 05 06:10:39 PM PDT 24
Peak memory 257468 kb
Host smart-521c2060-6673-4a05-97fc-c1d83a6f1786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90290523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle.90290523
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3777227940
Short name T211
Test name
Test status
Simulation time 1419367238 ps
CPU time 22.81 seconds
Started Jul 05 06:07:27 PM PDT 24
Finished Jul 05 06:07:50 PM PDT 24
Peak memory 240892 kb
Host smart-f0be6314-c83b-4b2d-ac45-1244bc9e6aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3777227940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3777227940
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.160502705
Short name T250
Test name
Test status
Simulation time 23851945946 ps
CPU time 74.5 seconds
Started Jul 05 06:07:21 PM PDT 24
Finished Jul 05 06:08:36 PM PDT 24
Peak memory 256904 kb
Host smart-4d451a21-8c09-4099-9d21-ec9eec52a176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160502705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds.
160502705
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.816209454
Short name T482
Test name
Test status
Simulation time 99178587 ps
CPU time 2.26 seconds
Started Jul 05 06:07:26 PM PDT 24
Finished Jul 05 06:07:29 PM PDT 24
Peak memory 224480 kb
Host smart-bb511c1e-92ea-4c7b-8339-0f945c53d6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816209454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.816209454
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.82329013
Short name T601
Test name
Test status
Simulation time 132820506910 ps
CPU time 129.18 seconds
Started Jul 05 06:07:32 PM PDT 24
Finished Jul 05 06:09:41 PM PDT 24
Peak memory 232780 kb
Host smart-d648aa09-09f2-441e-8d08-988afdd316f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82329013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.82329013
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1931226116
Short name T473
Test name
Test status
Simulation time 446897346 ps
CPU time 4.76 seconds
Started Jul 05 06:07:26 PM PDT 24
Finished Jul 05 06:07:31 PM PDT 24
Peak memory 232708 kb
Host smart-aaa12afc-3fad-4a87-9a44-051871e5fde2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1931226116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1931226116
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2754071424
Short name T637
Test name
Test status
Simulation time 33796995 ps
CPU time 2.59 seconds
Started Jul 05 06:07:24 PM PDT 24
Finished Jul 05 06:07:27 PM PDT 24
Peak memory 232392 kb
Host smart-536c76b7-25d7-4ad0-9c0c-dc8c5212b89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754071424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2754071424
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.449352314
Short name T582
Test name
Test status
Simulation time 4836838882 ps
CPU time 11.62 seconds
Started Jul 05 06:07:29 PM PDT 24
Finished Jul 05 06:07:41 PM PDT 24
Peak memory 222400 kb
Host smart-d974a6f2-7b37-4c06-9d44-86e20e9afd99
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=449352314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_direc
t.449352314
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.2369088880
Short name T281
Test name
Test status
Simulation time 5091537839 ps
CPU time 24.82 seconds
Started Jul 05 06:07:45 PM PDT 24
Finished Jul 05 06:08:11 PM PDT 24
Peak memory 216340 kb
Host smart-efba0f24-baea-48e0-bf36-c7293d3dec8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369088880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.2369088880
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.1850086186
Short name T976
Test name
Test status
Simulation time 1595604735 ps
CPU time 4.54 seconds
Started Jul 05 06:07:24 PM PDT 24
Finished Jul 05 06:07:29 PM PDT 24
Peak memory 216172 kb
Host smart-c5908979-e619-4473-9a97-ab4e909445f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850086186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.1850086186
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3664942489
Short name T935
Test name
Test status
Simulation time 372535012 ps
CPU time 1.48 seconds
Started Jul 05 06:07:23 PM PDT 24
Finished Jul 05 06:07:24 PM PDT 24
Peak memory 216208 kb
Host smart-7a062d4f-b367-40fe-bac5-4b54c6435bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664942489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3664942489
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.278618326
Short name T358
Test name
Test status
Simulation time 28546918 ps
CPU time 0.81 seconds
Started Jul 05 06:07:26 PM PDT 24
Finished Jul 05 06:07:28 PM PDT 24
Peak memory 205944 kb
Host smart-bd4a791f-24e4-4119-85a5-ff02ff23d81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278618326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.278618326
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.747239392
Short name T385
Test name
Test status
Simulation time 14220591329 ps
CPU time 7.78 seconds
Started Jul 05 06:07:29 PM PDT 24
Finished Jul 05 06:07:37 PM PDT 24
Peak memory 224888 kb
Host smart-46d7db23-88e8-4240-9ad4-3f679c83989e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=747239392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.747239392
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.1010462983
Short name T672
Test name
Test status
Simulation time 15142390 ps
CPU time 0.7 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:08:46 PM PDT 24
Peak memory 205852 kb
Host smart-9b8d0aa4-cbde-4ea7-9ae5-6c01f67a6548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010462983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
1010462983
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.3801999680
Short name T640
Test name
Test status
Simulation time 688696260 ps
CPU time 3.41 seconds
Started Jul 05 06:08:41 PM PDT 24
Finished Jul 05 06:08:45 PM PDT 24
Peak memory 224440 kb
Host smart-24225cbc-0878-4f80-a459-16a49354dd20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3801999680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.3801999680
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1868194118
Short name T1
Test name
Test status
Simulation time 15201274 ps
CPU time 0.73 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:08:40 PM PDT 24
Peak memory 205584 kb
Host smart-a5e6edff-fa2a-471a-8756-15b6927cc6b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868194118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1868194118
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.3450895850
Short name T501
Test name
Test status
Simulation time 16469587312 ps
CPU time 43.81 seconds
Started Jul 05 06:08:37 PM PDT 24
Finished Jul 05 06:09:21 PM PDT 24
Peak memory 249864 kb
Host smart-47a87ee7-3a8c-4189-af04-9df38d2b6fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450895850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.3450895850
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.1304199089
Short name T196
Test name
Test status
Simulation time 32536071585 ps
CPU time 278.97 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:13:18 PM PDT 24
Peak memory 266304 kb
Host smart-7b65a317-09e4-4bd5-9f36-dac358c38dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304199089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.1304199089
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.877037
Short name T232
Test name
Test status
Simulation time 4066150183 ps
CPU time 49.64 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:09:30 PM PDT 24
Peak memory 252372 kb
Host smart-b3126128-794f-449e-8b10-5a8791e8597d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=877037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle.877037
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.1257180629
Short name T472
Test name
Test status
Simulation time 719611187 ps
CPU time 4.02 seconds
Started Jul 05 06:08:41 PM PDT 24
Finished Jul 05 06:08:46 PM PDT 24
Peak memory 224492 kb
Host smart-5aeb92ed-2467-45d6-bc3f-01268c7ab229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257180629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.1257180629
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_intercept.4285335242
Short name T448
Test name
Test status
Simulation time 634257978 ps
CPU time 3.74 seconds
Started Jul 05 06:08:40 PM PDT 24
Finished Jul 05 06:08:44 PM PDT 24
Peak memory 224440 kb
Host smart-f98eba85-bc57-4b21-a7a6-c7fd3ca75ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285335242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.4285335242
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3611173410
Short name T431
Test name
Test status
Simulation time 1867453299 ps
CPU time 24.5 seconds
Started Jul 05 06:08:37 PM PDT 24
Finished Jul 05 06:09:02 PM PDT 24
Peak memory 232648 kb
Host smart-b116dfd9-0a60-4893-8bd9-74ad404ba595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611173410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3611173410
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.3785771254
Short name T187
Test name
Test status
Simulation time 385656191 ps
CPU time 4.32 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:08:43 PM PDT 24
Peak memory 224404 kb
Host smart-2f090fba-0054-4bfc-8c4c-2c884e5d4154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785771254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.3785771254
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.1903573515
Short name T722
Test name
Test status
Simulation time 549736597 ps
CPU time 6.39 seconds
Started Jul 05 06:08:36 PM PDT 24
Finished Jul 05 06:08:43 PM PDT 24
Peak memory 232628 kb
Host smart-9c37f8a6-6c70-48fc-ab4a-5e317fd51090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903573515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.1903573515
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.4274400813
Short name T708
Test name
Test status
Simulation time 705466492 ps
CPU time 6.1 seconds
Started Jul 05 06:08:40 PM PDT 24
Finished Jul 05 06:08:47 PM PDT 24
Peak memory 218776 kb
Host smart-89030f66-41bb-4ab9-8e86-18cf0d44cab1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4274400813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dir
ect.4274400813
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1295008776
Short name T872
Test name
Test status
Simulation time 24340165019 ps
CPU time 131.58 seconds
Started Jul 05 06:08:36 PM PDT 24
Finished Jul 05 06:10:48 PM PDT 24
Peak memory 265660 kb
Host smart-fd64ec63-34eb-4459-a5ca-83fbbc77e029
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295008776 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1295008776
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.4024198406
Short name T391
Test name
Test status
Simulation time 9948007116 ps
CPU time 37 seconds
Started Jul 05 06:08:42 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 216464 kb
Host smart-73749372-6fb8-4d13-90be-0ccf52a30baa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024198406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.4024198406
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.2054703256
Short name T931
Test name
Test status
Simulation time 849468892 ps
CPU time 3.94 seconds
Started Jul 05 06:08:35 PM PDT 24
Finished Jul 05 06:08:39 PM PDT 24
Peak memory 216280 kb
Host smart-f1ed1515-44b2-4153-b5a0-79cd5bf68f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054703256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.2054703256
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.12640046
Short name T303
Test name
Test status
Simulation time 165692060 ps
CPU time 1.46 seconds
Started Jul 05 06:08:42 PM PDT 24
Finished Jul 05 06:08:43 PM PDT 24
Peak memory 216172 kb
Host smart-21d6875e-8eda-45af-a31d-f6835a08a8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12640046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.12640046
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.580447832
Short name T867
Test name
Test status
Simulation time 20409994 ps
CPU time 0.79 seconds
Started Jul 05 06:08:36 PM PDT 24
Finished Jul 05 06:08:37 PM PDT 24
Peak memory 206012 kb
Host smart-c9d5afcb-3348-47ab-a477-e14d3a5f4993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580447832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.580447832
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.224747035
Short name T791
Test name
Test status
Simulation time 1401673639 ps
CPU time 7.82 seconds
Started Jul 05 06:08:40 PM PDT 24
Finished Jul 05 06:08:49 PM PDT 24
Peak memory 224528 kb
Host smart-38208016-fbd4-40c4-b929-ebd8c3f79407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224747035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.224747035
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.529964645
Short name T507
Test name
Test status
Simulation time 36678918 ps
CPU time 0.72 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:08:41 PM PDT 24
Peak memory 205544 kb
Host smart-d978ef98-00c9-41d0-b651-e184771da663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529964645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.529964645
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2520543897
Short name T738
Test name
Test status
Simulation time 262666194 ps
CPU time 2.6 seconds
Started Jul 05 06:08:35 PM PDT 24
Finished Jul 05 06:08:38 PM PDT 24
Peak memory 224412 kb
Host smart-87a6231a-e2fa-45b7-abf2-8e2a808b5afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520543897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2520543897
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.2311316960
Short name T538
Test name
Test status
Simulation time 31317024 ps
CPU time 0.75 seconds
Started Jul 05 06:08:41 PM PDT 24
Finished Jul 05 06:08:42 PM PDT 24
Peak memory 205920 kb
Host smart-49b61263-e220-444a-91eb-d73583e17330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2311316960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.2311316960
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.3152549061
Short name T666
Test name
Test status
Simulation time 8409295223 ps
CPU time 77.46 seconds
Started Jul 05 06:08:41 PM PDT 24
Finished Jul 05 06:09:59 PM PDT 24
Peak memory 254748 kb
Host smart-9e8afb83-1fea-458c-9833-88933a36c571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152549061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.3152549061
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3470647647
Short name T801
Test name
Test status
Simulation time 27264290294 ps
CPU time 62.59 seconds
Started Jul 05 06:08:36 PM PDT 24
Finished Jul 05 06:09:40 PM PDT 24
Peak memory 241076 kb
Host smart-718c8f39-adb4-4b14-97df-96e87f832b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470647647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3470647647
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.1108952448
Short name T512
Test name
Test status
Simulation time 101712090027 ps
CPU time 204.2 seconds
Started Jul 05 06:08:40 PM PDT 24
Finished Jul 05 06:12:05 PM PDT 24
Peak memory 249276 kb
Host smart-0b8daf13-29f6-486b-9199-37471b00a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108952448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.1108952448
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.325200418
Short name T318
Test name
Test status
Simulation time 848341460 ps
CPU time 18.27 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:09:03 PM PDT 24
Peak memory 232648 kb
Host smart-4c9ba93a-8977-4f49-a86d-8b32f09d17a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325200418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.325200418
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.503286268
Short name T906
Test name
Test status
Simulation time 6174922247 ps
CPU time 111.81 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:10:32 PM PDT 24
Peak memory 264132 kb
Host smart-98d7a343-c0f3-4413-8c9e-f36f5f63bb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503286268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.503286268
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.1231196015
Short name T700
Test name
Test status
Simulation time 669732319 ps
CPU time 4.21 seconds
Started Jul 05 06:08:39 PM PDT 24
Finished Jul 05 06:08:44 PM PDT 24
Peak memory 224464 kb
Host smart-24661b76-f9f8-4712-bc36-454b975d19b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231196015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.1231196015
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2165159743
Short name T401
Test name
Test status
Simulation time 8456142872 ps
CPU time 37.14 seconds
Started Jul 05 06:08:40 PM PDT 24
Finished Jul 05 06:09:18 PM PDT 24
Peak memory 237780 kb
Host smart-9c42b6c7-89ef-498d-986e-e19d3a209aa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165159743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2165159743
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.4168766751
Short name T850
Test name
Test status
Simulation time 2888001944 ps
CPU time 5.57 seconds
Started Jul 05 06:08:36 PM PDT 24
Finished Jul 05 06:08:42 PM PDT 24
Peak memory 232728 kb
Host smart-20726943-a2fe-42d9-8204-dacaeb51e9c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168766751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.4168766751
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.999190601
Short name T244
Test name
Test status
Simulation time 1596092099 ps
CPU time 4.03 seconds
Started Jul 05 06:08:36 PM PDT 24
Finished Jul 05 06:08:41 PM PDT 24
Peak memory 224460 kb
Host smart-a011a0d7-19f2-4d01-8c39-585c83448cee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999190601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.999190601
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.4085692085
Short name T390
Test name
Test status
Simulation time 205024679 ps
CPU time 4.64 seconds
Started Jul 05 06:08:35 PM PDT 24
Finished Jul 05 06:08:41 PM PDT 24
Peak memory 223120 kb
Host smart-db67f388-0ea9-412e-8da1-bacfdaae7c47
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4085692085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.4085692085
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2669338026
Short name T809
Test name
Test status
Simulation time 41338972753 ps
CPU time 155.38 seconds
Started Jul 05 06:08:43 PM PDT 24
Finished Jul 05 06:11:19 PM PDT 24
Peak memory 257420 kb
Host smart-1a2882e7-cecf-4e4c-a0e2-65a0bb4139df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669338026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2669338026
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.1166934901
Short name T383
Test name
Test status
Simulation time 1794679129 ps
CPU time 11.99 seconds
Started Jul 05 06:08:37 PM PDT 24
Finished Jul 05 06:08:49 PM PDT 24
Peak memory 216188 kb
Host smart-fec4b594-f1c6-4a65-b772-a5ff4537f7a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166934901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.1166934901
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.3119800038
Short name T600
Test name
Test status
Simulation time 1980136202 ps
CPU time 7.1 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:08:46 PM PDT 24
Peak memory 216252 kb
Host smart-5383bda1-372f-4235-8df5-9f2d59a6a85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119800038 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.3119800038
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.932386288
Short name T709
Test name
Test status
Simulation time 125754013 ps
CPU time 5.94 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:08:44 PM PDT 24
Peak memory 216276 kb
Host smart-64d947ea-4c42-4b72-bbe1-159596b514f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932386288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.932386288
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.1715428464
Short name T447
Test name
Test status
Simulation time 31369119 ps
CPU time 0.69 seconds
Started Jul 05 06:08:38 PM PDT 24
Finished Jul 05 06:08:39 PM PDT 24
Peak memory 205652 kb
Host smart-76a89653-25dd-411a-8af2-cae1091d1f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715428464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.1715428464
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.3213925192
Short name T581
Test name
Test status
Simulation time 413714470 ps
CPU time 3.61 seconds
Started Jul 05 06:08:41 PM PDT 24
Finished Jul 05 06:08:45 PM PDT 24
Peak memory 224472 kb
Host smart-5e79e49a-728d-47e6-8b4b-f42fa7608dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213925192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.3213925192
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.492122623
Short name T682
Test name
Test status
Simulation time 23411731 ps
CPU time 0.73 seconds
Started Jul 05 06:08:43 PM PDT 24
Finished Jul 05 06:08:44 PM PDT 24
Peak memory 205480 kb
Host smart-22543352-c753-4b75-b48a-62543c7fa6bf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492122623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.492122623
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3105227905
Short name T563
Test name
Test status
Simulation time 20271645899 ps
CPU time 20.07 seconds
Started Jul 05 06:08:53 PM PDT 24
Finished Jul 05 06:09:14 PM PDT 24
Peak memory 224628 kb
Host smart-ce0e871e-21f1-481e-b75b-7fb7d8898ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3105227905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3105227905
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.1890699061
Short name T291
Test name
Test status
Simulation time 59805655 ps
CPU time 0.78 seconds
Started Jul 05 06:08:49 PM PDT 24
Finished Jul 05 06:08:51 PM PDT 24
Peak memory 206612 kb
Host smart-7a3c25f2-38fe-43ec-abe9-00c3896071d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890699061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.1890699061
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.3866702322
Short name T479
Test name
Test status
Simulation time 330938997 ps
CPU time 6.93 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:08:52 PM PDT 24
Peak memory 249076 kb
Host smart-b92ba675-766b-4c01-8c26-3233641423b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866702322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.3866702322
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.62885943
Short name T283
Test name
Test status
Simulation time 9942502750 ps
CPU time 124.57 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:10:52 PM PDT 24
Peak memory 249280 kb
Host smart-12b4837b-e5ee-4e49-9e2c-419e9d51c0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62885943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.62885943
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.4188191259
Short name T949
Test name
Test status
Simulation time 13533356950 ps
CPU time 54.71 seconds
Started Jul 05 06:08:43 PM PDT 24
Finished Jul 05 06:09:38 PM PDT 24
Peak memory 249212 kb
Host smart-92bfa04b-d7fd-46e5-8eae-afb368b0c575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188191259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.4188191259
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.818987605
Short name T135
Test name
Test status
Simulation time 667232490 ps
CPU time 15.66 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:09:03 PM PDT 24
Peak memory 232640 kb
Host smart-a4deb7a1-436e-40bc-9736-db21621fc409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818987605 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.818987605
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2151828728
Short name T400
Test name
Test status
Simulation time 1251732101 ps
CPU time 8.44 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 224512 kb
Host smart-c5084ff7-8d5a-47a5-9bd1-d63070ff7f9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151828728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2151828728
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.1567939723
Short name T122
Test name
Test status
Simulation time 393624143 ps
CPU time 9.02 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:08:57 PM PDT 24
Peak memory 224080 kb
Host smart-295859e1-04b8-4dc5-a0b4-f1c4e3edf03a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567939723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.1567939723
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.3091908338
Short name T838
Test name
Test status
Simulation time 1010458937 ps
CPU time 5.21 seconds
Started Jul 05 06:08:45 PM PDT 24
Finished Jul 05 06:08:51 PM PDT 24
Peak memory 232704 kb
Host smart-3bdf25b3-7282-4ed5-94ae-fbbf6df76412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3091908338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.3091908338
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.1961366120
Short name T214
Test name
Test status
Simulation time 3553648682 ps
CPU time 11.1 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:08:59 PM PDT 24
Peak memory 232752 kb
Host smart-cbec2071-7913-4587-ba61-3a3a66199d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961366120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.1961366120
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.3798876807
Short name T871
Test name
Test status
Simulation time 5828526921 ps
CPU time 9.97 seconds
Started Jul 05 06:08:45 PM PDT 24
Finished Jul 05 06:08:56 PM PDT 24
Peak memory 220324 kb
Host smart-f38b4918-fe3c-48aa-8c7e-76ccb840fc2c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3798876807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.3798876807
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.3657386044
Short name T647
Test name
Test status
Simulation time 1772388321 ps
CPU time 17.05 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:09:04 PM PDT 24
Peak memory 224500 kb
Host smart-4bdf0e9d-2305-4e9d-b3ea-95b316861506
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657386044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.3657386044
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.634554229
Short name T840
Test name
Test status
Simulation time 28743366293 ps
CPU time 33.38 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:09:20 PM PDT 24
Peak memory 216392 kb
Host smart-f2b061e2-9274-4412-a121-43f09349fe4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634554229 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.634554229
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.3649271219
Short name T812
Test name
Test status
Simulation time 2434482010 ps
CPU time 2.96 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:08:50 PM PDT 24
Peak memory 216316 kb
Host smart-61e4242f-ec93-4e9a-b986-880c669b6e93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649271219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.3649271219
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1740100445
Short name T492
Test name
Test status
Simulation time 234545276 ps
CPU time 1.57 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:08:49 PM PDT 24
Peak memory 216200 kb
Host smart-2bc2f70f-7aca-406d-831f-59cda25fc0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1740100445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1740100445
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.4104714662
Short name T594
Test name
Test status
Simulation time 306658755 ps
CPU time 0.96 seconds
Started Jul 05 06:08:48 PM PDT 24
Finished Jul 05 06:08:49 PM PDT 24
Peak memory 206004 kb
Host smart-dfe9a9e3-56cb-4182-978d-83c92e589927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104714662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.4104714662
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.3768708017
Short name T422
Test name
Test status
Simulation time 173273422699 ps
CPU time 31.26 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 239292 kb
Host smart-963ad262-a151-4aa3-a896-658ac8a60053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3768708017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.3768708017
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2422674738
Short name T729
Test name
Test status
Simulation time 14593082 ps
CPU time 0.74 seconds
Started Jul 05 06:08:50 PM PDT 24
Finished Jul 05 06:08:51 PM PDT 24
Peak memory 204892 kb
Host smart-5c961791-0dd1-493b-a504-ead80b70a398
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2422674738 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2422674738
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.296147110
Short name T928
Test name
Test status
Simulation time 324936801 ps
CPU time 5.55 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:08:50 PM PDT 24
Peak memory 224504 kb
Host smart-2f12a792-fb7d-4cfa-8e2f-9e89aba5cba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296147110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.296147110
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.1305645833
Short name T609
Test name
Test status
Simulation time 30278278 ps
CPU time 0.8 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:08:46 PM PDT 24
Peak memory 206624 kb
Host smart-24885892-e9a9-4faf-865b-dd8ad3c054f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1305645833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.1305645833
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.782800164
Short name T655
Test name
Test status
Simulation time 24563353301 ps
CPU time 170.87 seconds
Started Jul 05 06:08:53 PM PDT 24
Finished Jul 05 06:11:45 PM PDT 24
Peak memory 255564 kb
Host smart-8ee06065-6e2e-4e41-8ea6-8bf4a1cd001c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782800164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.782800164
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2124477842
Short name T129
Test name
Test status
Simulation time 4352343951 ps
CPU time 71.02 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:09:58 PM PDT 24
Peak memory 249284 kb
Host smart-026590d0-376f-49a6-9249-619ede207dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124477842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2124477842
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.3271132763
Short name T16
Test name
Test status
Simulation time 3302667954 ps
CPU time 11.85 seconds
Started Jul 05 06:08:50 PM PDT 24
Finished Jul 05 06:09:02 PM PDT 24
Peak memory 224440 kb
Host smart-2ac6eec0-01fd-4b07-9d91-f03dabb27841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271132763 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.3271132763
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.941812739
Short name T815
Test name
Test status
Simulation time 86192259281 ps
CPU time 180.98 seconds
Started Jul 05 06:08:50 PM PDT 24
Finished Jul 05 06:11:52 PM PDT 24
Peak memory 248992 kb
Host smart-612fe3d2-9454-4d6f-8066-4a3adbe37a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941812739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmds
.941812739
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1955101923
Short name T155
Test name
Test status
Simulation time 607673981 ps
CPU time 4.64 seconds
Started Jul 05 06:08:42 PM PDT 24
Finished Jul 05 06:08:47 PM PDT 24
Peak memory 232640 kb
Host smart-e7069caf-7047-489d-9653-3b692c756602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1955101923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1955101923
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3446159525
Short name T364
Test name
Test status
Simulation time 4594861264 ps
CPU time 12.88 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:09:01 PM PDT 24
Peak memory 240716 kb
Host smart-267a4dbe-b71c-4cd6-ae58-d7d1ade8527d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446159525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3446159525
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.1920031454
Short name T589
Test name
Test status
Simulation time 31487045755 ps
CPU time 18.4 seconds
Started Jul 05 06:08:43 PM PDT 24
Finished Jul 05 06:09:02 PM PDT 24
Peak memory 224648 kb
Host smart-e0d87bbf-3be5-4b6b-ad21-f69593b712fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920031454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.1920031454
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.3322494120
Short name T675
Test name
Test status
Simulation time 74728299 ps
CPU time 2.3 seconds
Started Jul 05 06:08:45 PM PDT 24
Finished Jul 05 06:08:48 PM PDT 24
Peak memory 223928 kb
Host smart-dec8ef79-5a0e-40a6-a123-9e718b7a409f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322494120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.3322494120
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.1521951604
Short name T134
Test name
Test status
Simulation time 166958096 ps
CPU time 3.46 seconds
Started Jul 05 06:08:48 PM PDT 24
Finished Jul 05 06:08:52 PM PDT 24
Peak memory 218844 kb
Host smart-9e58138d-4f7c-4c1c-a9f5-00a4658b017e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1521951604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.1521951604
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.3445463000
Short name T148
Test name
Test status
Simulation time 50033259 ps
CPU time 0.97 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:08:49 PM PDT 24
Peak memory 206612 kb
Host smart-02fcece9-864a-45a3-af54-db9bd0707a46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445463000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.3445463000
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1052662837
Short name T701
Test name
Test status
Simulation time 46912573578 ps
CPU time 35.07 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 216296 kb
Host smart-9aed483f-b74e-47d2-ab91-d7fde75fadc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052662837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1052662837
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2077189145
Short name T781
Test name
Test status
Simulation time 7833195029 ps
CPU time 12.36 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:08:57 PM PDT 24
Peak memory 216376 kb
Host smart-4a5347d2-0b54-4d45-b63c-e6163974852f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077189145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2077189145
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3860574478
Short name T695
Test name
Test status
Simulation time 68410052 ps
CPU time 1.45 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:08:46 PM PDT 24
Peak memory 216180 kb
Host smart-76875970-50d3-4890-a9de-ccd5e7bf0be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860574478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3860574478
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.1825950901
Short name T663
Test name
Test status
Simulation time 15095887 ps
CPU time 0.74 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:08:47 PM PDT 24
Peak memory 205996 kb
Host smart-1b191c2e-3cab-4e91-b1bb-84165bcbf5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825950901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.1825950901
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.878787532
Short name T228
Test name
Test status
Simulation time 11444405305 ps
CPU time 18.17 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:09:05 PM PDT 24
Peak memory 233920 kb
Host smart-c3894956-6efa-49ac-80e2-fed7e39df8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878787532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.878787532
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.1887494697
Short name T568
Test name
Test status
Simulation time 144964716 ps
CPU time 0.69 seconds
Started Jul 05 06:08:54 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 205876 kb
Host smart-52c97b4c-4adf-4d34-9c67-186ef152c1f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1887494697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.
1887494697
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.626198353
Short name T578
Test name
Test status
Simulation time 498488361 ps
CPU time 3.78 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:08:50 PM PDT 24
Peak memory 232712 kb
Host smart-7cbaac80-268a-4be2-8813-24ea15b00a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626198353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.626198353
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3027614258
Short name T359
Test name
Test status
Simulation time 13984370 ps
CPU time 0.76 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:08:45 PM PDT 24
Peak memory 206576 kb
Host smart-4dbfcb18-c2b4-465a-a200-86d162af31b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3027614258 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3027614258
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2759150644
Short name T883
Test name
Test status
Simulation time 5722257002 ps
CPU time 75.28 seconds
Started Jul 05 06:08:52 PM PDT 24
Finished Jul 05 06:10:08 PM PDT 24
Peak memory 252880 kb
Host smart-95db650d-cdb9-409a-9711-f2653c4afeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759150644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2759150644
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.3402294286
Short name T914
Test name
Test status
Simulation time 7878098751 ps
CPU time 53.5 seconds
Started Jul 05 06:08:55 PM PDT 24
Finished Jul 05 06:09:49 PM PDT 24
Peak memory 255908 kb
Host smart-7ee76b31-9da6-4422-ba55-90a2d376dba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402294286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.3402294286
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.2473368938
Short name T950
Test name
Test status
Simulation time 68793674 ps
CPU time 0.87 seconds
Started Jul 05 06:08:56 PM PDT 24
Finished Jul 05 06:08:57 PM PDT 24
Peak memory 215808 kb
Host smart-0acaa9d0-2f44-4315-b8f8-dcde8eaaf88a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473368938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.2473368938
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3739240522
Short name T885
Test name
Test status
Simulation time 1375621621 ps
CPU time 5.38 seconds
Started Jul 05 06:08:45 PM PDT 24
Finished Jul 05 06:08:51 PM PDT 24
Peak memory 224464 kb
Host smart-04bd54f8-f719-4d08-876c-9efccece0d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739240522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3739240522
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.1093735726
Short name T995
Test name
Test status
Simulation time 854324733 ps
CPU time 20.26 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:09:08 PM PDT 24
Peak memory 249048 kb
Host smart-35fee7d1-e317-4eb0-a312-a49965536547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1093735726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.1093735726
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3676119336
Short name T830
Test name
Test status
Simulation time 1494244879 ps
CPU time 9.49 seconds
Started Jul 05 06:08:43 PM PDT 24
Finished Jul 05 06:08:53 PM PDT 24
Peak memory 232572 kb
Host smart-6c93a175-e698-48f7-8ade-53e4636b9331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676119336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3676119336
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2134308635
Short name T197
Test name
Test status
Simulation time 23887184711 ps
CPU time 17.83 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:09:06 PM PDT 24
Peak memory 232844 kb
Host smart-830730ad-b75f-43b2-9019-bfb579b3635e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134308635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2134308635
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.830090020
Short name T988
Test name
Test status
Simulation time 878469577 ps
CPU time 4.61 seconds
Started Jul 05 06:08:55 PM PDT 24
Finished Jul 05 06:09:01 PM PDT 24
Peak memory 219104 kb
Host smart-28143064-8914-40ff-be75-bd2d71cc95d7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=830090020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dire
ct.830090020
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.75639058
Short name T776
Test name
Test status
Simulation time 376359662 ps
CPU time 2.63 seconds
Started Jul 05 06:08:47 PM PDT 24
Finished Jul 05 06:08:50 PM PDT 24
Peak memory 218376 kb
Host smart-647dd2a8-48d6-47d6-b501-8ff1ee39b1c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75639058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.75639058
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.520903161
Short name T572
Test name
Test status
Simulation time 5406365045 ps
CPU time 11.17 seconds
Started Jul 05 06:08:53 PM PDT 24
Finished Jul 05 06:09:05 PM PDT 24
Peak memory 216168 kb
Host smart-b1cfc0d9-f97f-4b97-8a8d-c8bb5a4f80f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520903161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.520903161
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3252627857
Short name T409
Test name
Test status
Simulation time 460888073 ps
CPU time 9.29 seconds
Started Jul 05 06:08:46 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 216188 kb
Host smart-c5f3f5ec-02ed-49ae-8f7e-9c803d742e4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252627857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3252627857
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3158661737
Short name T752
Test name
Test status
Simulation time 80231721 ps
CPU time 0.76 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:08:46 PM PDT 24
Peak memory 205996 kb
Host smart-032492a7-abc1-4244-9cd1-307447b24375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158661737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3158661737
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2835871285
Short name T699
Test name
Test status
Simulation time 15821240731 ps
CPU time 15.27 seconds
Started Jul 05 06:08:44 PM PDT 24
Finished Jul 05 06:09:00 PM PDT 24
Peak memory 239980 kb
Host smart-15a8be61-529a-402b-a104-33c3936224fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835871285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2835871285
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.836008658
Short name T978
Test name
Test status
Simulation time 48345898 ps
CPU time 0.7 seconds
Started Jul 05 06:08:52 PM PDT 24
Finished Jul 05 06:08:53 PM PDT 24
Peak memory 204980 kb
Host smart-da007ae0-b92b-4796-a339-6c44819b50cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836008658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.836008658
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1510280054
Short name T519
Test name
Test status
Simulation time 350452489 ps
CPU time 4.51 seconds
Started Jul 05 06:08:51 PM PDT 24
Finished Jul 05 06:08:56 PM PDT 24
Peak memory 232576 kb
Host smart-959f154a-076d-432f-adf8-0e38ae6a968d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510280054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1510280054
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.1484331983
Short name T942
Test name
Test status
Simulation time 21623001 ps
CPU time 0.74 seconds
Started Jul 05 06:08:54 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 205916 kb
Host smart-cb2830ff-05fb-45df-8e28-c194fa986d8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484331983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.1484331983
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.899738935
Short name T252
Test name
Test status
Simulation time 2570719763 ps
CPU time 61.3 seconds
Started Jul 05 06:08:56 PM PDT 24
Finished Jul 05 06:09:58 PM PDT 24
Peak memory 253420 kb
Host smart-75289e44-cb02-4bf8-ab9f-6ad06f996f7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899738935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.899738935
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1894766471
Short name T206
Test name
Test status
Simulation time 153138652985 ps
CPU time 176.13 seconds
Started Jul 05 06:08:49 PM PDT 24
Finished Jul 05 06:11:46 PM PDT 24
Peak memory 250248 kb
Host smart-696f349d-826b-4bdd-8be8-e7458e23b822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1894766471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1894766471
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.844613810
Short name T287
Test name
Test status
Simulation time 2510565955 ps
CPU time 23.25 seconds
Started Jul 05 06:08:53 PM PDT 24
Finished Jul 05 06:09:17 PM PDT 24
Peak memory 217488 kb
Host smart-b1cef77f-caf9-456c-84df-1b4add13ce1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=844613810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.844613810
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3367352111
Short name T612
Test name
Test status
Simulation time 2491246958 ps
CPU time 25.97 seconds
Started Jul 05 06:08:53 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 239400 kb
Host smart-320d359b-798e-4ea3-b494-e99965d3780c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3367352111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3367352111
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1854577921
Short name T347
Test name
Test status
Simulation time 434930936 ps
CPU time 4.93 seconds
Started Jul 05 06:08:55 PM PDT 24
Finished Jul 05 06:09:01 PM PDT 24
Peak memory 232708 kb
Host smart-62ec33b8-8981-4859-beb5-5202d9683fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854577921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1854577921
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.1669170309
Short name T339
Test name
Test status
Simulation time 7023718675 ps
CPU time 16.79 seconds
Started Jul 05 06:08:54 PM PDT 24
Finished Jul 05 06:09:11 PM PDT 24
Peak memory 240324 kb
Host smart-f49d3666-aa98-487c-8fb0-def9344a3cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669170309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.1669170309
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.2340735287
Short name T265
Test name
Test status
Simulation time 84178986 ps
CPU time 2.12 seconds
Started Jul 05 06:08:59 PM PDT 24
Finished Jul 05 06:09:02 PM PDT 24
Peak memory 224436 kb
Host smart-b792cd0e-3d3b-4539-ae72-e4f0effa7fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340735287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.2340735287
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.3552123614
Short name T503
Test name
Test status
Simulation time 2925868163 ps
CPU time 3.26 seconds
Started Jul 05 06:08:51 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 224628 kb
Host smart-67e8cc5f-6210-499a-b40a-a95c4149d703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552123614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.3552123614
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1663383211
Short name T742
Test name
Test status
Simulation time 188047377 ps
CPU time 2.94 seconds
Started Jul 05 06:08:52 PM PDT 24
Finished Jul 05 06:08:56 PM PDT 24
Peak memory 218936 kb
Host smart-51079f0f-7f9c-4e11-98bd-17e417a3cfde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1663383211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1663383211
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.1451134809
Short name T205
Test name
Test status
Simulation time 11073367583 ps
CPU time 170.32 seconds
Started Jul 05 06:08:53 PM PDT 24
Finished Jul 05 06:11:43 PM PDT 24
Peak memory 263664 kb
Host smart-df721b68-8a9e-4a4d-8864-191f7317c272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451134809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.1451134809
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2853004417
Short name T992
Test name
Test status
Simulation time 13595315 ps
CPU time 0.72 seconds
Started Jul 05 06:08:51 PM PDT 24
Finished Jul 05 06:08:52 PM PDT 24
Peak memory 205736 kb
Host smart-2764a7cc-a5ec-4cf8-9ab6-bf14a6ecaff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853004417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2853004417
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1697084453
Short name T292
Test name
Test status
Simulation time 30083184 ps
CPU time 0.67 seconds
Started Jul 05 06:08:57 PM PDT 24
Finished Jul 05 06:08:58 PM PDT 24
Peak memory 205740 kb
Host smart-66bf3394-ce55-4ecc-a141-666a5177894c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697084453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1697084453
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.3001477115
Short name T714
Test name
Test status
Simulation time 58432493 ps
CPU time 0.92 seconds
Started Jul 05 06:08:52 PM PDT 24
Finished Jul 05 06:08:53 PM PDT 24
Peak memory 205976 kb
Host smart-07c3695b-c04f-4e47-b477-9d0ef6b78e42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001477115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.3001477115
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.3269641490
Short name T427
Test name
Test status
Simulation time 90043822 ps
CPU time 0.8 seconds
Started Jul 05 06:08:53 PM PDT 24
Finished Jul 05 06:08:54 PM PDT 24
Peak memory 205964 kb
Host smart-aeb6fc33-157f-4f5f-ad17-7df3821c8e78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269641490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.3269641490
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3915015803
Short name T362
Test name
Test status
Simulation time 238068823 ps
CPU time 2.35 seconds
Started Jul 05 06:08:55 PM PDT 24
Finished Jul 05 06:08:58 PM PDT 24
Peak memory 224412 kb
Host smart-3978ac51-052e-4159-bb2a-58345c3687a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915015803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3915015803
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.2705515986
Short name T154
Test name
Test status
Simulation time 47926238 ps
CPU time 0.73 seconds
Started Jul 05 06:09:00 PM PDT 24
Finished Jul 05 06:09:01 PM PDT 24
Peak memory 205848 kb
Host smart-3fee16b4-d9eb-4d2d-bff4-05b2132d422b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705515986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
2705515986
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.4276788120
Short name T912
Test name
Test status
Simulation time 1162256178 ps
CPU time 11.13 seconds
Started Jul 05 06:09:00 PM PDT 24
Finished Jul 05 06:09:12 PM PDT 24
Peak memory 224432 kb
Host smart-bac02440-e3db-40f3-83be-9680cbc0ebc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276788120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.4276788120
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2053529164
Short name T417
Test name
Test status
Simulation time 51268898 ps
CPU time 0.76 seconds
Started Jul 05 06:08:51 PM PDT 24
Finished Jul 05 06:08:52 PM PDT 24
Peak memory 206616 kb
Host smart-061e9353-3f3a-4aed-9c4e-dac274c2d12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053529164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2053529164
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2285205951
Short name T256
Test name
Test status
Simulation time 19175866116 ps
CPU time 109.33 seconds
Started Jul 05 06:08:59 PM PDT 24
Finished Jul 05 06:10:49 PM PDT 24
Peak memory 264620 kb
Host smart-7779574a-cba8-40ad-a2eb-e058be1c523c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285205951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2285205951
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1252678317
Short name T651
Test name
Test status
Simulation time 40560142717 ps
CPU time 35.06 seconds
Started Jul 05 06:08:59 PM PDT 24
Finished Jul 05 06:09:34 PM PDT 24
Peak memory 234940 kb
Host smart-898e5cce-a393-45f6-a5db-1569ec0a76d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1252678317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1252678317
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.2167014768
Short name T910
Test name
Test status
Simulation time 3468862292 ps
CPU time 60.19 seconds
Started Jul 05 06:09:00 PM PDT 24
Finished Jul 05 06:10:01 PM PDT 24
Peak memory 255768 kb
Host smart-fa855bea-d95b-471b-8c72-8f5ae5986991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2167014768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.2167014768
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.3220233350
Short name T768
Test name
Test status
Simulation time 1420886894 ps
CPU time 8.42 seconds
Started Jul 05 06:09:02 PM PDT 24
Finished Jul 05 06:09:11 PM PDT 24
Peak memory 240816 kb
Host smart-45436d55-8fe8-4c2b-a4f8-89617ee5e634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220233350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.3220233350
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.975313624
Short name T839
Test name
Test status
Simulation time 10482605439 ps
CPU time 50.21 seconds
Started Jul 05 06:09:01 PM PDT 24
Finished Jul 05 06:09:51 PM PDT 24
Peak memory 252820 kb
Host smart-7138079a-8ed9-4add-88e1-b09a6a10a5b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975313624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.975313624
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.1153637700
Short name T551
Test name
Test status
Simulation time 93375884 ps
CPU time 2.06 seconds
Started Jul 05 06:08:56 PM PDT 24
Finished Jul 05 06:08:59 PM PDT 24
Peak memory 222736 kb
Host smart-f063bd7f-de8e-4b36-a385-a813e0fb8266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1153637700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.1153637700
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1365681035
Short name T421
Test name
Test status
Simulation time 2608016324 ps
CPU time 15.76 seconds
Started Jul 05 06:09:01 PM PDT 24
Finished Jul 05 06:09:18 PM PDT 24
Peak memory 232764 kb
Host smart-167a3a7d-5529-43cb-91ee-c8845415a434
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365681035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1365681035
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.3722427447
Short name T930
Test name
Test status
Simulation time 55810779923 ps
CPU time 31.72 seconds
Started Jul 05 06:08:53 PM PDT 24
Finished Jul 05 06:09:25 PM PDT 24
Peak memory 232844 kb
Host smart-34473801-4cae-4c83-a3a6-7cd6739147e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722427447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swa
p.3722427447
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.2363736740
Short name T813
Test name
Test status
Simulation time 492190151 ps
CPU time 3.77 seconds
Started Jul 05 06:08:51 PM PDT 24
Finished Jul 05 06:08:56 PM PDT 24
Peak memory 224456 kb
Host smart-0c618883-98d1-448e-8ac2-ffc6bfa31c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363736740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.2363736740
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.454327726
Short name T948
Test name
Test status
Simulation time 1611611281 ps
CPU time 4.06 seconds
Started Jul 05 06:09:01 PM PDT 24
Finished Jul 05 06:09:06 PM PDT 24
Peak memory 218816 kb
Host smart-122d64f8-df79-4e26-9b50-4084fcbbd94c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=454327726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dire
ct.454327726
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.108447842
Short name T927
Test name
Test status
Simulation time 3666644921 ps
CPU time 82.41 seconds
Started Jul 05 06:09:01 PM PDT 24
Finished Jul 05 06:10:24 PM PDT 24
Peak memory 264060 kb
Host smart-e86490ee-d515-4ac7-adb9-15f2c119d980
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=108447842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stres
s_all.108447842
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.1571440833
Short name T820
Test name
Test status
Simulation time 4226989580 ps
CPU time 21 seconds
Started Jul 05 06:08:57 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 220028 kb
Host smart-d1ca8624-a86a-45f2-9550-085b2624b4f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571440833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.1571440833
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.2438850352
Short name T374
Test name
Test status
Simulation time 544687703 ps
CPU time 4.35 seconds
Started Jul 05 06:08:54 PM PDT 24
Finished Jul 05 06:08:59 PM PDT 24
Peak memory 216196 kb
Host smart-c290ed51-f9cd-46de-be3f-d99cf2022021
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2438850352 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.2438850352
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2123227077
Short name T725
Test name
Test status
Simulation time 23184763 ps
CPU time 1.34 seconds
Started Jul 05 06:08:55 PM PDT 24
Finished Jul 05 06:08:57 PM PDT 24
Peak memory 216212 kb
Host smart-2ddf5e65-c219-4f0d-b8c7-b7de2b23320e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123227077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2123227077
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2886849094
Short name T897
Test name
Test status
Simulation time 85999726 ps
CPU time 0.79 seconds
Started Jul 05 06:08:54 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 205964 kb
Host smart-574be8ff-ba33-49ac-9518-0c239a564472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886849094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2886849094
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1618329714
Short name T925
Test name
Test status
Simulation time 869048862 ps
CPU time 2.93 seconds
Started Jul 05 06:08:57 PM PDT 24
Finished Jul 05 06:09:01 PM PDT 24
Peak memory 224556 kb
Host smart-03c3e9c8-92e8-43c9-9b4e-ec6667cf522c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618329714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1618329714
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.2235988890
Short name T669
Test name
Test status
Simulation time 10981518 ps
CPU time 0.71 seconds
Started Jul 05 06:09:07 PM PDT 24
Finished Jul 05 06:09:08 PM PDT 24
Peak memory 205532 kb
Host smart-42f895cf-5ba7-41bf-9dfa-04796a5362b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235988890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
2235988890
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.785437911
Short name T372
Test name
Test status
Simulation time 2151911568 ps
CPU time 3.87 seconds
Started Jul 05 06:09:04 PM PDT 24
Finished Jul 05 06:09:08 PM PDT 24
Peak memory 232752 kb
Host smart-a55e1d8e-519e-4d78-8d24-a01076d82ad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785437911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.785437911
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.2745499933
Short name T378
Test name
Test status
Simulation time 33793824 ps
CPU time 0.79 seconds
Started Jul 05 06:09:02 PM PDT 24
Finished Jul 05 06:09:03 PM PDT 24
Peak memory 206632 kb
Host smart-f5439729-6581-4c39-bc79-b624f0f51af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745499933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.2745499933
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3956864727
Short name T629
Test name
Test status
Simulation time 4113282482 ps
CPU time 81.97 seconds
Started Jul 05 06:09:02 PM PDT 24
Finished Jul 05 06:10:25 PM PDT 24
Peak memory 257492 kb
Host smart-2b0a36a0-489b-4f40-8570-b25bc4d606da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3956864727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3956864727
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.3503353790
Short name T866
Test name
Test status
Simulation time 8579946763 ps
CPU time 104.86 seconds
Started Jul 05 06:09:02 PM PDT 24
Finished Jul 05 06:10:48 PM PDT 24
Peak memory 253448 kb
Host smart-08e36913-454d-48bf-8437-3ce219aed64a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503353790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.3503353790
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.613466982
Short name T793
Test name
Test status
Simulation time 883595079 ps
CPU time 5.71 seconds
Started Jul 05 06:09:01 PM PDT 24
Finished Jul 05 06:09:07 PM PDT 24
Peak memory 224416 kb
Host smart-47e8aec3-5118-43e4-be3e-c7f3ce07848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613466982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.613466982
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.89447130
Short name T874
Test name
Test status
Simulation time 5054562716 ps
CPU time 16.99 seconds
Started Jul 05 06:09:03 PM PDT 24
Finished Jul 05 06:09:21 PM PDT 24
Peak memory 224632 kb
Host smart-ad90cde2-e000-4ccb-95fd-916339397b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89447130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmds.89447130
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.473981664
Short name T227
Test name
Test status
Simulation time 4614910718 ps
CPU time 12.54 seconds
Started Jul 05 06:09:02 PM PDT 24
Finished Jul 05 06:09:15 PM PDT 24
Peak memory 232848 kb
Host smart-59419906-84de-4425-babb-3fb900849c9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473981664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.473981664
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.694316328
Short name T835
Test name
Test status
Simulation time 117389607 ps
CPU time 2.53 seconds
Started Jul 05 06:09:02 PM PDT 24
Finished Jul 05 06:09:05 PM PDT 24
Peak memory 232652 kb
Host smart-4988f283-ab29-4322-9034-09986b37635f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694316328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.694316328
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.577380826
Short name T451
Test name
Test status
Simulation time 4441725264 ps
CPU time 12.73 seconds
Started Jul 05 06:09:01 PM PDT 24
Finished Jul 05 06:09:14 PM PDT 24
Peak memory 232684 kb
Host smart-e6af7792-16dd-4959-8b2e-bcc7b70f2e7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=577380826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swap
.577380826
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.4132125629
Short name T794
Test name
Test status
Simulation time 947234353 ps
CPU time 11.18 seconds
Started Jul 05 06:09:00 PM PDT 24
Finished Jul 05 06:09:11 PM PDT 24
Peak memory 249000 kb
Host smart-121c1088-4e66-4243-8c08-a555d67d95cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4132125629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.4132125629
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.4013692739
Short name T365
Test name
Test status
Simulation time 939607809 ps
CPU time 9.17 seconds
Started Jul 05 06:09:02 PM PDT 24
Finished Jul 05 06:09:11 PM PDT 24
Peak memory 218816 kb
Host smart-758ee459-4bdc-49db-9a2e-e80711ec2c7b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4013692739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.4013692739
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3695797082
Short name T20
Test name
Test status
Simulation time 212454775 ps
CPU time 0.99 seconds
Started Jul 05 06:09:07 PM PDT 24
Finished Jul 05 06:09:08 PM PDT 24
Peak memory 207560 kb
Host smart-e214ff16-585d-49ab-a2be-edafa4466b29
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695797082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3695797082
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.2374575767
Short name T777
Test name
Test status
Simulation time 1108752317 ps
CPU time 4.42 seconds
Started Jul 05 06:09:01 PM PDT 24
Finished Jul 05 06:09:06 PM PDT 24
Peak memory 216236 kb
Host smart-3670173c-efda-4d72-9f2e-d3a80f50f478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374575767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.2374575767
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.4074697238
Short name T509
Test name
Test status
Simulation time 16090870133 ps
CPU time 11.93 seconds
Started Jul 05 06:09:01 PM PDT 24
Finished Jul 05 06:09:14 PM PDT 24
Peak memory 216324 kb
Host smart-ef2e4f81-2659-485e-9b2c-43e3413da276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074697238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.4074697238
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1579906541
Short name T787
Test name
Test status
Simulation time 145469860 ps
CPU time 0.86 seconds
Started Jul 05 06:09:00 PM PDT 24
Finished Jul 05 06:09:02 PM PDT 24
Peak memory 207012 kb
Host smart-d6447fe3-4f1f-441f-a1bf-6cda1a2265ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579906541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1579906541
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1522355524
Short name T539
Test name
Test status
Simulation time 24676032 ps
CPU time 0.73 seconds
Started Jul 05 06:08:59 PM PDT 24
Finished Jul 05 06:09:00 PM PDT 24
Peak memory 205668 kb
Host smart-c6f7295e-7e72-4047-bc78-f4fcbafeceaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522355524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1522355524
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2368241963
Short name T443
Test name
Test status
Simulation time 2234703257 ps
CPU time 3.99 seconds
Started Jul 05 06:09:02 PM PDT 24
Finished Jul 05 06:09:06 PM PDT 24
Peak memory 224480 kb
Host smart-4eda6233-b071-4693-a43f-fae1ccefc1f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368241963 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2368241963
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.1542325565
Short name T677
Test name
Test status
Simulation time 12771493 ps
CPU time 0.73 seconds
Started Jul 05 06:09:08 PM PDT 24
Finished Jul 05 06:09:09 PM PDT 24
Peak memory 205432 kb
Host smart-616777e1-b1cf-4d9a-84c4-54c34208d1c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542325565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.
1542325565
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1001313409
Short name T467
Test name
Test status
Simulation time 87449238 ps
CPU time 3.49 seconds
Started Jul 05 06:09:05 PM PDT 24
Finished Jul 05 06:09:09 PM PDT 24
Peak memory 232644 kb
Host smart-abb13470-b40b-45b4-9aff-93bf22072fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001313409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1001313409
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3691519312
Short name T363
Test name
Test status
Simulation time 25680974 ps
CPU time 0.81 seconds
Started Jul 05 06:09:04 PM PDT 24
Finished Jul 05 06:09:05 PM PDT 24
Peak memory 206612 kb
Host smart-c7ba2464-494e-4008-b61f-3b30a4c0a721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691519312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3691519312
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.3810328090
Short name T153
Test name
Test status
Simulation time 118547686425 ps
CPU time 131.34 seconds
Started Jul 05 06:09:08 PM PDT 24
Finished Jul 05 06:11:20 PM PDT 24
Peak memory 250260 kb
Host smart-1ed432be-6fd6-47f2-99ff-76ab1712a9a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810328090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.3810328090
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.172506730
Short name T733
Test name
Test status
Simulation time 103694905280 ps
CPU time 156.15 seconds
Started Jul 05 06:09:11 PM PDT 24
Finished Jul 05 06:11:47 PM PDT 24
Peak memory 249592 kb
Host smart-e5dbaaf3-aec9-4c4e-88d1-12f3f6f6d3e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172506730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.172506730
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3015282
Short name T322
Test name
Test status
Simulation time 1657700623 ps
CPU time 12.69 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:30 PM PDT 24
Peak memory 217272 kb
Host smart-0daba100-50b4-4196-8924-e36c4f74ea80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idle.3015282
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.2426746697
Short name T41
Test name
Test status
Simulation time 682263589 ps
CPU time 6.96 seconds
Started Jul 05 06:09:05 PM PDT 24
Finished Jul 05 06:09:12 PM PDT 24
Peak memory 240864 kb
Host smart-698fb43d-cfb8-475a-b93e-529ed398c7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426746697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.2426746697
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.262501974
Short name T506
Test name
Test status
Simulation time 33411429239 ps
CPU time 248.7 seconds
Started Jul 05 06:09:09 PM PDT 24
Finished Jul 05 06:13:18 PM PDT 24
Peak memory 255372 kb
Host smart-a4b8f2dd-97b6-4c24-9b57-cc8bb9462efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262501974 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmds
.262501974
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1062653255
Short name T306
Test name
Test status
Simulation time 6944564458 ps
CPU time 11.71 seconds
Started Jul 05 06:09:03 PM PDT 24
Finished Jul 05 06:09:16 PM PDT 24
Peak memory 224600 kb
Host smart-fdf531f8-8dbe-4b22-be14-cea398ac6c6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062653255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1062653255
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2145540837
Short name T732
Test name
Test status
Simulation time 964143468 ps
CPU time 6.21 seconds
Started Jul 05 06:09:06 PM PDT 24
Finished Jul 05 06:09:12 PM PDT 24
Peak memory 233612 kb
Host smart-16c21996-88ff-4a08-a11a-5bfe22c01903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2145540837 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2145540837
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.2818152469
Short name T82
Test name
Test status
Simulation time 2287493121 ps
CPU time 8.5 seconds
Started Jul 05 06:09:07 PM PDT 24
Finished Jul 05 06:09:16 PM PDT 24
Peak memory 232656 kb
Host smart-58ba438c-3da0-42a5-bd39-a4d28b7edebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818152469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.2818152469
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.3973654899
Short name T58
Test name
Test status
Simulation time 201585378 ps
CPU time 4.82 seconds
Started Jul 05 06:09:08 PM PDT 24
Finished Jul 05 06:09:13 PM PDT 24
Peak memory 232652 kb
Host smart-e0ae718e-d1f3-4a66-972c-4edcfeb17112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973654899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.3973654899
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2096317921
Short name T1006
Test name
Test status
Simulation time 2556829223 ps
CPU time 12.65 seconds
Started Jul 05 06:09:06 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 220168 kb
Host smart-319a26a1-4585-4ce8-b933-211ab4e19ecf
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2096317921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2096317921
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.515849296
Short name T253
Test name
Test status
Simulation time 11133863669 ps
CPU time 178.72 seconds
Started Jul 05 06:09:11 PM PDT 24
Finished Jul 05 06:12:10 PM PDT 24
Peak memory 269316 kb
Host smart-981c332b-7090-4e67-a828-b813588339e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515849296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stres
s_all.515849296
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.1346404541
Short name T591
Test name
Test status
Simulation time 5673481540 ps
CPU time 24.77 seconds
Started Jul 05 06:09:06 PM PDT 24
Finished Jul 05 06:09:31 PM PDT 24
Peak memory 219852 kb
Host smart-6d0a652f-eda9-471d-8072-2af6c32efaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346404541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.1346404541
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1862636049
Short name T75
Test name
Test status
Simulation time 14452508668 ps
CPU time 5.02 seconds
Started Jul 05 06:09:07 PM PDT 24
Finished Jul 05 06:09:12 PM PDT 24
Peak memory 216380 kb
Host smart-26275ddc-a123-4459-af9f-28050875ee13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862636049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1862636049
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2874312966
Short name T915
Test name
Test status
Simulation time 69528086 ps
CPU time 0.96 seconds
Started Jul 05 06:09:07 PM PDT 24
Finished Jul 05 06:09:09 PM PDT 24
Peak memory 207288 kb
Host smart-3e28fcb4-b8a9-4ada-8c2f-f09e30aa1eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874312966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2874312966
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3314926852
Short name T989
Test name
Test status
Simulation time 162098020 ps
CPU time 0.74 seconds
Started Jul 05 06:09:08 PM PDT 24
Finished Jul 05 06:09:09 PM PDT 24
Peak memory 206012 kb
Host smart-4633556e-8a26-46ef-ab55-98c90e471a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314926852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3314926852
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.3263602667
Short name T345
Test name
Test status
Simulation time 40349895 ps
CPU time 2.07 seconds
Started Jul 05 06:09:11 PM PDT 24
Finished Jul 05 06:09:14 PM PDT 24
Peak memory 224136 kb
Host smart-d14a8009-3088-4c4a-96e3-f553a26e9f33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263602667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.3263602667
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.3094984802
Short name T887
Test name
Test status
Simulation time 42680473 ps
CPU time 0.68 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:17 PM PDT 24
Peak memory 205480 kb
Host smart-68e0a601-2f19-41ea-8155-2023f78505cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094984802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
3094984802
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2271642581
Short name T633
Test name
Test status
Simulation time 363709935 ps
CPU time 3.28 seconds
Started Jul 05 06:09:06 PM PDT 24
Finished Jul 05 06:09:10 PM PDT 24
Peak memory 224432 kb
Host smart-a9eeb09f-8caa-4d7d-b2d5-4a39176622bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2271642581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2271642581
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3794293135
Short name T423
Test name
Test status
Simulation time 16396978 ps
CPU time 0.73 seconds
Started Jul 05 06:09:09 PM PDT 24
Finished Jul 05 06:09:10 PM PDT 24
Peak memory 206156 kb
Host smart-001797db-680f-452a-abd1-bcf7c7a22a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794293135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3794293135
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.4186993124
Short name T161
Test name
Test status
Simulation time 5671591402 ps
CPU time 50.71 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:10:08 PM PDT 24
Peak memory 249220 kb
Host smart-acc506b3-661b-4d63-ad65-71ae50438630
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186993124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.4186993124
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.186034561
Short name T18
Test name
Test status
Simulation time 18696129720 ps
CPU time 82.56 seconds
Started Jul 05 06:09:09 PM PDT 24
Finished Jul 05 06:10:32 PM PDT 24
Peak memory 256820 kb
Host smart-1cd1dd2f-1153-47b4-a1e7-19bfc45117b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=186034561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.186034561
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.4050545903
Short name T500
Test name
Test status
Simulation time 2788669189 ps
CPU time 24.87 seconds
Started Jul 05 06:09:17 PM PDT 24
Finished Jul 05 06:09:43 PM PDT 24
Peak memory 232904 kb
Host smart-c6705cc1-472c-4727-a2c0-6342f4e7f37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050545903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.4050545903
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.779044086
Short name T317
Test name
Test status
Simulation time 934363448 ps
CPU time 14.05 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:31 PM PDT 24
Peak memory 235356 kb
Host smart-10fdacbb-fc94-4dac-97c2-10b303fba509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779044086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.779044086
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.2787031864
Short name T43
Test name
Test status
Simulation time 838991282 ps
CPU time 16.38 seconds
Started Jul 05 06:09:09 PM PDT 24
Finished Jul 05 06:09:26 PM PDT 24
Peak memory 234208 kb
Host smart-b517dd29-e95e-449d-a5e7-24810dadc914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787031864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.2787031864
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.2936094962
Short name T121
Test name
Test status
Simulation time 685449218 ps
CPU time 3.69 seconds
Started Jul 05 06:09:09 PM PDT 24
Finished Jul 05 06:09:13 PM PDT 24
Peak memory 232640 kb
Host smart-612dcb03-461b-49a3-8cb3-6e686956a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936094962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.2936094962
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.4025068334
Short name T968
Test name
Test status
Simulation time 932194910 ps
CPU time 3.79 seconds
Started Jul 05 06:09:08 PM PDT 24
Finished Jul 05 06:09:12 PM PDT 24
Peak memory 224460 kb
Host smart-66df4eaf-cdac-4da7-b1ae-7a622e248b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025068334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.4025068334
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.764570308
Short name T45
Test name
Test status
Simulation time 2532796817 ps
CPU time 6.56 seconds
Started Jul 05 06:09:08 PM PDT 24
Finished Jul 05 06:09:15 PM PDT 24
Peak memory 232764 kb
Host smart-95215946-196b-4af7-a18b-288b0244f33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764570308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swap
.764570308
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.1420991218
Short name T498
Test name
Test status
Simulation time 693077633 ps
CPU time 3.85 seconds
Started Jul 05 06:09:08 PM PDT 24
Finished Jul 05 06:09:13 PM PDT 24
Peak memory 232652 kb
Host smart-98f1b9b4-aff0-4913-93b0-fd3e1e8741f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420991218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.1420991218
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1180238095
Short name T899
Test name
Test status
Simulation time 202400849 ps
CPU time 4.6 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:22 PM PDT 24
Peak memory 223008 kb
Host smart-31e8bb07-bf2d-4b57-a359-9c0394cc648a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1180238095 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1180238095
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.3391347732
Short name T125
Test name
Test status
Simulation time 385236251391 ps
CPU time 248.85 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:13:25 PM PDT 24
Peak memory 250312 kb
Host smart-b8ae898e-0d37-4149-b07f-cc63b9f9b6e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391347732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.3391347732
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.2695396023
Short name T124
Test name
Test status
Simulation time 2357809020 ps
CPU time 23.21 seconds
Started Jul 05 06:09:06 PM PDT 24
Finished Jul 05 06:09:29 PM PDT 24
Peak memory 216388 kb
Host smart-8c01f6dc-6bb6-435e-80ce-7c2b70c44de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2695396023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.2695396023
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.1853913392
Short name T719
Test name
Test status
Simulation time 1447034813 ps
CPU time 2.09 seconds
Started Jul 05 06:09:11 PM PDT 24
Finished Jul 05 06:09:13 PM PDT 24
Peak memory 216124 kb
Host smart-93796d53-296c-43f8-86fe-1e305b33629a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853913392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.1853913392
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3231289914
Short name T929
Test name
Test status
Simulation time 13464391 ps
CPU time 0.71 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:18 PM PDT 24
Peak memory 205668 kb
Host smart-c99417f3-a6b8-4feb-b949-27057a125229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231289914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3231289914
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2079490902
Short name T959
Test name
Test status
Simulation time 29480734 ps
CPU time 0.74 seconds
Started Jul 05 06:09:06 PM PDT 24
Finished Jul 05 06:09:08 PM PDT 24
Peak memory 206032 kb
Host smart-8e77d6f8-ef9e-4818-9f28-c76b31d42c47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079490902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2079490902
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.979123222
Short name T4
Test name
Test status
Simulation time 2767549192 ps
CPU time 7.85 seconds
Started Jul 05 06:09:08 PM PDT 24
Finished Jul 05 06:09:17 PM PDT 24
Peak memory 234028 kb
Host smart-4352153e-7908-4eca-a763-bab2f9a9154b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979123222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.979123222
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.4151195201
Short name T323
Test name
Test status
Simulation time 46214024 ps
CPU time 0.7 seconds
Started Jul 05 06:07:35 PM PDT 24
Finished Jul 05 06:07:36 PM PDT 24
Peak memory 204976 kb
Host smart-424d6829-1737-4fd8-9c3d-0f03b3d12813
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151195201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.4
151195201
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.511202739
Short name T746
Test name
Test status
Simulation time 987073186 ps
CPU time 5.9 seconds
Started Jul 05 06:07:37 PM PDT 24
Finished Jul 05 06:07:43 PM PDT 24
Peak memory 232664 kb
Host smart-b75cc8cd-1781-4dca-8fe6-f91ab1ed7faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511202739 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.511202739
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.621830250
Short name T340
Test name
Test status
Simulation time 12962148 ps
CPU time 0.73 seconds
Started Jul 05 06:07:27 PM PDT 24
Finished Jul 05 06:07:29 PM PDT 24
Peak memory 205560 kb
Host smart-465f94fb-548e-464d-9667-0af1909d0575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621830250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.621830250
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1976848308
Short name T159
Test name
Test status
Simulation time 120996159458 ps
CPU time 209.88 seconds
Started Jul 05 06:07:33 PM PDT 24
Finished Jul 05 06:11:04 PM PDT 24
Peak memory 250224 kb
Host smart-380afcd8-8f12-488b-a532-8a287dd0622e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1976848308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1976848308
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.2139527208
Short name T52
Test name
Test status
Simulation time 51247311445 ps
CPU time 478.42 seconds
Started Jul 05 06:07:43 PM PDT 24
Finished Jul 05 06:15:42 PM PDT 24
Peak memory 249292 kb
Host smart-75cd9ec3-0851-4bc1-96e9-a789adb66136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2139527208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.2139527208
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.1297652161
Short name T219
Test name
Test status
Simulation time 49340100709 ps
CPU time 189.72 seconds
Started Jul 05 06:07:36 PM PDT 24
Finished Jul 05 06:10:46 PM PDT 24
Peak memory 239120 kb
Host smart-47b512f9-d32b-4318-89fe-d19a275865ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297652161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.1297652161
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.355541042
Short name T951
Test name
Test status
Simulation time 157658611 ps
CPU time 5.91 seconds
Started Jul 05 06:07:35 PM PDT 24
Finished Jul 05 06:07:41 PM PDT 24
Peak memory 224460 kb
Host smart-efd5259b-fa66-4dbf-85ab-e7cccdaa9abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355541042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.355541042
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.2413012481
Short name T744
Test name
Test status
Simulation time 16680412109 ps
CPU time 74 seconds
Started Jul 05 06:07:35 PM PDT 24
Finished Jul 05 06:08:50 PM PDT 24
Peak memory 252880 kb
Host smart-7b5f575f-6f79-4dbf-9814-05f052820f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413012481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.2413012481
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1602768313
Short name T529
Test name
Test status
Simulation time 1432033653 ps
CPU time 13.11 seconds
Started Jul 05 06:07:33 PM PDT 24
Finished Jul 05 06:07:47 PM PDT 24
Peak memory 232676 kb
Host smart-83a533e6-4b2f-4bfc-9ad4-623f5cd3fe12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602768313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1602768313
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.3060990206
Short name T330
Test name
Test status
Simulation time 34323001 ps
CPU time 2.45 seconds
Started Jul 05 06:07:36 PM PDT 24
Finished Jul 05 06:07:39 PM PDT 24
Peak memory 232420 kb
Host smart-71ed9d84-db27-4c20-aa10-48c64d7732ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060990206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.3060990206
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.3127330153
Short name T762
Test name
Test status
Simulation time 1284745092 ps
CPU time 3.84 seconds
Started Jul 05 06:07:24 PM PDT 24
Finished Jul 05 06:07:29 PM PDT 24
Peak memory 224472 kb
Host smart-10ad7ca0-b7d2-4bbc-9c59-24b4e4658acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127330153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.3127330153
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.86987694
Short name T857
Test name
Test status
Simulation time 1276553869 ps
CPU time 2.71 seconds
Started Jul 05 06:07:26 PM PDT 24
Finished Jul 05 06:07:29 PM PDT 24
Peak memory 224408 kb
Host smart-11a5000d-4614-4bbb-a5fd-78be1cf61b7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86987694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.86987694
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2428231932
Short name T137
Test name
Test status
Simulation time 652906477 ps
CPU time 4.9 seconds
Started Jul 05 06:07:37 PM PDT 24
Finished Jul 05 06:07:43 PM PDT 24
Peak memory 222552 kb
Host smart-1f6466e6-47cb-4f51-b01f-502ccc1ec4be
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2428231932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2428231932
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.2935936777
Short name T68
Test name
Test status
Simulation time 38525453 ps
CPU time 1.08 seconds
Started Jul 05 06:07:37 PM PDT 24
Finished Jul 05 06:07:38 PM PDT 24
Peak memory 235988 kb
Host smart-9ef65d98-fec6-4529-94e2-e7b2f7c86677
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935936777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.2935936777
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.269587700
Short name T671
Test name
Test status
Simulation time 43253240 ps
CPU time 1.06 seconds
Started Jul 05 06:07:34 PM PDT 24
Finished Jul 05 06:07:35 PM PDT 24
Peak memory 206928 kb
Host smart-2cd45399-b6b6-4670-94c5-711e7694ec68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=269587700 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stress
_all.269587700
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.2749926984
Short name T990
Test name
Test status
Simulation time 2135903343 ps
CPU time 2.16 seconds
Started Jul 05 06:07:27 PM PDT 24
Finished Jul 05 06:07:30 PM PDT 24
Peak memory 207728 kb
Host smart-5d954c04-a875-4739-8a88-8f829781e9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749926984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.2749926984
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.3623257022
Short name T527
Test name
Test status
Simulation time 61053040 ps
CPU time 0.85 seconds
Started Jul 05 06:07:25 PM PDT 24
Finished Jul 05 06:07:26 PM PDT 24
Peak memory 207248 kb
Host smart-405ce9bb-4eb3-41be-9467-a5c6a4cc43ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623257022 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.3623257022
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.2757841397
Short name T15
Test name
Test status
Simulation time 36886079 ps
CPU time 0.82 seconds
Started Jul 05 06:07:25 PM PDT 24
Finished Jul 05 06:07:27 PM PDT 24
Peak memory 206000 kb
Host smart-10be54ab-7c5b-4878-a171-3eb3ac6d3a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757841397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.2757841397
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1534059082
Short name T541
Test name
Test status
Simulation time 460019925 ps
CPU time 3.24 seconds
Started Jul 05 06:07:35 PM PDT 24
Finished Jul 05 06:07:38 PM PDT 24
Peak memory 224444 kb
Host smart-f638f61e-d02a-4834-882f-44b248a29e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534059082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1534059082
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.3862454860
Short name T548
Test name
Test status
Simulation time 43752564 ps
CPU time 0.73 seconds
Started Jul 05 06:09:15 PM PDT 24
Finished Jul 05 06:09:16 PM PDT 24
Peak memory 204884 kb
Host smart-18d1f738-f3de-4fd1-8fe8-469612d8ca9a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862454860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
3862454860
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1691445714
Short name T530
Test name
Test status
Simulation time 40309437 ps
CPU time 2.54 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 232668 kb
Host smart-aaba020b-79b6-4622-a3f1-1fa684340931
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691445714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1691445714
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2778507736
Short name T496
Test name
Test status
Simulation time 50761990 ps
CPU time 0.8 seconds
Started Jul 05 06:09:17 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 206948 kb
Host smart-844d1f5e-e7ce-403e-aac7-1a54823d0120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778507736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2778507736
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2120546418
Short name T61
Test name
Test status
Simulation time 1122542367 ps
CPU time 18.46 seconds
Started Jul 05 06:09:17 PM PDT 24
Finished Jul 05 06:09:36 PM PDT 24
Peak memory 234688 kb
Host smart-67247996-55bc-4bc5-ab94-574127fa212b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120546418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2120546418
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.467155545
Short name T189
Test name
Test status
Simulation time 21382832659 ps
CPU time 213.71 seconds
Started Jul 05 06:09:12 PM PDT 24
Finished Jul 05 06:12:47 PM PDT 24
Peak memory 256440 kb
Host smart-bee69524-c179-4681-8654-e7303dab354a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467155545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.467155545
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1893220353
Short name T163
Test name
Test status
Simulation time 3075741595 ps
CPU time 14.72 seconds
Started Jul 05 06:09:14 PM PDT 24
Finished Jul 05 06:09:29 PM PDT 24
Peak memory 239348 kb
Host smart-fd8fa251-7b60-4e5d-a03e-5916263e333d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893220353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1893220353
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.1807160186
Short name T770
Test name
Test status
Simulation time 1726154675 ps
CPU time 7.21 seconds
Started Jul 05 06:09:11 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 224492 kb
Host smart-1e2da29d-f6ba-4ce9-a368-dc26573575e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807160186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.1807160186
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.2644470640
Short name T177
Test name
Test status
Simulation time 63396854676 ps
CPU time 113.2 seconds
Started Jul 05 06:09:14 PM PDT 24
Finished Jul 05 06:11:08 PM PDT 24
Peak memory 251188 kb
Host smart-5e23adfe-2e2a-4ea8-be6e-cc0d670ace58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644470640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.2644470640
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1634160885
Short name T627
Test name
Test status
Simulation time 1855954764 ps
CPU time 10.2 seconds
Started Jul 05 06:09:14 PM PDT 24
Finished Jul 05 06:09:25 PM PDT 24
Peak memory 232680 kb
Host smart-f8b64b9d-3973-44b0-a63e-7609cad26a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634160885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1634160885
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.1026067890
Short name T821
Test name
Test status
Simulation time 27369451931 ps
CPU time 67.07 seconds
Started Jul 05 06:09:15 PM PDT 24
Finished Jul 05 06:10:23 PM PDT 24
Peak memory 240884 kb
Host smart-a3daa61a-afc0-4f06-9f3f-23678b526d25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026067890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.1026067890
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1890507082
Short name T534
Test name
Test status
Simulation time 215137047 ps
CPU time 4.84 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:21 PM PDT 24
Peak memory 232640 kb
Host smart-bfa4fc2a-6caf-40d0-b0f1-465f073eda55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890507082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1890507082
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2168471012
Short name T673
Test name
Test status
Simulation time 2133255842 ps
CPU time 4.71 seconds
Started Jul 05 06:09:18 PM PDT 24
Finished Jul 05 06:09:24 PM PDT 24
Peak memory 232600 kb
Host smart-d38ec7ae-c242-466d-bd1e-59976ed96194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168471012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2168471012
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.2535709683
Short name T939
Test name
Test status
Simulation time 610118409 ps
CPU time 9.99 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:26 PM PDT 24
Peak memory 219420 kb
Host smart-2a41fe80-df4a-4e06-b679-42e36ef75f81
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2535709683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.2535709683
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1314197639
Short name T788
Test name
Test status
Simulation time 8110602861 ps
CPU time 36.33 seconds
Started Jul 05 06:09:18 PM PDT 24
Finished Jul 05 06:09:55 PM PDT 24
Peak memory 216372 kb
Host smart-fc5d725a-71a2-4536-9643-e11bf84a832e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314197639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1314197639
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1211538683
Short name T712
Test name
Test status
Simulation time 11521185906 ps
CPU time 18.67 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:35 PM PDT 24
Peak memory 216312 kb
Host smart-16496aa7-cbff-4204-9ac7-91760d4bb0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1211538683 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1211538683
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.826936777
Short name T343
Test name
Test status
Simulation time 403148237 ps
CPU time 2.11 seconds
Started Jul 05 06:09:17 PM PDT 24
Finished Jul 05 06:09:20 PM PDT 24
Peak memory 216276 kb
Host smart-67af3c0b-1474-42c7-8f23-7777d4d9ae1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826936777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.826936777
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.1683625464
Short name T411
Test name
Test status
Simulation time 100074336 ps
CPU time 0.83 seconds
Started Jul 05 06:09:18 PM PDT 24
Finished Jul 05 06:09:20 PM PDT 24
Peak memory 205772 kb
Host smart-16568fc7-5438-4147-9500-1f707f94c3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683625464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.1683625464
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.44676886
Short name T895
Test name
Test status
Simulation time 8487150059 ps
CPU time 11.87 seconds
Started Jul 05 06:09:14 PM PDT 24
Finished Jul 05 06:09:26 PM PDT 24
Peak memory 239484 kb
Host smart-35cb492a-d73d-4dfe-9e47-78973b7c8972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=44676886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.44676886
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1529228495
Short name T23
Test name
Test status
Simulation time 26085105 ps
CPU time 0.71 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:09:27 PM PDT 24
Peak memory 205528 kb
Host smart-1fd143bb-aa57-41fd-a44b-da7e229261b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1529228495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1529228495
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.1155836623
Short name T849
Test name
Test status
Simulation time 366109926 ps
CPU time 3.69 seconds
Started Jul 05 06:09:17 PM PDT 24
Finished Jul 05 06:09:21 PM PDT 24
Peak memory 232704 kb
Host smart-47e79c8e-52d5-4166-a410-bd1b7eb54a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155836623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.1155836623
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.1156211681
Short name T350
Test name
Test status
Simulation time 43838360 ps
CPU time 0.75 seconds
Started Jul 05 06:09:11 PM PDT 24
Finished Jul 05 06:09:12 PM PDT 24
Peak memory 206624 kb
Host smart-384c6ccb-4206-417f-9b5e-b0012c34217f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156211681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.1156211681
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.1963993773
Short name T769
Test name
Test status
Simulation time 62189861074 ps
CPU time 119.68 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:11:25 PM PDT 24
Peak memory 244284 kb
Host smart-040f8283-367d-44ee-81be-ec985ed2561f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963993773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.1963993773
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2925174631
Short name T280
Test name
Test status
Simulation time 3362142669 ps
CPU time 22.81 seconds
Started Jul 05 06:09:23 PM PDT 24
Finished Jul 05 06:09:46 PM PDT 24
Peak memory 217552 kb
Host smart-7da4e97e-8e41-49f7-bd65-c0ae6b6d6e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925174631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2925174631
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.3033492297
Short name T478
Test name
Test status
Simulation time 48438692367 ps
CPU time 127.12 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:11:33 PM PDT 24
Peak memory 259472 kb
Host smart-8bfe2c68-41f1-44ac-97cb-a5dafccc30f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033492297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.3033492297
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.1461660649
Short name T837
Test name
Test status
Simulation time 2206061922 ps
CPU time 36.38 seconds
Started Jul 05 06:09:18 PM PDT 24
Finished Jul 05 06:09:55 PM PDT 24
Peak memory 232760 kb
Host smart-312b1389-13fa-4d52-9b81-3967cb138055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461660649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.1461660649
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2685547268
Short name T44
Test name
Test status
Simulation time 1979414280 ps
CPU time 51.91 seconds
Started Jul 05 06:09:24 PM PDT 24
Finished Jul 05 06:10:17 PM PDT 24
Peak memory 249120 kb
Host smart-b68ca5f2-b828-441d-a83d-8dc834c4fc1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685547268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2685547268
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3672784057
Short name T344
Test name
Test status
Simulation time 315487838 ps
CPU time 4.27 seconds
Started Jul 05 06:09:17 PM PDT 24
Finished Jul 05 06:09:22 PM PDT 24
Peak memory 224420 kb
Host smart-3c662f3a-45c9-4a99-b7c1-496e5842c73a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672784057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3672784057
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2019382814
Short name T845
Test name
Test status
Simulation time 4315838396 ps
CPU time 39.42 seconds
Started Jul 05 06:09:17 PM PDT 24
Finished Jul 05 06:09:57 PM PDT 24
Peak memory 232848 kb
Host smart-3a296a73-b1c2-4711-89cf-08da799c9b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019382814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2019382814
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1194418491
Short name T573
Test name
Test status
Simulation time 19946759657 ps
CPU time 18.79 seconds
Started Jul 05 06:09:15 PM PDT 24
Finished Jul 05 06:09:34 PM PDT 24
Peak memory 232836 kb
Host smart-a0f45025-204f-4e0a-90eb-741b6f315064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194418491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1194418491
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.661024400
Short name T831
Test name
Test status
Simulation time 2604310677 ps
CPU time 7.74 seconds
Started Jul 05 06:09:18 PM PDT 24
Finished Jul 05 06:09:26 PM PDT 24
Peak memory 224592 kb
Host smart-a9c471a0-336c-41fa-b82d-b80781082c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661024400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.661024400
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3173906156
Short name T389
Test name
Test status
Simulation time 5325855703 ps
CPU time 12.96 seconds
Started Jul 05 06:09:24 PM PDT 24
Finished Jul 05 06:09:37 PM PDT 24
Peak memory 220472 kb
Host smart-b23d26bf-d8b8-4bd1-83ec-3fbcca77f82e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3173906156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3173906156
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.2829733691
Short name T508
Test name
Test status
Simulation time 73195569 ps
CPU time 0.95 seconds
Started Jul 05 06:09:19 PM PDT 24
Finished Jul 05 06:09:21 PM PDT 24
Peak memory 206872 kb
Host smart-5ee0f4cd-c8fa-48cb-97ea-8dd45606a2bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2829733691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.2829733691
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.1827557986
Short name T587
Test name
Test status
Simulation time 741757282 ps
CPU time 3.44 seconds
Started Jul 05 06:09:14 PM PDT 24
Finished Jul 05 06:09:18 PM PDT 24
Peak memory 216568 kb
Host smart-bf5c649a-eebb-49b3-8cb0-8f115c027452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827557986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.1827557986
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.1083794102
Short name T76
Test name
Test status
Simulation time 1389350422 ps
CPU time 8.04 seconds
Started Jul 05 06:09:16 PM PDT 24
Finished Jul 05 06:09:25 PM PDT 24
Peak memory 216200 kb
Host smart-136761bc-7e16-4843-bdfc-a46f69326ac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083794102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.1083794102
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.634279510
Short name T327
Test name
Test status
Simulation time 56903490 ps
CPU time 0.84 seconds
Started Jul 05 06:09:18 PM PDT 24
Finished Jul 05 06:09:19 PM PDT 24
Peak memory 205944 kb
Host smart-642240e9-ab83-4db9-b426-1d1240edd0c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634279510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.634279510
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1698593503
Short name T25
Test name
Test status
Simulation time 155558899 ps
CPU time 0.83 seconds
Started Jul 05 06:09:15 PM PDT 24
Finished Jul 05 06:09:17 PM PDT 24
Peak memory 206004 kb
Host smart-469d52a6-3d0c-46bf-ac83-174ce9c0c51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698593503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1698593503
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3424380600
Short name T901
Test name
Test status
Simulation time 5145700735 ps
CPU time 17.81 seconds
Started Jul 05 06:09:15 PM PDT 24
Finished Jul 05 06:09:34 PM PDT 24
Peak memory 232780 kb
Host smart-913e1afe-6a0d-427c-bcfd-103b4bff22a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424380600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3424380600
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.638850408
Short name T487
Test name
Test status
Simulation time 25863437 ps
CPU time 0.72 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:09:26 PM PDT 24
Peak memory 205872 kb
Host smart-d76017eb-31b3-4dad-a338-a6e30403afcb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638850408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.638850408
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2183762771
Short name T985
Test name
Test status
Simulation time 1669041358 ps
CPU time 2.37 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:09:28 PM PDT 24
Peak memory 224428 kb
Host smart-5aea5ec6-a5fc-46ca-a7de-3c2531bce157
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183762771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2183762771
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.689493162
Short name T844
Test name
Test status
Simulation time 23206079 ps
CPU time 0.84 seconds
Started Jul 05 06:09:20 PM PDT 24
Finished Jul 05 06:09:21 PM PDT 24
Peak memory 206576 kb
Host smart-26dda5bf-e789-4d0b-8d6f-440c8a2b507f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689493162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.689493162
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.474956032
Short name T202
Test name
Test status
Simulation time 41324348328 ps
CPU time 316.11 seconds
Started Jul 05 06:09:24 PM PDT 24
Finished Jul 05 06:14:41 PM PDT 24
Peak memory 264604 kb
Host smart-d603b255-1eb2-42cd-95f0-b8d530ee6430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474956032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.474956032
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.298559280
Short name T864
Test name
Test status
Simulation time 7139000841 ps
CPU time 54.86 seconds
Started Jul 05 06:09:26 PM PDT 24
Finished Jul 05 06:10:21 PM PDT 24
Peak memory 238292 kb
Host smart-3b757437-d738-49fc-b475-fb95d674418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298559280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.298559280
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3279421960
Short name T35
Test name
Test status
Simulation time 59190782400 ps
CPU time 533.6 seconds
Started Jul 05 06:09:24 PM PDT 24
Finished Jul 05 06:18:18 PM PDT 24
Peak memory 257472 kb
Host smart-fe811909-6776-40c1-a37d-dbd3df2a4f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279421960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3279421960
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.1086486348
Short name T275
Test name
Test status
Simulation time 660860393 ps
CPU time 5.08 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:09:31 PM PDT 24
Peak memory 232600 kb
Host smart-75fa9718-53b3-45d2-9f8a-cc438e5e1d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086486348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.1086486348
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.2958836906
Short name T484
Test name
Test status
Simulation time 4426462361 ps
CPU time 11.43 seconds
Started Jul 05 06:09:28 PM PDT 24
Finished Jul 05 06:09:40 PM PDT 24
Peak memory 251280 kb
Host smart-c0a89b44-9826-4c44-8387-d3ef1252b336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958836906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.2958836906
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.4122767131
Short name T917
Test name
Test status
Simulation time 1350215872 ps
CPU time 16.64 seconds
Started Jul 05 06:09:26 PM PDT 24
Finished Jul 05 06:09:43 PM PDT 24
Peak memory 224496 kb
Host smart-3c4d41d4-ab0a-46c0-af18-3a801039c3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122767131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.4122767131
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3855536997
Short name T521
Test name
Test status
Simulation time 40439039229 ps
CPU time 76.2 seconds
Started Jul 05 06:09:23 PM PDT 24
Finished Jul 05 06:10:40 PM PDT 24
Peak memory 224640 kb
Host smart-8d1d5329-38c4-4786-b80e-49516993e3d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855536997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3855536997
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3174609585
Short name T810
Test name
Test status
Simulation time 1070858290 ps
CPU time 5.62 seconds
Started Jul 05 06:09:28 PM PDT 24
Finished Jul 05 06:09:34 PM PDT 24
Peak memory 238024 kb
Host smart-54ddd17e-9c81-4cbf-910f-49539a5d473b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174609585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3174609585
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.788608290
Short name T504
Test name
Test status
Simulation time 32695056417 ps
CPU time 34.71 seconds
Started Jul 05 06:09:21 PM PDT 24
Finished Jul 05 06:09:56 PM PDT 24
Peak memory 251280 kb
Host smart-b0522db2-b781-45fd-95be-95b61916b0a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=788608290 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.788608290
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.84159740
Short name T934
Test name
Test status
Simulation time 595110065 ps
CPU time 3.29 seconds
Started Jul 05 06:09:23 PM PDT 24
Finished Jul 05 06:09:26 PM PDT 24
Peak memory 218676 kb
Host smart-1d5ea91e-0320-47b4-9e34-83a49407e5af
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=84159740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_direc
t.84159740
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.2692336523
Short name T126
Test name
Test status
Simulation time 43023708178 ps
CPU time 259.88 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:13:46 PM PDT 24
Peak memory 272976 kb
Host smart-582f8f68-c8b1-4a9e-8ef1-1d89b573edac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692336523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.2692336523
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1730382586
Short name T634
Test name
Test status
Simulation time 5194389903 ps
CPU time 36.88 seconds
Started Jul 05 06:09:23 PM PDT 24
Finished Jul 05 06:10:00 PM PDT 24
Peak memory 216364 kb
Host smart-311b1f4d-cd79-4666-925e-8c0564d9b644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730382586 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1730382586
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.1893273938
Short name T305
Test name
Test status
Simulation time 13876149 ps
CPU time 0.72 seconds
Started Jul 05 06:09:23 PM PDT 24
Finished Jul 05 06:09:24 PM PDT 24
Peak memory 205732 kb
Host smart-716b8d95-56bb-486c-b5e3-6b160055e168
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1893273938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.1893273938
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.1787334297
Short name T436
Test name
Test status
Simulation time 35942041 ps
CPU time 1.06 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:09:27 PM PDT 24
Peak memory 207180 kb
Host smart-8ce4cd24-5156-458f-b1ba-1af11d19b976
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787334297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.1787334297
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1143333786
Short name T718
Test name
Test status
Simulation time 222802473 ps
CPU time 0.83 seconds
Started Jul 05 06:09:22 PM PDT 24
Finished Jul 05 06:09:24 PM PDT 24
Peak memory 206004 kb
Host smart-67d7a1cf-10e1-4a2f-9750-64425bc326a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143333786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1143333786
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1263971397
Short name T224
Test name
Test status
Simulation time 19830558794 ps
CPU time 15.42 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:09:41 PM PDT 24
Peak memory 232784 kb
Host smart-af695594-6ac3-48c7-8bc7-0af6b802afdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263971397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1263971397
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.1962236675
Short name T332
Test name
Test status
Simulation time 12944018 ps
CPU time 0.7 seconds
Started Jul 05 06:09:33 PM PDT 24
Finished Jul 05 06:09:34 PM PDT 24
Peak memory 205540 kb
Host smart-dc70129a-8909-46dc-bf4c-8901f9437663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1962236675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
1962236675
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.2652986989
Short name T556
Test name
Test status
Simulation time 693385688 ps
CPU time 7.05 seconds
Started Jul 05 06:09:20 PM PDT 24
Finished Jul 05 06:09:27 PM PDT 24
Peak memory 232684 kb
Host smart-c9bd2057-0b85-4a33-85f3-ccede3aa5247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652986989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.2652986989
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.1644683669
Short name T763
Test name
Test status
Simulation time 17275909 ps
CPU time 0.8 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:09:27 PM PDT 24
Peak memory 206636 kb
Host smart-b16fbae7-a8d2-45a2-adf5-6997183ce2e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644683669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.1644683669
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.2875193971
Short name T668
Test name
Test status
Simulation time 25672803941 ps
CPU time 168.34 seconds
Started Jul 05 06:09:32 PM PDT 24
Finished Jul 05 06:12:21 PM PDT 24
Peak memory 257192 kb
Host smart-e7d16edb-1f4a-4d3f-b46f-2db60986a8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875193971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.2875193971
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.850159368
Short name T646
Test name
Test status
Simulation time 20236305432 ps
CPU time 185.56 seconds
Started Jul 05 06:09:36 PM PDT 24
Finished Jul 05 06:12:42 PM PDT 24
Peak memory 249284 kb
Host smart-403386dc-7161-46b1-8808-0e2859b09f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850159368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.850159368
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2314755906
Short name T806
Test name
Test status
Simulation time 17801040343 ps
CPU time 30.31 seconds
Started Jul 05 06:09:33 PM PDT 24
Finished Jul 05 06:10:04 PM PDT 24
Peak memory 241028 kb
Host smart-5febbcf5-0f2e-402f-a88d-e517bb7ea98e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314755906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2314755906
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2619694170
Short name T274
Test name
Test status
Simulation time 3396690317 ps
CPU time 24.81 seconds
Started Jul 05 06:09:24 PM PDT 24
Finished Jul 05 06:09:49 PM PDT 24
Peak memory 224592 kb
Host smart-ea7e4b1d-fb89-41b6-9531-4a154e68bfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619694170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2619694170
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.3893815640
Short name T577
Test name
Test status
Simulation time 1115422758 ps
CPU time 28.04 seconds
Started Jul 05 06:09:24 PM PDT 24
Finished Jul 05 06:09:52 PM PDT 24
Peak memory 240916 kb
Host smart-dacab65a-7ddb-44fa-be6c-1ff88af2785c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893815640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.3893815640
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.2700671639
Short name T886
Test name
Test status
Simulation time 970188197 ps
CPU time 8.89 seconds
Started Jul 05 06:09:26 PM PDT 24
Finished Jul 05 06:09:36 PM PDT 24
Peak memory 232648 kb
Host smart-73eaab54-0141-4e25-8906-aea8fdd5952b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2700671639 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.2700671639
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3005649647
Short name T408
Test name
Test status
Simulation time 1346361610 ps
CPU time 4.92 seconds
Started Jul 05 06:09:23 PM PDT 24
Finished Jul 05 06:09:29 PM PDT 24
Peak memory 224456 kb
Host smart-e0752974-db54-4343-81a2-9f72870ab7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005649647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3005649647
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1855952588
Short name T846
Test name
Test status
Simulation time 14705754329 ps
CPU time 19.62 seconds
Started Jul 05 06:09:23 PM PDT 24
Finished Jul 05 06:09:44 PM PDT 24
Peak memory 232728 kb
Host smart-2a4ad5c4-5748-4a29-ae35-2af7e3b20897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855952588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1855952588
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.4104743736
Short name T369
Test name
Test status
Simulation time 1187484099 ps
CPU time 7.22 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:09:34 PM PDT 24
Peak memory 233732 kb
Host smart-3a25199d-0744-44a9-af1c-5e91e6c9a8f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104743736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.4104743736
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.1030188361
Short name T644
Test name
Test status
Simulation time 3707484289 ps
CPU time 10.02 seconds
Started Jul 05 06:09:37 PM PDT 24
Finished Jul 05 06:09:47 PM PDT 24
Peak memory 219412 kb
Host smart-8667ca0f-1472-47be-985b-5c432ed11651
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1030188361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.1030188361
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.4679391
Short name T239
Test name
Test status
Simulation time 55660366106 ps
CPU time 624.51 seconds
Started Jul 05 06:09:36 PM PDT 24
Finished Jul 05 06:20:01 PM PDT 24
Peak memory 284864 kb
Host smart-fdbb29b1-6910-4574-b22a-f18dfd52820e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4679391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_stre
ss_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stress_
all.4679391
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.767457890
Short name T943
Test name
Test status
Simulation time 5861259979 ps
CPU time 16.56 seconds
Started Jul 05 06:09:25 PM PDT 24
Finished Jul 05 06:09:42 PM PDT 24
Peak memory 216264 kb
Host smart-0bfaf393-4625-49f0-96fc-d6e8a346b9bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767457890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.767457890
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.4081648220
Short name T851
Test name
Test status
Simulation time 39012606816 ps
CPU time 23.6 seconds
Started Jul 05 06:09:22 PM PDT 24
Finished Jul 05 06:09:46 PM PDT 24
Peak memory 216388 kb
Host smart-6d62174a-aad9-4049-8a02-ca290ea5b331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081648220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.4081648220
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2216453280
Short name T328
Test name
Test status
Simulation time 462687066 ps
CPU time 3.88 seconds
Started Jul 05 06:09:26 PM PDT 24
Finished Jul 05 06:09:30 PM PDT 24
Peak memory 216216 kb
Host smart-e6f1d652-d072-4d21-8635-1a8a1291be92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216453280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2216453280
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.2100008413
Short name T569
Test name
Test status
Simulation time 53984389 ps
CPU time 0.84 seconds
Started Jul 05 06:09:22 PM PDT 24
Finished Jul 05 06:09:23 PM PDT 24
Peak memory 207020 kb
Host smart-6c173812-a44e-4e84-977d-5861815ffbcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100008413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.2100008413
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.2461597893
Short name T734
Test name
Test status
Simulation time 43450986684 ps
CPU time 35.23 seconds
Started Jul 05 06:09:22 PM PDT 24
Finished Jul 05 06:09:58 PM PDT 24
Peak memory 249208 kb
Host smart-6ac5feab-e0b0-46a2-96a3-550b62aa0a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461597893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.2461597893
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1071986901
Short name T765
Test name
Test status
Simulation time 18303262 ps
CPU time 0.7 seconds
Started Jul 05 06:09:30 PM PDT 24
Finished Jul 05 06:09:31 PM PDT 24
Peak memory 205804 kb
Host smart-915c2c81-d189-4c5f-9d36-c664ac01afb4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071986901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1071986901
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.1266901618
Short name T393
Test name
Test status
Simulation time 117427593 ps
CPU time 2.3 seconds
Started Jul 05 06:09:34 PM PDT 24
Finished Jul 05 06:09:37 PM PDT 24
Peak memory 232376 kb
Host smart-b7bf8e0b-e215-47ed-814b-4262bf1f53f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266901618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.1266901618
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.1140322783
Short name T937
Test name
Test status
Simulation time 19069934 ps
CPU time 0.79 seconds
Started Jul 05 06:09:32 PM PDT 24
Finished Jul 05 06:09:33 PM PDT 24
Peak memory 206632 kb
Host smart-88b2e9eb-19c4-4e47-a4a4-041120b7a4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140322783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.1140322783
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.611381361
Short name T905
Test name
Test status
Simulation time 13837965033 ps
CPU time 84.53 seconds
Started Jul 05 06:09:34 PM PDT 24
Finished Jul 05 06:10:59 PM PDT 24
Peak memory 263812 kb
Host smart-aaac0144-4c9e-4dd8-be07-163544ddf9e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611381361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.611381361
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3038352596
Short name T991
Test name
Test status
Simulation time 22016837860 ps
CPU time 42.08 seconds
Started Jul 05 06:09:33 PM PDT 24
Finished Jul 05 06:10:16 PM PDT 24
Peak memory 240748 kb
Host smart-2ca7318c-4f79-46ca-8c58-0a625f4e185b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038352596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3038352596
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.399742419
Short name T175
Test name
Test status
Simulation time 108999946801 ps
CPU time 226.1 seconds
Started Jul 05 06:09:34 PM PDT 24
Finished Jul 05 06:13:21 PM PDT 24
Peak memory 252928 kb
Host smart-eb65a55e-8ebe-438a-8d5f-c7c3a0f7f834
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399742419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.399742419
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.2178646448
Short name T543
Test name
Test status
Simulation time 1062346439 ps
CPU time 5.07 seconds
Started Jul 05 06:09:32 PM PDT 24
Finished Jul 05 06:09:38 PM PDT 24
Peak memory 224488 kb
Host smart-658a58c4-f698-4635-81e7-3265e16c9313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178646448 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.2178646448
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2556379937
Short name T616
Test name
Test status
Simulation time 204288135 ps
CPU time 2.72 seconds
Started Jul 05 06:09:35 PM PDT 24
Finished Jul 05 06:09:38 PM PDT 24
Peak memory 232668 kb
Host smart-eea8a7c7-ee21-4ceb-9891-518cf87474cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556379937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2556379937
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.1129399546
Short name T861
Test name
Test status
Simulation time 5490536590 ps
CPU time 4.22 seconds
Started Jul 05 06:09:31 PM PDT 24
Finished Jul 05 06:09:35 PM PDT 24
Peak memory 224636 kb
Host smart-8ea706c5-957b-4d27-b2b7-37341501c14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129399546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.1129399546
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.376136616
Short name T215
Test name
Test status
Simulation time 385166594 ps
CPU time 4.07 seconds
Started Jul 05 06:09:34 PM PDT 24
Finished Jul 05 06:09:39 PM PDT 24
Peak memory 224452 kb
Host smart-e2d621a1-c28a-43ab-ba10-43595c82f6ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376136616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.376136616
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2302531222
Short name T826
Test name
Test status
Simulation time 181996173 ps
CPU time 4.59 seconds
Started Jul 05 06:09:36 PM PDT 24
Finished Jul 05 06:09:41 PM PDT 24
Peak memory 223080 kb
Host smart-dc677809-22d6-4996-8e47-a33fe8401287
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2302531222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2302531222
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1174210203
Short name T19
Test name
Test status
Simulation time 87666192053 ps
CPU time 140.81 seconds
Started Jul 05 06:09:32 PM PDT 24
Finished Jul 05 06:11:54 PM PDT 24
Peak memory 251928 kb
Host smart-7385544e-1270-41be-8a97-19e8dcb55238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1174210203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1174210203
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3925489043
Short name T288
Test name
Test status
Simulation time 378727179 ps
CPU time 2.41 seconds
Started Jul 05 06:09:31 PM PDT 24
Finished Jul 05 06:09:34 PM PDT 24
Peak memory 216440 kb
Host smart-64c09b29-22d6-4d48-abe4-7bc12d7b4ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925489043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3925489043
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.4273005148
Short name T158
Test name
Test status
Simulation time 389281526 ps
CPU time 3.01 seconds
Started Jul 05 06:09:31 PM PDT 24
Finished Jul 05 06:09:35 PM PDT 24
Peak memory 216280 kb
Host smart-80b434c4-b13c-483f-b64d-403c8744f13a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273005148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.4273005148
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4265193713
Short name T650
Test name
Test status
Simulation time 544672392 ps
CPU time 0.85 seconds
Started Jul 05 06:09:32 PM PDT 24
Finished Jul 05 06:09:33 PM PDT 24
Peak memory 205980 kb
Host smart-d66a880f-0e20-45e7-9c0e-05103ed7587c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265193713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4265193713
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.153756313
Short name T463
Test name
Test status
Simulation time 77435313 ps
CPU time 0.79 seconds
Started Jul 05 06:09:31 PM PDT 24
Finished Jul 05 06:09:32 PM PDT 24
Peak memory 206000 kb
Host smart-9928146c-0ae6-4e0b-8e49-26125686bcc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153756313 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.153756313
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.3279709865
Short name T670
Test name
Test status
Simulation time 496706691 ps
CPU time 9.86 seconds
Started Jul 05 06:09:33 PM PDT 24
Finished Jul 05 06:09:43 PM PDT 24
Peak memory 232688 kb
Host smart-5ecffd14-4951-4dd3-88f7-de2c523b895b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279709865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.3279709865
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.1927081581
Short name T622
Test name
Test status
Simulation time 13516646 ps
CPU time 0.74 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:09:43 PM PDT 24
Peak memory 205776 kb
Host smart-7512deff-be3f-45c3-b327-c18b69be4c3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927081581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
1927081581
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3163524312
Short name T828
Test name
Test status
Simulation time 5091808084 ps
CPU time 17.5 seconds
Started Jul 05 06:09:31 PM PDT 24
Finished Jul 05 06:09:49 PM PDT 24
Peak memory 224656 kb
Host smart-6ee22123-fbfa-44f1-963a-d22138d36c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3163524312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3163524312
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.252551557
Short name T760
Test name
Test status
Simulation time 13326770 ps
CPU time 0.82 seconds
Started Jul 05 06:09:36 PM PDT 24
Finished Jul 05 06:09:38 PM PDT 24
Peak memory 206616 kb
Host smart-de9177c7-e03f-4401-94b7-6d343803b77e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252551557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.252551557
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3893713697
Short name T606
Test name
Test status
Simulation time 1077557103 ps
CPU time 6.36 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:09:49 PM PDT 24
Peak memory 224488 kb
Host smart-f837194c-9580-4600-8b93-6124935d3373
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893713697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3893713697
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.1216515275
Short name T235
Test name
Test status
Simulation time 17914301495 ps
CPU time 61.4 seconds
Started Jul 05 06:09:43 PM PDT 24
Finished Jul 05 06:10:45 PM PDT 24
Peak memory 253912 kb
Host smart-892ae8bc-c422-489e-98d1-4bd8cba9cff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216515275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.1216515275
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.3985178445
Short name T290
Test name
Test status
Simulation time 12552736700 ps
CPU time 97 seconds
Started Jul 05 06:09:43 PM PDT 24
Finished Jul 05 06:11:21 PM PDT 24
Peak memory 238892 kb
Host smart-c0a9925e-9a64-4c8a-93d1-54f62254956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985178445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.3985178445
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1240795335
Short name T294
Test name
Test status
Simulation time 85978581 ps
CPU time 2.93 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:09:46 PM PDT 24
Peak memory 224444 kb
Host smart-dc3179f4-8bd7-4001-bcf2-bc5b004b855a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240795335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1240795335
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3999623527
Short name T246
Test name
Test status
Simulation time 2664966555 ps
CPU time 65.4 seconds
Started Jul 05 06:09:41 PM PDT 24
Finished Jul 05 06:10:47 PM PDT 24
Peak memory 257280 kb
Host smart-62bd70f6-4f11-4ee4-becf-56629c942eab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999623527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3999623527
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2205473968
Short name T854
Test name
Test status
Simulation time 603133447 ps
CPU time 2.7 seconds
Started Jul 05 06:09:32 PM PDT 24
Finished Jul 05 06:09:35 PM PDT 24
Peak memory 232696 kb
Host smart-2dbcb206-4819-49bc-a9e0-10a17fa02780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205473968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2205473968
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.170260523
Short name T388
Test name
Test status
Simulation time 878692575 ps
CPU time 14.52 seconds
Started Jul 05 06:09:34 PM PDT 24
Finished Jul 05 06:09:50 PM PDT 24
Peak memory 235936 kb
Host smart-61592910-6b1b-4bbd-b4fa-b3f07f70e9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170260523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.170260523
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.799073437
Short name T261
Test name
Test status
Simulation time 15794532511 ps
CPU time 21.75 seconds
Started Jul 05 06:09:33 PM PDT 24
Finished Jul 05 06:09:55 PM PDT 24
Peak memory 249240 kb
Host smart-e3cf120b-ec64-4f32-b977-eb016d5f9e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799073437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.799073437
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.849467151
Short name T502
Test name
Test status
Simulation time 3935268239 ps
CPU time 4.77 seconds
Started Jul 05 06:09:30 PM PDT 24
Finished Jul 05 06:09:35 PM PDT 24
Peak memory 232792 kb
Host smart-506de2a6-42c8-4912-b00a-7850aeb9b025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849467151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.849467151
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.1729600319
Short name T136
Test name
Test status
Simulation time 1784617309 ps
CPU time 4.33 seconds
Started Jul 05 06:09:39 PM PDT 24
Finished Jul 05 06:09:44 PM PDT 24
Peak memory 220524 kb
Host smart-4b618cb2-2ffa-4df9-8428-6d14f02d1c02
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1729600319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.1729600319
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.3206743234
Short name T123
Test name
Test status
Simulation time 19726315152 ps
CPU time 123.92 seconds
Started Jul 05 06:09:43 PM PDT 24
Finished Jul 05 06:11:48 PM PDT 24
Peak memory 240932 kb
Host smart-5b4549db-15bf-4750-90c4-6e097a2360bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3206743234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.3206743234
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.1918354850
Short name T433
Test name
Test status
Simulation time 4537927031 ps
CPU time 23.67 seconds
Started Jul 05 06:09:34 PM PDT 24
Finished Jul 05 06:09:58 PM PDT 24
Peak memory 216360 kb
Host smart-3efd2f19-8a71-4492-a5b9-cb6d0532174f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1918354850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.1918354850
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3475485210
Short name T807
Test name
Test status
Simulation time 532081376 ps
CPU time 4.11 seconds
Started Jul 05 06:09:32 PM PDT 24
Finished Jul 05 06:09:36 PM PDT 24
Peak memory 216176 kb
Host smart-0a8dcfe5-b395-4a9e-8318-9b171976e599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475485210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3475485210
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.2785543556
Short name T286
Test name
Test status
Simulation time 1278246279 ps
CPU time 3.29 seconds
Started Jul 05 06:09:32 PM PDT 24
Finished Jul 05 06:09:35 PM PDT 24
Peak memory 216200 kb
Host smart-041bdcaa-f41c-4875-8b6e-c9732e88bcbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785543556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.2785543556
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.1377206292
Short name T795
Test name
Test status
Simulation time 371824134 ps
CPU time 1.04 seconds
Started Jul 05 06:09:38 PM PDT 24
Finished Jul 05 06:09:39 PM PDT 24
Peak memory 207024 kb
Host smart-eeaa5332-0020-4a56-8244-8bea399baa0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1377206292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.1377206292
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3825067567
Short name T841
Test name
Test status
Simulation time 70378380 ps
CPU time 2.67 seconds
Started Jul 05 06:09:39 PM PDT 24
Finished Jul 05 06:09:42 PM PDT 24
Peak memory 236856 kb
Host smart-6508cc59-9e35-4c99-8e85-936c738dd8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825067567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3825067567
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3338112077
Short name T394
Test name
Test status
Simulation time 59815676 ps
CPU time 0.76 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:09:44 PM PDT 24
Peak memory 205844 kb
Host smart-7f01c658-5887-4450-97c2-f8981aba1701
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338112077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3338112077
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.1012750711
Short name T439
Test name
Test status
Simulation time 117640341 ps
CPU time 2.8 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:09:59 PM PDT 24
Peak memory 232692 kb
Host smart-9dac401e-88fa-4215-9dc8-879e5853d0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012750711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.1012750711
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3055225730
Short name T919
Test name
Test status
Simulation time 15073301 ps
CPU time 0.79 seconds
Started Jul 05 06:09:44 PM PDT 24
Finished Jul 05 06:09:46 PM PDT 24
Peak memory 206612 kb
Host smart-67c06675-402c-4576-a483-589c21d64f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055225730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3055225730
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.4090942697
Short name T747
Test name
Test status
Simulation time 34866035635 ps
CPU time 242.05 seconds
Started Jul 05 06:09:41 PM PDT 24
Finished Jul 05 06:13:44 PM PDT 24
Peak memory 249148 kb
Host smart-87415d6c-fe52-42de-90c0-5f169c812d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090942697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.4090942697
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3745875735
Short name T162
Test name
Test status
Simulation time 8377341568 ps
CPU time 85.12 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:11:14 PM PDT 24
Peak memory 249832 kb
Host smart-eca402f5-4fa5-4c3c-9441-a40a0424f596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745875735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3745875735
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4256546019
Short name T449
Test name
Test status
Simulation time 10358501247 ps
CPU time 41.77 seconds
Started Jul 05 06:09:41 PM PDT 24
Finished Jul 05 06:10:23 PM PDT 24
Peak memory 224672 kb
Host smart-d88d836a-fc2e-4b0e-bf1f-d1c13489540b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256546019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4256546019
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.2383825896
Short name T879
Test name
Test status
Simulation time 1053053968 ps
CPU time 14.76 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:10:11 PM PDT 24
Peak memory 249092 kb
Host smart-004e702c-786d-458d-978d-7b8fe48724bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383825896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.2383825896
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1295960399
Short name T982
Test name
Test status
Simulation time 49240094455 ps
CPU time 134.14 seconds
Started Jul 05 06:09:41 PM PDT 24
Finished Jul 05 06:11:56 PM PDT 24
Peak memory 241020 kb
Host smart-fb6a0062-6cd6-4f54-a7c4-69c85a6ca792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1295960399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1295960399
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.2668465647
Short name T1007
Test name
Test status
Simulation time 10980841007 ps
CPU time 21.73 seconds
Started Jul 05 06:09:43 PM PDT 24
Finished Jul 05 06:10:06 PM PDT 24
Peak memory 224600 kb
Host smart-29411c51-1b72-4bac-813b-685702bd39fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668465647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.2668465647
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2824551883
Short name T471
Test name
Test status
Simulation time 29369439353 ps
CPU time 44.99 seconds
Started Jul 05 06:09:44 PM PDT 24
Finished Jul 05 06:10:30 PM PDT 24
Peak memory 236700 kb
Host smart-40966305-883d-41bb-a3c2-4458aac925be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824551883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2824551883
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.1362441516
Short name T342
Test name
Test status
Simulation time 7500940435 ps
CPU time 13.53 seconds
Started Jul 05 06:09:39 PM PDT 24
Finished Jul 05 06:09:53 PM PDT 24
Peak memory 232804 kb
Host smart-599e93e0-92a2-4bea-87f9-5bf210480273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362441516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.1362441516
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.3673184061
Short name T986
Test name
Test status
Simulation time 10640424962 ps
CPU time 33.56 seconds
Started Jul 05 06:09:49 PM PDT 24
Finished Jul 05 06:10:23 PM PDT 24
Peak memory 232788 kb
Host smart-0a67f77d-ebfa-4fa3-8294-cb6332813111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673184061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.3673184061
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.195427945
Short name T626
Test name
Test status
Simulation time 1126555141 ps
CPU time 11.76 seconds
Started Jul 05 06:09:49 PM PDT 24
Finished Jul 05 06:10:01 PM PDT 24
Peak memory 219320 kb
Host smart-7ec2a39d-c333-47c8-94db-eeac223905b3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=195427945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dire
ct.195427945
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.2956698891
Short name T181
Test name
Test status
Simulation time 106229118024 ps
CPU time 280.57 seconds
Started Jul 05 06:09:41 PM PDT 24
Finished Jul 05 06:14:22 PM PDT 24
Peak memory 257404 kb
Host smart-85c9b97b-d69d-4b75-beeb-2e36448756c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2956698891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.2956698891
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1696642182
Short name T28
Test name
Test status
Simulation time 8564927646 ps
CPU time 23.75 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:10:12 PM PDT 24
Peak memory 216536 kb
Host smart-fdeeb7a7-b7e0-4d20-aade-6cf4cf68bfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696642182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1696642182
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.4254216247
Short name T289
Test name
Test status
Simulation time 3143210518 ps
CPU time 10.78 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:09:59 PM PDT 24
Peak memory 216344 kb
Host smart-433bcabc-415c-4633-8059-02036957bc95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254216247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.4254216247
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.1009987439
Short name T585
Test name
Test status
Simulation time 148329736 ps
CPU time 2.73 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:09:46 PM PDT 24
Peak memory 216272 kb
Host smart-100b6cfe-3998-413f-8642-c57161a2ee29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009987439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.1009987439
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.1860074997
Short name T457
Test name
Test status
Simulation time 57059977 ps
CPU time 0.82 seconds
Started Jul 05 06:09:43 PM PDT 24
Finished Jul 05 06:09:45 PM PDT 24
Peak memory 206008 kb
Host smart-5cc39420-87a4-42e6-b3c3-4ed266f7c873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860074997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.1860074997
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.832447269
Short name T222
Test name
Test status
Simulation time 15076582421 ps
CPU time 7.23 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:09:50 PM PDT 24
Peak memory 232836 kb
Host smart-0924666d-3952-49e0-ab43-a28546c7dc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832447269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.832447269
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.1221521198
Short name T458
Test name
Test status
Simulation time 12638064 ps
CPU time 0.71 seconds
Started Jul 05 06:09:54 PM PDT 24
Finished Jul 05 06:09:55 PM PDT 24
Peak memory 205540 kb
Host smart-5cc3ff7e-dbce-4641-be28-cceaa12b0d3f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1221521198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
1221521198
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3736435937
Short name T580
Test name
Test status
Simulation time 269400309 ps
CPU time 2.32 seconds
Started Jul 05 06:09:43 PM PDT 24
Finished Jul 05 06:09:47 PM PDT 24
Peak memory 224152 kb
Host smart-a6e2afa4-31a0-458e-bb33-2e3470e829f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736435937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3736435937
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.286999964
Short name T329
Test name
Test status
Simulation time 36372847 ps
CPU time 0.72 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:09:50 PM PDT 24
Peak memory 206940 kb
Host smart-364b24cc-e76a-423a-a4e8-b838aaaf6573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286999964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.286999964
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.4194554269
Short name T748
Test name
Test status
Simulation time 1407054344 ps
CPU time 9.12 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:10:06 PM PDT 24
Peak memory 224540 kb
Host smart-8dcb9c5b-3478-40de-bdd5-cf42084c8605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194554269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.4194554269
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.297165449
Short name T70
Test name
Test status
Simulation time 4643252610 ps
CPU time 43.88 seconds
Started Jul 05 06:09:43 PM PDT 24
Finished Jul 05 06:10:28 PM PDT 24
Peak memory 249204 kb
Host smart-4fb28c84-329a-439b-8400-4272f4ecb417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297165449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.297165449
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2312748219
Short name T619
Test name
Test status
Simulation time 3370776469 ps
CPU time 28.64 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:10:12 PM PDT 24
Peak memory 253756 kb
Host smart-08642342-7274-4541-a66d-fd3b685e5f95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312748219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2312748219
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.269434454
Short name T268
Test name
Test status
Simulation time 405327735 ps
CPU time 5.97 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:09:50 PM PDT 24
Peak memory 224448 kb
Host smart-337fcf33-bba5-4ff3-87c8-57a4308f7e16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269434454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.269434454
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4028995130
Short name T376
Test name
Test status
Simulation time 807032913 ps
CPU time 5.18 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:10:02 PM PDT 24
Peak memory 224428 kb
Host smart-f8898805-95bf-4e3b-8c18-a9ca022a5c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028995130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4028995130
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.1997413342
Short name T430
Test name
Test status
Simulation time 7105686956 ps
CPU time 61.82 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:10:50 PM PDT 24
Peak memory 240924 kb
Host smart-97166f95-ade6-461e-9ef7-425f76eb5357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997413342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.1997413342
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.944418511
Short name T524
Test name
Test status
Simulation time 2987271445 ps
CPU time 6.73 seconds
Started Jul 05 06:09:43 PM PDT 24
Finished Jul 05 06:09:51 PM PDT 24
Peak memory 232792 kb
Host smart-713f3822-2a9f-4005-a3da-c90b2d0b302a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=944418511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swap
.944418511
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3141760840
Short name T753
Test name
Test status
Simulation time 851806724 ps
CPU time 5.8 seconds
Started Jul 05 06:09:37 PM PDT 24
Finished Jul 05 06:09:44 PM PDT 24
Peak memory 232684 kb
Host smart-1f665cd3-5aa8-4037-9c68-767c091d4a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141760840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3141760840
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.4010562421
Short name T583
Test name
Test status
Simulation time 554402836 ps
CPU time 7.86 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:09:52 PM PDT 24
Peak memory 222616 kb
Host smart-9fc52cc9-c0c5-4665-acca-4a5e6ca085fb
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4010562421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.4010562421
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.812764875
Short name T146
Test name
Test status
Simulation time 18822512581 ps
CPU time 113.65 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:11:49 PM PDT 24
Peak memory 256208 kb
Host smart-80295437-7230-4917-8570-dcaa127ca504
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812764875 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stres
s_all.812764875
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.1848580080
Short name T779
Test name
Test status
Simulation time 4725443484 ps
CPU time 20.95 seconds
Started Jul 05 06:09:41 PM PDT 24
Finished Jul 05 06:10:03 PM PDT 24
Peak memory 216264 kb
Host smart-7c2633e7-eb45-4e3a-b136-615cdc44e48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1848580080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.1848580080
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2324854481
Short name T775
Test name
Test status
Simulation time 5774871637 ps
CPU time 17.01 seconds
Started Jul 05 06:09:42 PM PDT 24
Finished Jul 05 06:10:00 PM PDT 24
Peak memory 216400 kb
Host smart-1f4c40bd-6b9c-47de-b4d4-4cfc3075608f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324854481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2324854481
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.3933210778
Short name T386
Test name
Test status
Simulation time 355867300 ps
CPU time 2.19 seconds
Started Jul 05 06:09:40 PM PDT 24
Finished Jul 05 06:09:42 PM PDT 24
Peak memory 216112 kb
Host smart-0a631374-de1a-45d6-9ef1-6a4176c3d99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933210778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.3933210778
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2962434559
Short name T24
Test name
Test status
Simulation time 146510330 ps
CPU time 1.02 seconds
Started Jul 05 06:09:43 PM PDT 24
Finished Jul 05 06:09:45 PM PDT 24
Peak memory 207024 kb
Host smart-5b22d2ff-eb67-41fc-b6a0-6f186d0f96d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962434559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2962434559
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.1133832287
Short name T201
Test name
Test status
Simulation time 7202125611 ps
CPU time 12.51 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:10:09 PM PDT 24
Peak memory 224624 kb
Host smart-743c084d-4c2c-4870-b022-61e29041699d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1133832287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.1133832287
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.2060147294
Short name T346
Test name
Test status
Simulation time 13574333 ps
CPU time 0.75 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:09:49 PM PDT 24
Peak memory 205524 kb
Host smart-76703bd2-d48b-4cee-8792-2920aa007be1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060147294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
2060147294
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.812090252
Short name T617
Test name
Test status
Simulation time 613166018 ps
CPU time 4.71 seconds
Started Jul 05 06:09:47 PM PDT 24
Finished Jul 05 06:09:52 PM PDT 24
Peak memory 224460 kb
Host smart-098dcec3-0b16-4784-9bce-ad6225a3ef7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812090252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.812090252
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.1877223188
Short name T702
Test name
Test status
Simulation time 29933316 ps
CPU time 0.83 seconds
Started Jul 05 06:09:49 PM PDT 24
Finished Jul 05 06:09:50 PM PDT 24
Peak memory 205564 kb
Host smart-ce93f935-523b-4030-9702-f98196afc309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877223188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.1877223188
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2978169311
Short name T736
Test name
Test status
Simulation time 2913619782 ps
CPU time 36.8 seconds
Started Jul 05 06:09:57 PM PDT 24
Finished Jul 05 06:10:35 PM PDT 24
Peak memory 249192 kb
Host smart-606d4dcb-01d5-497d-8f31-79a39487149d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978169311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2978169311
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3951269849
Short name T535
Test name
Test status
Simulation time 33297833363 ps
CPU time 250.27 seconds
Started Jul 05 06:09:57 PM PDT 24
Finished Jul 05 06:14:08 PM PDT 24
Peak memory 255076 kb
Host smart-0f02097b-e63e-497e-a100-108e6255bb4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951269849 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3951269849
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.327887672
Short name T191
Test name
Test status
Simulation time 4233402514 ps
CPU time 111.43 seconds
Started Jul 05 06:09:44 PM PDT 24
Finished Jul 05 06:11:36 PM PDT 24
Peak memory 266524 kb
Host smart-61effb78-4ca9-449d-a736-c2cd1771614f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327887672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle
.327887672
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.840812209
Short name T961
Test name
Test status
Simulation time 1102794446 ps
CPU time 5.1 seconds
Started Jul 05 06:09:51 PM PDT 24
Finished Jul 05 06:09:57 PM PDT 24
Peak memory 224504 kb
Host smart-95daaae2-9508-466a-a9bf-7311413f8cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=840812209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.840812209
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2212547054
Short name T300
Test name
Test status
Simulation time 37382800 ps
CPU time 0.74 seconds
Started Jul 05 06:09:50 PM PDT 24
Finished Jul 05 06:09:51 PM PDT 24
Peak memory 215804 kb
Host smart-c456df95-e853-4778-91ea-ad6550bffd0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212547054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2212547054
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1409676906
Short name T520
Test name
Test status
Simulation time 1218055964 ps
CPU time 4.62 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:10:00 PM PDT 24
Peak memory 224424 kb
Host smart-3f4ee44a-edf9-4989-9e95-08ca5738e103
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409676906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1409676906
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.4181117054
Short name T799
Test name
Test status
Simulation time 18601391402 ps
CPU time 76.64 seconds
Started Jul 05 06:09:50 PM PDT 24
Finished Jul 05 06:11:08 PM PDT 24
Peak memory 249056 kb
Host smart-d92c55b7-64b2-440f-9d23-ea8d57dd277a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181117054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.4181117054
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.1730662113
Short name T264
Test name
Test status
Simulation time 15288289242 ps
CPU time 12.49 seconds
Started Jul 05 06:09:51 PM PDT 24
Finished Jul 05 06:10:04 PM PDT 24
Peak memory 240688 kb
Host smart-472451ac-b5df-43ef-b5bb-f9e9b2bccc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730662113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.1730662113
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3847290263
Short name T414
Test name
Test status
Simulation time 12473287915 ps
CPU time 20.6 seconds
Started Jul 05 06:09:51 PM PDT 24
Finished Jul 05 06:10:12 PM PDT 24
Peak memory 251796 kb
Host smart-598d786a-14b9-4d56-a04b-8a219bf7e451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847290263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3847290263
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.2267896168
Short name T404
Test name
Test status
Simulation time 283198099 ps
CPU time 3.51 seconds
Started Jul 05 06:09:50 PM PDT 24
Finished Jul 05 06:09:54 PM PDT 24
Peak memory 223160 kb
Host smart-e37090fe-4809-4528-a46c-66c55edf288c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2267896168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dir
ect.2267896168
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3696047475
Short name T360
Test name
Test status
Simulation time 144823135 ps
CPU time 0.98 seconds
Started Jul 05 06:09:47 PM PDT 24
Finished Jul 05 06:09:49 PM PDT 24
Peak memory 206728 kb
Host smart-d9eada09-7ab7-451c-a80b-d174e84b3922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696047475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3696047475
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.4011754835
Short name T513
Test name
Test status
Simulation time 2288138112 ps
CPU time 26.47 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:10:15 PM PDT 24
Peak memory 216292 kb
Host smart-641e6af7-b439-48f2-9217-cc4171ab7e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011754835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.4011754835
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.1369676355
Short name T367
Test name
Test status
Simulation time 12857428 ps
CPU time 0.72 seconds
Started Jul 05 06:09:47 PM PDT 24
Finished Jul 05 06:09:48 PM PDT 24
Peak memory 205640 kb
Host smart-32556868-bd39-4a9b-842c-fc53627534c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369676355 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.1369676355
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.2120926798
Short name T282
Test name
Test status
Simulation time 59487114 ps
CPU time 1.53 seconds
Started Jul 05 06:09:47 PM PDT 24
Finished Jul 05 06:09:49 PM PDT 24
Peak memory 216172 kb
Host smart-f01dc83f-d839-431d-bfd8-41ade2048760
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120926798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.2120926798
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.2263755225
Short name T410
Test name
Test status
Simulation time 115373863 ps
CPU time 0.89 seconds
Started Jul 05 06:09:47 PM PDT 24
Finished Jul 05 06:09:48 PM PDT 24
Peak memory 207024 kb
Host smart-a5b0492e-cac0-46aa-96e1-228dcea8177d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263755225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.2263755225
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.3919614073
Short name T965
Test name
Test status
Simulation time 487820372 ps
CPU time 2.61 seconds
Started Jul 05 06:09:51 PM PDT 24
Finished Jul 05 06:09:54 PM PDT 24
Peak memory 224468 kb
Host smart-5d78a169-fa87-4c8e-a1a0-97a33e0c21a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919614073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.3919614073
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.966293475
Short name T552
Test name
Test status
Simulation time 13001752 ps
CPU time 0.76 seconds
Started Jul 05 06:09:49 PM PDT 24
Finished Jul 05 06:09:51 PM PDT 24
Peak memory 204980 kb
Host smart-03a10322-9e5c-4fe9-8523-a48b8d8e721a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=966293475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.966293475
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.1633223477
Short name T829
Test name
Test status
Simulation time 89697810 ps
CPU time 3.59 seconds
Started Jul 05 06:09:50 PM PDT 24
Finished Jul 05 06:09:55 PM PDT 24
Peak memory 232608 kb
Host smart-fa689bd2-d942-4b80-83f2-542be679b589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633223477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.1633223477
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.3083993506
Short name T11
Test name
Test status
Simulation time 98977194 ps
CPU time 0.79 seconds
Started Jul 05 06:09:51 PM PDT 24
Finished Jul 05 06:09:52 PM PDT 24
Peak memory 206876 kb
Host smart-fb09fae5-81d1-4b07-816b-6b1a0ece5bab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083993506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.3083993506
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.3435135997
Short name T790
Test name
Test status
Simulation time 1108718007 ps
CPU time 20.56 seconds
Started Jul 05 06:09:50 PM PDT 24
Finished Jul 05 06:10:11 PM PDT 24
Peak memory 244540 kb
Host smart-d1b44659-a553-4f8a-8532-37bd956154cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435135997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.3435135997
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3943880957
Short name T652
Test name
Test status
Simulation time 11288604938 ps
CPU time 96.75 seconds
Started Jul 05 06:09:57 PM PDT 24
Finished Jul 05 06:11:35 PM PDT 24
Peak memory 253876 kb
Host smart-ac919ca9-d1d8-4d98-8352-feb34f6cae6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3943880957 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3943880957
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.2885281119
Short name T117
Test name
Test status
Simulation time 8203707132 ps
CPU time 107.2 seconds
Started Jul 05 06:09:49 PM PDT 24
Finished Jul 05 06:11:37 PM PDT 24
Peak memory 269072 kb
Host smart-dbb0d5fa-a5fa-46f0-9981-7b14f3e07d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885281119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.2885281119
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.3937314493
Short name T880
Test name
Test status
Simulation time 299657489 ps
CPU time 2.65 seconds
Started Jul 05 06:09:50 PM PDT 24
Finished Jul 05 06:09:54 PM PDT 24
Peak memory 224472 kb
Host smart-28912f77-2c7d-4a48-a50d-801d69a525c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937314493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.3937314493
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.3493620642
Short name T604
Test name
Test status
Simulation time 5586920722 ps
CPU time 42.37 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:10:38 PM PDT 24
Peak memory 237480 kb
Host smart-7f37f1cf-8650-4df6-b85b-e76db66ea095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493620642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.3493620642
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.1033257893
Short name T727
Test name
Test status
Simulation time 128428073 ps
CPU time 2.52 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:09:52 PM PDT 24
Peak memory 232708 kb
Host smart-8122e453-f234-4a76-8cbe-7b0fd1ae40a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033257893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.1033257893
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.2907080316
Short name T873
Test name
Test status
Simulation time 2544092773 ps
CPU time 23.65 seconds
Started Jul 05 06:09:50 PM PDT 24
Finished Jul 05 06:10:14 PM PDT 24
Peak memory 236908 kb
Host smart-f15362b4-eed1-4284-984e-b9cc33f57b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907080316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.2907080316
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.1256503919
Short name T954
Test name
Test status
Simulation time 1548797732 ps
CPU time 5.49 seconds
Started Jul 05 06:09:51 PM PDT 24
Finished Jul 05 06:09:57 PM PDT 24
Peak memory 232684 kb
Host smart-e10b614c-ff93-4a30-af60-78914d0e1456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256503919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.1256503919
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.2270695376
Short name T973
Test name
Test status
Simulation time 129686519 ps
CPU time 2.4 seconds
Started Jul 05 06:09:50 PM PDT 24
Finished Jul 05 06:09:53 PM PDT 24
Peak memory 232316 kb
Host smart-e6e85d56-2043-4c93-b3a7-a9fff4a95619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270695376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.2270695376
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.1331191630
Short name T486
Test name
Test status
Simulation time 196096140 ps
CPU time 4.55 seconds
Started Jul 05 06:09:51 PM PDT 24
Finished Jul 05 06:09:56 PM PDT 24
Peak memory 219256 kb
Host smart-dfb05de2-1692-40c9-9fd9-9f455fa933e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1331191630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.1331191630
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.639423907
Short name T149
Test name
Test status
Simulation time 280553080 ps
CPU time 1.1 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:09:50 PM PDT 24
Peak memory 206908 kb
Host smart-efcc8e8e-4472-4773-9eb7-132ebc693363
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639423907 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.639423907
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.4007223168
Short name T517
Test name
Test status
Simulation time 4808054313 ps
CPU time 13.11 seconds
Started Jul 05 06:09:54 PM PDT 24
Finished Jul 05 06:10:07 PM PDT 24
Peak memory 217884 kb
Host smart-ae9f94d3-1fe4-432e-a392-375ab535dac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007223168 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.4007223168
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.267452148
Short name T678
Test name
Test status
Simulation time 15832283420 ps
CPU time 20.08 seconds
Started Jul 05 06:09:48 PM PDT 24
Finished Jul 05 06:10:09 PM PDT 24
Peak memory 216352 kb
Host smart-85aa54a8-c4f5-462b-a987-4589d15b9db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267452148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.267452148
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.72403419
Short name T863
Test name
Test status
Simulation time 209190636 ps
CPU time 2.32 seconds
Started Jul 05 06:09:50 PM PDT 24
Finished Jul 05 06:09:54 PM PDT 24
Peak memory 216180 kb
Host smart-67431b81-f96f-41ca-811d-440de8a0d324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72403419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.72403419
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.543599937
Short name T468
Test name
Test status
Simulation time 205066470 ps
CPU time 0.95 seconds
Started Jul 05 06:09:45 PM PDT 24
Finished Jul 05 06:09:46 PM PDT 24
Peak memory 206976 kb
Host smart-6928249d-3635-41eb-bf58-bce51befef6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543599937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.543599937
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3403307813
Short name T903
Test name
Test status
Simulation time 2085163907 ps
CPU time 8.69 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:10:06 PM PDT 24
Peak memory 239880 kb
Host smart-a5751da3-906d-4d46-ab4d-714b82fe4302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403307813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3403307813
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.3254316395
Short name T336
Test name
Test status
Simulation time 42584073 ps
CPU time 0.74 seconds
Started Jul 05 06:07:40 PM PDT 24
Finished Jul 05 06:07:41 PM PDT 24
Peak memory 204980 kb
Host smart-590fd17e-0426-4501-8cd7-b784884f06e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254316395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.3
254316395
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.1799573912
Short name T576
Test name
Test status
Simulation time 46544347 ps
CPU time 2.59 seconds
Started Jul 05 06:07:36 PM PDT 24
Finished Jul 05 06:07:39 PM PDT 24
Peak memory 232640 kb
Host smart-6d4611b5-8d1b-4ecb-bac2-4ad1c36d1764
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799573912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.1799573912
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.794291105
Short name T396
Test name
Test status
Simulation time 20056713 ps
CPU time 0.76 seconds
Started Jul 05 06:07:38 PM PDT 24
Finished Jul 05 06:07:40 PM PDT 24
Peak memory 206640 kb
Host smart-7e4ccd08-5586-463b-b16b-0a20f412541b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794291105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.794291105
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.3035829170
Short name T922
Test name
Test status
Simulation time 12157673831 ps
CPU time 57.56 seconds
Started Jul 05 06:07:33 PM PDT 24
Finished Jul 05 06:08:31 PM PDT 24
Peak memory 252904 kb
Host smart-11558615-7fd6-4818-9c0e-48bacf3dda60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035829170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.3035829170
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2378360850
Short name T480
Test name
Test status
Simulation time 5952101681 ps
CPU time 19.74 seconds
Started Jul 05 06:07:35 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 237192 kb
Host smart-2884cf83-cab4-4a60-9679-804a402fb0b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2378360850 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2378360850
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2819477567
Short name T249
Test name
Test status
Simulation time 57216740427 ps
CPU time 538.47 seconds
Started Jul 05 06:07:35 PM PDT 24
Finished Jul 05 06:16:34 PM PDT 24
Peak memory 265232 kb
Host smart-ab0313a8-abfa-4b40-a8ba-9cdb78391cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819477567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2819477567
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.2304228591
Short name T876
Test name
Test status
Simulation time 3237508897 ps
CPU time 12.68 seconds
Started Jul 05 06:07:32 PM PDT 24
Finished Jul 05 06:07:45 PM PDT 24
Peak memory 224616 kb
Host smart-6bb1bbf8-4b79-46d5-8dd1-1b27d3184898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304228591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.2304228591
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.763706930
Short name T642
Test name
Test status
Simulation time 23823980529 ps
CPU time 195.31 seconds
Started Jul 05 06:07:37 PM PDT 24
Finished Jul 05 06:10:52 PM PDT 24
Peak memory 249240 kb
Host smart-0b3ff772-86ff-4f70-92db-061b0d637564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763706930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
763706930
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1513344009
Short name T908
Test name
Test status
Simulation time 323317701 ps
CPU time 3.6 seconds
Started Jul 05 06:07:36 PM PDT 24
Finished Jul 05 06:07:40 PM PDT 24
Peak memory 224504 kb
Host smart-bfd39cff-9a35-4604-8c07-ae53673cbfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513344009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1513344009
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1935495755
Short name T351
Test name
Test status
Simulation time 116037929 ps
CPU time 2.46 seconds
Started Jul 05 06:07:35 PM PDT 24
Finished Jul 05 06:07:38 PM PDT 24
Peak memory 232356 kb
Host smart-5c5e3c6d-7c6d-40db-aca8-b8b6f93342a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935495755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1935495755
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.924627615
Short name T429
Test name
Test status
Simulation time 347680843 ps
CPU time 3.3 seconds
Started Jul 05 06:07:34 PM PDT 24
Finished Jul 05 06:07:37 PM PDT 24
Peak memory 232732 kb
Host smart-8fb93379-1f11-4f60-bb57-04186818392d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=924627615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
924627615
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.4093379968
Short name T566
Test name
Test status
Simulation time 27884564 ps
CPU time 2.2 seconds
Started Jul 05 06:07:33 PM PDT 24
Finished Jul 05 06:07:36 PM PDT 24
Peak memory 223648 kb
Host smart-75d45bf3-1a72-4f7a-a458-e1d7e3252a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093379968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.4093379968
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.345378813
Short name T356
Test name
Test status
Simulation time 4456388261 ps
CPU time 7.69 seconds
Started Jul 05 06:07:38 PM PDT 24
Finished Jul 05 06:07:46 PM PDT 24
Peak memory 219004 kb
Host smart-d751526f-f761-4761-adf7-1359e42efebc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=345378813 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.345378813
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.1900794103
Short name T32
Test name
Test status
Simulation time 34977800 ps
CPU time 1 seconds
Started Jul 05 06:07:32 PM PDT 24
Finished Jul 05 06:07:33 PM PDT 24
Peak memory 236612 kb
Host smart-3a40a91f-1b7a-4b35-84c0-f5207d0050c5
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900794103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.1900794103
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.2857714510
Short name T792
Test name
Test status
Simulation time 90913530029 ps
CPU time 36.91 seconds
Started Jul 05 06:07:36 PM PDT 24
Finished Jul 05 06:08:14 PM PDT 24
Peak memory 216368 kb
Host smart-bccb3bc9-e4af-42f7-ac42-3d3ecce0b79c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857714510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.2857714510
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.3945607838
Short name T312
Test name
Test status
Simulation time 1830698058 ps
CPU time 5.45 seconds
Started Jul 05 06:07:37 PM PDT 24
Finished Jul 05 06:07:43 PM PDT 24
Peak memory 216144 kb
Host smart-2a24da4d-c5a5-446c-9f79-423b4f4a662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945607838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.3945607838
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.2141401456
Short name T654
Test name
Test status
Simulation time 90134793 ps
CPU time 0.79 seconds
Started Jul 05 06:07:34 PM PDT 24
Finished Jul 05 06:07:36 PM PDT 24
Peak memory 206072 kb
Host smart-e23f4117-b2f4-4fe0-8224-e1bbb5cf0a5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141401456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.2141401456
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.4120263468
Short name T680
Test name
Test status
Simulation time 19485297 ps
CPU time 0.79 seconds
Started Jul 05 06:07:37 PM PDT 24
Finished Jul 05 06:07:38 PM PDT 24
Peak memory 205996 kb
Host smart-8343dd2b-0a0d-4cc2-8f5d-11a18b8ceab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120263468 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.4120263468
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2782049385
Short name T325
Test name
Test status
Simulation time 97406069 ps
CPU time 2.42 seconds
Started Jul 05 06:07:39 PM PDT 24
Finished Jul 05 06:07:42 PM PDT 24
Peak memory 224088 kb
Host smart-df778d48-f0ce-42a9-9b6e-1e0e6c88b46c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782049385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2782049385
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.693289192
Short name T1003
Test name
Test status
Simulation time 13717798 ps
CPU time 0.75 seconds
Started Jul 05 06:09:58 PM PDT 24
Finished Jul 05 06:10:00 PM PDT 24
Peak memory 204960 kb
Host smart-c18e8cf9-62d4-4cf6-b439-4038f17f280e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693289192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.693289192
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.621607821
Short name T7
Test name
Test status
Simulation time 5176387983 ps
CPU time 14.28 seconds
Started Jul 05 06:09:58 PM PDT 24
Finished Jul 05 06:10:13 PM PDT 24
Peak memory 232804 kb
Host smart-23e871f8-b9ad-4070-8c21-7321b147fb64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621607821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.621607821
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.1892263253
Short name T352
Test name
Test status
Simulation time 39406563 ps
CPU time 0.77 seconds
Started Jul 05 06:09:49 PM PDT 24
Finished Jul 05 06:09:51 PM PDT 24
Peak memory 206632 kb
Host smart-86d25bea-adb1-4da7-ad6c-863b19608eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892263253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.1892263253
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1661279489
Short name T55
Test name
Test status
Simulation time 159220476 ps
CPU time 0.91 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:09:58 PM PDT 24
Peak memory 215932 kb
Host smart-3921130d-b27c-425b-a570-4e501fe96a6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661279489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1661279489
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.504396704
Short name T593
Test name
Test status
Simulation time 28323465433 ps
CPU time 113.98 seconds
Started Jul 05 06:09:53 PM PDT 24
Finished Jul 05 06:11:48 PM PDT 24
Peak memory 256724 kb
Host smart-a816b773-94b6-4400-b9bf-1202aeb74ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504396704 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.504396704
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.2629488870
Short name T814
Test name
Test status
Simulation time 3849767475 ps
CPU time 31.72 seconds
Started Jul 05 06:09:57 PM PDT 24
Finished Jul 05 06:10:29 PM PDT 24
Peak memory 239920 kb
Host smart-0980297b-de2c-4b9e-979d-57918ad2a388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629488870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.2629488870
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3440637118
Short name T878
Test name
Test status
Simulation time 10455460561 ps
CPU time 11.66 seconds
Started Jul 05 06:09:58 PM PDT 24
Finished Jul 05 06:10:11 PM PDT 24
Peak memory 224536 kb
Host smart-3e4a7374-21e1-4cd0-929a-075a83a1cb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440637118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3440637118
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.841706936
Short name T842
Test name
Test status
Simulation time 860767518 ps
CPU time 7.95 seconds
Started Jul 05 06:09:59 PM PDT 24
Finished Jul 05 06:10:08 PM PDT 24
Peak memory 224492 kb
Host smart-80873645-d631-4600-be8a-e474c762f27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841706936 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.841706936
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.1710635886
Short name T302
Test name
Test status
Simulation time 273651002 ps
CPU time 2.25 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:09:58 PM PDT 24
Peak memory 232668 kb
Host smart-639c7c64-f42a-4e90-acf0-00832637c63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710635886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.1710635886
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.2065152745
Short name T550
Test name
Test status
Simulation time 109679025 ps
CPU time 2.11 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:09:58 PM PDT 24
Peak memory 223876 kb
Host smart-7cc5429d-1296-4964-b7a0-49927aa4c80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065152745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.2065152745
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.125614567
Short name T599
Test name
Test status
Simulation time 7733480009 ps
CPU time 12.17 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:10:09 PM PDT 24
Peak memory 232832 kb
Host smart-8006c66f-8ded-44af-ae1f-3ae8f9e414f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125614567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.125614567
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.2030804035
Short name T735
Test name
Test status
Simulation time 474715704 ps
CPU time 3.73 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:09:59 PM PDT 24
Peak memory 232652 kb
Host smart-2ab875cd-cbe4-42e9-9f3b-7226902d4034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030804035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.2030804035
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.3992152736
Short name T772
Test name
Test status
Simulation time 2989062579 ps
CPU time 6.1 seconds
Started Jul 05 06:09:58 PM PDT 24
Finished Jul 05 06:10:05 PM PDT 24
Peak memory 221384 kb
Host smart-66115bb2-6b88-4de7-a5f5-2fd538e03b7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3992152736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.3992152736
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1503054351
Short name T29
Test name
Test status
Simulation time 6692909851 ps
CPU time 96.54 seconds
Started Jul 05 06:09:59 PM PDT 24
Finished Jul 05 06:11:37 PM PDT 24
Peak memory 254844 kb
Host smart-a0c9a9a2-2eff-44dd-add3-56c67655f8da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1503054351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1503054351
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2708511121
Short name T450
Test name
Test status
Simulation time 87528872358 ps
CPU time 49.77 seconds
Started Jul 05 06:09:54 PM PDT 24
Finished Jul 05 06:10:45 PM PDT 24
Peak memory 216344 kb
Host smart-79767b38-b3ef-4656-9371-6131182664f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2708511121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2708511121
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.2488029685
Short name T757
Test name
Test status
Simulation time 4223126627 ps
CPU time 7.13 seconds
Started Jul 05 06:09:51 PM PDT 24
Finished Jul 05 06:09:59 PM PDT 24
Peak memory 216304 kb
Host smart-be7d5fdd-d918-457b-b9ca-074464ff1fcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488029685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.2488029685
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.1651294578
Short name T285
Test name
Test status
Simulation time 71156380 ps
CPU time 1.33 seconds
Started Jul 05 06:11:40 PM PDT 24
Finished Jul 05 06:11:41 PM PDT 24
Peak memory 216236 kb
Host smart-94498387-5aa5-498e-b5a5-443b6194b092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651294578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.1651294578
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.1286885636
Short name T555
Test name
Test status
Simulation time 29014322 ps
CPU time 0.78 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:09:56 PM PDT 24
Peak memory 206004 kb
Host smart-2726c251-a00c-4a3b-814b-598802162a55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286885636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.1286885636
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.3222920692
Short name T180
Test name
Test status
Simulation time 303051693 ps
CPU time 2.69 seconds
Started Jul 05 06:09:59 PM PDT 24
Finished Jul 05 06:10:03 PM PDT 24
Peak memory 236788 kb
Host smart-eea4d095-1637-43e8-adc5-faf9b140dae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222920692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.3222920692
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.3233164294
Short name T405
Test name
Test status
Simulation time 11923770 ps
CPU time 0.7 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:09:56 PM PDT 24
Peak memory 205536 kb
Host smart-b0ffe400-675d-42cd-bb0f-5bcaaaea18c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233164294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
3233164294
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.2925114615
Short name T767
Test name
Test status
Simulation time 127349801 ps
CPU time 2.49 seconds
Started Jul 05 06:09:59 PM PDT 24
Finished Jul 05 06:10:03 PM PDT 24
Peak memory 224504 kb
Host smart-6b2617fa-0db0-409d-ae71-2e3492b18556
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925114615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.2925114615
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.2948477989
Short name T782
Test name
Test status
Simulation time 17736201 ps
CPU time 0.76 seconds
Started Jul 05 06:09:57 PM PDT 24
Finished Jul 05 06:09:58 PM PDT 24
Peak memory 206940 kb
Host smart-9dff1100-62d4-4c49-96f9-570229310f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948477989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.2948477989
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4117597166
Short name T195
Test name
Test status
Simulation time 23495388982 ps
CPU time 71.59 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:11:09 PM PDT 24
Peak memory 255244 kb
Host smart-77e2ebb1-56d2-42bc-8d54-ce95025425b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117597166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4117597166
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3420882919
Short name T355
Test name
Test status
Simulation time 173299437046 ps
CPU time 394.82 seconds
Started Jul 05 06:09:59 PM PDT 24
Finished Jul 05 06:16:35 PM PDT 24
Peak memory 261436 kb
Host smart-608fc7b1-2b55-4d74-b081-eff0657fdf18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420882919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3420882919
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.2022260059
Short name T510
Test name
Test status
Simulation time 53775592535 ps
CPU time 219.37 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:13:35 PM PDT 24
Peak memory 252980 kb
Host smart-6ee2e608-27a6-4efd-a04d-6626ca11eb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022260059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.2022260059
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.2110042226
Short name T488
Test name
Test status
Simulation time 1281938335 ps
CPU time 17.32 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:10:14 PM PDT 24
Peak memory 238544 kb
Host smart-7cd95eae-9f8a-4a3c-a1e9-eac158404cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110042226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.2110042226
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.2026743832
Short name T242
Test name
Test status
Simulation time 6664144050 ps
CPU time 85.83 seconds
Started Jul 05 06:09:58 PM PDT 24
Finished Jul 05 06:11:25 PM PDT 24
Peak memory 255228 kb
Host smart-1f045cc8-477d-4b0b-938b-e122a0ef2867
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026743832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.2026743832
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.3096783481
Short name T833
Test name
Test status
Simulation time 2528104363 ps
CPU time 14.22 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:10:11 PM PDT 24
Peak memory 232788 kb
Host smart-837e89c5-dffa-4598-bbcc-f1e8fe927472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096783481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.3096783481
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.3313277159
Short name T892
Test name
Test status
Simulation time 11309401123 ps
CPU time 51.51 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:10:49 PM PDT 24
Peak memory 239372 kb
Host smart-c8af7145-5f0b-4523-a9d5-65d4aeec0305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313277159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.3313277159
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1514495304
Short name T523
Test name
Test status
Simulation time 1902951244 ps
CPU time 4.38 seconds
Started Jul 05 06:09:58 PM PDT 24
Finished Jul 05 06:10:03 PM PDT 24
Peak memory 232624 kb
Host smart-a528ded8-d27a-46bb-af41-de8898100dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514495304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1514495304
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.2811373053
Short name T771
Test name
Test status
Simulation time 29904814760 ps
CPU time 27.47 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:10:24 PM PDT 24
Peak memory 232800 kb
Host smart-b44164e4-f9b9-4e9d-a099-1ec3813accd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811373053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.2811373053
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.3336631089
Short name T42
Test name
Test status
Simulation time 1283298032 ps
CPU time 6.21 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:10:04 PM PDT 24
Peak memory 220600 kb
Host smart-cb63d4b8-f77c-4c6a-a9f6-4c1031b05c6b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3336631089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.3336631089
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3096933380
Short name T615
Test name
Test status
Simulation time 37165795 ps
CPU time 0.96 seconds
Started Jul 05 06:09:58 PM PDT 24
Finished Jul 05 06:10:00 PM PDT 24
Peak memory 207572 kb
Host smart-72a2ceb7-85ae-490c-a642-66e35084adcc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096933380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3096933380
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2874572913
Short name T278
Test name
Test status
Simulation time 3322833376 ps
CPU time 15.25 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:10:13 PM PDT 24
Peak memory 216652 kb
Host smart-223c645b-c4dc-4e60-986e-a293086fea3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874572913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2874572913
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.570399183
Short name T481
Test name
Test status
Simulation time 698291553 ps
CPU time 5.32 seconds
Started Jul 05 06:09:59 PM PDT 24
Finished Jul 05 06:10:05 PM PDT 24
Peak memory 216228 kb
Host smart-ba60e67b-a1ff-4630-98d8-32d7ac6c5e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570399183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.570399183
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.372183533
Short name T694
Test name
Test status
Simulation time 792545035 ps
CPU time 4.23 seconds
Started Jul 05 06:09:56 PM PDT 24
Finished Jul 05 06:10:01 PM PDT 24
Peak memory 216172 kb
Host smart-54c62251-315d-40b8-af5c-3cbe91741930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372183533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.372183533
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2200460248
Short name T586
Test name
Test status
Simulation time 159341568 ps
CPU time 0.82 seconds
Started Jul 05 06:09:55 PM PDT 24
Finished Jul 05 06:09:57 PM PDT 24
Peak memory 206004 kb
Host smart-d533517d-1386-4201-8d03-dbf0ddead2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200460248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2200460248
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.209270013
Short name T984
Test name
Test status
Simulation time 2259512389 ps
CPU time 9.51 seconds
Started Jul 05 06:09:57 PM PDT 24
Finished Jul 05 06:10:07 PM PDT 24
Peak memory 232676 kb
Host smart-872df6b8-2d4b-46e7-8deb-6344f7c1107c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209270013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.209270013
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.2075320817
Short name T62
Test name
Test status
Simulation time 29113942 ps
CPU time 0.69 seconds
Started Jul 05 06:10:04 PM PDT 24
Finished Jul 05 06:10:05 PM PDT 24
Peak memory 204956 kb
Host smart-a838ac4c-4ec7-420b-9cc6-f92a3f1876e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075320817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
2075320817
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.1188594553
Short name T229
Test name
Test status
Simulation time 1055981610 ps
CPU time 6.1 seconds
Started Jul 05 06:10:04 PM PDT 24
Finished Jul 05 06:10:11 PM PDT 24
Peak memory 224284 kb
Host smart-fafd28b2-e4ff-4716-87ed-24bb106ec1c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188594553 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.1188594553
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.2602609483
Short name T983
Test name
Test status
Simulation time 39301287 ps
CPU time 0.8 seconds
Started Jul 05 06:09:57 PM PDT 24
Finished Jul 05 06:09:59 PM PDT 24
Peak memory 205548 kb
Host smart-dcc7d573-b791-4fc2-93c7-1696ea0c9717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602609483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.2602609483
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1722361065
Short name T186
Test name
Test status
Simulation time 162838437871 ps
CPU time 304.22 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:15:07 PM PDT 24
Peak memory 251744 kb
Host smart-9f83bff9-31d2-40e4-bb0c-16aeaa4791f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722361065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1722361065
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.850322422
Short name T39
Test name
Test status
Simulation time 92596437435 ps
CPU time 151.58 seconds
Started Jul 05 06:10:04 PM PDT 24
Finished Jul 05 06:12:36 PM PDT 24
Peak memory 248776 kb
Host smart-ae2cd3e7-e2f5-459e-b88c-5b2a05441105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850322422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.850322422
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1803091187
Short name T751
Test name
Test status
Simulation time 19734683453 ps
CPU time 147.96 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:12:30 PM PDT 24
Peak memory 249296 kb
Host smart-7976c5ef-71a9-4492-be83-6ef2c71bef77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803091187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1803091187
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.1379307264
Short name T970
Test name
Test status
Simulation time 448403688 ps
CPU time 5.23 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:10:08 PM PDT 24
Peak memory 240036 kb
Host smart-dc464f72-9876-4012-9aae-1d010b9b277e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379307264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.1379307264
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.4147231339
Short name T536
Test name
Test status
Simulation time 586780268 ps
CPU time 8.43 seconds
Started Jul 05 06:10:04 PM PDT 24
Finished Jul 05 06:10:13 PM PDT 24
Peak memory 232724 kb
Host smart-ebc21007-d3ad-4121-9899-1d4e4f3e264a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4147231339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.4147231339
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1903242230
Short name T216
Test name
Test status
Simulation time 2621580396 ps
CPU time 4.04 seconds
Started Jul 05 06:10:04 PM PDT 24
Finished Jul 05 06:10:09 PM PDT 24
Peak memory 232856 kb
Host smart-cd0c02ae-f302-4b09-9be4-a7c2958b6c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903242230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1903242230
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.4141250928
Short name T802
Test name
Test status
Simulation time 268527121 ps
CPU time 7.02 seconds
Started Jul 05 06:10:01 PM PDT 24
Finished Jul 05 06:10:08 PM PDT 24
Peak memory 232680 kb
Host smart-0cc1d78d-07b8-4bed-bfe1-0e59022d8bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141250928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.4141250928
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.2791624106
Short name T259
Test name
Test status
Simulation time 4876633147 ps
CPU time 11.57 seconds
Started Jul 05 06:10:03 PM PDT 24
Finished Jul 05 06:10:16 PM PDT 24
Peak memory 234764 kb
Host smart-e9364981-5952-42a5-85a9-b9748f94ddf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791624106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.2791624106
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1030674705
Short name T559
Test name
Test status
Simulation time 1555181670 ps
CPU time 8.82 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:10:12 PM PDT 24
Peak memory 232660 kb
Host smart-47e921df-6049-479c-aabf-d6399f6ac00c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030674705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1030674705
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.4073630267
Short name T958
Test name
Test status
Simulation time 181353458 ps
CPU time 3.65 seconds
Started Jul 05 06:10:03 PM PDT 24
Finished Jul 05 06:10:08 PM PDT 24
Peak memory 220540 kb
Host smart-af0cab9f-aa3b-40ae-9e31-1b9d5166721f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4073630267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.4073630267
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2840651877
Short name T425
Test name
Test status
Simulation time 8883121078 ps
CPU time 22.88 seconds
Started Jul 05 06:10:03 PM PDT 24
Finished Jul 05 06:10:27 PM PDT 24
Peak memory 224568 kb
Host smart-b38d339f-563e-4d78-ba4a-4f614510f3a7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2840651877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2840651877
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.687804071
Short name T120
Test name
Test status
Simulation time 3760581151 ps
CPU time 18.13 seconds
Started Jul 05 06:10:06 PM PDT 24
Finished Jul 05 06:10:25 PM PDT 24
Peak memory 216320 kb
Host smart-db140cd8-52a3-417b-94a1-127eb562c762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687804071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.687804071
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.115337953
Short name T515
Test name
Test status
Simulation time 12766952903 ps
CPU time 10.06 seconds
Started Jul 05 06:09:57 PM PDT 24
Finished Jul 05 06:10:08 PM PDT 24
Peak memory 216284 kb
Host smart-413c7656-afac-486e-90ee-0dca43708bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=115337953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.115337953
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2802039431
Short name T293
Test name
Test status
Simulation time 40607740 ps
CPU time 0.72 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:10:03 PM PDT 24
Peak memory 205632 kb
Host smart-3c2e0310-9472-4dac-a162-3d89f9b5a860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802039431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2802039431
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1911692533
Short name T737
Test name
Test status
Simulation time 96105949 ps
CPU time 0.87 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:10:03 PM PDT 24
Peak memory 206004 kb
Host smart-581af4e2-75b3-422e-a046-fa0854fda212
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911692533 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1911692533
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.1658971277
Short name T923
Test name
Test status
Simulation time 131300361 ps
CPU time 2.78 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:10:05 PM PDT 24
Peak memory 224468 kb
Host smart-9c1e3aed-da0c-4565-9eb5-0f18915e3aec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1658971277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.1658971277
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.2631504201
Short name T442
Test name
Test status
Simulation time 21158242 ps
CPU time 0.7 seconds
Started Jul 05 06:10:11 PM PDT 24
Finished Jul 05 06:10:12 PM PDT 24
Peak memory 204960 kb
Host smart-f35a2fb3-8a4e-4d08-bf48-72ded15713d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2631504201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
2631504201
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.1357753827
Short name T178
Test name
Test status
Simulation time 96320116 ps
CPU time 3 seconds
Started Jul 05 06:10:03 PM PDT 24
Finished Jul 05 06:10:07 PM PDT 24
Peak memory 224468 kb
Host smart-5a0db3ca-a1c6-4469-9e0f-45342f8d3ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1357753827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.1357753827
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.3964798341
Short name T697
Test name
Test status
Simulation time 45028058 ps
CPU time 0.78 seconds
Started Jul 05 06:10:05 PM PDT 24
Finished Jul 05 06:10:06 PM PDT 24
Peak memory 206568 kb
Host smart-31e65b1d-cbcb-477f-be7e-97f8c734900c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964798341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.3964798341
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.2419237592
Short name T884
Test name
Test status
Simulation time 100404368836 ps
CPU time 174.62 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:12:58 PM PDT 24
Peak memory 265792 kb
Host smart-156a030a-7cf5-4eb2-845d-b57ae93f40aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2419237592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.2419237592
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.533902318
Short name T361
Test name
Test status
Simulation time 4427208522 ps
CPU time 6.35 seconds
Started Jul 05 06:10:07 PM PDT 24
Finished Jul 05 06:10:14 PM PDT 24
Peak memory 217780 kb
Host smart-f54f0213-e5b5-4c04-b107-ed8b6f913a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533902318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.533902318
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.2858353984
Short name T692
Test name
Test status
Simulation time 4142227334 ps
CPU time 55.95 seconds
Started Jul 05 06:10:10 PM PDT 24
Finished Jul 05 06:11:06 PM PDT 24
Peak memory 256676 kb
Host smart-377468e2-6684-411a-b276-c2565aecb76c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858353984 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.2858353984
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1000531203
Short name T969
Test name
Test status
Simulation time 2022763333 ps
CPU time 20.57 seconds
Started Jul 05 06:10:00 PM PDT 24
Finished Jul 05 06:10:21 PM PDT 24
Peak memory 224384 kb
Host smart-34a3af04-670a-4e42-9618-8b08d417ebf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000531203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1000531203
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.631998186
Short name T437
Test name
Test status
Simulation time 68814617010 ps
CPU time 142.62 seconds
Started Jul 05 06:10:05 PM PDT 24
Finished Jul 05 06:12:28 PM PDT 24
Peak memory 249220 kb
Host smart-2321220b-30f5-4af8-8956-423c8b54267b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631998186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmds
.631998186
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1640084893
Short name T868
Test name
Test status
Simulation time 242171891 ps
CPU time 3.27 seconds
Started Jul 05 06:10:04 PM PDT 24
Finished Jul 05 06:10:08 PM PDT 24
Peak memory 232684 kb
Host smart-f1008c0e-a6f4-4e02-b165-1a84d682f823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640084893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1640084893
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3334885424
Short name T975
Test name
Test status
Simulation time 1577243494 ps
CPU time 16.58 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:10:19 PM PDT 24
Peak memory 224528 kb
Host smart-acc45ec0-9ff7-49c7-afd8-0028f98df22f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334885424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3334885424
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2469031513
Short name T758
Test name
Test status
Simulation time 103444157 ps
CPU time 2.3 seconds
Started Jul 05 06:10:04 PM PDT 24
Finished Jul 05 06:10:07 PM PDT 24
Peak memory 224328 kb
Host smart-7cd1bb11-e758-4662-a383-3cb79d3095c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469031513 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2469031513
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.676462779
Short name T83
Test name
Test status
Simulation time 12528249389 ps
CPU time 16.4 seconds
Started Jul 05 06:10:00 PM PDT 24
Finished Jul 05 06:10:17 PM PDT 24
Peak memory 232784 kb
Host smart-b7dc1310-7a35-4244-8c7d-d5d3d3e405fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676462779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.676462779
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.2984258610
Short name T595
Test name
Test status
Simulation time 3839632137 ps
CPU time 15.52 seconds
Started Jul 05 06:10:01 PM PDT 24
Finished Jul 05 06:10:17 PM PDT 24
Peak memory 221612 kb
Host smart-df2af83d-aafa-4fc9-9f9d-7c2e68d902c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2984258610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.2984258610
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.129664000
Short name T571
Test name
Test status
Simulation time 246798427 ps
CPU time 1.17 seconds
Started Jul 05 06:10:11 PM PDT 24
Finished Jul 05 06:10:12 PM PDT 24
Peak memory 207088 kb
Host smart-52802aa7-5d8b-465d-a68b-e1320a2a79bc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129664000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.129664000
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.2385219616
Short name T610
Test name
Test status
Simulation time 2588551853 ps
CPU time 14.97 seconds
Started Jul 05 06:10:04 PM PDT 24
Finished Jul 05 06:10:20 PM PDT 24
Peak memory 220072 kb
Host smart-5ba2c9f3-c955-44d4-a989-62a717aa2b93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385219616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.2385219616
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.1727093125
Short name T819
Test name
Test status
Simulation time 7185652713 ps
CPU time 3.36 seconds
Started Jul 05 06:10:02 PM PDT 24
Finished Jul 05 06:10:06 PM PDT 24
Peak memory 216268 kb
Host smart-ef6d51f0-bb03-485d-be0e-edf24771f48e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727093125 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.1727093125
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.3929566681
Short name T561
Test name
Test status
Simulation time 221153798 ps
CPU time 1.38 seconds
Started Jul 05 06:10:01 PM PDT 24
Finished Jul 05 06:10:03 PM PDT 24
Peak memory 208040 kb
Host smart-b3a0e883-8e79-4838-9153-dfe5869529db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929566681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.3929566681
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2175578805
Short name T554
Test name
Test status
Simulation time 50993888 ps
CPU time 0.97 seconds
Started Jul 05 06:10:05 PM PDT 24
Finished Jul 05 06:10:06 PM PDT 24
Peak memory 205992 kb
Host smart-11c7ad1a-afad-4396-979d-76447b75bbd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175578805 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2175578805
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.1802143981
Short name T320
Test name
Test status
Simulation time 54525974 ps
CPU time 2.57 seconds
Started Jul 05 06:10:04 PM PDT 24
Finished Jul 05 06:10:07 PM PDT 24
Peak memory 224184 kb
Host smart-13e9ae71-89ba-47df-a466-13195c50a04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1802143981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.1802143981
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1061218937
Short name T998
Test name
Test status
Simulation time 12813413 ps
CPU time 0.75 seconds
Started Jul 05 06:10:09 PM PDT 24
Finished Jul 05 06:10:10 PM PDT 24
Peak memory 204956 kb
Host smart-719fe8d1-32af-4c6e-b6f3-ff1ff1745106
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061218937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1061218937
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.2406071825
Short name T607
Test name
Test status
Simulation time 1937664647 ps
CPU time 6.52 seconds
Started Jul 05 06:10:09 PM PDT 24
Finished Jul 05 06:10:15 PM PDT 24
Peak memory 232732 kb
Host smart-2494fb0f-f470-46ba-a141-07c1ec47838d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406071825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.2406071825
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3017865186
Short name T518
Test name
Test status
Simulation time 61374129 ps
CPU time 0.78 seconds
Started Jul 05 06:10:07 PM PDT 24
Finished Jul 05 06:10:08 PM PDT 24
Peak memory 206944 kb
Host smart-2d634a84-5700-4a50-8623-3d4ccb50d7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017865186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3017865186
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.237094540
Short name T118
Test name
Test status
Simulation time 2877445928 ps
CPU time 7.34 seconds
Started Jul 05 06:10:09 PM PDT 24
Finished Jul 05 06:10:17 PM PDT 24
Peak memory 233564 kb
Host smart-a57500cc-eab0-423d-bcf7-818d6426b942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237094540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.237094540
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.302005087
Short name T660
Test name
Test status
Simulation time 20280849526 ps
CPU time 55.55 seconds
Started Jul 05 06:10:14 PM PDT 24
Finished Jul 05 06:11:10 PM PDT 24
Peak memory 254324 kb
Host smart-3c081a61-c0ae-4d59-95db-3b73112150e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302005087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.302005087
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.890781073
Short name T707
Test name
Test status
Simulation time 15211889681 ps
CPU time 64.91 seconds
Started Jul 05 06:10:13 PM PDT 24
Finished Jul 05 06:11:18 PM PDT 24
Peak memory 251404 kb
Host smart-7551c0b2-694f-4779-ac9d-31593cc9603b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890781073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.890781073
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.3075706599
Short name T641
Test name
Test status
Simulation time 1575000853 ps
CPU time 6.33 seconds
Started Jul 05 06:10:12 PM PDT 24
Finished Jul 05 06:10:18 PM PDT 24
Peak memory 232692 kb
Host smart-7a815f60-1408-4f49-af85-01ee8dee81a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3075706599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.3075706599
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.1892580221
Short name T183
Test name
Test status
Simulation time 93576362705 ps
CPU time 278.58 seconds
Started Jul 05 06:10:14 PM PDT 24
Finished Jul 05 06:14:53 PM PDT 24
Peak memory 269048 kb
Host smart-eea730ce-8d33-45f6-beb2-a24c0965e501
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892580221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.1892580221
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.2516581421
Short name T445
Test name
Test status
Simulation time 1514243871 ps
CPU time 7.54 seconds
Started Jul 05 06:10:13 PM PDT 24
Finished Jul 05 06:10:21 PM PDT 24
Peak memory 232708 kb
Host smart-555b2e21-41d8-419a-ad90-1605c11babbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2516581421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.2516581421
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3384504828
Short name T241
Test name
Test status
Simulation time 7080788527 ps
CPU time 48.28 seconds
Started Jul 05 06:10:10 PM PDT 24
Finished Jul 05 06:10:59 PM PDT 24
Peak memory 250004 kb
Host smart-353021cc-a701-4b64-ad4e-eccb385d5601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384504828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3384504828
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.75413453
Short name T623
Test name
Test status
Simulation time 326593307 ps
CPU time 7.15 seconds
Started Jul 05 06:10:09 PM PDT 24
Finished Jul 05 06:10:17 PM PDT 24
Peak memory 232648 kb
Host smart-c40f8eca-ed30-4eca-9e96-d0b03788a80a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75413453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swap.75413453
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3357843184
Short name T207
Test name
Test status
Simulation time 557698196 ps
CPU time 6.02 seconds
Started Jul 05 06:10:12 PM PDT 24
Finished Jul 05 06:10:19 PM PDT 24
Peak memory 232656 kb
Host smart-5e0f7846-a695-41d6-bb62-e635fef77375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357843184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3357843184
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1410095682
Short name T138
Test name
Test status
Simulation time 536713832 ps
CPU time 5.7 seconds
Started Jul 05 06:10:08 PM PDT 24
Finished Jul 05 06:10:14 PM PDT 24
Peak memory 222500 kb
Host smart-8a574f02-ae61-49e9-bb1e-0cd83f3e2707
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1410095682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1410095682
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.1326825485
Short name T505
Test name
Test status
Simulation time 53583003 ps
CPU time 0.73 seconds
Started Jul 05 06:10:10 PM PDT 24
Finished Jul 05 06:10:11 PM PDT 24
Peak memory 205640 kb
Host smart-e06fc434-8147-46a6-b35f-b458428a14a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326825485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.1326825485
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4258200204
Short name T570
Test name
Test status
Simulation time 1621617539 ps
CPU time 2.72 seconds
Started Jul 05 06:10:08 PM PDT 24
Finished Jul 05 06:10:11 PM PDT 24
Peak memory 216136 kb
Host smart-5ce57925-37eb-4550-bb42-732a098d0c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258200204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4258200204
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.2915274367
Short name T407
Test name
Test status
Simulation time 133246830 ps
CPU time 1.61 seconds
Started Jul 05 06:10:10 PM PDT 24
Finished Jul 05 06:10:13 PM PDT 24
Peak memory 216180 kb
Host smart-b0a4ccdb-96d3-4199-a6fc-612102040d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2915274367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.2915274367
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1118186979
Short name T14
Test name
Test status
Simulation time 344231456 ps
CPU time 0.99 seconds
Started Jul 05 06:10:11 PM PDT 24
Finished Jul 05 06:10:13 PM PDT 24
Peak memory 207036 kb
Host smart-a7ba9999-9889-4035-84f4-fa3901776baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118186979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1118186979
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.4183208991
Short name T101
Test name
Test status
Simulation time 1815537112 ps
CPU time 17.68 seconds
Started Jul 05 06:10:13 PM PDT 24
Finished Jul 05 06:10:31 PM PDT 24
Peak memory 249112 kb
Host smart-588f06af-e571-4df5-aca5-236bf2d6bc80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4183208991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.4183208991
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.1669016349
Short name T295
Test name
Test status
Simulation time 22312253 ps
CPU time 0.67 seconds
Started Jul 05 06:10:18 PM PDT 24
Finished Jul 05 06:10:19 PM PDT 24
Peak memory 205520 kb
Host smart-7bd0420d-6b15-49e1-a076-a8c380588a00
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669016349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
1669016349
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1685401602
Short name T397
Test name
Test status
Simulation time 237161717 ps
CPU time 3.38 seconds
Started Jul 05 06:10:21 PM PDT 24
Finished Jul 05 06:10:25 PM PDT 24
Peak memory 224488 kb
Host smart-1d544104-036a-4322-9a47-f91341a02a50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685401602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1685401602
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.4189673122
Short name T565
Test name
Test status
Simulation time 20709208 ps
CPU time 0.76 seconds
Started Jul 05 06:10:09 PM PDT 24
Finished Jul 05 06:10:11 PM PDT 24
Peak memory 205612 kb
Host smart-7de59ffd-b832-4af2-905e-03dba1d4ab99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189673122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.4189673122
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.168403064
Short name T349
Test name
Test status
Simulation time 107270237222 ps
CPU time 91.46 seconds
Started Jul 05 06:10:16 PM PDT 24
Finished Jul 05 06:11:47 PM PDT 24
Peak memory 238768 kb
Host smart-6e5b9f36-66dd-4a45-b174-b253c333144d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=168403064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.168403064
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1940844601
Short name T855
Test name
Test status
Simulation time 45878387659 ps
CPU time 106.24 seconds
Started Jul 05 06:10:18 PM PDT 24
Finished Jul 05 06:12:04 PM PDT 24
Peak memory 234936 kb
Host smart-e82a2f6a-b48b-493d-9e3e-0c7cf29b5c18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940844601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1940844601
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.4256915454
Short name T217
Test name
Test status
Simulation time 22094573877 ps
CPU time 47.54 seconds
Started Jul 05 06:10:19 PM PDT 24
Finished Jul 05 06:11:07 PM PDT 24
Peak memory 232900 kb
Host smart-5a50aaff-0766-4067-90fa-cea6addef211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4256915454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idl
e.4256915454
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.4150615622
Short name T557
Test name
Test status
Simulation time 52012650 ps
CPU time 2.43 seconds
Started Jul 05 06:10:19 PM PDT 24
Finished Jul 05 06:10:22 PM PDT 24
Peak memory 232628 kb
Host smart-2e97e3c3-887e-46bb-aa77-13b34a4394c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150615622 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.4150615622
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.180145773
Short name T636
Test name
Test status
Simulation time 14850148821 ps
CPU time 35.19 seconds
Started Jul 05 06:10:17 PM PDT 24
Finished Jul 05 06:10:53 PM PDT 24
Peak memory 253992 kb
Host smart-bcb239f7-834c-4d38-a30f-fa0978bf1c33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180145773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmds
.180145773
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1712721758
Short name T321
Test name
Test status
Simulation time 290282913 ps
CPU time 5.43 seconds
Started Jul 05 06:10:18 PM PDT 24
Finished Jul 05 06:10:24 PM PDT 24
Peak memory 224404 kb
Host smart-81489bc0-9ec6-4e17-bab5-8b98bfa338e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1712721758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1712721758
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2160632084
Short name T412
Test name
Test status
Simulation time 13140617589 ps
CPU time 65.96 seconds
Started Jul 05 06:10:17 PM PDT 24
Finished Jul 05 06:11:24 PM PDT 24
Peak memory 240984 kb
Host smart-84b3f1b4-470b-4c21-9610-ea239b818c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160632084 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2160632084
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2497729271
Short name T584
Test name
Test status
Simulation time 3033255939 ps
CPU time 4.62 seconds
Started Jul 05 06:10:26 PM PDT 24
Finished Jul 05 06:10:31 PM PDT 24
Peak memory 232768 kb
Host smart-5e42ec82-b437-4bfc-9b11-e44a7f98dc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497729271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2497729271
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.511562978
Short name T8
Test name
Test status
Simulation time 36011327 ps
CPU time 2.36 seconds
Started Jul 05 06:10:18 PM PDT 24
Finished Jul 05 06:10:21 PM PDT 24
Peak memory 232672 kb
Host smart-223b28b8-a7f0-425f-b691-ded1e0b75633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511562978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.511562978
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3925914347
Short name T395
Test name
Test status
Simulation time 817172634 ps
CPU time 5.49 seconds
Started Jul 05 06:10:17 PM PDT 24
Finished Jul 05 06:10:23 PM PDT 24
Peak memory 223100 kb
Host smart-d0fecc4c-f5de-47d3-bd6a-d1110fdbb555
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3925914347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3925914347
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.226775225
Short name T740
Test name
Test status
Simulation time 27728142 ps
CPU time 0.69 seconds
Started Jul 05 06:10:10 PM PDT 24
Finished Jul 05 06:10:12 PM PDT 24
Peak memory 205728 kb
Host smart-3f294d06-436a-48ab-a661-022830d0a71c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226775225 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.226775225
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.542671058
Short name T967
Test name
Test status
Simulation time 3427090418 ps
CPU time 6 seconds
Started Jul 05 06:10:14 PM PDT 24
Finished Jul 05 06:10:21 PM PDT 24
Peak memory 216348 kb
Host smart-19086d3a-3ed9-45a8-9e76-889c15b35a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542671058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.542671058
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3362988955
Short name T441
Test name
Test status
Simulation time 303809584 ps
CPU time 10.48 seconds
Started Jul 05 06:10:15 PM PDT 24
Finished Jul 05 06:10:26 PM PDT 24
Peak memory 216288 kb
Host smart-21ee4500-ee05-439b-83d4-2ab50c1349bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3362988955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3362988955
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1581089537
Short name T528
Test name
Test status
Simulation time 330013414 ps
CPU time 0.8 seconds
Started Jul 05 06:10:16 PM PDT 24
Finished Jul 05 06:10:17 PM PDT 24
Peak memory 205952 kb
Host smart-1a41f64b-b9f3-4af9-92a4-e472f9e6ffea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581089537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1581089537
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.4258188388
Short name T562
Test name
Test status
Simulation time 1182874251 ps
CPU time 5.28 seconds
Started Jul 05 06:10:26 PM PDT 24
Finished Jul 05 06:10:32 PM PDT 24
Peak memory 224508 kb
Host smart-7c06958e-01a8-4fe2-98aa-401fcedabd78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258188388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.4258188388
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2323886032
Short name T588
Test name
Test status
Simulation time 32305440 ps
CPU time 0.69 seconds
Started Jul 05 06:10:16 PM PDT 24
Finished Jul 05 06:10:17 PM PDT 24
Peak memory 205540 kb
Host smart-61389703-73f1-40c0-88a8-fdf32aed3fa8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323886032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2323886032
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.732336795
Short name T314
Test name
Test status
Simulation time 1566783778 ps
CPU time 2.53 seconds
Started Jul 05 06:10:16 PM PDT 24
Finished Jul 05 06:10:19 PM PDT 24
Peak memory 224520 kb
Host smart-7d40f7b6-f44f-4e8b-9a1d-d03c0af85340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732336795 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.732336795
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.1348199200
Short name T620
Test name
Test status
Simulation time 65005448 ps
CPU time 0.8 seconds
Started Jul 05 06:10:17 PM PDT 24
Finished Jul 05 06:10:18 PM PDT 24
Peak memory 206636 kb
Host smart-07831b50-9895-413e-bab6-9f29b0c9cf08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348199200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.1348199200
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1163792068
Short name T160
Test name
Test status
Simulation time 22070503055 ps
CPU time 31.25 seconds
Started Jul 05 06:10:22 PM PDT 24
Finished Jul 05 06:10:53 PM PDT 24
Peak memory 254812 kb
Host smart-15f7ae7a-3109-4c77-b8b0-43f5f7a29fcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163792068 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1163792068
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1666093004
Short name T248
Test name
Test status
Simulation time 226152385198 ps
CPU time 198.79 seconds
Started Jul 05 06:10:18 PM PDT 24
Finished Jul 05 06:13:37 PM PDT 24
Peak memory 253648 kb
Host smart-1b0cf3f6-ed13-4962-8780-e1b3eff5a8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666093004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1666093004
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.4108446626
Short name T27
Test name
Test status
Simulation time 42787284556 ps
CPU time 392.61 seconds
Started Jul 05 06:10:19 PM PDT 24
Finished Jul 05 06:16:52 PM PDT 24
Peak memory 256212 kb
Host smart-6bbea7da-9812-4303-9a97-a7266819be33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108446626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.4108446626
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1605011879
Short name T811
Test name
Test status
Simulation time 644782218 ps
CPU time 13.24 seconds
Started Jul 05 06:10:18 PM PDT 24
Finished Jul 05 06:10:32 PM PDT 24
Peak memory 233704 kb
Host smart-4b9c4d6a-f1c7-4723-ac0b-b653e9769eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605011879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1605011879
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.4020500521
Short name T1004
Test name
Test status
Simulation time 518257615 ps
CPU time 5.94 seconds
Started Jul 05 06:10:20 PM PDT 24
Finished Jul 05 06:10:27 PM PDT 24
Peak memory 232716 kb
Host smart-e2f45dd7-8fc7-4b1a-8992-151d637c62ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020500521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.4020500521
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.2882845283
Short name T891
Test name
Test status
Simulation time 587753998 ps
CPU time 3.44 seconds
Started Jul 05 06:10:15 PM PDT 24
Finished Jul 05 06:10:19 PM PDT 24
Peak memory 224432 kb
Host smart-70797c41-ff31-4734-96d6-3dc676562192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882845283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.2882845283
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.1575725733
Short name T13
Test name
Test status
Simulation time 7049483370 ps
CPU time 26.18 seconds
Started Jul 05 06:10:17 PM PDT 24
Finished Jul 05 06:10:44 PM PDT 24
Peak memory 224536 kb
Host smart-dfd39817-5ab2-4409-853a-244e72c06238
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575725733 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.1575725733
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.1824278652
Short name T212
Test name
Test status
Simulation time 9149275571 ps
CPU time 14.23 seconds
Started Jul 05 06:10:15 PM PDT 24
Finished Jul 05 06:10:30 PM PDT 24
Peak memory 224636 kb
Host smart-2bae109b-b278-4f7f-8d13-1f0989beb41f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1824278652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.1824278652
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.2958658417
Short name T955
Test name
Test status
Simulation time 1000118168 ps
CPU time 5.04 seconds
Started Jul 05 06:10:19 PM PDT 24
Finished Jul 05 06:10:25 PM PDT 24
Peak memory 224496 kb
Host smart-6aa35fb2-b0c4-43ac-984d-2743715f2135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958658417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.2958658417
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2383423886
Short name T402
Test name
Test status
Simulation time 3812875243 ps
CPU time 11.12 seconds
Started Jul 05 06:10:19 PM PDT 24
Finished Jul 05 06:10:30 PM PDT 24
Peak memory 221800 kb
Host smart-b9f1ca82-cca9-4c63-b6a3-702a66340f29
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2383423886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2383423886
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.1522571901
Short name T33
Test name
Test status
Simulation time 3442197808 ps
CPU time 40.96 seconds
Started Jul 05 06:10:17 PM PDT 24
Finished Jul 05 06:10:58 PM PDT 24
Peak memory 236292 kb
Host smart-29400dba-dca3-48ee-8008-dede26805871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522571901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.1522571901
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1044822008
Short name T800
Test name
Test status
Simulation time 5577246399 ps
CPU time 16.31 seconds
Started Jul 05 06:10:18 PM PDT 24
Finished Jul 05 06:10:35 PM PDT 24
Peak memory 216320 kb
Host smart-ea80d433-acc0-4732-b92e-27ba43e300dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044822008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1044822008
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.1128397937
Short name T384
Test name
Test status
Simulation time 13036148 ps
CPU time 0.66 seconds
Started Jul 05 06:10:21 PM PDT 24
Finished Jul 05 06:10:22 PM PDT 24
Peak memory 205648 kb
Host smart-9f2fe6d4-4e69-4067-b402-3140c9aea37e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1128397937 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.1128397937
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2673279132
Short name T51
Test name
Test status
Simulation time 27414248 ps
CPU time 0.77 seconds
Started Jul 05 06:10:18 PM PDT 24
Finished Jul 05 06:10:20 PM PDT 24
Peak memory 205996 kb
Host smart-5b565f3c-b121-4b99-85a0-009d46fb6e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673279132 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2673279132
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3666918420
Short name T218
Test name
Test status
Simulation time 5595923775 ps
CPU time 7.64 seconds
Started Jul 05 06:10:20 PM PDT 24
Finished Jul 05 06:10:29 PM PDT 24
Peak memory 232808 kb
Host smart-9431309c-3310-4270-8e7a-b3426bb82c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3666918420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3666918420
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.871113262
Short name T338
Test name
Test status
Simulation time 25427897 ps
CPU time 0.73 seconds
Started Jul 05 06:10:27 PM PDT 24
Finished Jul 05 06:10:28 PM PDT 24
Peak memory 205524 kb
Host smart-5e952ce3-7b8c-4ac4-9722-e1df17e927e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871113262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.871113262
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.3164876753
Short name T476
Test name
Test status
Simulation time 607131478 ps
CPU time 4.69 seconds
Started Jul 05 06:10:24 PM PDT 24
Finished Jul 05 06:10:29 PM PDT 24
Peak memory 232692 kb
Host smart-a1592fe2-0f85-44c9-b8c9-e404638be4c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164876753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.3164876753
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.315245447
Short name T299
Test name
Test status
Simulation time 71542644 ps
CPU time 0.76 seconds
Started Jul 05 06:10:15 PM PDT 24
Finished Jul 05 06:10:16 PM PDT 24
Peak memory 206624 kb
Host smart-6b9ef60d-9b28-43cd-b8cc-fb48c8323e54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315245447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.315245447
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.2186497465
Short name T511
Test name
Test status
Simulation time 763084635 ps
CPU time 0.95 seconds
Started Jul 05 06:10:27 PM PDT 24
Finished Jul 05 06:10:28 PM PDT 24
Peak memory 215924 kb
Host smart-de80d827-4297-4372-b64f-e2d37daf2b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2186497465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.2186497465
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.1335516275
Short name T353
Test name
Test status
Simulation time 8757584795 ps
CPU time 23.54 seconds
Started Jul 05 06:10:29 PM PDT 24
Finished Jul 05 06:10:52 PM PDT 24
Peak memory 219300 kb
Host smart-2f35e145-5b82-4a99-84c5-dac5da194186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335516275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.1335516275
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2453214951
Short name T237
Test name
Test status
Simulation time 11608837472 ps
CPU time 108.67 seconds
Started Jul 05 06:10:24 PM PDT 24
Finished Jul 05 06:12:14 PM PDT 24
Peak memory 256444 kb
Host smart-e9adaae7-e8c6-41a1-8096-71ed699081f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453214951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2453214951
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.3641350630
Short name T921
Test name
Test status
Simulation time 64644694 ps
CPU time 3.25 seconds
Started Jul 05 06:10:26 PM PDT 24
Finished Jul 05 06:10:30 PM PDT 24
Peak memory 224344 kb
Host smart-7cf4c45a-3b19-4da2-aa34-a0a4f9a07901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641350630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.3641350630
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.304295729
Short name T193
Test name
Test status
Simulation time 2514688432 ps
CPU time 62.48 seconds
Started Jul 05 06:10:24 PM PDT 24
Finished Jul 05 06:11:27 PM PDT 24
Peak memory 254112 kb
Host smart-9e1df364-bbbd-42a7-8a14-71a5e4ac09b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304295729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmds
.304295729
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2265957253
Short name T613
Test name
Test status
Simulation time 6331569173 ps
CPU time 13.39 seconds
Started Jul 05 06:10:24 PM PDT 24
Finished Jul 05 06:10:38 PM PDT 24
Peak memory 220292 kb
Host smart-3a0fc9d2-86d0-4c42-8165-7862153ec1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2265957253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2265957253
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.2650771746
Short name T778
Test name
Test status
Simulation time 6992622375 ps
CPU time 38.02 seconds
Started Jul 05 06:10:22 PM PDT 24
Finished Jul 05 06:11:00 PM PDT 24
Peak memory 232852 kb
Host smart-b53481d1-bf0a-44cf-9ad3-2b810845ce0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650771746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.2650771746
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.3644152654
Short name T446
Test name
Test status
Simulation time 1923582734 ps
CPU time 4.09 seconds
Started Jul 05 06:10:25 PM PDT 24
Finished Jul 05 06:10:29 PM PDT 24
Peak memory 224440 kb
Host smart-338579cf-cfb5-4f83-82e7-e2ee9df5a70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3644152654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swa
p.3644152654
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.4049698940
Short name T624
Test name
Test status
Simulation time 6278468601 ps
CPU time 9.04 seconds
Started Jul 05 06:10:26 PM PDT 24
Finished Jul 05 06:10:35 PM PDT 24
Peak memory 232848 kb
Host smart-a3d8b881-4725-4f02-9a30-584e543b2d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049698940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.4049698940
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.4005966511
Short name T549
Test name
Test status
Simulation time 245659373 ps
CPU time 4.61 seconds
Started Jul 05 06:10:26 PM PDT 24
Finished Jul 05 06:10:31 PM PDT 24
Peak memory 218848 kb
Host smart-f4aa41ec-532a-49bb-962d-38966319a358
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4005966511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.4005966511
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.3703322570
Short name T184
Test name
Test status
Simulation time 49689913518 ps
CPU time 508.62 seconds
Started Jul 05 06:10:26 PM PDT 24
Finished Jul 05 06:18:55 PM PDT 24
Peak memory 284700 kb
Host smart-09240d33-b4a9-423d-a24f-2bf9b4e368e7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703322570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.3703322570
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.3812653787
Short name T696
Test name
Test status
Simulation time 3796573974 ps
CPU time 18.58 seconds
Started Jul 05 06:10:25 PM PDT 24
Finished Jul 05 06:10:44 PM PDT 24
Peak memory 216708 kb
Host smart-1b37b0d9-9092-409c-a945-7fc956ed90f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812653787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.3812653787
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.4190880433
Short name T382
Test name
Test status
Simulation time 14073436579 ps
CPU time 14.01 seconds
Started Jul 05 06:10:27 PM PDT 24
Finished Jul 05 06:10:41 PM PDT 24
Peak memory 216332 kb
Host smart-f6678d6e-868f-4686-9b76-9d093865306b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4190880433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.4190880433
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3736948668
Short name T916
Test name
Test status
Simulation time 65874263 ps
CPU time 3.51 seconds
Started Jul 05 06:10:25 PM PDT 24
Finished Jul 05 06:10:29 PM PDT 24
Peak memory 216224 kb
Host smart-9355111a-d1ec-494c-99eb-ff2f3c89f792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736948668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3736948668
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.268211612
Short name T890
Test name
Test status
Simulation time 88297734 ps
CPU time 0.73 seconds
Started Jul 05 06:10:26 PM PDT 24
Finished Jul 05 06:10:27 PM PDT 24
Peak memory 205980 kb
Host smart-fcd5e0fb-801c-40f5-b172-4f16685a4009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268211612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.268211612
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.2088476108
Short name T766
Test name
Test status
Simulation time 81996868 ps
CPU time 2.27 seconds
Started Jul 05 06:10:30 PM PDT 24
Finished Jul 05 06:10:33 PM PDT 24
Peak memory 224412 kb
Host smart-7250ec1a-fb9f-47a1-b8ac-9f95e978fef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088476108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.2088476108
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3130961335
Short name T947
Test name
Test status
Simulation time 20037033 ps
CPU time 0.74 seconds
Started Jul 05 06:11:04 PM PDT 24
Finished Jul 05 06:11:05 PM PDT 24
Peak memory 205852 kb
Host smart-1f565c2d-a231-44ab-9ebb-8bf29f4af0a2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130961335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3130961335
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1667668356
Short name T230
Test name
Test status
Simulation time 1314057256 ps
CPU time 12.36 seconds
Started Jul 05 06:10:21 PM PDT 24
Finished Jul 05 06:10:34 PM PDT 24
Peak memory 224468 kb
Host smart-e4d8ccc9-f37e-4e46-95fd-eee752db8cce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1667668356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1667668356
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.3498157864
Short name T805
Test name
Test status
Simulation time 21109400 ps
CPU time 0.79 seconds
Started Jul 05 06:10:31 PM PDT 24
Finished Jul 05 06:10:32 PM PDT 24
Peak memory 206648 kb
Host smart-352b35bd-57a0-48b6-b47b-ecd3c981b35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498157864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.3498157864
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.4077991302
Short name T236
Test name
Test status
Simulation time 8880133365 ps
CPU time 29.97 seconds
Started Jul 05 06:10:34 PM PDT 24
Finished Jul 05 06:11:05 PM PDT 24
Peak memory 235308 kb
Host smart-e17825b2-c120-4112-a5f3-1be5b413c3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4077991302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.4077991302
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.4127344764
Short name T632
Test name
Test status
Simulation time 23624560384 ps
CPU time 232.83 seconds
Started Jul 05 06:10:35 PM PDT 24
Finished Jul 05 06:14:29 PM PDT 24
Peak memory 255132 kb
Host smart-b658bbfe-aee4-40c8-9a76-ccaaaa5dacc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127344764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.4127344764
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1348841596
Short name T128
Test name
Test status
Simulation time 13225528005 ps
CPU time 167.75 seconds
Started Jul 05 06:10:33 PM PDT 24
Finished Jul 05 06:13:22 PM PDT 24
Peak memory 265684 kb
Host smart-8796fd77-22d2-4247-9ae5-9e3f60da9cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1348841596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1348841596
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3045169051
Short name T843
Test name
Test status
Simulation time 2806081753 ps
CPU time 13.59 seconds
Started Jul 05 06:10:25 PM PDT 24
Finished Jul 05 06:10:39 PM PDT 24
Peak memory 224636 kb
Host smart-7adc60be-0750-4047-ad2c-fd7cb5992730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045169051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3045169051
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.3608554060
Short name T704
Test name
Test status
Simulation time 15657043426 ps
CPU time 42.16 seconds
Started Jul 05 06:10:35 PM PDT 24
Finished Jul 05 06:11:18 PM PDT 24
Peak memory 249292 kb
Host smart-bbf5630c-3e65-4bdf-9825-4dbfa2a77027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3608554060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.3608554060
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2211411377
Short name T676
Test name
Test status
Simulation time 935723327 ps
CPU time 9.04 seconds
Started Jul 05 06:10:25 PM PDT 24
Finished Jul 05 06:10:34 PM PDT 24
Peak memory 232728 kb
Host smart-049fbfbd-6093-4e3c-8a91-779f3d094f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211411377 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2211411377
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.2190343394
Short name T630
Test name
Test status
Simulation time 10843935115 ps
CPU time 30.66 seconds
Started Jul 05 06:10:23 PM PDT 24
Finished Jul 05 06:10:54 PM PDT 24
Peak memory 232844 kb
Host smart-4e2ce798-6c6c-4367-9ee5-6ef4807f0b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190343394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.2190343394
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.3428893817
Short name T728
Test name
Test status
Simulation time 229289373 ps
CPU time 2.27 seconds
Started Jul 05 06:10:25 PM PDT 24
Finished Jul 05 06:10:28 PM PDT 24
Peak memory 224092 kb
Host smart-248200dc-7032-4279-ae4d-403fa0259915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3428893817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.3428893817
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2867639235
Short name T759
Test name
Test status
Simulation time 285696206 ps
CPU time 2.3 seconds
Started Jul 05 06:10:26 PM PDT 24
Finished Jul 05 06:10:29 PM PDT 24
Peak memory 224136 kb
Host smart-4708ab05-16ab-4e57-a401-7a92cc1135b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867639235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2867639235
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.4121372070
Short name T981
Test name
Test status
Simulation time 698630407 ps
CPU time 3.21 seconds
Started Jul 05 06:10:35 PM PDT 24
Finished Jul 05 06:10:38 PM PDT 24
Peak memory 219044 kb
Host smart-bb631a3e-4f44-42d8-aff7-8b8597e3554d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4121372070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.4121372070
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.4275706129
Short name T150
Test name
Test status
Simulation time 10005629875 ps
CPU time 149.87 seconds
Started Jul 05 06:10:29 PM PDT 24
Finished Jul 05 06:12:59 PM PDT 24
Peak memory 255864 kb
Host smart-1fa1499b-c6bb-4cf3-8dc3-29c957677f8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275706129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.4275706129
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.3194200201
Short name T49
Test name
Test status
Simulation time 7007063757 ps
CPU time 37.08 seconds
Started Jul 05 06:10:27 PM PDT 24
Finished Jul 05 06:11:05 PM PDT 24
Peak memory 216404 kb
Host smart-fc5eafe5-38ba-4d8e-a69a-a960ab373a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194200201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.3194200201
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.3918417394
Short name T597
Test name
Test status
Simulation time 895065414 ps
CPU time 2.8 seconds
Started Jul 05 06:10:30 PM PDT 24
Finished Jul 05 06:10:34 PM PDT 24
Peak memory 216256 kb
Host smart-16c56bcc-b8fb-4d8e-93b1-c455886038dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918417394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.3918417394
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.3709862224
Short name T859
Test name
Test status
Simulation time 13223664 ps
CPU time 0.78 seconds
Started Jul 05 06:10:24 PM PDT 24
Finished Jul 05 06:10:25 PM PDT 24
Peak memory 205976 kb
Host smart-cd5276b5-aaaf-454b-97bf-274db4a294d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709862224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.3709862224
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1995276179
Short name T739
Test name
Test status
Simulation time 16625590 ps
CPU time 0.75 seconds
Started Jul 05 06:10:28 PM PDT 24
Finished Jul 05 06:10:29 PM PDT 24
Peak memory 206004 kb
Host smart-ed593c8f-5e82-4c92-a3ac-4c7cf9c72fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995276179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1995276179
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.339650561
Short name T77
Test name
Test status
Simulation time 13476692378 ps
CPU time 13.21 seconds
Started Jul 05 06:10:27 PM PDT 24
Finished Jul 05 06:10:40 PM PDT 24
Peak memory 224592 kb
Host smart-6d14b8a7-8739-40bc-a31a-ba46aa366520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=339650561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.339650561
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2080226231
Short name T730
Test name
Test status
Simulation time 12894311 ps
CPU time 0.74 seconds
Started Jul 05 06:10:34 PM PDT 24
Finished Jul 05 06:10:35 PM PDT 24
Peak memory 205536 kb
Host smart-47d3e4ec-a71f-4a19-afbb-fd3dd9d437b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080226231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2080226231
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.3818663562
Short name T715
Test name
Test status
Simulation time 30623300 ps
CPU time 2.51 seconds
Started Jul 05 06:10:35 PM PDT 24
Finished Jul 05 06:10:38 PM PDT 24
Peak memory 232692 kb
Host smart-23a17057-48f3-4c64-bbcc-a6c8fef80356
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818663562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.3818663562
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1254979273
Short name T596
Test name
Test status
Simulation time 20879721 ps
CPU time 0.8 seconds
Started Jul 05 06:10:33 PM PDT 24
Finished Jul 05 06:10:35 PM PDT 24
Peak memory 206636 kb
Host smart-0e49f45d-aaa2-4142-ad5f-47e482ff3086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1254979273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1254979273
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.3688760667
Short name T38
Test name
Test status
Simulation time 101110312961 ps
CPU time 216.11 seconds
Started Jul 05 06:10:36 PM PDT 24
Finished Jul 05 06:14:13 PM PDT 24
Peak memory 250672 kb
Host smart-d1d98bab-67d3-4653-8a3f-ad5052a0a3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688760667 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.3688760667
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2180189338
Short name T522
Test name
Test status
Simulation time 9014847081 ps
CPU time 69.63 seconds
Started Jul 05 06:10:33 PM PDT 24
Finished Jul 05 06:11:43 PM PDT 24
Peak memory 249336 kb
Host smart-8ac79cc1-ac1b-4183-9258-428e9f183913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180189338 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2180189338
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.828613207
Short name T656
Test name
Test status
Simulation time 154797318 ps
CPU time 5.98 seconds
Started Jul 05 06:10:30 PM PDT 24
Finished Jul 05 06:10:37 PM PDT 24
Peak memory 232688 kb
Host smart-2bf9eb2b-7cc9-4f7b-9a66-8fc4d0879c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828613207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.828613207
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.1524752139
Short name T796
Test name
Test status
Simulation time 25178658888 ps
CPU time 194.98 seconds
Started Jul 05 06:10:36 PM PDT 24
Finished Jul 05 06:13:51 PM PDT 24
Peak memory 249184 kb
Host smart-1c6da85d-6139-4b5c-b9c6-92d5962ef83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524752139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.1524752139
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.2377984073
Short name T823
Test name
Test status
Simulation time 9078938927 ps
CPU time 28.12 seconds
Started Jul 05 06:10:32 PM PDT 24
Finished Jul 05 06:11:00 PM PDT 24
Peak memory 224600 kb
Host smart-a29578e3-d934-4698-a600-396e3bb7f055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377984073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.2377984073
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.4207601294
Short name T608
Test name
Test status
Simulation time 10737114271 ps
CPU time 25.51 seconds
Started Jul 05 06:10:33 PM PDT 24
Finished Jul 05 06:10:59 PM PDT 24
Peak memory 248948 kb
Host smart-11c1d932-0c79-40d6-a423-178f082c3038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207601294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.4207601294
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.1706942269
Short name T46
Test name
Test status
Simulation time 1041819502 ps
CPU time 7.95 seconds
Started Jul 05 06:10:31 PM PDT 24
Finished Jul 05 06:10:39 PM PDT 24
Peak memory 235364 kb
Host smart-1516a718-7234-466f-87d1-f9501967c2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706942269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.1706942269
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3204590505
Short name T319
Test name
Test status
Simulation time 84708181 ps
CPU time 2.54 seconds
Started Jul 05 06:10:33 PM PDT 24
Finished Jul 05 06:10:36 PM PDT 24
Peak memory 232676 kb
Host smart-c06cc869-7d58-4f19-a88b-3f768d4c02cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204590505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3204590505
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4129410233
Short name T621
Test name
Test status
Simulation time 1514972431 ps
CPU time 12.01 seconds
Started Jul 05 06:10:31 PM PDT 24
Finished Jul 05 06:10:44 PM PDT 24
Peak memory 222180 kb
Host smart-66f5dc07-cdce-4d1b-9068-bf3dfb87533d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4129410233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4129410233
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1524106851
Short name T804
Test name
Test status
Simulation time 6145331464 ps
CPU time 20.48 seconds
Started Jul 05 06:10:33 PM PDT 24
Finished Jul 05 06:10:54 PM PDT 24
Peak memory 220068 kb
Host smart-c7aeed3f-3cb6-4663-bf03-c1b40a0b0c72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524106851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1524106851
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.395168263
Short name T373
Test name
Test status
Simulation time 2522578640 ps
CPU time 7.08 seconds
Started Jul 05 06:10:33 PM PDT 24
Finished Jul 05 06:10:41 PM PDT 24
Peak memory 216388 kb
Host smart-e652301e-0253-4b3a-8038-9ec0180424ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395168263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.395168263
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.2571367231
Short name T54
Test name
Test status
Simulation time 1144736426 ps
CPU time 11.17 seconds
Started Jul 05 06:10:34 PM PDT 24
Finished Jul 05 06:10:45 PM PDT 24
Peak memory 216276 kb
Host smart-6ec599dc-709d-4ccf-a2b4-2d38117ed661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571367231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.2571367231
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.978631976
Short name T304
Test name
Test status
Simulation time 48575947 ps
CPU time 0.81 seconds
Started Jul 05 06:10:35 PM PDT 24
Finished Jul 05 06:10:36 PM PDT 24
Peak memory 206004 kb
Host smart-bb5d1b03-d8a5-4e91-95e6-5d287f1688ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978631976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.978631976
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.2837640838
Short name T894
Test name
Test status
Simulation time 779443356 ps
CPU time 3.75 seconds
Started Jul 05 06:10:35 PM PDT 24
Finished Jul 05 06:10:39 PM PDT 24
Peak memory 235592 kb
Host smart-99c9d36f-7132-4135-a800-7ffd464b4e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837640838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.2837640838
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.2499828732
Short name T301
Test name
Test status
Simulation time 47838652 ps
CPU time 0.72 seconds
Started Jul 05 06:07:46 PM PDT 24
Finished Jul 05 06:07:48 PM PDT 24
Peak memory 205548 kb
Host smart-9be6299b-39a2-49f8-8395-6067da4e8b6c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499828732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.2
499828732
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2176355758
Short name T316
Test name
Test status
Simulation time 62427490 ps
CPU time 3.23 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 232584 kb
Host smart-55fa11cc-7ca8-4d5f-9e95-f541cdf1cc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176355758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2176355758
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.2364156812
Short name T489
Test name
Test status
Simulation time 40018313 ps
CPU time 0.78 seconds
Started Jul 05 06:07:35 PM PDT 24
Finished Jul 05 06:07:36 PM PDT 24
Peak memory 206616 kb
Host smart-5d073a11-7d04-4e1c-a15f-574d452d974e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364156812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.2364156812
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.2651512834
Short name T234
Test name
Test status
Simulation time 85193786319 ps
CPU time 225.78 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:11:41 PM PDT 24
Peak memory 273652 kb
Host smart-9af4564f-9d4d-4f5e-a3da-8bca0574d65b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651512834 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.2651512834
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.1766671897
Short name T754
Test name
Test status
Simulation time 204138617193 ps
CPU time 202.1 seconds
Started Jul 05 06:07:42 PM PDT 24
Finished Jul 05 06:11:05 PM PDT 24
Peak memory 249292 kb
Host smart-a7f58790-974b-4a7f-8b1e-b711e873e351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766671897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.1766671897
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.808901434
Short name T262
Test name
Test status
Simulation time 2069355861 ps
CPU time 28.56 seconds
Started Jul 05 06:07:56 PM PDT 24
Finished Jul 05 06:08:26 PM PDT 24
Peak memory 239820 kb
Host smart-7082f2f5-206e-4d5a-9037-7da78a37036b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808901434 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
808901434
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.2428156832
Short name T435
Test name
Test status
Simulation time 449523888 ps
CPU time 3.37 seconds
Started Jul 05 06:07:47 PM PDT 24
Finished Jul 05 06:07:51 PM PDT 24
Peak memory 224440 kb
Host smart-a4fe42a2-adda-4ebb-bfae-b49e601e6eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428156832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.2428156832
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.3198251406
Short name T603
Test name
Test status
Simulation time 70463582787 ps
CPU time 120.78 seconds
Started Jul 05 06:07:50 PM PDT 24
Finished Jul 05 06:09:52 PM PDT 24
Peak memory 236436 kb
Host smart-ae747eb6-a67d-4ddd-952c-1bca13ab0860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198251406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.3198251406
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.21455363
Short name T918
Test name
Test status
Simulation time 5230464190 ps
CPU time 13.97 seconds
Started Jul 05 06:07:50 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 224544 kb
Host smart-c19442fb-a179-4a61-b802-5e0fa19a576b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21455363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.21455363
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.955007240
Short name T56
Test name
Test status
Simulation time 366044261 ps
CPU time 4.19 seconds
Started Jul 05 06:07:41 PM PDT 24
Finished Jul 05 06:07:46 PM PDT 24
Peak memory 224356 kb
Host smart-d0a52cb0-8e14-4ad9-ad3c-ea47d132081e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955007240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.955007240
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.151156139
Short name T674
Test name
Test status
Simulation time 3185728307 ps
CPU time 12.16 seconds
Started Jul 05 06:07:45 PM PDT 24
Finished Jul 05 06:07:58 PM PDT 24
Peak memory 230396 kb
Host smart-e417c980-629f-40c4-8610-5e330a34339a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151156139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap.
151156139
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1716944970
Short name T602
Test name
Test status
Simulation time 16741412699 ps
CPU time 13.82 seconds
Started Jul 05 06:07:44 PM PDT 24
Finished Jul 05 06:07:58 PM PDT 24
Peak memory 232768 kb
Host smart-8bcd960d-41e1-4ef2-9960-c58259e431e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716944970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1716944970
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.696820043
Short name T564
Test name
Test status
Simulation time 1761147371 ps
CPU time 4.94 seconds
Started Jul 05 06:07:46 PM PDT 24
Finished Jul 05 06:07:52 PM PDT 24
Peak memory 221808 kb
Host smart-c5bf35f0-79ec-4940-9548-70f87f6efdea
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=696820043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_direc
t.696820043
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.3773803096
Short name T798
Test name
Test status
Simulation time 331208367 ps
CPU time 4.23 seconds
Started Jul 05 06:07:39 PM PDT 24
Finished Jul 05 06:07:44 PM PDT 24
Peak memory 216312 kb
Host smart-9ab237fc-2602-4f01-9e3c-f606b6a9b6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773803096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.3773803096
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.3853464746
Short name T817
Test name
Test status
Simulation time 435973769 ps
CPU time 1.82 seconds
Started Jul 05 06:07:38 PM PDT 24
Finished Jul 05 06:07:41 PM PDT 24
Peak memory 207928 kb
Host smart-574a8c42-7d21-47b3-9d38-d126e7efa6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853464746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.3853464746
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.93726766
Short name T698
Test name
Test status
Simulation time 300393740 ps
CPU time 4.26 seconds
Started Jul 05 06:07:43 PM PDT 24
Finished Jul 05 06:07:47 PM PDT 24
Peak memory 216204 kb
Host smart-794a87dc-ad67-4fac-b9ee-73faab478b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93726766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.93726766
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4016700603
Short name T477
Test name
Test status
Simulation time 323841531 ps
CPU time 0.98 seconds
Started Jul 05 06:07:45 PM PDT 24
Finished Jul 05 06:07:46 PM PDT 24
Peak memory 206000 kb
Host smart-9859daa8-6dff-431a-a4c7-31f5191c1807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016700603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4016700603
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2236391539
Short name T686
Test name
Test status
Simulation time 15143977527 ps
CPU time 5.68 seconds
Started Jul 05 06:07:44 PM PDT 24
Finished Jul 05 06:07:50 PM PDT 24
Peak memory 224628 kb
Host smart-43ac2174-d05e-4857-bbb3-0834d9dbc59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236391539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2236391539
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2887080051
Short name T546
Test name
Test status
Simulation time 64210252 ps
CPU time 0.71 seconds
Started Jul 05 06:07:40 PM PDT 24
Finished Jul 05 06:07:41 PM PDT 24
Peak memory 205556 kb
Host smart-e3e801c7-1f30-4b99-8892-c814b9f2107f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887080051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
887080051
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1532568793
Short name T392
Test name
Test status
Simulation time 3004593009 ps
CPU time 8.24 seconds
Started Jul 05 06:07:51 PM PDT 24
Finished Jul 05 06:07:59 PM PDT 24
Peak memory 232784 kb
Host smart-7f71c4c1-bea3-45b5-8014-e77656ea39e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1532568793 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1532568793
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2141281041
Short name T631
Test name
Test status
Simulation time 41876979 ps
CPU time 0.77 seconds
Started Jul 05 06:07:45 PM PDT 24
Finished Jul 05 06:07:47 PM PDT 24
Peak memory 206536 kb
Host smart-99871fe6-7aaf-4cc7-82a9-e78bf599203b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141281041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2141281041
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1441233396
Short name T896
Test name
Test status
Simulation time 254232286208 ps
CPU time 160.78 seconds
Started Jul 05 06:08:00 PM PDT 24
Finished Jul 05 06:10:42 PM PDT 24
Peak memory 268148 kb
Host smart-29cdb463-ef7b-4c1a-85bf-542b341e5cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1441233396 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1441233396
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1889109139
Short name T284
Test name
Test status
Simulation time 38628383114 ps
CPU time 376.59 seconds
Started Jul 05 06:07:45 PM PDT 24
Finished Jul 05 06:14:02 PM PDT 24
Peak memory 265536 kb
Host smart-b611b2e0-2b92-4d67-8411-1ac95e1b92ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889109139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1889109139
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3870325392
Short name T723
Test name
Test status
Simulation time 19960891300 ps
CPU time 59.34 seconds
Started Jul 05 06:07:49 PM PDT 24
Finished Jul 05 06:08:48 PM PDT 24
Peak memory 261680 kb
Host smart-b94c8c41-6e82-4ec2-be4e-37ce77d52626
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870325392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3870325392
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.1902899784
Short name T269
Test name
Test status
Simulation time 2924123745 ps
CPU time 38.87 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:08:32 PM PDT 24
Peak memory 240980 kb
Host smart-7bd06027-8c16-4808-abd8-16648ac682f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902899784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.1902899784
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.4203821631
Short name T188
Test name
Test status
Simulation time 4758473118 ps
CPU time 12.9 seconds
Started Jul 05 06:07:43 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 249216 kb
Host smart-f9330bfd-dcd9-46e4-b98d-d3e648b2e1e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203821631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.4203821631
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.3483183566
Short name T667
Test name
Test status
Simulation time 1699207139 ps
CPU time 15.6 seconds
Started Jul 05 06:07:48 PM PDT 24
Finished Jul 05 06:08:04 PM PDT 24
Peak memory 232644 kb
Host smart-f4a039d3-36fe-4795-bc74-5316808e3b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483183566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.3483183566
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.1396968062
Short name T225
Test name
Test status
Simulation time 39908198075 ps
CPU time 71.11 seconds
Started Jul 05 06:07:43 PM PDT 24
Finished Jul 05 06:08:55 PM PDT 24
Peak memory 233780 kb
Host smart-acec6345-bc45-48da-b173-71afebdb7857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1396968062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.1396968062
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.3637363612
Short name T494
Test name
Test status
Simulation time 2358746964 ps
CPU time 8.61 seconds
Started Jul 05 06:07:47 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 232832 kb
Host smart-349be76e-3000-4210-9dcb-806262bec661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637363612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap
.3637363612
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.3476712958
Short name T226
Test name
Test status
Simulation time 14330906855 ps
CPU time 12.08 seconds
Started Jul 05 06:07:44 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 232660 kb
Host smart-cfda15fb-a735-4392-bfb9-397c3b47808a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476712958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.3476712958
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.1863404995
Short name T1005
Test name
Test status
Simulation time 228920037 ps
CPU time 5.29 seconds
Started Jul 05 06:07:46 PM PDT 24
Finished Jul 05 06:07:53 PM PDT 24
Peak memory 222576 kb
Host smart-973be182-7b44-41a9-a45d-a0d6b45c6c2b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1863404995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.1863404995
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.3890183764
Short name T1002
Test name
Test status
Simulation time 184650176276 ps
CPU time 405.18 seconds
Started Jul 05 06:07:42 PM PDT 24
Finished Jul 05 06:14:28 PM PDT 24
Peak memory 251264 kb
Host smart-2aac6326-cf44-4d9b-a5ac-8d63b9241065
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890183764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.3890183764
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.2772403422
Short name T277
Test name
Test status
Simulation time 22559846744 ps
CPU time 8.4 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:07 PM PDT 24
Peak memory 216652 kb
Host smart-0bf594a7-c5d8-4636-8be8-de371270de07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772403422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.2772403422
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.284070279
Short name T324
Test name
Test status
Simulation time 846112494 ps
CPU time 3.23 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:02 PM PDT 24
Peak memory 216276 kb
Host smart-980e5acb-0473-4104-a9aa-41da70d97bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284070279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.284070279
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.1214846965
Short name T420
Test name
Test status
Simulation time 78037008 ps
CPU time 1.38 seconds
Started Jul 05 06:07:40 PM PDT 24
Finished Jul 05 06:07:42 PM PDT 24
Peak memory 216168 kb
Host smart-05c81e95-adea-465d-a3b1-5c47656d4595
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214846965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.1214846965
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.971043947
Short name T684
Test name
Test status
Simulation time 98161275 ps
CPU time 0.8 seconds
Started Jul 05 06:07:44 PM PDT 24
Finished Jul 05 06:07:46 PM PDT 24
Peak memory 207028 kb
Host smart-476f1ed8-521c-41ab-97ae-a5c9df1f82c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971043947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.971043947
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.2174796464
Short name T920
Test name
Test status
Simulation time 12148715083 ps
CPU time 14.62 seconds
Started Jul 05 06:07:44 PM PDT 24
Finished Jul 05 06:07:59 PM PDT 24
Peak memory 239644 kb
Host smart-4dee3d73-1865-4391-9f70-7f7679160b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174796464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.2174796464
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.3410555893
Short name T461
Test name
Test status
Simulation time 38997387 ps
CPU time 0.72 seconds
Started Jul 05 06:07:53 PM PDT 24
Finished Jul 05 06:07:55 PM PDT 24
Peak memory 204956 kb
Host smart-d771da90-1a7f-4558-977e-7459d2fc53b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410555893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.3
410555893
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.486244915
Short name T882
Test name
Test status
Simulation time 131635785 ps
CPU time 3.42 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 224460 kb
Host smart-344bfb4d-4f4c-4aea-a5b9-3632cd6ff3d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486244915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.486244915
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2758099233
Short name T731
Test name
Test status
Simulation time 53151767 ps
CPU time 0.75 seconds
Started Jul 05 06:07:48 PM PDT 24
Finished Jul 05 06:07:49 PM PDT 24
Peak memory 206936 kb
Host smart-5848bb62-baa3-4461-a481-2ab30b128fff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758099233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2758099233
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3000415913
Short name T257
Test name
Test status
Simulation time 65967473701 ps
CPU time 175.61 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:10:51 PM PDT 24
Peak memory 272140 kb
Host smart-30884b0c-5b80-4503-bd6d-be97241050bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000415913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3000415913
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.1683931886
Short name T653
Test name
Test status
Simulation time 15831873699 ps
CPU time 54.39 seconds
Started Jul 05 06:07:53 PM PDT 24
Finished Jul 05 06:08:49 PM PDT 24
Peak memory 238752 kb
Host smart-739e767a-1feb-44fc-85f1-be07c53010c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683931886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.1683931886
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2992408713
Short name T57
Test name
Test status
Simulation time 5835825436 ps
CPU time 30.38 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:08:24 PM PDT 24
Peak memory 224608 kb
Host smart-bfc84dab-f01d-4965-b5d8-9d4781f63204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992408713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2992408713
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.3652162105
Short name T267
Test name
Test status
Simulation time 8518291628 ps
CPU time 13.05 seconds
Started Jul 05 06:07:42 PM PDT 24
Finished Jul 05 06:07:55 PM PDT 24
Peak memory 249200 kb
Host smart-39f45829-4f40-460f-9c2b-20a536f2879a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3652162105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.3652162105
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.1417802154
Short name T693
Test name
Test status
Simulation time 1761753852 ps
CPU time 23.73 seconds
Started Jul 05 06:07:53 PM PDT 24
Finished Jul 05 06:08:17 PM PDT 24
Peak memory 249112 kb
Host smart-fa335cfa-9415-40f6-81ac-bd3e53e06c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417802154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.1417802154
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.1914651379
Short name T638
Test name
Test status
Simulation time 765882523 ps
CPU time 4.18 seconds
Started Jul 05 06:07:49 PM PDT 24
Finished Jul 05 06:07:54 PM PDT 24
Peak memory 232656 kb
Host smart-af9d808d-05dd-442a-a4ce-a06d2f074964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914651379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.1914651379
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.3630804791
Short name T119
Test name
Test status
Simulation time 1414377956 ps
CPU time 14.38 seconds
Started Jul 05 06:07:42 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 237448 kb
Host smart-549476c4-0c1b-49cc-9e48-d90ae950fc8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630804791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.3630804791
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3119496742
Short name T703
Test name
Test status
Simulation time 7632414438 ps
CPU time 6.96 seconds
Started Jul 05 06:07:46 PM PDT 24
Finished Jul 05 06:07:54 PM PDT 24
Peak memory 232828 kb
Host smart-315544e8-7afe-4ed3-b070-b10f2962a247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119496742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3119496742
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.164780701
Short name T213
Test name
Test status
Simulation time 18629329979 ps
CPU time 12.28 seconds
Started Jul 05 06:07:49 PM PDT 24
Finished Jul 05 06:08:02 PM PDT 24
Peak memory 232800 kb
Host smart-dadf8f6e-3e4c-4e8f-ab87-28f9103f46d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164780701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.164780701
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.1942622824
Short name T944
Test name
Test status
Simulation time 444001366 ps
CPU time 4.19 seconds
Started Jul 05 06:07:57 PM PDT 24
Finished Jul 05 06:08:03 PM PDT 24
Peak memory 222560 kb
Host smart-0ddc0c92-50dd-4f83-88cb-0f9f5af2757c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1942622824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.1942622824
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.712739055
Short name T1000
Test name
Test status
Simulation time 3794091613 ps
CPU time 6.65 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:07 PM PDT 24
Peak memory 217564 kb
Host smart-20795203-52b7-43e7-a8ec-381eb86ed013
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712739055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stress
_all.712739055
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.3005867105
Short name T756
Test name
Test status
Simulation time 2491520272 ps
CPU time 18.21 seconds
Started Jul 05 06:07:49 PM PDT 24
Finished Jul 05 06:08:08 PM PDT 24
Peak memory 216532 kb
Host smart-a09bc990-06d3-4489-ad7e-1ae0c96da774
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005867105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.3005867105
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2909195869
Short name T614
Test name
Test status
Simulation time 569466212 ps
CPU time 1.72 seconds
Started Jul 05 06:07:41 PM PDT 24
Finished Jul 05 06:07:43 PM PDT 24
Peak memory 207924 kb
Host smart-b9b98424-7382-4fca-bd8b-b6cf8f2fa8e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909195869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2909195869
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.1126030121
Short name T832
Test name
Test status
Simulation time 16267310 ps
CPU time 0.78 seconds
Started Jul 05 06:07:44 PM PDT 24
Finished Jul 05 06:07:45 PM PDT 24
Peak memory 206008 kb
Host smart-a8eb29e1-896c-47d9-98cd-97b69fece7b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126030121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.1126030121
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.515006954
Short name T618
Test name
Test status
Simulation time 128274732 ps
CPU time 0.84 seconds
Started Jul 05 06:07:46 PM PDT 24
Finished Jul 05 06:07:47 PM PDT 24
Peak memory 205904 kb
Host smart-53bf57ab-060c-48d2-8a63-23fcc8974dd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515006954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.515006954
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2493033053
Short name T971
Test name
Test status
Simulation time 2092910186 ps
CPU time 10.44 seconds
Started Jul 05 06:07:51 PM PDT 24
Finished Jul 05 06:08:02 PM PDT 24
Peak memory 232696 kb
Host smart-da92b0d6-8d6d-4596-ad88-a0a81180dfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2493033053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2493033053
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.192120141
Short name T1001
Test name
Test status
Simulation time 24024789 ps
CPU time 0.74 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 205552 kb
Host smart-d296051d-e516-4e75-9bb4-e69844b4b242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192120141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.192120141
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.786340447
Short name T665
Test name
Test status
Simulation time 4049154647 ps
CPU time 14.96 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:08:07 PM PDT 24
Peak memory 224508 kb
Host smart-da7f5402-4f2d-4ad0-a0a9-9c69062ce309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786340447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.786340447
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1233465626
Short name T368
Test name
Test status
Simulation time 48901906 ps
CPU time 0.76 seconds
Started Jul 05 06:07:49 PM PDT 24
Finished Jul 05 06:07:51 PM PDT 24
Peak memory 205884 kb
Host smart-32802f51-d303-4dab-9656-ed4459ea6ec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233465626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1233465626
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.3197762707
Short name T164
Test name
Test status
Simulation time 2955511288 ps
CPU time 28.1 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:28 PM PDT 24
Peak memory 238208 kb
Host smart-7698219f-7d7d-48ea-b7ff-431ad2c43827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197762707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.3197762707
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.962696509
Short name T964
Test name
Test status
Simulation time 12243138809 ps
CPU time 120.79 seconds
Started Jul 05 06:07:51 PM PDT 24
Finished Jul 05 06:09:52 PM PDT 24
Peak memory 249288 kb
Host smart-7701cc6f-f8c5-4252-bf60-06c23bff6cef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962696509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.962696509
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.459199869
Short name T953
Test name
Test status
Simulation time 24152470744 ps
CPU time 115.3 seconds
Started Jul 05 06:07:55 PM PDT 24
Finished Jul 05 06:09:52 PM PDT 24
Peak memory 241076 kb
Host smart-a93fa01c-121c-4d86-8311-bcc1396a4691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459199869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
459199869
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.1978333862
Short name T598
Test name
Test status
Simulation time 2270823805 ps
CPU time 4.31 seconds
Started Jul 05 06:07:51 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 224420 kb
Host smart-e64a8a9f-8b88-48e6-a203-7f9d74445325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978333862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.1978333862
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2276764216
Short name T79
Test name
Test status
Simulation time 3322924677 ps
CPU time 45.37 seconds
Started Jul 05 06:07:53 PM PDT 24
Finished Jul 05 06:08:39 PM PDT 24
Peak memory 251708 kb
Host smart-6d69e92a-340d-4c76-8004-6508d7d14a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276764216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2276764216
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.1881673296
Short name T209
Test name
Test status
Simulation time 2619647879 ps
CPU time 5.14 seconds
Started Jul 05 06:07:51 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 224636 kb
Host smart-68741788-2255-49b9-a373-c3e4df1137ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1881673296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.1881673296
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.331138375
Short name T208
Test name
Test status
Simulation time 1115628722 ps
CPU time 11.36 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:11 PM PDT 24
Peak memory 224456 kb
Host smart-77e3bf51-9e0f-47d4-a6bb-c622895f4af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=331138375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.331138375
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.3954675368
Short name T190
Test name
Test status
Simulation time 1728276081 ps
CPU time 4.94 seconds
Started Jul 05 06:07:56 PM PDT 24
Finished Jul 05 06:08:02 PM PDT 24
Peak memory 224432 kb
Host smart-ddadff24-e590-4a77-bab7-c61695f3a8e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954675368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.3954675368
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.248395832
Short name T334
Test name
Test status
Simulation time 677076842 ps
CPU time 6.79 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:08:00 PM PDT 24
Peak memory 232652 kb
Host smart-ad3da180-397a-4788-9a19-0d6961b7f50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248395832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.248395832
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.3128230467
Short name T485
Test name
Test status
Simulation time 3188595300 ps
CPU time 21.8 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:08:18 PM PDT 24
Peak memory 219488 kb
Host smart-6b61c282-38c9-4bc3-a66e-07179f5e71ae
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3128230467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_dire
ct.3128230467
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2278680750
Short name T147
Test name
Test status
Simulation time 94222874 ps
CPU time 0.93 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:00 PM PDT 24
Peak memory 207600 kb
Host smart-0d2ee59e-d582-4796-b3e7-4ae66f3d30a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278680750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2278680750
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.223737037
Short name T406
Test name
Test status
Simulation time 4708298136 ps
CPU time 21.22 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:08:17 PM PDT 24
Peak memory 216400 kb
Host smart-ef7f8ffc-ce3f-45a9-a7bb-05b1d394b50e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223737037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.223737037
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.1977531235
Short name T963
Test name
Test status
Simulation time 862039811 ps
CPU time 5.67 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:08:06 PM PDT 24
Peak memory 216232 kb
Host smart-f31343a4-086d-4886-9a3e-eea0e15a9f28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977531235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.1977531235
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.3171068238
Short name T454
Test name
Test status
Simulation time 331899209 ps
CPU time 1.3 seconds
Started Jul 05 06:07:55 PM PDT 24
Finished Jul 05 06:07:58 PM PDT 24
Peak memory 216028 kb
Host smart-f878166b-d5ea-4145-bf0a-f09544b0543c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171068238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.3171068238
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.2371946137
Short name T308
Test name
Test status
Simulation time 50400417 ps
CPU time 0.83 seconds
Started Jul 05 06:07:55 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 206000 kb
Host smart-d1f65ac9-18d6-4d6d-8b96-7b99f1517c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371946137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.2371946137
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1234350383
Short name T493
Test name
Test status
Simulation time 363245238 ps
CPU time 4.77 seconds
Started Jul 05 06:07:55 PM PDT 24
Finished Jul 05 06:08:01 PM PDT 24
Peak memory 232676 kb
Host smart-f054e616-b402-4aef-b073-7b78e4b083f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234350383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1234350383
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.1077483891
Short name T459
Test name
Test status
Simulation time 12153328 ps
CPU time 0.72 seconds
Started Jul 05 06:07:51 PM PDT 24
Finished Jul 05 06:07:53 PM PDT 24
Peak memory 205488 kb
Host smart-160e2fd5-4420-46be-ae79-ee0b398b01fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077483891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.1
077483891
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.25845481
Short name T785
Test name
Test status
Simulation time 106779164 ps
CPU time 2.34 seconds
Started Jul 05 06:07:59 PM PDT 24
Finished Jul 05 06:08:03 PM PDT 24
Peak memory 224024 kb
Host smart-b113542e-3843-4b53-8ed5-b2c5f8d3b916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=25845481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.25845481
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.1891039260
Short name T298
Test name
Test status
Simulation time 67293717 ps
CPU time 0.8 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 206632 kb
Host smart-d1eabf07-0d1f-47f1-9757-2daa87cc55c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891039260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.1891039260
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.199703990
Short name T960
Test name
Test status
Simulation time 18627122708 ps
CPU time 67.86 seconds
Started Jul 05 06:07:53 PM PDT 24
Finished Jul 05 06:09:02 PM PDT 24
Peak memory 250328 kb
Host smart-0843fe7b-3d42-4038-8541-0767dfc37ef0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199703990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.199703990
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.928998155
Short name T721
Test name
Test status
Simulation time 88209327445 ps
CPU time 193.04 seconds
Started Jul 05 06:07:53 PM PDT 24
Finished Jul 05 06:11:08 PM PDT 24
Peak memory 257484 kb
Host smart-70509456-e1d8-4698-a6b5-ae6f6912bf7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928998155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.928998155
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4019013546
Short name T59
Test name
Test status
Simulation time 2547637792 ps
CPU time 57.36 seconds
Started Jul 05 06:08:00 PM PDT 24
Finished Jul 05 06:08:59 PM PDT 24
Peak memory 257392 kb
Host smart-d495ded9-5a28-491e-b881-55d620b32928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019013546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4019013546
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.2626637148
Short name T375
Test name
Test status
Simulation time 287552604 ps
CPU time 5.57 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:08:01 PM PDT 24
Peak memory 234732 kb
Host smart-70d3ab62-dca9-4085-b016-3de3c3df32cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626637148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.2626637148
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1697620888
Short name T605
Test name
Test status
Simulation time 15898446517 ps
CPU time 127.09 seconds
Started Jul 05 06:07:58 PM PDT 24
Finished Jul 05 06:10:07 PM PDT 24
Peak memory 249220 kb
Host smart-d27394ce-18f2-410e-9ef1-c813b8ce34c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697620888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1697620888
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2658542483
Short name T979
Test name
Test status
Simulation time 249373591 ps
CPU time 2.93 seconds
Started Jul 05 06:07:53 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 232724 kb
Host smart-bf11de7d-0ba3-47b1-b06a-eb154e690f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658542483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2658542483
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.1575823139
Short name T499
Test name
Test status
Simulation time 8108901492 ps
CPU time 34.24 seconds
Started Jul 05 06:07:57 PM PDT 24
Finished Jul 05 06:08:33 PM PDT 24
Peak memory 240148 kb
Host smart-d3282d79-2344-4a87-ad16-c813458789fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575823139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.1575823139
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.2373667248
Short name T47
Test name
Test status
Simulation time 2259745158 ps
CPU time 7.78 seconds
Started Jul 05 06:07:48 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 232736 kb
Host smart-a75f2423-f8e9-458e-bb09-3f694ea278da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373667248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.2373667248
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.2302406220
Short name T911
Test name
Test status
Simulation time 1097645727 ps
CPU time 5.77 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:08:01 PM PDT 24
Peak memory 232676 kb
Host smart-e580886a-0e28-45f0-87cd-c30da39b95d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302406220 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.2302406220
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.2195787752
Short name T544
Test name
Test status
Simulation time 173082390 ps
CPU time 3.93 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:07:57 PM PDT 24
Peak memory 222656 kb
Host smart-939780aa-65a5-4021-929a-dd8aa61373e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2195787752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.2195787752
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3477350716
Short name T936
Test name
Test status
Simulation time 5004771303 ps
CPU time 16.83 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:08:10 PM PDT 24
Peak memory 220012 kb
Host smart-2997741e-5712-459a-893c-c863d3ed82dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477350716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3477350716
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.4291484713
Short name T309
Test name
Test status
Simulation time 8819222630 ps
CPU time 12.12 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:08:05 PM PDT 24
Peak memory 216336 kb
Host smart-d8d31f0f-3621-46fb-9778-de4cf6851104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4291484713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.4291484713
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.2157789466
Short name T689
Test name
Test status
Simulation time 33962448 ps
CPU time 1.1 seconds
Started Jul 05 06:07:52 PM PDT 24
Finished Jul 05 06:07:54 PM PDT 24
Peak memory 207864 kb
Host smart-b6d9b484-7c34-4061-9ed7-e74f58443462
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157789466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.2157789466
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.1369966270
Short name T464
Test name
Test status
Simulation time 141275322 ps
CPU time 0.77 seconds
Started Jul 05 06:07:54 PM PDT 24
Finished Jul 05 06:07:56 PM PDT 24
Peak memory 204840 kb
Host smart-5287383b-a36a-4d20-a222-75bd52f1ec6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369966270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.1369966270
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3085288833
Short name T497
Test name
Test status
Simulation time 614372023 ps
CPU time 4.11 seconds
Started Jul 05 06:07:56 PM PDT 24
Finished Jul 05 06:08:02 PM PDT 24
Peak memory 224480 kb
Host smart-075b6ec0-57b5-4a6e-9387-a89c73f3238b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085288833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3085288833
Directory /workspace/9.spi_device_upload/latest
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