Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2386978	1			T1	1		T4	2271		T5	1
all_values[1]	2386978	1			T1	1		T4	2271		T5	1
all_values[2]	2386978	1			T1	1		T4	2271		T5	1
all_values[3]	2386978	1			T1	1		T4	2271		T5	1
all_values[4]	2386978	1			T1	1		T4	2271		T5	1
all_values[5]	2386978	1			T1	1		T4	2271		T5	1
all_values[6]	2386978	1			T1	1		T4	2271		T5	1
all_values[7]	2386978	1			T1	1		T4	2271		T5	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

18969576

1

T1

8

T4

13617

T5

8

auto[1]

126248

1

T4

4551

T17

184

T18

35519

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19069473

1

T1

8

T4

18013

T5

8

auto[1]

26351

1

T4

155

T17

150

T18

37

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2369920	1			T1	1		T4	4		T5	1
all_values[0]	auto[0]	auto[1]	12472	1			T17	4		T18	3		T19	2
all_values[0]	auto[1]	auto[0]	4315	1			T4	2180		T17	14		T18	4
all_values[0]	auto[1]	auto[1]	271	1			T4	87		T17	8		T18	2
all_values[1]	auto[0]	auto[0]	2364498	1			T1	1		T4	2233		T5	1
all_values[1]	auto[0]	auto[1]	8069	1			T4	34		T17	13		T18	1
all_values[1]	auto[1]	auto[0]	14104	1			T4	2		T17	8		T18	7100
all_values[1]	auto[1]	auto[1]	307	1			T4	2		T17	11		T18	3
all_values[2]	auto[0]	auto[0]	2360585	1			T1	1		T4	2263		T5	1
all_values[2]	auto[0]	auto[1]	3028	1			T4	7		T17	14		T18	4
all_values[2]	auto[1]	auto[0]	23033	1			T17	10		T18	7095		T19	3
all_values[2]	auto[1]	auto[1]	332	1			T4	1		T17	12		T18	3
all_values[3]	auto[0]	auto[0]	2362841	1			T1	1		T4	2		T5	1
all_values[3]	auto[0]	auto[1]	178	1			T17	9		T18	2		T19	3
all_values[3]	auto[1]	auto[0]	23788	1			T4	2266		T17	19		T18	7097
all_values[3]	auto[1]	auto[1]	171	1			T4	3		T17	5		T18	2
all_values[4]	auto[0]	auto[0]	2371949	1			T1	1		T4	2265		T5	1
all_values[4]	auto[0]	auto[1]	210	1			T4	5		T17	6		T18	1
all_values[4]	auto[1]	auto[0]	14642	1			T4	1		T17	17		T18	7097
all_values[4]	auto[1]	auto[1]	177	1			T17	7		T18	3		T19	1
all_values[5]	auto[0]	auto[0]	2368797	1			T1	1		T4	2266		T5	1
all_values[5]	auto[0]	auto[1]	164	1			T4	3		T17	8		T18	2
all_values[5]	auto[1]	auto[0]	17837	1			T17	10		T18	7099		T19	5
all_values[5]	auto[1]	auto[1]	180	1			T4	2		T17	11		T18	4
all_values[6]	auto[0]	auto[0]	2370837	1			T1	1		T4	2264		T5	1
all_values[6]	auto[0]	auto[1]	199	1			T4	3		T17	7		T18	3
all_values[6]	auto[1]	auto[0]	15742	1			T4	1		T17	13		T18	6
all_values[6]	auto[1]	auto[1]	200	1			T4	3		T17	12		T19	1
all_values[7]	auto[0]	auto[0]	2375643	1			T1	1		T4	2265		T5	1
all_values[7]	auto[0]	auto[1]	186	1			T4	3		T17	11		T18	4
all_values[7]	auto[1]	auto[0]	10942	1			T4	1		T17	15		T18	4
all_values[7]	auto[1]	auto[1]	207	1			T4	2		T17	12		T19	4