Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	36598	1			T4	300		T7	8		T12	102
auto[SpiFlashAddrCfg]	7766	1			T4	30		T12	37		T35	2
auto[SpiFlashAddr3b]	9139	1			T4	57		T8	8		T12	63
auto[SpiFlashAddr4b]	7572	1			T4	37		T12	38		T13	2

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34527

1

T4

352

T7

8

T8

8

auto[1]

26548

1

T4

72

T12

104

T13

4

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32587

1

T4

322

T7

6

T8

8

auto[1]

28488

1

T4

102

T7

2

T12

113

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	41201	1			T4	319		T7	8		T8	8
values[1]	1143	1			T4	8		T12	6		T41	4
values[2]	1439	1			T4	14		T12	4		T15	2
values[3]	1443	1			T4	8		T12	5		T14	1
values[4]	1418	1			T12	9		T46	2		T39	9
values[5]	1451	1			T4	10		T12	7		T41	2
values[6]	1485	1			T4	18		T12	6		T14	1
values[7]	1393	1			T4	2		T12	7		T35	2
values[8]	10102	1			T4	45		T12	71		T13	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

35457

1

T4

424

T7

8

T8

8

auto[1]

25618

1

T12

240

T14

2

T40

140

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

57737

1

T4

413

T7

8

T8

8

write

3338

1

T4

11

T12

25

T41

6

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

19161

1

T4

99

T12

107

T13

2

valids[0x1]

41914

1

T4

325

T7

8

T8

8

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1600	1			T4	6		T7	2		T12	8
internal_process_ops[0x5a]	1595	1			T4	10		T12	12		T16	2
internal_process_ops[0x05]	22606	1			T4	248		T12	8		T46	2
internal_process_ops[0x35]	1516	1			T4	6		T7	2		T12	15
internal_process_ops[0x15]	1615	1			T4	4		T7	4		T12	11
internal_process_ops[0x03]	1068	1			T4	12		T8	8		T15	2
internal_process_ops[0x0b]	1076	1			T4	7		T12	1		T14	1
internal_process_ops[0x3b]	1089	1			T4	10		T12	4		T35	2
internal_process_ops[0x6b]	1052	1			T4	7		T12	4		T56	2
internal_process_ops[0xbb]	1144	1			T4	3		T12	4		T14	1
internal_process_ops[0xeb]	1053	1			T4	8		T12	3		T41	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

59478

1

T4

419

T7

8

T8

8

auto[1]

1597

1

T4

5

T12

12

T46

2

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

58626

1

T4

409

T7

8

T8

8

auto[1]

2449

1

T4

15

T12

14

T39

21

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

12028

1

T4

269

T7

8

T16

2

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8657

1

T4

29

T46

4

T39

344

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

2225

1

T4

14

T41

6

T57

6

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1976

1

T4

14

T35

2

T46

6

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2679

1

T4

38

T8

8

T15

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2132

1

T4

15

T13

2

T35

2

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

2107

1

T4

24

T15

2

T41

6

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1879

1

T4

10

T13

2

T46

8

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

135

1

T20

1

T22

2

T55

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T39

1

T20

1

T52

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

114

1

T4

2

T39

2

T52

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

104

1

T39

2

T47

2

T53

6

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

158

1

T41

6

T39

3

T175

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

83

1

T20

1

T52

2

T54

4

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

112

1

T39

1

T20

2

T52

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

102

1

T4

2

T20

4

T52

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

161

1

T4

2

T20

7

T176

6

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

96

1

T4

2

T20

3

T52

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

89

1

T39

2

T20

3

T52

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

105

1

T52

1

T22

2

T55

3

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

100

1

T4

2

T39

1

T20

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

86

1

T4

1

T39

3

T54

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

97

1

T20

1

T52

3

T55

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

129

1

T46

2

T39

1

T20

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

9101

1

T12

61

T40

31

T31

65

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

5972

1

T12

37

T40

19

T31

116

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1449

1

T12

14

T40

15

T31

17

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1305

1

T12

12

T40

6

T31

17

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1736

1

T12

27

T14

2

T40

16

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1712

1

T12

31

T40

10

T31

13

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1483

1

T12

20

T40

10

T31

9

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1296

1

T12

13

T40

10

T31

15

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

84

1

T40

1

T42

1

T22

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

107

1

T12

2

T97

5

T22

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

107

1

T12

2

T40

4

T60

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

86

1

T40

2

T31

2

T97

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

95

1

T12

3

T31

2

T60

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

95

1

T12

4

T40

2

T31

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

73

1

T12

2

T40

2

T31

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

93

1

T12

2

T40

2

T31

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

104

1

T12

2

T40

3

T42

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

110

1

T31

4

T42

1

T43

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

112

1

T12

3

T31

1

T60

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

103

1

T40

7

T60

1

T42

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

95

1

T12

1

T60

2

T42

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

107

1

T12

2

T60

1

T43

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

105

1

T31

1

T60

1

T98

3

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

88

1

T12

2

T60

1

T42

1

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	4012	1			T4	35		T48	18		T50	4
auto[0]	values[0]	valids[0x1]	19727	1			T4	284		T7	8		T8	8
auto[0]	values[1]	valids[0x1]	593	1			T4	8		T41	4		T39	5
auto[0]	values[2]	valids[0x0]	533	1			T4	6		T15	2		T56	2
auto[0]	values[2]	valids[0x1]	312	1			T4	8		T39	1		T108	4
auto[0]	values[3]	valids[0x0]	577	1			T4	7		T39	4		T47	2
auto[0]	values[3]	valids[0x1]	315	1			T4	1		T15	2		T39	1
auto[0]	values[4]	valids[0x0]	562	1			T46	2		T39	4		T177	2
auto[0]	values[4]	valids[0x1]	268	1			T39	5		T20	2		T52	2
auto[0]	values[5]	valids[0x0]	565	1			T4	6		T41	2		T51	2
auto[0]	values[5]	valids[0x1]	332	1			T4	4		T39	3		T52	3
auto[0]	values[6]	valids[0x0]	616	1			T4	11		T35	2		T107	4
auto[0]	values[6]	valids[0x1]	287	1			T4	7		T39	1		T47	2
auto[0]	values[7]	valids[0x0]	527	1			T4	1		T35	2		T107	2
auto[0]	values[7]	valids[0x1]	301	1			T4	1		T39	2		T52	1
auto[0]	values[8]	valids[0x0]	3600	1			T4	33		T13	2		T41	4
auto[0]	values[8]	valids[0x1]	2330	1			T4	12		T13	2		T16	4
auto[1]	values[0]	valids[0x0]	3713	1			T12	47		T40	30		T31	27
auto[1]	values[0]	valids[0x1]	13749	1			T12	78		T40	50		T31	176
auto[1]	values[1]	valids[0x1]	550	1			T12	6		T40	6		T31	8
auto[1]	values[2]	valids[0x0]	355	1			T12	2		T40	3		T31	1
auto[1]	values[2]	valids[0x1]	239	1			T12	2		T40	3		T60	3
auto[1]	values[3]	valids[0x0]	338	1			T12	5		T40	3		T31	4
auto[1]	values[3]	valids[0x1]	213	1			T14	1		T40	4		T60	1
auto[1]	values[4]	valids[0x0]	360	1			T12	4		T40	2		T31	4
auto[1]	values[4]	valids[0x1]	228	1			T12	5		T60	1		T42	4
auto[1]	values[5]	valids[0x0]	329	1			T12	6		T40	5		T31	3
auto[1]	values[5]	valids[0x1]	225	1			T12	1		T31	2		T60	8
auto[1]	values[6]	valids[0x0]	336	1			T12	6		T14	1		T40	4
auto[1]	values[6]	valids[0x1]	246	1			T40	6		T31	2		T178	1
auto[1]	values[7]	valids[0x0]	328	1			T12	4		T40	3		T31	4
auto[1]	values[7]	valids[0x1]	237	1			T12	3		T31	3		T60	6
auto[1]	values[8]	valids[0x0]	2410	1			T12	33		T40	8		T31	26
auto[1]	values[8]	valids[0x1]	1762	1			T12	38		T40	13		T31	22