Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3440299

1

T1

1

T4

10724

T7

10590

auto[1]

29271

1

T4

244

T12

57

T39

493

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

877907

1

T1

1

T4

70

T7

9560

auto[1]

2591663

1

T4

10898

T7

1030

T12

15960

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	738131	1			T1	1		T4	5725		T7	2098
auto[524288:1048575]	402392	1			T4	30		T7	3445		T8	128
auto[1048576:1572863]	411634	1			T4	2854		T11	328		T12	2404
auto[1572864:2097151]	392984	1			T4	840		T8	222		T12	3203
auto[2097152:2621439]	426408	1			T4	156		T8	245		T12	2652
auto[2621440:3145727]	376697	1			T4	15		T7	5034		T8	2930
auto[3145728:3670015]	344111	1			T4	385		T7	2		T8	7
auto[3670016:4194303]	377213	1			T4	963		T7	11		T8	235

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2625686

1

T1

1

T4

10963

T7

1051

auto[1]

843884

1

T4

5

T7

9539

T8

10697

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3006659

1

T1

1

T4

10700

T7

10590

auto[1]

462911

1

T4

268

T12

5913

T48

7

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	240477	1			T1	1		T4	4		T7	1330
auto[0]	auto[0]	auto[0:524287]	auto[1]	430028	1			T4	5706		T7	768		T12	1664
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	92543	1			T4	6		T7	3440		T8	128
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	262624	1			T4	7		T7	5		T12	1435
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	94523	1			T4	10		T11	328		T12	57
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	247244	1			T4	2843		T12	1095		T39	256
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	85671	1			T4	6		T8	222		T12	53
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	245759	1			T4	771		T12	3129		T40	656
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	99421	1			T4	8		T8	245		T12	47
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	257206	1			T4	4		T39	390		T40	2795
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	94747	1			T4	2		T7	4777		T8	2930
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	218760	1			T4	1		T7	257		T12	256
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	97287	1			T7	2		T8	7		T11	1264
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	197767	1			T4	128		T12	1374		T39	523
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	61311	1			T4	7		T7	11		T8	235
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	257615	1			T4	953		T12	1221		T39	389
auto[0]	auto[1]	auto[0:524287]	auto[0]	2859	1			T4	1		T12	7		T50	25
auto[0]	auto[1]	auto[0:524287]	auto[1]	60669	1			T40	128		T31	640		T60	3
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	588	1			T4	1		T12	2		T39	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	42383	1			T39	1		T60	512		T43	1294
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	834	1			T12	63		T31	1		T60	17
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	65624	1			T12	1180		T60	256		T42	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	980	1			T4	5		T12	4		T48	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	57291	1			T12	4		T40	516		T97	256
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	644	1			T4	3		T12	23		T60	48
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	64893	1			T12	2574		T60	137		T20	600
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	567	1			T40	12		T31	3		T60	4
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	59555	1			T40	9		T31	6		T60	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	842	1			T4	1		T12	11		T48	3
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	45123	1			T4	256		T39	128		T31	1
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	560	1			T4	1		T12	6		T48	3
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	53904	1			T12	2028		T31	1		T42	3
auto[1]	auto[0]	auto[0:524287]	auto[0]	524	1			T4	2		T12	3		T39	7
auto[1]	auto[0]	auto[0:524287]	auto[1]	2935	1			T4	12		T39	118		T31	1
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	502	1			T4	2		T39	1		T40	5
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	3161	1			T4	14		T39	7		T31	23
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	383	1			T4	1		T12	6		T31	6
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2210	1			T31	10		T43	3		T97	12
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	402	1			T4	3		T12	11		T40	10
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2145	1			T4	55		T42	2		T20	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	444	1			T4	4		T12	5		T39	2
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3326	1			T4	137		T39	71		T20	11
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	324	1			T4	1		T12	9		T39	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	2087	1			T4	11		T39	11		T60	70
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	370	1			T12	8		T39	4		T60	6
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2080	1			T39	113		T42	62		T20	6
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	399	1			T4	2		T12	4		T39	5
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2384	1			T39	133		T97	16		T52	22
auto[1]	auto[1]	auto[0:524287]	auto[0]	119	1			T42	6		T98	2		T55	1
auto[1]	auto[1]	auto[0:524287]	auto[1]	520	1			T98	19		T55	1		T44	1
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	66	1			T39	1		T60	3		T97	2
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	525	1			T39	19		T97	5		T22	15
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	80	1			T12	3		T20	1		T97	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	736	1			T20	9		T97	35		T22	1
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	91	1			T12	2		T40	5		T60	5
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	645	1			T209	35		T214	1		T245	512
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	84	1			T12	3		T60	10		T20	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	390	1			T60	123		T20	14		T206	3
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	79	1			T31	3		T193	2		T221	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	578	1			T31	55		T193	25		T221	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	87	1			T12	3		T31	1		T97	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	555	1			T31	9		T97	4		T55	12
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	99	1			T31	1		T52	1		T98	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	941	1			T31	10		T52	62		T98	31

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	2143033	1			T1	1		T4	10452		T7	1051
auto[0]	auto[0]	auto[1]	839950	1			T4	4		T7	9539		T8	10697
auto[0]	auto[1]	auto[0]	454083	1			T4	268		T12	5902		T48	7
auto[0]	auto[1]	auto[1]	3233	1			T50	68		T31	4		T97	3
auto[1]	auto[0]	auto[0]	23094	1			T4	243		T12	40		T39	471
auto[1]	auto[0]	auto[1]	582	1			T4	1		T12	6		T39	2
auto[1]	auto[1]	auto[0]	5476	1			T12	8		T39	19		T40	4
auto[1]	auto[1]	auto[1]	119	1			T12	3		T39	1		T40	1