Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2386978	1			T1	1		T4	2271		T5	1
all_pins[1]	2386978	1			T1	1		T4	2271		T5	1
all_pins[2]	2386978	1			T1	1		T4	2271		T5	1
all_pins[3]	2386978	1			T1	1		T4	2271		T5	1
all_pins[4]	2386978	1			T1	1		T4	2271		T5	1
all_pins[5]	2386978	1			T1	1		T4	2271		T5	1
all_pins[6]	2386978	1			T1	1		T4	2271		T5	1
all_pins[7]	2386978	1			T1	1		T4	2271		T5	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19077721	1			T1	8		T4	18053		T5	8
values[0x1]	18103	1			T4	115		T17	78		T18	394
transitions[0x0=>0x1]	17515	1			T4	111		T17	59		T18	387
transitions[0x1=>0x0]	17521	1			T4	111		T17	60		T18	387

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2386683	1			T1	1		T4	2169		T5	1
all_pins[0]	values[0x1]	295	1			T4	102		T17	8		T18	2
all_pins[0]	transitions[0x0=>0x1]	246	1			T4	101		T17	6		T18	2
all_pins[0]	transitions[0x1=>0x0]	265	1			T4	1		T17	9		T18	3
all_pins[1]	values[0x0]	2386664	1			T1	1		T4	2269		T5	1
all_pins[1]	values[0x1]	314	1			T4	2		T17	11		T18	3
all_pins[1]	transitions[0x0=>0x1]	220	1			T4	1		T17	7		T18	1
all_pins[1]	transitions[0x1=>0x0]	253	1			T17	8		T18	1		T21	2
all_pins[2]	values[0x0]	2386631	1			T1	1		T4	2270		T5	1
all_pins[2]	values[0x1]	347	1			T4	1		T17	12		T18	3
all_pins[2]	transitions[0x0=>0x1]	293	1			T17	11		T18	1		T19	2
all_pins[2]	transitions[0x1=>0x0]	117	1			T4	2		T17	4		T19	1
all_pins[3]	values[0x0]	2386807	1			T1	1		T4	2268		T5	1
all_pins[3]	values[0x1]	171	1			T4	3		T17	5		T18	2
all_pins[3]	transitions[0x0=>0x1]	134	1			T4	3		T17	3		T19	2
all_pins[3]	transitions[0x1=>0x0]	140	1			T17	5		T18	1		T19	1
all_pins[4]	values[0x0]	2386801	1			T1	1		T4	2271		T5	1
all_pins[4]	values[0x1]	177	1			T17	7		T18	3		T19	1
all_pins[4]	transitions[0x0=>0x1]	145	1			T17	7		T18	2		T19	1
all_pins[4]	transitions[0x1=>0x0]	1271	1			T4	2		T17	11		T18	380
all_pins[5]	values[0x0]	2385675	1			T1	1		T4	2269		T5	1
all_pins[5]	values[0x1]	1303	1			T4	2		T17	11		T18	381
all_pins[5]	transitions[0x0=>0x1]	1068	1			T4	2		T17	7		T18	381
all_pins[5]	transitions[0x1=>0x0]	15054	1			T4	3		T17	8		T19	1
all_pins[6]	values[0x0]	2371689	1			T1	1		T4	2268		T5	1
all_pins[6]	values[0x1]	15289	1			T4	3		T17	12		T19	1
all_pins[6]	transitions[0x0=>0x1]	15245	1			T4	2		T17	8		T19	1
all_pins[6]	transitions[0x1=>0x0]	163	1			T4	1		T17	8		T19	4
all_pins[7]	values[0x0]	2386771	1			T1	1		T4	2269		T5	1
all_pins[7]	values[0x1]	207	1			T4	2		T17	12		T19	4
all_pins[7]	transitions[0x0=>0x1]	164	1			T4	2		T17	10		T19	4
all_pins[7]	transitions[0x1=>0x0]	258	1			T4	102		T17	7		T18	2