Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19961

1

T4

352

T7

8

T8

8

auto[1]

15496

1

T4

72

T13

4

T35

4

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4519	1			T4	40		T7	8		T56	2
values[1]	3795	1			T4	20		T39	213		T254	2
values[2]	4515	1			T8	8		T20	126		T72	22
values[3]	4369	1			T13	4		T48	18		T57	10
values[4]	4408	1			T4	22		T39	121		T108	20
values[5]	5264	1			T4	140		T15	4		T20	53
values[6]	4078	1			T4	128		T35	4		T41	20
values[7]	4509	1			T4	74		T16	6		T46	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4889	1			T4	20		T13	4		T16	6
values[1]	3867	1			T39	61		T254	2		T20	45
values[2]	4005	1			T4	20		T48	18		T175	4
values[3]	5850	1			T4	56		T8	8		T15	4
values[4]	4124	1			T20	100		T52	32		T22	42
values[5]	4266	1			T4	38		T50	4		T39	152
values[6]	4558	1			T4	162		T7	8		T39	108
values[7]	3898	1			T4	128		T35	4		T41	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	258	1			T54	13		T55	11		T255	4
auto[0]	values[0]	values[1]	307	1			T22	74		T71	2		T54	12
auto[0]	values[0]	values[2]	387	1			T4	13		T175	4		T256	4
auto[0]	values[0]	values[3]	453	1			T4	15		T56	2		T51	20
auto[0]	values[0]	values[4]	272	1			T20	16		T55	18		T209	10
auto[0]	values[0]	values[5]	306	1			T22	16		T209	17		T211	11
auto[0]	values[0]	values[6]	299	1			T7	8		T39	17		T219	6
auto[0]	values[0]	values[7]	196	1			T52	14		T22	17		T55	11
auto[0]	values[1]	values[0]	387	1			T4	12		T177	20		T23	14
auto[0]	values[1]	values[1]	259	1			T39	7		T254	2		T22	12
auto[0]	values[1]	values[2]	340	1			T20	14		T55	8		T24	12
auto[0]	values[1]	values[3]	375	1			T257	20		T215	11		T258	14
auto[0]	values[1]	values[4]	220	1			T52	19		T22	10		T74	10
auto[0]	values[1]	values[5]	349	1			T39	14		T259	6		T214	9
auto[0]	values[1]	values[6]	182	1			T217	8		T218	16		T260	2
auto[0]	values[1]	values[7]	147	1			T247	8		T44	26		T226	16
auto[0]	values[2]	values[0]	455	1			T261	14		T204	10		T262	153
auto[0]	values[2]	values[1]	203	1			T209	111		T263	2		T261	10
auto[0]	values[2]	values[2]	252	1			T20	29		T232	14		T264	6
auto[0]	values[2]	values[3]	204	1			T8	8		T72	22		T214	12
auto[0]	values[2]	values[4]	302	1			T20	25		T211	13		T251	10
auto[0]	values[2]	values[5]	594	1			T20	11		T202	18		T34	111
auto[0]	values[2]	values[6]	301	1			T55	30		T248	8		T265	6
auto[0]	values[2]	values[7]	181	1			T266	2		T251	12		T262	9
auto[0]	values[3]	values[0]	194	1			T209	16		T217	6		T267	2
auto[0]	values[3]	values[1]	275	1			T20	7		T52	36		T55	9
auto[0]	values[3]	values[2]	267	1			T48	18		T44	19		T167	58
auto[0]	values[3]	values[3]	310	1			T57	10		T39	69		T20	7
auto[0]	values[3]	values[4]	203	1			T55	12		T211	14		T268	4
auto[0]	values[3]	values[5]	430	1			T52	12		T231	14		T199	11
auto[0]	values[3]	values[6]	381	1			T39	9		T244	53		T212	20
auto[0]	values[3]	values[7]	264	1			T240	10		T217	32		T207	7
auto[0]	values[4]	values[0]	534	1			T39	116		T23	17		T234	8
auto[0]	values[4]	values[1]	328	1			T55	24		T269	2		T218	11
auto[0]	values[4]	values[2]	298	1			T270	6		T206	21		T211	8
auto[0]	values[4]	values[3]	447	1			T54	29		T44	9		T209	178
auto[0]	values[4]	values[4]	410	1			T44	13		T209	53		T169	20
auto[0]	values[4]	values[5]	108	1			T44	14		T214	11		T262	9
auto[0]	values[4]	values[6]	243	1			T4	19		T108	20		T55	8
auto[0]	values[4]	values[7]	267	1			T54	8		T34	6		T167	10
auto[0]	values[5]	values[0]	402	1			T20	12		T70	16		T23	13
auto[0]	values[5]	values[1]	375	1			T20	15		T52	55		T271	12
auto[0]	values[5]	values[2]	160	1			T44	10		T272	10		T273	6
auto[0]	values[5]	values[3]	442	1			T15	4		T23	7		T44	17
auto[0]	values[5]	values[4]	487	1			T22	11		T55	70		T198	15
auto[0]	values[5]	values[5]	259	1			T274	4		T275	12		T204	11
auto[0]	values[5]	values[6]	391	1			T4	128		T52	12		T44	22
auto[0]	values[5]	values[7]	433	1			T52	14		T23	13		T198	20
auto[0]	values[6]	values[0]	399	1			T107	10		T22	23		T54	14
auto[0]	values[6]	values[1]	184	1			T22	15		T208	4		T44	21
auto[0]	values[6]	values[2]	150	1			T52	14		T227	6		T232	9
auto[0]	values[6]	values[3]	374	1			T39	9		T176	26		T55	62
auto[0]	values[6]	values[4]	212	1			T20	10		T276	16		T199	7
auto[0]	values[6]	values[5]	277	1			T44	14		T232	9		T211	12
auto[0]	values[6]	values[6]	306	1			T23	6		T44	35		T211	20
auto[0]	values[6]	values[7]	394	1			T4	122		T41	20		T49	37
auto[0]	values[7]	values[0]	235	1			T16	6		T76	10		T202	12
auto[0]	values[7]	values[1]	206	1			T202	9		T166	9		T277	12
auto[0]	values[7]	values[2]	310	1			T20	12		T278	6		T217	9
auto[0]	values[7]	values[3]	675	1			T4	12		T52	13		T22	102
auto[0]	values[7]	values[4]	285	1			T20	15		T279	8		T200	25
auto[0]	values[7]	values[5]	175	1			T4	31		T50	4		T206	11
auto[0]	values[7]	values[6]	335	1			T202	10		T209	15		T166	11
auto[0]	values[7]	values[7]	307	1			T39	12		T20	13		T44	9
auto[1]	values[0]	values[0]	292	1			T47	16		T54	7		T55	9
auto[1]	values[0]	values[1]	126	1			T22	5		T54	8		T251	10
auto[1]	values[0]	values[2]	350	1			T4	7		T217	40		T199	11
auto[1]	values[0]	values[3]	419	1			T4	5		T54	69		T198	7
auto[1]	values[0]	values[4]	209	1			T20	7		T55	2		T209	10
auto[1]	values[0]	values[5]	272	1			T22	11		T209	23		T211	9
auto[1]	values[0]	values[6]	141	1			T39	15		T211	6		T280	7
auto[1]	values[0]	values[7]	232	1			T52	6		T22	12		T55	11
auto[1]	values[1]	values[0]	228	1			T4	8		T23	28		T44	15
auto[1]	values[1]	values[1]	238	1			T39	54		T22	12		T34	40
auto[1]	values[1]	values[2]	234	1			T20	6		T55	12		T24	13
auto[1]	values[1]	values[3]	183	1			T281	12		T215	23		T229	8
auto[1]	values[1]	values[4]	83	1			T52	13		T22	10		T229	8
auto[1]	values[1]	values[5]	233	1			T39	138		T214	11		T282	9
auto[1]	values[1]	values[6]	233	1			T217	12		T218	4		T169	6
auto[1]	values[1]	values[7]	104	1			T44	24		T226	6		T280	6
auto[1]	values[2]	values[0]	187	1			T261	45		T204	11		T262	5
auto[1]	values[2]	values[1]	182	1			T209	6		T261	10		T200	21
auto[1]	values[2]	values[2]	315	1			T20	5		T232	6		T214	9
auto[1]	values[2]	values[3]	210	1			T214	9		T262	10		T283	13
auto[1]	values[2]	values[4]	276	1			T20	10		T211	7		T251	33
auto[1]	values[2]	values[5]	520	1			T20	46		T202	5		T34	26
auto[1]	values[2]	values[6]	187	1			T55	9		T248	12		T226	10
auto[1]	values[2]	values[7]	146	1			T251	8		T262	11		T226	8
auto[1]	values[3]	values[0]	172	1			T13	4		T209	4		T217	22
auto[1]	values[3]	values[1]	316	1			T20	13		T52	6		T55	11
auto[1]	values[3]	values[2]	337	1			T44	1		T167	6		T262	195
auto[1]	values[3]	values[3]	175	1			T39	12		T20	13		T229	9
auto[1]	values[3]	values[4]	214	1			T55	30		T211	7		T226	13
auto[1]	values[3]	values[5]	103	1			T52	8		T199	9		T204	7
auto[1]	values[3]	values[6]	416	1			T39	67		T214	13		T217	14
auto[1]	values[3]	values[7]	312	1			T217	64		T207	43		T225	40
auto[1]	values[4]	values[0]	328	1			T39	5		T23	7		T232	6
auto[1]	values[4]	values[1]	198	1			T55	9		T218	9		T284	6
auto[1]	values[4]	values[2]	206	1			T285	18		T206	7		T211	12
auto[1]	values[4]	values[3]	139	1			T54	7		T44	13		T209	5
auto[1]	values[4]	values[4]	339	1			T44	10		T209	8		T286	6
auto[1]	values[4]	values[5]	126	1			T44	6		T287	16		T214	10
auto[1]	values[4]	values[6]	211	1			T4	3		T55	33		T34	5
auto[1]	values[4]	values[7]	226	1			T54	12		T34	14		T167	10
auto[1]	values[5]	values[0]	390	1			T20	16		T23	7		T202	12
auto[1]	values[5]	values[1]	321	1			T20	10		T52	11		T228	22
auto[1]	values[5]	values[2]	80	1			T44	10		T214	8		T215	14
auto[1]	values[5]	values[3]	589	1			T23	113		T44	3		T211	7
auto[1]	values[5]	values[4]	267	1			T22	11		T55	6		T198	9
auto[1]	values[5]	values[5]	187	1			T204	12		T288	8		T195	11
auto[1]	values[5]	values[6]	247	1			T4	12		T52	14		T44	10
auto[1]	values[5]	values[7]	234	1			T52	8		T23	7		T198	6
auto[1]	values[6]	values[0]	244	1			T22	23		T54	68		T34	6
auto[1]	values[6]	values[1]	146	1			T22	12		T44	4		T218	9
auto[1]	values[6]	values[2]	123	1			T52	6		T232	11		T218	9
auto[1]	values[6]	values[3]	406	1			T39	84		T55	5		T34	9
auto[1]	values[6]	values[4]	110	1			T20	12		T276	4		T199	13
auto[1]	values[6]	values[5]	193	1			T44	13		T232	11		T211	45
auto[1]	values[6]	values[6]	293	1			T23	14		T44	7		T211	44
auto[1]	values[6]	values[7]	267	1			T4	6		T35	4		T209	10
auto[1]	values[7]	values[0]	184	1			T202	54		T232	8		T261	11
auto[1]	values[7]	values[1]	203	1			T53	20		T202	18		T166	11
auto[1]	values[7]	values[2]	196	1			T20	12		T217	15		T199	13
auto[1]	values[7]	values[3]	449	1			T4	24		T52	70		T22	13
auto[1]	values[7]	values[4]	235	1			T20	5		T289	24		T200	34
auto[1]	values[7]	values[5]	134	1			T4	7		T206	9		T214	17
auto[1]	values[7]	values[6]	392	1			T202	10		T209	5		T166	9
auto[1]	values[7]	values[7]	188	1			T46	20		T39	25		T20	7