Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	348	1			T4	2		T39	2		T219	2
auto[ReadAddrCrossIntoMailbox]	317	1			T4	2		T8	4		T39	3
auto[ReadAddrCrossOutOfMailbox]	310	1			T4	3		T8	4		T57	2
auto[ReadAddrCrossAllMailbox]	189	1			T57	2		T39	4		T20	1
auto[ReadAddrOutsideMailbox]	3803	1			T4	40		T15	2		T16	2

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2501

1

T4

21

T8

4

T15

1

auto[1]

2466

1

T4

26

T8

4

T15

1

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	804	1			T4	12		T8	8		T15	2
read_ops[0x0b]	850	1			T4	7		T16	2		T57	6
read_ops[0x3b]	857	1			T4	10		T35	2		T41	2
read_ops[0x6b]	779	1			T4	7		T56	2		T107	2
read_ops[0xbb]	883	1			T4	3		T35	2		T46	4
read_ops[0xeb]	794	1			T4	8		T41	2		T46	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	20	1			T292	2		T265	1		T293	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T22	1		T292	2		T23	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T8	2		T39	1		T52	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	35	1			T4	2		T8	2		T20	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T8	2		T52	1		T22	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T4	2		T8	2		T20	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	11	1			T207	2		T149	1		T294	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T39	2		T20	1		T209	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	315	1			T4	3		T15	1		T46	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T4	5		T15	1		T46	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T20	1		T52	1		T198	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	34	1			T22	1		T54	1		T55	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T166	2		T199	2		T261	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	29	1			T55	1		T217	1		T167	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T55	1		T265	2		T166	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T248	1		T44	1		T265	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T52	1		T227	1		T44	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	22	1			T227	1		T217	1		T199	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	339	1			T4	4		T16	1		T57	3
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	314	1			T4	3		T16	1		T57	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	32	1			T39	1		T219	1		T22	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	35	1			T219	1		T44	1		T166	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	27	1			T20	2		T54	1		T202	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T54	1		T44	1		T261	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T20	1		T209	1		T295	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T23	1		T44	1		T211	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	19	1			T39	1		T54	1		T202	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	12	1			T52	2		T44	1		T204	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	323	1			T4	5		T35	1		T41	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	340	1			T4	5		T35	1		T41	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T52	1		T23	1		T209	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	24	1			T20	1		T54	1		T55	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T52	1		T22	1		T214	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T54	1		T55	1		T166	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	22	1			T52	1		T22	1		T44	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T52	1		T54	1		T23	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T23	1		T217	1		T204	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T55	1		T261	1		T204	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	327	1			T4	4		T56	1		T107	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	277	1			T4	3		T56	1		T107	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T20	1		T292	1		T248	1
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	28	1			T4	1		T39	1		T292	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T39	1		T23	2		T199	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T39	1		T22	2		T44	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	33	1			T20	2		T52	1		T44	3
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	37	1			T39	1		T52	1		T22	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	20	1			T39	1		T23	1		T248	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	14	1			T217	1		T167	1		T199	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	330	1			T4	2		T35	1		T46	2
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	344	1			T35	1		T46	2		T107	2
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	37	1			T55	1		T23	1		T44	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	23	1			T4	1		T20	1		T55	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T22	1		T34	1		T44	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T52	1		T54	1		T55	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	31	1			T57	1		T54	1		T55	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T4	1		T57	1		T20	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T57	1		T55	1		T217	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T57	1		T52	1		T55	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	287	1			T4	3		T41	1		T46	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	311	1			T4	3		T41	1		T46	1