Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	4084	1			T4	120		T8	8		T48	18
values[1]	4454	1			T46	20		T39	145		T175	4
values[2]	3630	1			T13	4		T41	20		T50	4
values[3]	4826	1			T4	42		T35	4		T219	6
values[4]	4149	1			T4	36		T16	6		T56	2
values[5]	4423	1			T4	168		T7	8		T15	4
values[6]	4425	1			T4	38		T107	10		T20	20
values[7]	5466	1			T4	20		T39	233		T49	37

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	5038	1			T39	37		T49	37		T20	92
values[1]	4404	1			T107	10		T39	81		T219	6
values[2]	3500	1			T4	56		T48	18		T50	4
values[3]	4643	1			T4	58		T7	8		T16	6
values[4]	4219	1			T4	150		T57	10		T39	76
values[5]	4729	1			T41	20		T39	61		T47	16
values[6]	4456	1			T4	140		T8	8		T13	4
values[7]	4468	1			T4	20		T39	277		T254	2

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

34649

1

T4

419

T7

8

T8

8

auto[1]

808

1

T4

5

T46

2

T39

7

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	658	1			T278	6		T24	25		T44	35
auto[0]	values[0]	values[1]	600	1			T20	34		T22	80		T296	12
auto[0]	values[0]	values[2]	229	1			T48	18		T166	19		T297	12
auto[0]	values[0]	values[3]	491	1			T76	10		T44	27		T232	18
auto[0]	values[0]	values[4]	472	1			T108	20		T55	20		T44	24
auto[0]	values[0]	values[5]	431	1			T20	21		T52	31		T217	20
auto[0]	values[0]	values[6]	446	1			T4	120		T8	8		T52	20
auto[0]	values[0]	values[7]	646	1			T22	24		T55	19		T198	24
auto[0]	values[1]	values[0]	556	1			T39	35		T54	82		T166	19
auto[0]	values[1]	values[1]	602	1			T34	25		T232	19		T265	6
auto[0]	values[1]	values[2]	350	1			T175	4		T298	18		T262	30
auto[0]	values[1]	values[3]	892	1			T46	18		T20	20		T202	66
auto[0]	values[1]	values[4]	440	1			T39	74		T259	6		T209	20
auto[0]	values[1]	values[5]	624	1			T74	10		T34	20		T44	19
auto[0]	values[1]	values[6]	239	1			T22	29		T232	20		T214	19
auto[0]	values[1]	values[7]	647	1			T39	32		T211	20		T293	2
auto[0]	values[2]	values[0]	357	1			T20	90		T52	19		T208	4
auto[0]	values[2]	values[1]	295	1			T198	39		T216	4		T199	20
auto[0]	values[2]	values[2]	478	1			T50	4		T44	20		T209	20
auto[0]	values[2]	values[3]	267	1			T209	20		T211	52		T214	20
auto[0]	values[2]	values[4]	300	1			T57	10		T55	38		T299	6
auto[0]	values[2]	values[5]	892	1			T41	20		T52	123		T22	27
auto[0]	values[2]	values[6]	587	1			T13	4		T52	20		T217	75
auto[0]	values[2]	values[7]	379	1			T22	20		T209	20		T215	108
auto[0]	values[3]	values[0]	820	1			T22	79		T211	20		T261	20
auto[0]	values[3]	values[1]	340	1			T219	6		T55	19		T247	8
auto[0]	values[3]	values[2]	491	1			T52	65		T202	27		T214	22
auto[0]	values[3]	values[3]	803	1			T4	20		T176	26		T44	42
auto[0]	values[3]	values[4]	592	1			T4	22		T51	20		T23	40
auto[0]	values[3]	values[5]	336	1			T55	20		T233	4		T217	60
auto[0]	values[3]	values[6]	634	1			T35	4		T248	20		T209	61
auto[0]	values[3]	values[7]	705	1			T53	14		T22	26		T23	24
auto[0]	values[4]	values[0]	396	1			T55	33		T44	32		T272	10
auto[0]	values[4]	values[1]	506	1			T44	22		T225	41		T226	23
auto[0]	values[4]	values[2]	653	1			T4	36		T55	39		T34	20
auto[0]	values[4]	values[3]	336	1			T16	6		T56	2		T209	38
auto[0]	values[4]	values[4]	506	1			T215	59		T300	84		T239	8
auto[0]	values[4]	values[5]	570	1			T39	60		T270	6		T44	21
auto[0]	values[4]	values[6]	542	1			T44	27		T209	19		T206	26
auto[0]	values[4]	values[7]	544	1			T254	2		T20	20		T23	20
auto[0]	values[5]	values[0]	854	1			T44	23		T199	40		T215	59
auto[0]	values[5]	values[1]	479	1			T72	22		T167	61		T207	20
auto[0]	values[5]	values[2]	596	1			T39	120		T52	25		T55	67
auto[0]	values[5]	values[3]	544	1			T7	8		T177	20		T55	38
auto[0]	values[5]	values[4]	405	1			T4	125		T20	91		T54	19
auto[0]	values[5]	values[5]	515	1			T47	14		T217	28		T167	20
auto[0]	values[5]	values[6]	436	1			T4	20		T15	4		T23	117
auto[0]	values[5]	values[7]	485	1			T4	20		T39	93		T202	20
auto[0]	values[6]	values[0]	593	1			T198	20		T34	136		T44	17
auto[0]	values[6]	values[1]	669	1			T107	10		T256	4		T214	22
auto[0]	values[6]	values[2]	430	1			T292	10		T44	19		T234	8
auto[0]	values[6]	values[3]	564	1			T4	36		T52	20		T227	6
auto[0]	values[6]	values[4]	678	1			T20	16		T214	20		T199	20
auto[0]	values[6]	values[5]	330	1			T232	18		T291	6		T206	37
auto[0]	values[6]	values[6]	719	1			T54	20		T23	20		T255	4
auto[0]	values[6]	values[7]	333	1			T22	41		T70	16		T34	44
auto[0]	values[7]	values[0]	662	1			T49	37		T54	34		T285	18
auto[0]	values[7]	values[1]	809	1			T39	80		T271	12		T209	180
auto[0]	values[7]	values[2]	192	1			T4	20		T55	20		T218	20
auto[0]	values[7]	values[3]	647	1			T20	25		T22	35		T23	20
auto[0]	values[7]	values[4]	732	1			T20	20		T22	25		T54	20
auto[0]	values[7]	values[5]	926	1			T54	80		T209	20		T90	6
auto[0]	values[7]	values[6]	762	1			T55	76		T240	10		T211	85
auto[0]	values[7]	values[7]	637	1			T39	152		T71	2		T211	17
auto[1]	values[0]	values[0]	29	1			T44	1		T211	4		T288	6
auto[1]	values[0]	values[1]	14	1			T201	3		T104	5		T301	2
auto[1]	values[0]	values[2]	7	1			T166	1		T226	1		T294	2
auto[1]	values[0]	values[3]	13	1			T232	2		T302	1		T303	3
auto[1]	values[0]	values[4]	6	1			T44	1		T211	3		T172	2
auto[1]	values[0]	values[5]	11	1			T20	1		T52	1		T167	1
auto[1]	values[0]	values[6]	5	1			T44	2		T171	2		T304	1
auto[1]	values[0]	values[7]	26	1			T55	1		T228	2		T167	4
auto[1]	values[1]	values[0]	13	1			T39	2		T166	1		T226	1
auto[1]	values[1]	values[1]	19	1			T34	1		T232	1		T209	1
auto[1]	values[1]	values[2]	11	1			T205	6		T283	1		T38	3
auto[1]	values[1]	values[3]	21	1			T46	2		T288	4		T149	2
auto[1]	values[1]	values[4]	11	1			T39	2		T226	2		T305	5
auto[1]	values[1]	values[5]	10	1			T44	1		T209	1		T195	4
auto[1]	values[1]	values[6]	6	1			T214	1		T210	1		T196	4
auto[1]	values[1]	values[7]	13	1			T149	4		T306	4		T64	2
auto[1]	values[2]	values[0]	18	1			T20	2		T52	1		T211	1
auto[1]	values[2]	values[1]	9	1			T215	2		T261	1		T191	2
auto[1]	values[2]	values[2]	3	1			T307	2		T308	1		-	-
auto[1]	values[2]	values[3]	2	1			T211	2		-	-		-	-
auto[1]	values[2]	values[4]	9	1			T55	3		T149	3		T306	1
auto[1]	values[2]	values[5]	12	1			T52	2		T217	2		T288	4
auto[1]	values[2]	values[6]	14	1			T52	2		T217	1		T262	2
auto[1]	values[2]	values[7]	8	1			T215	2		T171	1		T309	5
auto[1]	values[3]	values[0]	19	1			T253	2		T310	2		T302	4
auto[1]	values[3]	values[1]	11	1			T55	1		T280	1		T200	1
auto[1]	values[3]	values[2]	18	1			T52	1		T217	1		T311	2
auto[1]	values[3]	values[3]	10	1			T251	2		T262	1		T222	2
auto[1]	values[3]	values[4]	11	1			T23	2		T141	3		T312	1
auto[1]	values[3]	values[5]	5	1			T288	2		T313	2		T314	1
auto[1]	values[3]	values[6]	15	1			T214	2		T225	1		T201	1
auto[1]	values[3]	values[7]	16	1			T53	6		T217	3		T253	1
auto[1]	values[4]	values[0]	11	1			T211	1		T276	2		T210	1
auto[1]	values[4]	values[1]	14	1			T225	5		T253	1		T315	1
auto[1]	values[4]	values[2]	13	1			T55	3		T210	2		T222	2
auto[1]	values[4]	values[3]	11	1			T209	2		T141	2		T305	2
auto[1]	values[4]	values[4]	7	1			T300	1		T239	4		T316	2
auto[1]	values[4]	values[5]	15	1			T39	1		T44	2		T229	1
auto[1]	values[4]	values[6]	19	1			T44	3		T209	1		T206	2
auto[1]	values[4]	values[7]	6	1			T198	1		T309	2		T65	2
auto[1]	values[5]	values[0]	17	1			T199	4		T261	1		T262	2
auto[1]	values[5]	values[1]	10	1			T167	3		T300	1		T306	3
auto[1]	values[5]	values[2]	7	1			T39	1		T52	1		T169	1
auto[1]	values[5]	values[3]	18	1			T55	1		T166	1		T201	2
auto[1]	values[5]	values[4]	18	1			T4	3		T20	4		T54	1
auto[1]	values[5]	values[5]	26	1			T47	2		T204	1		T169	4
auto[1]	values[5]	values[6]	5	1			T23	3		T304	1		T317	1
auto[1]	values[5]	values[7]	8	1			T211	1		T316	1		T318	2
auto[1]	values[6]	values[0]	15	1			T34	5		T44	3		T214	1
auto[1]	values[6]	values[1]	17	1			T251	1		T207	1		T222	2
auto[1]	values[6]	values[2]	14	1			T44	1		T319	2		T316	2
auto[1]	values[6]	values[3]	17	1			T4	2		T251	4		T195	1
auto[1]	values[6]	values[4]	15	1			T20	4		T214	1		T215	1
auto[1]	values[6]	values[5]	8	1			T232	2		T320	1		T316	1
auto[1]	values[6]	values[6]	18	1			T282	1		T210	1		T280	3
auto[1]	values[6]	values[7]	5	1			T22	1		T34	2		T214	1
auto[1]	values[7]	values[0]	20	1			T54	2		T225	1		T200	2
auto[1]	values[7]	values[1]	10	1			T39	1		T209	3		T321	1
auto[1]	values[7]	values[2]	8	1			T55	2		T204	4		T169	1
auto[1]	values[7]	values[3]	7	1			T195	2		T312	1		T304	4
auto[1]	values[7]	values[4]	17	1			T22	2		T202	1		T322	2
auto[1]	values[7]	values[5]	18	1			T54	2		T251	1		T204	1
auto[1]	values[7]	values[6]	9	1			T323	2		T261	1		T236	1
auto[1]	values[7]	values[7]	10	1			T211	3		T300	1		T141	1