Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	811	1			T4	7		T17	38		T18	10
all_values[1]	811	1			T4	7		T17	38		T18	10
all_values[2]	811	1			T4	7		T17	38		T18	10
all_values[3]	811	1			T4	7		T17	38		T18	10
all_values[4]	811	1			T4	7		T17	38		T18	10
all_values[5]	811	1			T4	7		T17	38		T18	10
all_values[6]	811	1			T4	7		T17	38		T18	10
all_values[7]	811	1			T4	7		T17	38		T18	10

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3478

1

T4

37

T17

170

T18

43

auto[1]

3010

1

T4

19

T17

134

T18

37

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2688

1

T4

13

T17

121

T18

30

auto[1]

3800

1

T4

43

T17

183

T18

50

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3772

1

T4

25

T17

174

T18

45

auto[1]

2716

1

T4

31

T17

130

T18

35

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	178	1			T4	1		T17	13		T18	1
all_values[0]	auto[0]	auto[0]	auto[1]	84	1			T17	1		T18	2		T19	1
all_values[0]	auto[0]	auto[1]	auto[0]	131	1			T4	2		T17	8		T18	2
all_values[0]	auto[0]	auto[1]	auto[1]	71	1			T4	1		T17	2		T18	1
all_values[0]	auto[1]	auto[0]	auto[1]	187	1			T4	3		T17	8		T18	2
all_values[0]	auto[1]	auto[1]	auto[1]	160	1			T17	6		T18	2		T23	1
all_values[1]	auto[0]	auto[0]	auto[0]	184	1			T4	2		T17	6		T18	2
all_values[1]	auto[0]	auto[0]	auto[1]	70	1			T17	7		T23	1		T24	3
all_values[1]	auto[0]	auto[1]	auto[0]	150	1			T4	1		T17	3		T18	3
all_values[1]	auto[0]	auto[1]	auto[1]	85	1			T17	5		T18	1		T19	1
all_values[1]	auto[1]	auto[0]	auto[1]	165	1			T4	2		T17	13		T18	1
all_values[1]	auto[1]	auto[1]	auto[1]	157	1			T4	2		T17	4		T18	3
all_values[2]	auto[0]	auto[0]	auto[0]	170	1			T17	5		T18	1		T20	4
all_values[2]	auto[0]	auto[0]	auto[1]	61	1			T4	2		T17	5		T18	3
all_values[2]	auto[0]	auto[1]	auto[0]	142	1			T17	4		T20	4		T21	2
all_values[2]	auto[0]	auto[1]	auto[1]	90	1			T4	1		T17	5		T18	1
all_values[2]	auto[1]	auto[0]	auto[1]	191	1			T4	4		T17	11		T18	3
all_values[2]	auto[1]	auto[1]	auto[1]	157	1			T17	8		T18	2		T19	1
all_values[3]	auto[0]	auto[0]	auto[0]	178	1			T4	1		T17	10		T18	2
all_values[3]	auto[0]	auto[0]	auto[1]	73	1			T17	4		T18	1		T19	2
all_values[3]	auto[0]	auto[1]	auto[0]	165	1			T4	2		T17	8		T18	1
all_values[3]	auto[0]	auto[1]	auto[1]	66	1			T17	3		T18	1		T174	2
all_values[3]	auto[1]	auto[0]	auto[1]	175	1			T4	1		T17	6		T18	4
all_values[3]	auto[1]	auto[1]	auto[1]	154	1			T4	3		T17	7		T18	1
all_values[4]	auto[0]	auto[0]	auto[0]	173	1			T4	1		T17	9		T18	2
all_values[4]	auto[0]	auto[0]	auto[1]	82	1			T4	2		T17	3		T20	2
all_values[4]	auto[0]	auto[1]	auto[0]	150	1			T17	11		T18	2		T19	1
all_values[4]	auto[0]	auto[1]	auto[1]	72	1			T17	3		T18	1		T21	1
all_values[4]	auto[1]	auto[0]	auto[1]	200	1			T4	4		T17	7		T18	4
all_values[4]	auto[1]	auto[1]	auto[1]	134	1			T17	5		T18	1		T19	2
all_values[5]	auto[0]	auto[0]	auto[0]	245	1			T4	2		T17	13		T18	1
all_values[5]	auto[0]	auto[1]	auto[0]	222	1			T17	6		T18	3		T19	2
all_values[5]	auto[1]	auto[0]	auto[1]	181	1			T4	4		T17	7		T18	2
all_values[5]	auto[1]	auto[1]	auto[1]	163	1			T4	1		T17	12		T18	4
all_values[6]	auto[0]	auto[0]	auto[0]	159	1			T17	9		T18	2		T19	1
all_values[6]	auto[0]	auto[0]	auto[1]	88	1			T4	1		T17	5		T18	1
all_values[6]	auto[0]	auto[1]	auto[0]	132	1			T17	4		T18	3		T21	1
all_values[6]	auto[0]	auto[1]	auto[1]	85	1			T4	3		T17	3		T18	1
all_values[6]	auto[1]	auto[0]	auto[1]	190	1			T4	2		T17	7		T18	2
all_values[6]	auto[1]	auto[1]	auto[1]	157	1			T4	1		T17	10		T18	1
all_values[7]	auto[0]	auto[0]	auto[0]	167	1			T4	1		T17	5		T18	2
all_values[7]	auto[0]	auto[0]	auto[1]	76	1			T4	1		T17	3		T18	2
all_values[7]	auto[0]	auto[1]	auto[0]	142	1			T17	7		T18	3		T19	1
all_values[7]	auto[0]	auto[1]	auto[1]	81	1			T4	1		T17	4		T19	2
all_values[7]	auto[1]	auto[0]	auto[1]	201	1			T4	3		T17	13		T18	3
all_values[7]	auto[1]	auto[1]	auto[1]	144	1			T4	1		T17	6		T19	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal