Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1805

1

T4

4

T6

4

T10

1

auto[1]

1714

1

T4

3

T6

5

T18

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1967

1

T4

5

T10

1

T18

11

auto[1]

1552

1

T4

2

T6

9

T18

3

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2805

1

T4

7

T6

9

T10

1

auto[1]

714

1

T18

2

T28

5

T29

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	751	1			T4	2		T6	1		T18	3
valid[1]	716	1			T4	3		T6	5		T10	1
valid[2]	685	1			T4	1		T6	2		T18	2
valid[3]	678	1			T4	1		T6	1		T28	1
valid[4]	689	1			T18	3		T28	2		T29	4

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	136	1			T4	1		T18	1		T28	1
auto[0]	auto[0]	valid[0]	auto[1]	164	1			T6	1		T18	1		T28	1
auto[0]	auto[0]	valid[1]	auto[0]	126	1			T4	1		T10	1		T18	2
auto[0]	auto[0]	valid[1]	auto[1]	159	1			T4	1		T6	1		T31	1
auto[0]	auto[0]	valid[2]	auto[0]	124	1			T4	1		T18	1		T29	3
auto[0]	auto[0]	valid[2]	auto[1]	160	1			T6	1		T18	1		T32	1
auto[0]	auto[0]	valid[3]	auto[0]	117	1			T29	1		T30	1		T31	1
auto[0]	auto[0]	valid[3]	auto[1]	158	1			T6	1		T31	1		T32	4
auto[0]	auto[0]	valid[4]	auto[0]	120	1			T29	1		T30	1		T75	1
auto[0]	auto[0]	valid[4]	auto[1]	165	1			T28	1		T32	2		T33	2
auto[0]	auto[1]	valid[0]	auto[0]	121	1			T28	1		T30	2		T341	1
auto[0]	auto[1]	valid[0]	auto[1]	171	1			T4	1		T32	3		T33	3
auto[0]	auto[1]	valid[1]	auto[0]	142	1			T4	1		T18	4		T28	1
auto[0]	auto[1]	valid[1]	auto[1]	140	1			T6	4		T30	1		T31	1
auto[0]	auto[1]	valid[2]	auto[0]	132	1			T28	2		T29	3		T59	2
auto[0]	auto[1]	valid[2]	auto[1]	152	1			T6	1		T30	1		T32	2
auto[0]	auto[1]	valid[3]	auto[0]	131	1			T4	1		T30	1		T341	1
auto[0]	auto[1]	valid[3]	auto[1]	142	1			T32	5		T102	1		T69	1
auto[0]	auto[1]	valid[4]	auto[0]	104	1			T18	1		T29	1		T43	1
auto[0]	auto[1]	valid[4]	auto[1]	141	1			T18	1		T32	2		T33	1
auto[1]	auto[0]	valid[0]	auto[0]	79	1			T28	1		T29	1		T30	1
auto[1]	auto[0]	valid[1]	auto[0]	86	1			T29	1		T20	1		T22	2
auto[1]	auto[0]	valid[2]	auto[0]	70	1			T52	1		T22	4		T69	1
auto[1]	auto[0]	valid[3]	auto[0]	63	1			T341	1		T22	5		T337	2
auto[1]	auto[0]	valid[4]	auto[0]	78	1			T18	1		T28	1		T29	2
auto[1]	auto[1]	valid[0]	auto[0]	80	1			T18	1		T28	1		T29	1
auto[1]	auto[1]	valid[1]	auto[0]	63	1			T28	1		T30	1		T341	1
auto[1]	auto[1]	valid[2]	auto[0]	47	1			T341	1		T22	1		T69	1
auto[1]	auto[1]	valid[3]	auto[0]	67	1			T28	1		T30	1		T20	1
auto[1]	auto[1]	valid[4]	auto[0]	81	1			T337	1		T248	1		T44	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal