Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

47943

1

T4

121

T10

4

T18

379

auto[1]

16244

1

T4

18

T6

9

T18

51

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46725

1

T4

93

T6

9

T10

3

auto[1]

17462

1

T4

46

T10

1

T18

139

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32988	1			T4	71		T6	9		T10	3
others[1]	5411	1			T4	16		T18	36		T28	46
others[2]	5310	1			T4	11		T10	1		T18	29
others[3]	6213	1			T4	11		T18	46		T28	29
interest[1]	3582	1			T4	7		T18	22		T28	14
interest[4]	21548	1			T4	47		T6	9		T10	2
interest[64]	10683	1			T4	23		T18	80		T28	67

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	15558	1			T4	39		T10	2		T18	118
auto[0]	auto[0]	others[1]	2610	1			T4	9		T18	19		T28	24
auto[0]	auto[0]	others[2]	2561	1			T4	5		T10	1		T18	17
auto[0]	auto[0]	others[3]	2927	1			T4	4		T18	23		T28	14
auto[0]	auto[0]	interest[1]	1702	1			T4	4		T18	13		T28	7
auto[0]	auto[0]	interest[4]	10111	1			T4	27		T10	2		T18	80
auto[0]	auto[0]	interest[64]	5123	1			T4	14		T18	50		T28	32
auto[0]	auto[1]	others[0]	8502	1			T4	8		T6	9		T18	24
auto[0]	auto[1]	others[1]	1339	1			T4	2		T18	5		T28	5
auto[0]	auto[1]	others[2]	1331	1			T4	3		T18	2		T28	5
auto[0]	auto[1]	others[3]	1534	1			T4	2		T18	9		T28	6
auto[0]	auto[1]	interest[1]	877	1			T18	2		T30	3		T31	1
auto[0]	auto[1]	interest[4]	5638	1			T4	5		T6	9		T18	16
auto[0]	auto[1]	interest[64]	2661	1			T4	3		T18	9		T28	9
auto[1]	auto[0]	others[0]	8928	1			T4	24		T10	1		T18	75
auto[1]	auto[0]	others[1]	1462	1			T4	5		T18	12		T28	17
auto[1]	auto[0]	others[2]	1418	1			T4	3		T18	10		T28	10
auto[1]	auto[0]	others[3]	1752	1			T4	5		T18	14		T28	9
auto[1]	auto[0]	interest[1]	1003	1			T4	3		T18	7		T28	7
auto[1]	auto[0]	interest[4]	5799	1			T4	15		T18	45		T28	50
auto[1]	auto[0]	interest[64]	2899	1			T4	6		T18	21		T28	26

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal