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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.39 93.99 98.62 89.36 97.21 95.45 99.26


Total test records in report: 1130
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T1028 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2913135210 Jul 06 05:03:18 PM PDT 24 Jul 06 05:03:21 PM PDT 24 41882525 ps
T1029 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1524872086 Jul 06 05:03:38 PM PDT 24 Jul 06 05:03:40 PM PDT 24 12958864 ps
T132 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.131926343 Jul 06 05:02:57 PM PDT 24 Jul 06 05:02:59 PM PDT 24 85870429 ps
T1030 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2272583587 Jul 06 05:03:42 PM PDT 24 Jul 06 05:03:43 PM PDT 24 13042445 ps
T164 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.631332074 Jul 06 05:02:36 PM PDT 24 Jul 06 05:03:02 PM PDT 24 1879624926 ps
T181 /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3497372505 Jul 06 05:02:24 PM PDT 24 Jul 06 05:02:37 PM PDT 24 737331025 ps
T1031 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2868405368 Jul 06 05:03:13 PM PDT 24 Jul 06 05:03:14 PM PDT 24 90889660 ps
T1032 /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4100920494 Jul 06 05:03:11 PM PDT 24 Jul 06 05:03:13 PM PDT 24 20765738 ps
T185 /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.897280490 Jul 06 05:03:19 PM PDT 24 Jul 06 05:03:26 PM PDT 24 172208956 ps
T133 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3994907457 Jul 06 05:02:49 PM PDT 24 Jul 06 05:02:58 PM PDT 24 407861419 ps
T165 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3461029489 Jul 06 05:03:35 PM PDT 24 Jul 06 05:03:39 PM PDT 24 1756847009 ps
T1033 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2077879171 Jul 06 05:03:07 PM PDT 24 Jul 06 05:03:12 PM PDT 24 68932573 ps
T1034 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2968696595 Jul 06 05:03:19 PM PDT 24 Jul 06 05:03:22 PM PDT 24 225654522 ps
T1035 /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.276837049 Jul 06 05:02:31 PM PDT 24 Jul 06 05:02:32 PM PDT 24 17733257 ps
T1036 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.717056268 Jul 06 05:02:24 PM PDT 24 Jul 06 05:02:26 PM PDT 24 29259588 ps
T134 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3267144133 Jul 06 05:02:17 PM PDT 24 Jul 06 05:02:18 PM PDT 24 44059444 ps
T1037 /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1955827809 Jul 06 05:03:15 PM PDT 24 Jul 06 05:03:18 PM PDT 24 39710023 ps
T182 /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1536905767 Jul 06 05:02:55 PM PDT 24 Jul 06 05:03:16 PM PDT 24 805383642 ps
T1038 /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1113481318 Jul 06 05:02:29 PM PDT 24 Jul 06 05:02:31 PM PDT 24 36152365 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2730732351 Jul 06 05:03:24 PM PDT 24 Jul 06 05:03:28 PM PDT 24 256943569 ps
T135 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2020905149 Jul 06 05:02:48 PM PDT 24 Jul 06 05:02:50 PM PDT 24 59285492 ps
T1040 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.828187546 Jul 06 05:03:25 PM PDT 24 Jul 06 05:03:27 PM PDT 24 52700487 ps
T99 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2935187135 Jul 06 05:02:17 PM PDT 24 Jul 06 05:02:18 PM PDT 24 21186343 ps
T1041 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.891324310 Jul 06 05:03:36 PM PDT 24 Jul 06 05:03:37 PM PDT 24 27727601 ps
T1042 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.702298214 Jul 06 05:03:37 PM PDT 24 Jul 06 05:03:38 PM PDT 24 14782537 ps
T1043 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3122521019 Jul 06 05:02:37 PM PDT 24 Jul 06 05:02:40 PM PDT 24 167797787 ps
T1044 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1699689546 Jul 06 05:03:01 PM PDT 24 Jul 06 05:03:06 PM PDT 24 424985154 ps
T1045 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1138240010 Jul 06 05:02:54 PM PDT 24 Jul 06 05:02:58 PM PDT 24 162046645 ps
T125 /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2239503504 Jul 06 05:03:13 PM PDT 24 Jul 06 05:03:16 PM PDT 24 1348735944 ps
T1046 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.344373413 Jul 06 05:02:16 PM PDT 24 Jul 06 05:02:17 PM PDT 24 21105464 ps
T1047 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4053460063 Jul 06 05:03:07 PM PDT 24 Jul 06 05:03:08 PM PDT 24 152938974 ps
T1048 /workspace/coverage/cover_reg_top/16.spi_device_intr_test.953649119 Jul 06 05:03:35 PM PDT 24 Jul 06 05:03:36 PM PDT 24 11984844 ps
T1049 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3311248528 Jul 06 05:02:53 PM PDT 24 Jul 06 05:02:56 PM PDT 24 257381669 ps
T186 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1726534824 Jul 06 05:03:26 PM PDT 24 Jul 06 05:03:45 PM PDT 24 609685482 ps
T1050 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3306852581 Jul 06 05:02:49 PM PDT 24 Jul 06 05:02:50 PM PDT 24 17391687 ps
T136 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.340060880 Jul 06 05:02:30 PM PDT 24 Jul 06 05:02:33 PM PDT 24 61237213 ps
T1051 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3076835284 Jul 06 05:03:39 PM PDT 24 Jul 06 05:03:40 PM PDT 24 42013399 ps
T1052 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.50347407 Jul 06 05:03:16 PM PDT 24 Jul 06 05:03:24 PM PDT 24 339620552 ps
T1053 /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3128994034 Jul 06 05:02:24 PM PDT 24 Jul 06 05:02:31 PM PDT 24 115267864 ps
T1054 /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2860811026 Jul 06 05:03:36 PM PDT 24 Jul 06 05:03:39 PM PDT 24 82414456 ps
T1055 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3986753485 Jul 06 05:03:14 PM PDT 24 Jul 06 05:03:16 PM PDT 24 363100700 ps
T1056 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.382752176 Jul 06 05:03:14 PM PDT 24 Jul 06 05:03:22 PM PDT 24 738396715 ps
T1057 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2367748351 Jul 06 05:03:37 PM PDT 24 Jul 06 05:03:38 PM PDT 24 31129833 ps
T137 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.499012291 Jul 06 05:03:01 PM PDT 24 Jul 06 05:03:03 PM PDT 24 126159427 ps
T1058 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4247952019 Jul 06 05:03:00 PM PDT 24 Jul 06 05:03:03 PM PDT 24 371465600 ps
T1059 /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3515489716 Jul 06 05:02:25 PM PDT 24 Jul 06 05:02:27 PM PDT 24 57239173 ps
T1060 /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1279492170 Jul 06 05:03:07 PM PDT 24 Jul 06 05:03:10 PM PDT 24 436979363 ps
T1061 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2933158917 Jul 06 05:03:37 PM PDT 24 Jul 06 05:03:38 PM PDT 24 20520905 ps
T1062 /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3908078016 Jul 06 05:02:48 PM PDT 24 Jul 06 05:03:01 PM PDT 24 720721273 ps
T1063 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3174911467 Jul 06 05:02:36 PM PDT 24 Jul 06 05:02:39 PM PDT 24 145092515 ps
T1064 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.522078578 Jul 06 05:02:35 PM PDT 24 Jul 06 05:02:36 PM PDT 24 19028622 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1468223173 Jul 06 05:02:17 PM PDT 24 Jul 06 05:02:18 PM PDT 24 19071450 ps
T1066 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4106608829 Jul 06 05:03:25 PM PDT 24 Jul 06 05:03:29 PM PDT 24 881997775 ps
T179 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1966600507 Jul 06 05:03:01 PM PDT 24 Jul 06 05:03:04 PM PDT 24 275599943 ps
T1067 /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.903753312 Jul 06 05:02:48 PM PDT 24 Jul 06 05:02:51 PM PDT 24 122961645 ps
T120 /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4279165807 Jul 06 05:03:20 PM PDT 24 Jul 06 05:03:26 PM PDT 24 909884533 ps
T138 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.560668078 Jul 06 05:02:24 PM PDT 24 Jul 06 05:02:52 PM PDT 24 1810866767 ps
T1068 /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1723675051 Jul 06 05:03:07 PM PDT 24 Jul 06 05:03:09 PM PDT 24 330231548 ps
T140 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2207663571 Jul 06 05:02:16 PM PDT 24 Jul 06 05:02:18 PM PDT 24 33707404 ps
T1069 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2929919525 Jul 06 05:03:36 PM PDT 24 Jul 06 05:03:37 PM PDT 24 12298540 ps
T1070 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1504090112 Jul 06 05:02:55 PM PDT 24 Jul 06 05:02:59 PM PDT 24 313365321 ps
T1071 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1310889864 Jul 06 05:03:12 PM PDT 24 Jul 06 05:03:16 PM PDT 24 205454398 ps
T1072 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.464500791 Jul 06 05:02:42 PM PDT 24 Jul 06 05:02:43 PM PDT 24 40756940 ps
T100 /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3975727044 Jul 06 05:02:36 PM PDT 24 Jul 06 05:02:38 PM PDT 24 46962500 ps
T1073 /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2108334933 Jul 06 05:02:29 PM PDT 24 Jul 06 05:02:31 PM PDT 24 164455124 ps
T1074 /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2255830676 Jul 06 05:02:16 PM PDT 24 Jul 06 05:02:36 PM PDT 24 296644477 ps
T139 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2935778333 Jul 06 05:02:36 PM PDT 24 Jul 06 05:02:58 PM PDT 24 1252335550 ps
T121 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2327329484 Jul 06 05:03:34 PM PDT 24 Jul 06 05:03:37 PM PDT 24 447416085 ps
T1075 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3113875131 Jul 06 05:02:28 PM PDT 24 Jul 06 05:02:30 PM PDT 24 83569816 ps
T1076 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.384388148 Jul 06 05:03:26 PM PDT 24 Jul 06 05:03:29 PM PDT 24 129344645 ps
T1077 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.721466029 Jul 06 05:02:54 PM PDT 24 Jul 06 05:02:55 PM PDT 24 149761373 ps
T1078 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2880617534 Jul 06 05:02:36 PM PDT 24 Jul 06 05:02:39 PM PDT 24 126094481 ps
T1079 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2110491502 Jul 06 05:02:29 PM PDT 24 Jul 06 05:03:07 PM PDT 24 3757415463 ps
T1080 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.871774877 Jul 06 05:03:26 PM PDT 24 Jul 06 05:03:28 PM PDT 24 58817948 ps
T1081 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1773539965 Jul 06 05:03:12 PM PDT 24 Jul 06 05:03:14 PM PDT 24 380542073 ps
T183 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3102942912 Jul 06 05:02:36 PM PDT 24 Jul 06 05:02:52 PM PDT 24 575078367 ps
T1082 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3520413422 Jul 06 05:02:56 PM PDT 24 Jul 06 05:03:00 PM PDT 24 488020426 ps
T1083 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1743388207 Jul 06 05:03:42 PM PDT 24 Jul 06 05:03:43 PM PDT 24 26391082 ps
T1084 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3651035873 Jul 06 05:03:37 PM PDT 24 Jul 06 05:03:38 PM PDT 24 112466187 ps
T1085 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1428933089 Jul 06 05:03:06 PM PDT 24 Jul 06 05:03:09 PM PDT 24 195491957 ps
T184 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1440029221 Jul 06 05:02:56 PM PDT 24 Jul 06 05:03:15 PM PDT 24 1185575255 ps
T1086 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2302120202 Jul 06 05:03:31 PM PDT 24 Jul 06 05:03:32 PM PDT 24 42866986 ps
T1087 /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2164516309 Jul 06 05:02:36 PM PDT 24 Jul 06 05:02:38 PM PDT 24 577630760 ps
T1088 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4031640668 Jul 06 05:03:30 PM PDT 24 Jul 06 05:03:33 PM PDT 24 349024433 ps
T187 /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2816602106 Jul 06 05:02:42 PM PDT 24 Jul 06 05:02:57 PM PDT 24 1132893088 ps
T1089 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.179422688 Jul 06 05:02:50 PM PDT 24 Jul 06 05:02:53 PM PDT 24 109074077 ps
T122 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.22216191 Jul 06 05:03:20 PM PDT 24 Jul 06 05:03:23 PM PDT 24 71152099 ps
T1090 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2046991600 Jul 06 05:03:31 PM PDT 24 Jul 06 05:03:33 PM PDT 24 16964265 ps
T1091 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1238432263 Jul 06 05:02:24 PM PDT 24 Jul 06 05:02:25 PM PDT 24 54497926 ps
T1092 /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.770330006 Jul 06 05:02:50 PM PDT 24 Jul 06 05:02:51 PM PDT 24 122671744 ps
T101 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2211692591 Jul 06 05:02:49 PM PDT 24 Jul 06 05:02:50 PM PDT 24 56266293 ps
T1093 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3881835433 Jul 06 05:03:34 PM PDT 24 Jul 06 05:03:36 PM PDT 24 50961330 ps
T1094 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1201644474 Jul 06 05:03:42 PM PDT 24 Jul 06 05:03:43 PM PDT 24 65629975 ps
T1095 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2353781004 Jul 06 05:03:20 PM PDT 24 Jul 06 05:03:22 PM PDT 24 52699128 ps
T1096 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1707981949 Jul 06 05:02:42 PM PDT 24 Jul 06 05:02:43 PM PDT 24 10202947 ps
T1097 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1770924183 Jul 06 05:02:50 PM PDT 24 Jul 06 05:02:54 PM PDT 24 57967827 ps
T1098 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2239445381 Jul 06 05:03:26 PM PDT 24 Jul 06 05:03:27 PM PDT 24 74928926 ps
T1099 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.225929150 Jul 06 05:02:49 PM PDT 24 Jul 06 05:03:02 PM PDT 24 772181126 ps
T1100 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1549375284 Jul 06 05:03:24 PM PDT 24 Jul 06 05:03:29 PM PDT 24 133821571 ps
T1101 /workspace/coverage/cover_reg_top/31.spi_device_intr_test.977093469 Jul 06 05:03:37 PM PDT 24 Jul 06 05:03:38 PM PDT 24 13529699 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_intr_test.19191959 Jul 06 05:02:35 PM PDT 24 Jul 06 05:02:36 PM PDT 24 18364353 ps
T1103 /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3385510983 Jul 06 05:03:38 PM PDT 24 Jul 06 05:03:39 PM PDT 24 65961155 ps
T1104 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.57335812 Jul 06 05:03:12 PM PDT 24 Jul 06 05:03:14 PM PDT 24 46564231 ps
T1105 /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3863569299 Jul 06 05:02:15 PM PDT 24 Jul 06 05:02:19 PM PDT 24 63082934 ps
T188 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.547443403 Jul 06 05:03:19 PM PDT 24 Jul 06 05:03:41 PM PDT 24 1049382581 ps
T1106 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1864445015 Jul 06 05:03:36 PM PDT 24 Jul 06 05:03:37 PM PDT 24 14944531 ps
T1107 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3287216472 Jul 06 05:03:24 PM PDT 24 Jul 06 05:03:45 PM PDT 24 3307531955 ps
T1108 /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3989654846 Jul 06 05:03:07 PM PDT 24 Jul 06 05:03:12 PM PDT 24 206215629 ps
T1109 /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1323062357 Jul 06 05:03:24 PM PDT 24 Jul 06 05:03:26 PM PDT 24 59357019 ps
T1110 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.5641677 Jul 06 05:02:48 PM PDT 24 Jul 06 05:02:50 PM PDT 24 101499498 ps
T1111 /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3084923173 Jul 06 05:02:50 PM PDT 24 Jul 06 05:02:53 PM PDT 24 35855173 ps
T1112 /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.591596689 Jul 06 05:03:20 PM PDT 24 Jul 06 05:03:23 PM PDT 24 458115356 ps
T1113 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3800548761 Jul 06 05:03:38 PM PDT 24 Jul 06 05:03:39 PM PDT 24 16475948 ps
T1114 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2104567249 Jul 06 05:03:08 PM PDT 24 Jul 06 05:03:26 PM PDT 24 594056961 ps
T1115 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1113403562 Jul 06 05:03:27 PM PDT 24 Jul 06 05:03:29 PM PDT 24 82615665 ps
T1116 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4189883332 Jul 06 05:03:19 PM PDT 24 Jul 06 05:03:20 PM PDT 24 23166168 ps
T1117 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2711035973 Jul 06 05:03:24 PM PDT 24 Jul 06 05:03:25 PM PDT 24 29167618 ps
T1118 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.953579594 Jul 06 05:03:22 PM PDT 24 Jul 06 05:03:23 PM PDT 24 15373520 ps
T1119 /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3039249212 Jul 06 05:03:14 PM PDT 24 Jul 06 05:03:32 PM PDT 24 298947803 ps
T1120 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2538956217 Jul 06 05:03:15 PM PDT 24 Jul 06 05:03:17 PM PDT 24 202627499 ps
T1121 /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3032552404 Jul 06 05:03:01 PM PDT 24 Jul 06 05:03:24 PM PDT 24 3910071288 ps
T1122 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3364703306 Jul 06 05:03:12 PM PDT 24 Jul 06 05:03:13 PM PDT 24 32454916 ps
T1123 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2919279981 Jul 06 05:03:32 PM PDT 24 Jul 06 05:03:33 PM PDT 24 29490873 ps
T1124 /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1545971547 Jul 06 05:03:33 PM PDT 24 Jul 06 05:03:47 PM PDT 24 1012450598 ps
T1125 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3186808020 Jul 06 05:03:32 PM PDT 24 Jul 06 05:03:33 PM PDT 24 35774830 ps
T1126 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.884821276 Jul 06 05:02:56 PM PDT 24 Jul 06 05:02:57 PM PDT 24 117096209 ps
T1127 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4175616161 Jul 06 05:03:31 PM PDT 24 Jul 06 05:03:32 PM PDT 24 15104312 ps
T1128 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1752273500 Jul 06 05:02:54 PM PDT 24 Jul 06 05:02:57 PM PDT 24 200881412 ps
T1129 /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4205028886 Jul 06 05:03:07 PM PDT 24 Jul 06 05:03:12 PM PDT 24 971911040 ps
T1130 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.332467020 Jul 06 05:02:23 PM PDT 24 Jul 06 05:02:25 PM PDT 24 284587299 ps

Test location /workspace/coverage/default/25.spi_device_stress_all.3222839970
Short name T4
Test name
Test status
Simulation time 15749496219 ps
CPU time 87.14 seconds
Started Jul 06 06:41:35 PM PDT 24
Finished Jul 06 06:43:03 PM PDT 24
Peak memory 249248 kb
Host smart-1c891bc2-8ba0-476d-83a4-9b1bbbd297b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222839970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.3222839970
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.3177248273
Short name T29
Test name
Test status
Simulation time 4148307081 ps
CPU time 38.62 seconds
Started Jul 06 06:43:21 PM PDT 24
Finished Jul 06 06:44:00 PM PDT 24
Peak memory 216664 kb
Host smart-18e3cfdc-5011-404c-bfa3-f641095f07a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177248273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.3177248273
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.812461191
Short name T44
Test name
Test status
Simulation time 202465460657 ps
CPU time 311.36 seconds
Started Jul 06 06:42:17 PM PDT 24
Finished Jul 06 06:47:29 PM PDT 24
Peak memory 281332 kb
Host smart-447cf7e5-2294-4d37-9157-cfe57c146bf9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=812461191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stres
s_all.812461191
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.3223724058
Short name T111
Test name
Test status
Simulation time 1734944445 ps
CPU time 20.49 seconds
Started Jul 06 05:03:07 PM PDT 24
Finished Jul 06 05:03:28 PM PDT 24
Peak memory 216236 kb
Host smart-3e380f6c-9153-4089-a9ee-6b165ba96b30
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223724058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device
_tl_intg_err.3223724058
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.3300210099
Short name T22
Test name
Test status
Simulation time 13239136620 ps
CPU time 239.06 seconds
Started Jul 06 06:39:42 PM PDT 24
Finished Jul 06 06:43:42 PM PDT 24
Peak memory 270596 kb
Host smart-9cdaa83f-f702-4a72-875b-9813f89da6c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300210099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.3300210099
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.1604465275
Short name T52
Test name
Test status
Simulation time 4822798592 ps
CPU time 95.52 seconds
Started Jul 06 06:43:11 PM PDT 24
Finished Jul 06 06:44:47 PM PDT 24
Peak memory 272852 kb
Host smart-fc6a5e10-f5d5-44fc-9b3d-c1bc96d17af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604465275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.1604465275
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.766851944
Short name T82
Test name
Test status
Simulation time 16064826 ps
CPU time 0.78 seconds
Started Jul 06 06:39:30 PM PDT 24
Finished Jul 06 06:39:31 PM PDT 24
Peak memory 216084 kb
Host smart-9fc1c703-ad3a-45c2-919a-bca8287ed66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766851944 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.766851944
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.3854119298
Short name T214
Test name
Test status
Simulation time 162762202119 ps
CPU time 822.22 seconds
Started Jul 06 06:42:32 PM PDT 24
Finished Jul 06 06:56:15 PM PDT 24
Peak memory 281748 kb
Host smart-f6cb6c8f-078a-4107-a357-e57a20d78a3a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3854119298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stre
ss_all.3854119298
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.434992870
Short name T204
Test name
Test status
Simulation time 5058796124 ps
CPU time 130.21 seconds
Started Jul 06 06:39:45 PM PDT 24
Finished Jul 06 06:41:55 PM PDT 24
Peak memory 256032 kb
Host smart-a3910cdb-5714-4bc9-bd43-9724ca07b8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434992870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.434992870
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.2008221177
Short name T20
Test name
Test status
Simulation time 63123262078 ps
CPU time 534.64 seconds
Started Jul 06 06:41:20 PM PDT 24
Finished Jul 06 06:50:15 PM PDT 24
Peak memory 273356 kb
Host smart-43b3a379-a70d-4d51-88ee-34538eed9399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2008221177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stre
ss_all.2008221177
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1345171747
Short name T14
Test name
Test status
Simulation time 7188685277 ps
CPU time 27.77 seconds
Started Jul 06 06:41:07 PM PDT 24
Finished Jul 06 06:41:35 PM PDT 24
Peak memory 224568 kb
Host smart-8be3961d-e32e-4860-913d-bba02ad1d0c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345171747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1345171747
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.2908319260
Short name T83
Test name
Test status
Simulation time 126426006 ps
CPU time 0.97 seconds
Started Jul 06 06:39:41 PM PDT 24
Finished Jul 06 06:39:42 PM PDT 24
Peak memory 235980 kb
Host smart-afe7f2c4-4548-4aee-9279-dfc6004a83ac
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908319260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.2908319260
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.1433123719
Short name T226
Test name
Test status
Simulation time 125339548643 ps
CPU time 524.05 seconds
Started Jul 06 06:41:18 PM PDT 24
Finished Jul 06 06:50:02 PM PDT 24
Peak memory 268076 kb
Host smart-b146dc5f-cf6f-48ac-ad17-c4bda5324272
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433123719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.1433123719
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.2330772222
Short name T113
Test name
Test status
Simulation time 1808990323 ps
CPU time 4.6 seconds
Started Jul 06 05:03:27 PM PDT 24
Finished Jul 06 05:03:31 PM PDT 24
Peak memory 216260 kb
Host smart-5ed35ca9-788f-43a7-bd84-deeee1e9485c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330772222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
2330772222
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.21692597
Short name T141
Test name
Test status
Simulation time 423185697511 ps
CPU time 906.84 seconds
Started Jul 06 06:40:41 PM PDT 24
Finished Jul 06 06:55:48 PM PDT 24
Peak memory 273500 kb
Host smart-02581a8d-6f33-47c3-8765-b1498080cdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21692597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idle.21692597
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3773605066
Short name T217
Test name
Test status
Simulation time 45307341380 ps
CPU time 162.93 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:45:15 PM PDT 24
Peak memory 249212 kb
Host smart-7c86105a-4473-441d-8993-c8c3dcb23e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773605066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3773605066
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.560668078
Short name T138
Test name
Test status
Simulation time 1810866767 ps
CPU time 27.52 seconds
Started Jul 06 05:02:24 PM PDT 24
Finished Jul 06 05:02:52 PM PDT 24
Peak memory 207436 kb
Host smart-c4726f46-8e07-4bcd-bd7c-d5563f879547
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560668078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr
_bit_bash.560668078
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.3808216756
Short name T18
Test name
Test status
Simulation time 24266736211 ps
CPU time 37.06 seconds
Started Jul 06 06:42:08 PM PDT 24
Finished Jul 06 06:42:45 PM PDT 24
Peak memory 224476 kb
Host smart-64192517-8638-49fc-84e0-420f76757459
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808216756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stre
ss_all.3808216756
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.2876144615
Short name T211
Test name
Test status
Simulation time 5549072186 ps
CPU time 117.07 seconds
Started Jul 06 06:39:51 PM PDT 24
Finished Jul 06 06:41:48 PM PDT 24
Peak memory 273816 kb
Host smart-2217a02a-1c31-4a01-bf7d-9388fc960fd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876144615 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.2876144615
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.2848663647
Short name T42
Test name
Test status
Simulation time 18948866501 ps
CPU time 146.77 seconds
Started Jul 06 06:40:59 PM PDT 24
Finished Jul 06 06:43:27 PM PDT 24
Peak memory 250028 kb
Host smart-3018b2db-a398-43eb-89aa-27c33ed6ee87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848663647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmd
s.2848663647
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.763478560
Short name T316
Test name
Test status
Simulation time 207433012130 ps
CPU time 517.39 seconds
Started Jul 06 06:42:05 PM PDT 24
Finished Jul 06 06:50:43 PM PDT 24
Peak memory 289024 kb
Host smart-f2ee3f7e-8d88-4674-9e87-5171076845b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763478560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stres
s_all.763478560
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.3564692518
Short name T304
Test name
Test status
Simulation time 49178729065 ps
CPU time 158.23 seconds
Started Jul 06 06:39:43 PM PDT 24
Finished Jul 06 06:42:22 PM PDT 24
Peak memory 265588 kb
Host smart-e20fab8a-6ed5-400d-a0c5-34c48362e07f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564692518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.3564692518
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.3400447589
Short name T209
Test name
Test status
Simulation time 4050463919 ps
CPU time 90.4 seconds
Started Jul 06 06:42:10 PM PDT 24
Finished Jul 06 06:43:41 PM PDT 24
Peak memory 269172 kb
Host smart-fbd21f7b-0a27-423b-9fef-96feb0529749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400447589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.3400447589
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.4279165807
Short name T120
Test name
Test status
Simulation time 909884533 ps
CPU time 5.25 seconds
Started Jul 06 05:03:20 PM PDT 24
Finished Jul 06 05:03:26 PM PDT 24
Peak memory 216088 kb
Host smart-7d1b96e9-2568-4122-bfec-8ae56f32a75e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4279165807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.
4279165807
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.983680840
Short name T149
Test name
Test status
Simulation time 164251193307 ps
CPU time 382.92 seconds
Started Jul 06 06:42:16 PM PDT 24
Finished Jul 06 06:48:39 PM PDT 24
Peak memory 263152 kb
Host smart-c70b2144-bd40-4574-ac72-a4d54ccad1f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983680840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.983680840
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.3110238961
Short name T372
Test name
Test status
Simulation time 43913904 ps
CPU time 0.87 seconds
Started Jul 06 06:39:30 PM PDT 24
Finished Jul 06 06:39:32 PM PDT 24
Peak memory 204964 kb
Host smart-db1721cf-711c-4831-b788-c7c494d5bf2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110238961 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.3
110238961
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.547443403
Short name T188
Test name
Test status
Simulation time 1049382581 ps
CPU time 21.76 seconds
Started Jul 06 05:03:19 PM PDT 24
Finished Jul 06 05:03:41 PM PDT 24
Peak memory 215628 kb
Host smart-78b6d71b-6e48-4bba-a412-545c839c35a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547443403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.547443403
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.3116056624
Short name T305
Test name
Test status
Simulation time 42364106511 ps
CPU time 171.77 seconds
Started Jul 06 06:39:42 PM PDT 24
Finished Jul 06 06:42:35 PM PDT 24
Peak memory 269940 kb
Host smart-01cd3fdf-ed35-4e61-a8b7-5581bfc8d846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116056624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.3116056624
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.2934430853
Short name T236
Test name
Test status
Simulation time 12755487106 ps
CPU time 182.42 seconds
Started Jul 06 06:40:30 PM PDT 24
Finished Jul 06 06:43:33 PM PDT 24
Peak memory 267752 kb
Host smart-2b2dee7d-5eb5-4df9-9523-e1818bb16401
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934430853 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.2934430853
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.1548483034
Short name T355
Test name
Test status
Simulation time 30493829159 ps
CPU time 24.33 seconds
Started Jul 06 06:41:33 PM PDT 24
Finished Jul 06 06:41:57 PM PDT 24
Peak memory 216328 kb
Host smart-46d69626-2d98-4d6d-8b48-c2d0cb551953
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548483034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.1548483034
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.3572068564
Short name T210
Test name
Test status
Simulation time 36536266410 ps
CPU time 294.65 seconds
Started Jul 06 06:43:25 PM PDT 24
Finished Jul 06 06:48:20 PM PDT 24
Peak memory 256056 kb
Host smart-658fa5cc-c031-4230-b2b2-abaf222af1f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572068564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmd
s.3572068564
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1746193740
Short name T283
Test name
Test status
Simulation time 55301391582 ps
CPU time 155.31 seconds
Started Jul 06 06:40:40 PM PDT 24
Finished Jul 06 06:43:16 PM PDT 24
Peak memory 256416 kb
Host smart-b69e92c2-459c-4afc-99b6-26af9cb9e834
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1746193740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1746193740
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.2026640104
Short name T252
Test name
Test status
Simulation time 51747242310 ps
CPU time 266.41 seconds
Started Jul 06 06:41:59 PM PDT 24
Finished Jul 06 06:46:26 PM PDT 24
Peak memory 254316 kb
Host smart-6f42ab03-23a0-4b49-b882-b73c51d805eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2026640104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.2026640104
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.2379292372
Short name T7
Test name
Test status
Simulation time 2497223087 ps
CPU time 24.07 seconds
Started Jul 06 06:43:10 PM PDT 24
Finished Jul 06 06:43:34 PM PDT 24
Peak memory 232772 kb
Host smart-1142b4cd-8898-4eae-bb42-3d12d51460ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379292372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.2379292372
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.84754482
Short name T37
Test name
Test status
Simulation time 56844839920 ps
CPU time 71.41 seconds
Started Jul 06 06:42:38 PM PDT 24
Finished Jul 06 06:43:50 PM PDT 24
Peak memory 257400 kb
Host smart-80a65573-6de4-4f5a-a4b1-1e3d62e48d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84754482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idle.84754482
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.852416728
Short name T329
Test name
Test status
Simulation time 3118851027 ps
CPU time 41.46 seconds
Started Jul 06 06:39:42 PM PDT 24
Finished Jul 06 06:40:24 PM PDT 24
Peak memory 248296 kb
Host smart-29ea1785-733b-4c08-b7f0-cfe93d6bb9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=852416728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.852416728
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3037169539
Short name T857
Test name
Test status
Simulation time 1306667259 ps
CPU time 21.01 seconds
Started Jul 06 06:39:35 PM PDT 24
Finished Jul 06 06:39:56 PM PDT 24
Peak memory 233016 kb
Host smart-1ca2517f-44b8-470d-b85b-5ef5e84654b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037169539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3037169539
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.292578061
Short name T232
Test name
Test status
Simulation time 25495696136 ps
CPU time 50.1 seconds
Started Jul 06 06:42:01 PM PDT 24
Finished Jul 06 06:42:52 PM PDT 24
Peak memory 254200 kb
Host smart-c73bdeae-6ada-4b88-bf0e-a5013b13e16a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292578061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmds
.292578061
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.2489529517
Short name T171
Test name
Test status
Simulation time 52649628639 ps
CPU time 200.3 seconds
Started Jul 06 06:42:55 PM PDT 24
Finished Jul 06 06:46:16 PM PDT 24
Peak memory 253756 kb
Host smart-78c3e327-a826-4cf8-adff-144e97768d5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489529517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.2489529517
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.2996715357
Short name T104
Test name
Test status
Simulation time 16024133099 ps
CPU time 114.8 seconds
Started Jul 06 06:42:32 PM PDT 24
Finished Jul 06 06:44:27 PM PDT 24
Peak memory 249256 kb
Host smart-d4bb6a06-46f0-41a7-8db3-9b093cebe1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996715357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.2996715357
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.1966600507
Short name T179
Test name
Test status
Simulation time 275599943 ps
CPU time 2.33 seconds
Started Jul 06 05:03:01 PM PDT 24
Finished Jul 06 05:03:04 PM PDT 24
Peak memory 215848 kb
Host smart-631c1058-ebc4-421f-8293-8d843d8baf09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966600507 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.1
966600507
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/default/12.spi_device_upload.3925275648
Short name T190
Test name
Test status
Simulation time 2904172433 ps
CPU time 12.48 seconds
Started Jul 06 06:40:34 PM PDT 24
Finished Jul 06 06:40:47 PM PDT 24
Peak memory 240108 kb
Host smart-d51d5d04-9a0c-4b11-935d-5b32c3cbaf9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925275648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3925275648
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.1537252233
Short name T973
Test name
Test status
Simulation time 34399787032 ps
CPU time 56.53 seconds
Started Jul 06 06:40:47 PM PDT 24
Finished Jul 06 06:41:43 PM PDT 24
Peak memory 254800 kb
Host smart-e3580c94-195a-4c42-9e48-b266b291b7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537252233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.1537252233
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.4073325186
Short name T314
Test name
Test status
Simulation time 260436109819 ps
CPU time 149.48 seconds
Started Jul 06 06:41:34 PM PDT 24
Finished Jul 06 06:44:03 PM PDT 24
Peak memory 240984 kb
Host smart-d5b28437-89d3-4ec9-b236-c33c954167cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4073325186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.4073325186
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_upload.1188039509
Short name T610
Test name
Test status
Simulation time 5297484944 ps
CPU time 10.55 seconds
Started Jul 06 06:41:39 PM PDT 24
Finished Jul 06 06:41:50 PM PDT 24
Peak memory 224584 kb
Host smart-88de459d-2948-4e2f-bfef-55fe9ea956d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188039509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.1188039509
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.803643197
Short name T326
Test name
Test status
Simulation time 19750040785 ps
CPU time 32.36 seconds
Started Jul 06 06:41:46 PM PDT 24
Finished Jul 06 06:42:18 PM PDT 24
Peak memory 232824 kb
Host smart-016eaf0c-181c-4f31-9f20-28823b5191ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803643197 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.803643197
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.1807534033
Short name T307
Test name
Test status
Simulation time 61043270684 ps
CPU time 208.93 seconds
Started Jul 06 06:43:00 PM PDT 24
Finished Jul 06 06:46:29 PM PDT 24
Peak memory 265684 kb
Host smart-1d04d016-db5b-4439-a3b1-688c74c7d2b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807534033 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stre
ss_all.1807534033
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.3437627255
Short name T106
Test name
Test status
Simulation time 959151917 ps
CPU time 6.47 seconds
Started Jul 06 06:40:30 PM PDT 24
Finished Jul 06 06:40:37 PM PDT 24
Peak memory 221108 kb
Host smart-fc2b824a-6572-438f-815a-402a629b5a09
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3437627255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.3437627255
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.3970282226
Short name T117
Test name
Test status
Simulation time 679150256 ps
CPU time 4.03 seconds
Started Jul 06 05:03:07 PM PDT 24
Finished Jul 06 05:03:11 PM PDT 24
Peak memory 215920 kb
Host smart-1daf521a-3136-4ad9-8c09-9b06c2352d92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970282226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.
3970282226
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.438664405
Short name T70
Test name
Test status
Simulation time 25885340192 ps
CPU time 18.41 seconds
Started Jul 06 06:39:28 PM PDT 24
Finished Jul 06 06:39:47 PM PDT 24
Peak memory 240508 kb
Host smart-e2657974-fb64-451e-b120-ccf8e36a0d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438664405 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.438664405
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.3975727044
Short name T100
Test name
Test status
Simulation time 46962500 ps
CPU time 1.45 seconds
Started Jul 06 05:02:36 PM PDT 24
Finished Jul 06 05:02:38 PM PDT 24
Peak memory 207424 kb
Host smart-e4b6c6d8-da67-4959-bf18-8149836f637a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975727044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.3975727044
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.3128994034
Short name T1053
Test name
Test status
Simulation time 115267864 ps
CPU time 6.93 seconds
Started Jul 06 05:02:24 PM PDT 24
Finished Jul 06 05:02:31 PM PDT 24
Peak memory 207428 kb
Host smart-c323f25d-9468-484a-ac44-680f03f3cb10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128994034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.3128994034
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.2935187135
Short name T99
Test name
Test status
Simulation time 21186343 ps
CPU time 0.97 seconds
Started Jul 06 05:02:17 PM PDT 24
Finished Jul 06 05:02:18 PM PDT 24
Peak memory 207216 kb
Host smart-1d280e82-fb85-40ef-affa-18080f59f09e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935187135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.2935187135
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.3515489716
Short name T1059
Test name
Test status
Simulation time 57239173 ps
CPU time 1.93 seconds
Started Jul 06 05:02:25 PM PDT 24
Finished Jul 06 05:02:27 PM PDT 24
Peak memory 215760 kb
Host smart-a54c973c-941c-45d2-9e39-4ca8ab9827bf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515489716 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.3515489716
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.3267144133
Short name T134
Test name
Test status
Simulation time 44059444 ps
CPU time 1.31 seconds
Started Jul 06 05:02:17 PM PDT 24
Finished Jul 06 05:02:18 PM PDT 24
Peak memory 215628 kb
Host smart-e4eacd83-644a-4fe5-ae5e-a07da6075df1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267144133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.3
267144133
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1468223173
Short name T1065
Test name
Test status
Simulation time 19071450 ps
CPU time 0.76 seconds
Started Jul 06 05:02:17 PM PDT 24
Finished Jul 06 05:02:18 PM PDT 24
Peak memory 204580 kb
Host smart-c044d036-e199-41f0-aecf-da74485b034d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468223173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
468223173
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.2207663571
Short name T140
Test name
Test status
Simulation time 33707404 ps
CPU time 1.37 seconds
Started Jul 06 05:02:16 PM PDT 24
Finished Jul 06 05:02:18 PM PDT 24
Peak memory 215792 kb
Host smart-6e173967-600b-44a7-9efb-83e7dca14959
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207663571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.2207663571
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.344373413
Short name T1046
Test name
Test status
Simulation time 21105464 ps
CPU time 0.66 seconds
Started Jul 06 05:02:16 PM PDT 24
Finished Jul 06 05:02:17 PM PDT 24
Peak memory 203956 kb
Host smart-99ebd8e7-f092-4947-bf82-c06a9de56cf0
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=344373413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_mem
_walk.344373413
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.717056268
Short name T1036
Test name
Test status
Simulation time 29259588 ps
CPU time 1.78 seconds
Started Jul 06 05:02:24 PM PDT 24
Finished Jul 06 05:02:26 PM PDT 24
Peak memory 215788 kb
Host smart-5570895f-e852-4c1b-afe0-fddc0066ecb7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717056268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sp
i_device_same_csr_outstanding.717056268
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.3863569299
Short name T1105
Test name
Test status
Simulation time 63082934 ps
CPU time 3.67 seconds
Started Jul 06 05:02:15 PM PDT 24
Finished Jul 06 05:02:19 PM PDT 24
Peak memory 216124 kb
Host smart-24c95f3f-db68-4c79-857e-b3d0b42e5d50
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863569299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.3
863569299
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.2255830676
Short name T1074
Test name
Test status
Simulation time 296644477 ps
CPU time 19.84 seconds
Started Jul 06 05:02:16 PM PDT 24
Finished Jul 06 05:02:36 PM PDT 24
Peak memory 223848 kb
Host smart-77599d08-f292-4818-b46f-bc22177461d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255830676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device
_tl_intg_err.2255830676
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.2424922339
Short name T163
Test name
Test status
Simulation time 5946484213 ps
CPU time 17.69 seconds
Started Jul 06 05:02:29 PM PDT 24
Finished Jul 06 05:02:47 PM PDT 24
Peak memory 215736 kb
Host smart-8399e05d-6e6e-4e5d-b095-ba75c5b11e82
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424922339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_aliasing.2424922339
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2110491502
Short name T1079
Test name
Test status
Simulation time 3757415463 ps
CPU time 38.6 seconds
Started Jul 06 05:02:29 PM PDT 24
Finished Jul 06 05:03:07 PM PDT 24
Peak memory 207584 kb
Host smart-0080a754-e410-4668-8222-f30b4843e85b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2110491502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2110491502
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1113481318
Short name T1038
Test name
Test status
Simulation time 36152365 ps
CPU time 0.97 seconds
Started Jul 06 05:02:29 PM PDT 24
Finished Jul 06 05:02:31 PM PDT 24
Peak memory 207136 kb
Host smart-882a884f-ee86-484a-b2e3-4a3990f01116
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113481318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1113481318
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.3174911467
Short name T1063
Test name
Test status
Simulation time 145092515 ps
CPU time 2.83 seconds
Started Jul 06 05:02:36 PM PDT 24
Finished Jul 06 05:02:39 PM PDT 24
Peak memory 218564 kb
Host smart-9d2bfd30-2908-4fe8-b3ae-c34ed2b07a77
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174911467 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.3174911467
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3113875131
Short name T1075
Test name
Test status
Simulation time 83569816 ps
CPU time 2.03 seconds
Started Jul 06 05:02:28 PM PDT 24
Finished Jul 06 05:02:30 PM PDT 24
Peak memory 215532 kb
Host smart-6cc5d0a4-f6df-4def-bb06-9ccf54f11e68
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113875131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
113875131
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.1238432263
Short name T1091
Test name
Test status
Simulation time 54497926 ps
CPU time 0.74 seconds
Started Jul 06 05:02:24 PM PDT 24
Finished Jul 06 05:02:25 PM PDT 24
Peak memory 204584 kb
Host smart-139a9afe-68cc-46c7-b6be-5394ac0d64b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238432263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.1
238432263
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.340060880
Short name T136
Test name
Test status
Simulation time 61237213 ps
CPU time 2.2 seconds
Started Jul 06 05:02:30 PM PDT 24
Finished Jul 06 05:02:33 PM PDT 24
Peak memory 215796 kb
Host smart-23261a05-84cf-4645-ac67-8c4352ca1e46
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340060880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.340060880
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.276837049
Short name T1035
Test name
Test status
Simulation time 17733257 ps
CPU time 0.66 seconds
Started Jul 06 05:02:31 PM PDT 24
Finished Jul 06 05:02:32 PM PDT 24
Peak memory 204064 kb
Host smart-2edc17dc-994b-4574-94fa-4e6c08b45753
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276837049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.276837049
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.2108334933
Short name T1073
Test name
Test status
Simulation time 164455124 ps
CPU time 1.77 seconds
Started Jul 06 05:02:29 PM PDT 24
Finished Jul 06 05:02:31 PM PDT 24
Peak memory 215680 kb
Host smart-66d1b738-3c71-4b5a-a8b3-3012a33edf9a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2108334933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.2108334933
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.332467020
Short name T1130
Test name
Test status
Simulation time 284587299 ps
CPU time 1.59 seconds
Started Jul 06 05:02:23 PM PDT 24
Finished Jul 06 05:02:25 PM PDT 24
Peak memory 215796 kb
Host smart-17a12388-9733-43d4-bbf2-c6d67f4b0778
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332467020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.332467020
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3497372505
Short name T181
Test name
Test status
Simulation time 737331025 ps
CPU time 12.47 seconds
Started Jul 06 05:02:24 PM PDT 24
Finished Jul 06 05:02:37 PM PDT 24
Peak memory 215772 kb
Host smart-cf7c270d-7cad-459d-b157-6b65ed9a2da5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497372505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3497372505
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1537527059
Short name T81
Test name
Test status
Simulation time 42497280 ps
CPU time 2.96 seconds
Started Jul 06 05:03:08 PM PDT 24
Finished Jul 06 05:03:11 PM PDT 24
Peak memory 216840 kb
Host smart-4cb85cac-e9b5-4c3d-9556-cc8e65831802
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537527059 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1537527059
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.1723675051
Short name T1068
Test name
Test status
Simulation time 330231548 ps
CPU time 2.03 seconds
Started Jul 06 05:03:07 PM PDT 24
Finished Jul 06 05:03:09 PM PDT 24
Peak memory 207496 kb
Host smart-ea0cc951-12df-4b28-a8cb-7066561caec8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723675051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.
1723675051
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.2685458620
Short name T1023
Test name
Test status
Simulation time 15940310 ps
CPU time 0.77 seconds
Started Jul 06 05:03:15 PM PDT 24
Finished Jul 06 05:03:17 PM PDT 24
Peak memory 204248 kb
Host smart-905a4786-371d-40a3-bb17-247e80e49293
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2685458620 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
2685458620
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1606377794
Short name T154
Test name
Test status
Simulation time 740440447 ps
CPU time 3.71 seconds
Started Jul 06 05:03:16 PM PDT 24
Finished Jul 06 05:03:20 PM PDT 24
Peak memory 215712 kb
Host smart-4866396b-2cd6-4cc9-a6bd-40b947922f42
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606377794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1606377794
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.4205028886
Short name T1129
Test name
Test status
Simulation time 971911040 ps
CPU time 4.45 seconds
Started Jul 06 05:03:07 PM PDT 24
Finished Jul 06 05:03:12 PM PDT 24
Peak memory 217012 kb
Host smart-c4d8fcd4-1959-42d2-a5d1-0b408a7658dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205028886 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.
4205028886
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.50347407
Short name T1052
Test name
Test status
Simulation time 339620552 ps
CPU time 8.08 seconds
Started Jul 06 05:03:16 PM PDT 24
Finished Jul 06 05:03:24 PM PDT 24
Peak memory 215884 kb
Host smart-5bdbe0ea-b4a8-4ceb-846b-0338b4effcb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50347407 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_
tl_intg_err.50347407
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.2353781004
Short name T1095
Test name
Test status
Simulation time 52699128 ps
CPU time 1.77 seconds
Started Jul 06 05:03:20 PM PDT 24
Finished Jul 06 05:03:22 PM PDT 24
Peak memory 215752 kb
Host smart-e8e16e95-6dca-4557-8146-dbff970b39d5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353781004 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.2353781004
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.4100920494
Short name T1032
Test name
Test status
Simulation time 20765738 ps
CPU time 1.23 seconds
Started Jul 06 05:03:11 PM PDT 24
Finished Jul 06 05:03:13 PM PDT 24
Peak memory 207476 kb
Host smart-fde83b5f-5635-4807-bffb-ce656b5f904e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100920494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
4100920494
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.2868405368
Short name T1031
Test name
Test status
Simulation time 90889660 ps
CPU time 0.73 seconds
Started Jul 06 05:03:13 PM PDT 24
Finished Jul 06 05:03:14 PM PDT 24
Peak memory 204236 kb
Host smart-90ff315f-85d0-4c56-8e5f-3a4712d6e5d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2868405368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.
2868405368
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.1310889864
Short name T1071
Test name
Test status
Simulation time 205454398 ps
CPU time 4.22 seconds
Started Jul 06 05:03:12 PM PDT 24
Finished Jul 06 05:03:16 PM PDT 24
Peak memory 215800 kb
Host smart-053f505e-4f05-40e6-b1bd-f61f278da2b6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310889864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.1310889864
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.382752176
Short name T1056
Test name
Test status
Simulation time 738396715 ps
CPU time 8.07 seconds
Started Jul 06 05:03:14 PM PDT 24
Finished Jul 06 05:03:22 PM PDT 24
Peak memory 215864 kb
Host smart-c85f88ac-ff6d-464f-a008-6d3cc01f2f6f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382752176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device
_tl_intg_err.382752176
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.57335812
Short name T1104
Test name
Test status
Simulation time 46564231 ps
CPU time 1.69 seconds
Started Jul 06 05:03:12 PM PDT 24
Finished Jul 06 05:03:14 PM PDT 24
Peak memory 215920 kb
Host smart-ea1e3671-6367-43d3-ac4d-29bc5b15b08b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57335812 -assert nopostproc +UVM_TESTNAME=s
pi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.v
db -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.57335812
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.1773539965
Short name T1081
Test name
Test status
Simulation time 380542073 ps
CPU time 2.43 seconds
Started Jul 06 05:03:12 PM PDT 24
Finished Jul 06 05:03:14 PM PDT 24
Peak memory 215524 kb
Host smart-0a14d0bb-83c1-4a38-9b64-b99fc483728a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773539965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.
1773539965
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.3364703306
Short name T1122
Test name
Test status
Simulation time 32454916 ps
CPU time 0.7 seconds
Started Jul 06 05:03:12 PM PDT 24
Finished Jul 06 05:03:13 PM PDT 24
Peak memory 204612 kb
Host smart-a3986457-29de-4f24-a28a-561582d266ff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364703306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
3364703306
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.3986753485
Short name T1055
Test name
Test status
Simulation time 363100700 ps
CPU time 1.86 seconds
Started Jul 06 05:03:14 PM PDT 24
Finished Jul 06 05:03:16 PM PDT 24
Peak memory 215796 kb
Host smart-6a548be2-1ed3-4b4f-a825-07949e0cdc34
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3986753485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.3986753485
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.22216191
Short name T122
Test name
Test status
Simulation time 71152099 ps
CPU time 2.42 seconds
Started Jul 06 05:03:20 PM PDT 24
Finished Jul 06 05:03:23 PM PDT 24
Peak memory 215964 kb
Host smart-fcff8c8c-c104-4bd3-b106-6eb610f204f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22216191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.22216191
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.292080761
Short name T180
Test name
Test status
Simulation time 852253393 ps
CPU time 21.53 seconds
Started Jul 06 05:03:14 PM PDT 24
Finished Jul 06 05:03:36 PM PDT 24
Peak memory 215988 kb
Host smart-86a0d5db-a970-47e4-8a2c-7b410ded0eb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292080761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device
_tl_intg_err.292080761
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2570845361
Short name T127
Test name
Test status
Simulation time 226036598 ps
CPU time 1.76 seconds
Started Jul 06 05:03:18 PM PDT 24
Finished Jul 06 05:03:20 PM PDT 24
Peak memory 216772 kb
Host smart-6abd8a34-0e14-43c4-b67e-9a4947182b75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570845361 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2570845361
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.591596689
Short name T1112
Test name
Test status
Simulation time 458115356 ps
CPU time 2.65 seconds
Started Jul 06 05:03:20 PM PDT 24
Finished Jul 06 05:03:23 PM PDT 24
Peak memory 207484 kb
Host smart-2c1ece4a-995c-4a42-a7a1-10e76c864aed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591596689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.591596689
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.4144487883
Short name T1018
Test name
Test status
Simulation time 14722361 ps
CPU time 0.83 seconds
Started Jul 06 05:03:20 PM PDT 24
Finished Jul 06 05:03:21 PM PDT 24
Peak memory 204256 kb
Host smart-7b965a56-a3cd-4d53-be72-313e5f22f72b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144487883 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
4144487883
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.2913135210
Short name T1028
Test name
Test status
Simulation time 41882525 ps
CPU time 2.65 seconds
Started Jul 06 05:03:18 PM PDT 24
Finished Jul 06 05:03:21 PM PDT 24
Peak memory 215796 kb
Host smart-fd3284e0-6b02-410b-8cb9-35d53808176d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913135210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.2913135210
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2239503504
Short name T125
Test name
Test status
Simulation time 1348735944 ps
CPU time 3.12 seconds
Started Jul 06 05:03:13 PM PDT 24
Finished Jul 06 05:03:16 PM PDT 24
Peak memory 215896 kb
Host smart-cc99db65-122b-4bbb-83fe-24d11a5468b5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239503504 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2239503504
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.3039249212
Short name T1119
Test name
Test status
Simulation time 298947803 ps
CPU time 17.69 seconds
Started Jul 06 05:03:14 PM PDT 24
Finished Jul 06 05:03:32 PM PDT 24
Peak memory 216072 kb
Host smart-a2d2c32d-a991-4331-b716-eb1ff1a5359b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039249212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_devic
e_tl_intg_err.3039249212
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.2895753265
Short name T123
Test name
Test status
Simulation time 25178433 ps
CPU time 1.72 seconds
Started Jul 06 05:03:19 PM PDT 24
Finished Jul 06 05:03:21 PM PDT 24
Peak memory 215760 kb
Host smart-85d16ef3-c191-4ead-b1ab-1c139171ac73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895753265 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.2895753265
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.4189883332
Short name T1116
Test name
Test status
Simulation time 23166168 ps
CPU time 1.3 seconds
Started Jul 06 05:03:19 PM PDT 24
Finished Jul 06 05:03:20 PM PDT 24
Peak memory 207492 kb
Host smart-29974184-b7f9-4a09-ac3e-2c8b37c2e985
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189883332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
4189883332
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.850494801
Short name T1025
Test name
Test status
Simulation time 23269259 ps
CPU time 0.75 seconds
Started Jul 06 05:03:17 PM PDT 24
Finished Jul 06 05:03:18 PM PDT 24
Peak memory 204172 kb
Host smart-d1279b65-cd82-45a7-9c74-9836e33974a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850494801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.850494801
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2968696595
Short name T1034
Test name
Test status
Simulation time 225654522 ps
CPU time 2.77 seconds
Started Jul 06 05:03:19 PM PDT 24
Finished Jul 06 05:03:22 PM PDT 24
Peak memory 215744 kb
Host smart-4cc958d5-8e06-4fd9-8592-d64b547e6658
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968696595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2968696595
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.897280490
Short name T185
Test name
Test status
Simulation time 172208956 ps
CPU time 7.02 seconds
Started Jul 06 05:03:19 PM PDT 24
Finished Jul 06 05:03:26 PM PDT 24
Peak memory 215784 kb
Host smart-b300afd2-b0f8-4c24-9954-8a2742045d9b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897280490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.897280490
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.1549375284
Short name T1100
Test name
Test status
Simulation time 133821571 ps
CPU time 4.1 seconds
Started Jul 06 05:03:24 PM PDT 24
Finished Jul 06 05:03:29 PM PDT 24
Peak memory 217496 kb
Host smart-3a6e3e7f-f807-4ba5-9e96-0e95c56906e2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549375284 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.1549375284
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2239445381
Short name T1098
Test name
Test status
Simulation time 74928926 ps
CPU time 1.29 seconds
Started Jul 06 05:03:26 PM PDT 24
Finished Jul 06 05:03:27 PM PDT 24
Peak memory 215544 kb
Host smart-bda66c3c-edfa-4eb2-b73a-b8f29576bc86
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239445381 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2239445381
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.953579594
Short name T1118
Test name
Test status
Simulation time 15373520 ps
CPU time 0.76 seconds
Started Jul 06 05:03:22 PM PDT 24
Finished Jul 06 05:03:23 PM PDT 24
Peak memory 204284 kb
Host smart-7a78de90-4d89-484a-8331-af9a775f1cc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953579594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.953579594
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.4106608829
Short name T1066
Test name
Test status
Simulation time 881997775 ps
CPU time 3.85 seconds
Started Jul 06 05:03:25 PM PDT 24
Finished Jul 06 05:03:29 PM PDT 24
Peak memory 207576 kb
Host smart-9b301d93-a919-4cb2-8b0e-ce73645d4661
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106608829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.4106608829
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3370241947
Short name T124
Test name
Test status
Simulation time 512306095 ps
CPU time 2.44 seconds
Started Jul 06 05:03:19 PM PDT 24
Finished Jul 06 05:03:22 PM PDT 24
Peak memory 215892 kb
Host smart-a0200aa9-63b2-4c56-8c24-7dcfcff13c93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370241947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3370241947
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.3461029489
Short name T165
Test name
Test status
Simulation time 1756847009 ps
CPU time 4.13 seconds
Started Jul 06 05:03:35 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 218732 kb
Host smart-2939b396-bbbc-4c09-b721-42e353492212
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461029489 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.3461029489
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.384388148
Short name T1076
Test name
Test status
Simulation time 129344645 ps
CPU time 2.36 seconds
Started Jul 06 05:03:26 PM PDT 24
Finished Jul 06 05:03:29 PM PDT 24
Peak memory 215496 kb
Host smart-1f9c7e7f-9ec5-4f86-80e1-2e96b19a082c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384388148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.384388148
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.953649119
Short name T1048
Test name
Test status
Simulation time 11984844 ps
CPU time 0.71 seconds
Started Jul 06 05:03:35 PM PDT 24
Finished Jul 06 05:03:36 PM PDT 24
Peak memory 204532 kb
Host smart-e83f4e42-1d28-4ca1-9942-13de6403cf4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=953649119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.953649119
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.828187546
Short name T1040
Test name
Test status
Simulation time 52700487 ps
CPU time 1.8 seconds
Started Jul 06 05:03:25 PM PDT 24
Finished Jul 06 05:03:27 PM PDT 24
Peak memory 215712 kb
Host smart-9ce4129d-68ea-4d4c-abf0-d3f89296aa18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828187546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.828187546
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.1323062357
Short name T1109
Test name
Test status
Simulation time 59357019 ps
CPU time 1.84 seconds
Started Jul 06 05:03:24 PM PDT 24
Finished Jul 06 05:03:26 PM PDT 24
Peak memory 215840 kb
Host smart-a8b3971b-20b2-4fd7-88af-6df5e51d3d93
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323062357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
1323062357
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.1726534824
Short name T186
Test name
Test status
Simulation time 609685482 ps
CPU time 19.58 seconds
Started Jul 06 05:03:26 PM PDT 24
Finished Jul 06 05:03:45 PM PDT 24
Peak memory 215816 kb
Host smart-18b35293-17b2-47f8-bb8d-6acdde7e9bb0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726534824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_devic
e_tl_intg_err.1726534824
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.2730732351
Short name T1039
Test name
Test status
Simulation time 256943569 ps
CPU time 3.77 seconds
Started Jul 06 05:03:24 PM PDT 24
Finished Jul 06 05:03:28 PM PDT 24
Peak memory 219152 kb
Host smart-71f355b4-01a1-4a16-acee-a2e317064ee3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730732351 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.2730732351
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.1113403562
Short name T1115
Test name
Test status
Simulation time 82615665 ps
CPU time 1.35 seconds
Started Jul 06 05:03:27 PM PDT 24
Finished Jul 06 05:03:29 PM PDT 24
Peak memory 207356 kb
Host smart-df613d34-a103-4b36-84ec-d96a63b2ce50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113403562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
1113403562
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.1547323076
Short name T1020
Test name
Test status
Simulation time 33076566 ps
CPU time 0.76 seconds
Started Jul 06 05:03:25 PM PDT 24
Finished Jul 06 05:03:26 PM PDT 24
Peak memory 204188 kb
Host smart-57a328d7-e8fc-4787-8fd2-e17985e2fb07
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547323076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
1547323076
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.871774877
Short name T1080
Test name
Test status
Simulation time 58817948 ps
CPU time 1.68 seconds
Started Jul 06 05:03:26 PM PDT 24
Finished Jul 06 05:03:28 PM PDT 24
Peak memory 207592 kb
Host smart-00ec6116-41ce-4ce7-aeef-0f1b7b8a5264
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871774877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.s
pi_device_same_csr_outstanding.871774877
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2327329484
Short name T121
Test name
Test status
Simulation time 447416085 ps
CPU time 3.15 seconds
Started Jul 06 05:03:34 PM PDT 24
Finished Jul 06 05:03:37 PM PDT 24
Peak memory 215980 kb
Host smart-7b4da79f-ea95-4da2-a2c1-2b02e64e5bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327329484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2327329484
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3267714977
Short name T80
Test name
Test status
Simulation time 428181041 ps
CPU time 6.72 seconds
Started Jul 06 05:03:34 PM PDT 24
Finished Jul 06 05:03:41 PM PDT 24
Peak memory 215760 kb
Host smart-fc3a6d9e-ad17-4c20-a479-267ca9438257
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3267714977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3267714977
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.2763351455
Short name T118
Test name
Test status
Simulation time 413674646 ps
CPU time 2.61 seconds
Started Jul 06 05:03:32 PM PDT 24
Finished Jul 06 05:03:35 PM PDT 24
Peak memory 217516 kb
Host smart-2822dab3-bf09-4cf3-8ce7-7f526e9df8b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763351455 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.2763351455
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.3881835433
Short name T1093
Test name
Test status
Simulation time 50961330 ps
CPU time 1.97 seconds
Started Jul 06 05:03:34 PM PDT 24
Finished Jul 06 05:03:36 PM PDT 24
Peak memory 207620 kb
Host smart-d354978f-dc1a-42ba-9d40-1e406cfc2112
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3881835433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
3881835433
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.2711035973
Short name T1117
Test name
Test status
Simulation time 29167618 ps
CPU time 0.69 seconds
Started Jul 06 05:03:24 PM PDT 24
Finished Jul 06 05:03:25 PM PDT 24
Peak memory 204528 kb
Host smart-210822b3-24b6-4193-8986-79fc3a122bd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711035973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
2711035973
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.2860811026
Short name T1054
Test name
Test status
Simulation time 82414456 ps
CPU time 2.15 seconds
Started Jul 06 05:03:36 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 215736 kb
Host smart-aac2e5bf-a13b-4c94-a102-066475c58330
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860811026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
spi_device_same_csr_outstanding.2860811026
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.3287216472
Short name T1107
Test name
Test status
Simulation time 3307531955 ps
CPU time 21.03 seconds
Started Jul 06 05:03:24 PM PDT 24
Finished Jul 06 05:03:45 PM PDT 24
Peak memory 215860 kb
Host smart-bee1bde8-3963-4d57-a0ca-3be08560f764
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3287216472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_devic
e_tl_intg_err.3287216472
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.2581888871
Short name T126
Test name
Test status
Simulation time 607102865 ps
CPU time 3.7 seconds
Started Jul 06 05:03:32 PM PDT 24
Finished Jul 06 05:03:36 PM PDT 24
Peak memory 218364 kb
Host smart-e92dfd5a-4988-4f59-ab4a-030582c5c72e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581888871 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.2581888871
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.4234945057
Short name T156
Test name
Test status
Simulation time 41996738 ps
CPU time 1.38 seconds
Started Jul 06 05:03:31 PM PDT 24
Finished Jul 06 05:03:33 PM PDT 24
Peak memory 207512 kb
Host smart-ec3b4f68-910d-4f54-8459-e0239613d1e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234945057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
4234945057
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.1784529601
Short name T1009
Test name
Test status
Simulation time 54148840 ps
CPU time 0.73 seconds
Started Jul 06 05:03:32 PM PDT 24
Finished Jul 06 05:03:33 PM PDT 24
Peak memory 204484 kb
Host smart-3d0227a3-7009-4af2-9a69-2b1ae271c671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1784529601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
1784529601
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.4031640668
Short name T1088
Test name
Test status
Simulation time 349024433 ps
CPU time 2.79 seconds
Started Jul 06 05:03:30 PM PDT 24
Finished Jul 06 05:03:33 PM PDT 24
Peak memory 215744 kb
Host smart-e49cb585-73aa-435e-a790-201ed3ea27eb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031640668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.4031640668
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.1103076759
Short name T119
Test name
Test status
Simulation time 657678821 ps
CPU time 4 seconds
Started Jul 06 05:03:37 PM PDT 24
Finished Jul 06 05:03:41 PM PDT 24
Peak memory 215896 kb
Host smart-539bea91-9131-4c87-aff1-679d306bfa40
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103076759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
1103076759
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.1545971547
Short name T1124
Test name
Test status
Simulation time 1012450598 ps
CPU time 13.73 seconds
Started Jul 06 05:03:33 PM PDT 24
Finished Jul 06 05:03:47 PM PDT 24
Peak memory 215684 kb
Host smart-565326e9-ba52-4cfd-b3f9-9adb2a47772c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545971547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.1545971547
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2935778333
Short name T139
Test name
Test status
Simulation time 1252335550 ps
CPU time 21.74 seconds
Started Jul 06 05:02:36 PM PDT 24
Finished Jul 06 05:02:58 PM PDT 24
Peak memory 215732 kb
Host smart-2ad4cd55-7160-4e3d-afaa-c860cef03084
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935778333 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2935778333
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.631332074
Short name T164
Test name
Test status
Simulation time 1879624926 ps
CPU time 26.33 seconds
Started Jul 06 05:02:36 PM PDT 24
Finished Jul 06 05:03:02 PM PDT 24
Peak memory 207380 kb
Host smart-8e8712af-562a-47a6-aa74-cc360456a4f7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=631332074 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.631332074
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.3395287046
Short name T112
Test name
Test status
Simulation time 323058501 ps
CPU time 3.84 seconds
Started Jul 06 05:02:42 PM PDT 24
Finished Jul 06 05:02:46 PM PDT 24
Peak memory 217924 kb
Host smart-51e258ea-773b-4988-8ae6-32d84c0e2317
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395287046 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.3395287046
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.2880617534
Short name T1078
Test name
Test status
Simulation time 126094481 ps
CPU time 2.49 seconds
Started Jul 06 05:02:36 PM PDT 24
Finished Jul 06 05:02:39 PM PDT 24
Peak memory 207536 kb
Host smart-da104d5d-a15c-479f-b6ff-dcd16cde7b2a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2880617534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.2
880617534
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.19191959
Short name T1102
Test name
Test status
Simulation time 18364353 ps
CPU time 0.76 seconds
Started Jul 06 05:02:35 PM PDT 24
Finished Jul 06 05:02:36 PM PDT 24
Peak memory 204280 kb
Host smart-cb059a96-b89a-4d23-bb56-ef8fd24fcf7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19191959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.19191959
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.2164516309
Short name T1087
Test name
Test status
Simulation time 577630760 ps
CPU time 1.98 seconds
Started Jul 06 05:02:36 PM PDT 24
Finished Jul 06 05:02:38 PM PDT 24
Peak memory 215732 kb
Host smart-06eea961-6150-414f-aba2-96dc9bbc3ca3
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164516309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.2164516309
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.522078578
Short name T1064
Test name
Test status
Simulation time 19028622 ps
CPU time 0.63 seconds
Started Jul 06 05:02:35 PM PDT 24
Finished Jul 06 05:02:36 PM PDT 24
Peak memory 204104 kb
Host smart-26456506-7c0e-4c05-a21e-6bbf0a800649
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=522078578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_mem
_walk.522078578
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.3122521019
Short name T1043
Test name
Test status
Simulation time 167797787 ps
CPU time 2.75 seconds
Started Jul 06 05:02:37 PM PDT 24
Finished Jul 06 05:02:40 PM PDT 24
Peak memory 215816 kb
Host smart-b1a4e6d3-94de-43e0-b196-62108a48fe1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3122521019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.3122521019
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.729321226
Short name T109
Test name
Test status
Simulation time 96587523 ps
CPU time 1.96 seconds
Started Jul 06 05:02:37 PM PDT 24
Finished Jul 06 05:02:39 PM PDT 24
Peak memory 215860 kb
Host smart-137735ab-67b7-47c2-b4e2-4ac73c3649a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729321226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.729321226
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3102942912
Short name T183
Test name
Test status
Simulation time 575078367 ps
CPU time 15.07 seconds
Started Jul 06 05:02:36 PM PDT 24
Finished Jul 06 05:02:52 PM PDT 24
Peak memory 215800 kb
Host smart-c9d7f093-a112-4b93-96f4-f22f59b1d9df
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102942912 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3102942912
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.934843573
Short name T1015
Test name
Test status
Simulation time 12378492 ps
CPU time 0.71 seconds
Started Jul 06 05:03:32 PM PDT 24
Finished Jul 06 05:03:33 PM PDT 24
Peak memory 204272 kb
Host smart-18ed9c59-b472-4e48-bf02-fa92d6c68d76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=934843573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.934843573
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.2919279981
Short name T1123
Test name
Test status
Simulation time 29490873 ps
CPU time 0.73 seconds
Started Jul 06 05:03:32 PM PDT 24
Finished Jul 06 05:03:33 PM PDT 24
Peak memory 204180 kb
Host smart-78eb47df-124c-4b6b-9794-081c8e4a0a0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919279981 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
2919279981
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.2929919525
Short name T1069
Test name
Test status
Simulation time 12298540 ps
CPU time 0.71 seconds
Started Jul 06 05:03:36 PM PDT 24
Finished Jul 06 05:03:37 PM PDT 24
Peak memory 204268 kb
Host smart-148775c1-06a1-44f2-9bcd-7124775a5a00
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929919525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.
2929919525
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2302120202
Short name T1086
Test name
Test status
Simulation time 42866986 ps
CPU time 0.73 seconds
Started Jul 06 05:03:31 PM PDT 24
Finished Jul 06 05:03:32 PM PDT 24
Peak memory 204188 kb
Host smart-95d20ba7-296a-4480-bb94-70a325999e70
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302120202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2302120202
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.4175616161
Short name T1127
Test name
Test status
Simulation time 15104312 ps
CPU time 0.73 seconds
Started Jul 06 05:03:31 PM PDT 24
Finished Jul 06 05:03:32 PM PDT 24
Peak memory 204252 kb
Host smart-29f2a07d-af75-4975-82cb-3295b7a2e97f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4175616161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
4175616161
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3186808020
Short name T1125
Test name
Test status
Simulation time 35774830 ps
CPU time 0.71 seconds
Started Jul 06 05:03:32 PM PDT 24
Finished Jul 06 05:03:33 PM PDT 24
Peak memory 204168 kb
Host smart-40c4d1f7-b41b-4b07-bcf2-51a7654b33b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3186808020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3186808020
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.2046991600
Short name T1090
Test name
Test status
Simulation time 16964265 ps
CPU time 0.73 seconds
Started Jul 06 05:03:31 PM PDT 24
Finished Jul 06 05:03:33 PM PDT 24
Peak memory 204188 kb
Host smart-bf7527f2-2094-4de3-b73c-59043d565ba5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046991600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
2046991600
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.2933158917
Short name T1061
Test name
Test status
Simulation time 20520905 ps
CPU time 0.77 seconds
Started Jul 06 05:03:37 PM PDT 24
Finished Jul 06 05:03:38 PM PDT 24
Peak memory 204180 kb
Host smart-c9155967-f4c6-4702-989f-618559a419ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2933158917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
2933158917
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.2272583587
Short name T1030
Test name
Test status
Simulation time 13042445 ps
CPU time 0.71 seconds
Started Jul 06 05:03:42 PM PDT 24
Finished Jul 06 05:03:43 PM PDT 24
Peak memory 204608 kb
Host smart-47b47d13-aae2-4add-8b77-f8a094999f7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272583587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
2272583587
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.702298214
Short name T1042
Test name
Test status
Simulation time 14782537 ps
CPU time 0.7 seconds
Started Jul 06 05:03:37 PM PDT 24
Finished Jul 06 05:03:38 PM PDT 24
Peak memory 204612 kb
Host smart-0de3007b-f29c-411d-9779-c4916ee424c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702298214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.702298214
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.2849994931
Short name T129
Test name
Test status
Simulation time 1451554485 ps
CPU time 14.77 seconds
Started Jul 06 05:02:48 PM PDT 24
Finished Jul 06 05:03:03 PM PDT 24
Peak memory 215712 kb
Host smart-56c53cea-f67b-40fa-bd77-e13d490063ba
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849994931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.2849994931
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.3908078016
Short name T1062
Test name
Test status
Simulation time 720721273 ps
CPU time 11.95 seconds
Started Jul 06 05:02:48 PM PDT 24
Finished Jul 06 05:03:01 PM PDT 24
Peak memory 207428 kb
Host smart-7c620f38-b584-4f1b-83e5-f856ce6d920b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908078016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.3908078016
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.2020905149
Short name T135
Test name
Test status
Simulation time 59285492 ps
CPU time 1 seconds
Started Jul 06 05:02:48 PM PDT 24
Finished Jul 06 05:02:50 PM PDT 24
Peak memory 207220 kb
Host smart-e0ba9e97-7b19-4b27-af06-6d9d511f6ac7
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2020905149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_hw_reset.2020905149
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.5641677
Short name T1110
Test name
Test status
Simulation time 101499498 ps
CPU time 1.84 seconds
Started Jul 06 05:02:48 PM PDT 24
Finished Jul 06 05:02:50 PM PDT 24
Peak memory 216796 kb
Host smart-2c040e36-4fc3-4f78-9f24-1cde923d12ed
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5641677 -assert nopostproc +UVM_TESTNAME=sp
i_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vd
b -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.5641677
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3084923173
Short name T1111
Test name
Test status
Simulation time 35855173 ps
CPU time 2.38 seconds
Started Jul 06 05:02:50 PM PDT 24
Finished Jul 06 05:02:53 PM PDT 24
Peak memory 215720 kb
Host smart-172336a8-c587-4e42-ad87-db82c0fb457c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3084923173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
084923173
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.464500791
Short name T1072
Test name
Test status
Simulation time 40756940 ps
CPU time 0.71 seconds
Started Jul 06 05:02:42 PM PDT 24
Finished Jul 06 05:02:43 PM PDT 24
Peak memory 204512 kb
Host smart-b1d449cc-9ea3-4fa7-92e2-031851bacaaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464500791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.464500791
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.3219349021
Short name T131
Test name
Test status
Simulation time 84115008 ps
CPU time 1.7 seconds
Started Jul 06 05:02:49 PM PDT 24
Finished Jul 06 05:02:51 PM PDT 24
Peak memory 215704 kb
Host smart-100814ac-2393-4e74-a2bb-32e4109a6c32
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219349021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.3219349021
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.1707981949
Short name T1096
Test name
Test status
Simulation time 10202947 ps
CPU time 0.66 seconds
Started Jul 06 05:02:42 PM PDT 24
Finished Jul 06 05:02:43 PM PDT 24
Peak memory 204068 kb
Host smart-d13de717-77a9-4d78-b742-334d1e59f915
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707981949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.1707981949
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.1770924183
Short name T1097
Test name
Test status
Simulation time 57967827 ps
CPU time 3.77 seconds
Started Jul 06 05:02:50 PM PDT 24
Finished Jul 06 05:02:54 PM PDT 24
Peak memory 215648 kb
Host smart-263af889-15e4-4f92-b191-3257fdc68502
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1770924183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.s
pi_device_same_csr_outstanding.1770924183
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.3593973881
Short name T116
Test name
Test status
Simulation time 211801134 ps
CPU time 2.66 seconds
Started Jul 06 05:02:42 PM PDT 24
Finished Jul 06 05:02:45 PM PDT 24
Peak memory 215888 kb
Host smart-675743b4-19a8-447b-a0d1-1c545e706c43
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593973881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.3
593973881
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.2816602106
Short name T187
Test name
Test status
Simulation time 1132893088 ps
CPU time 15.17 seconds
Started Jul 06 05:02:42 PM PDT 24
Finished Jul 06 05:02:57 PM PDT 24
Peak memory 215696 kb
Host smart-0ce915fa-036a-4ae1-869e-061b2a69d928
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816602106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device
_tl_intg_err.2816602106
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1201644474
Short name T1094
Test name
Test status
Simulation time 65629975 ps
CPU time 0.77 seconds
Started Jul 06 05:03:42 PM PDT 24
Finished Jul 06 05:03:43 PM PDT 24
Peak memory 204260 kb
Host smart-12d56ca4-3d17-4a2f-9142-7c3cf2a82a8b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1201644474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1201644474
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.977093469
Short name T1101
Test name
Test status
Simulation time 13529699 ps
CPU time 0.71 seconds
Started Jul 06 05:03:37 PM PDT 24
Finished Jul 06 05:03:38 PM PDT 24
Peak memory 204520 kb
Host smart-7ebd1592-f775-4024-baf1-2779fea9efb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977093469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.977093469
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.3385510983
Short name T1103
Test name
Test status
Simulation time 65961155 ps
CPU time 0.73 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 204488 kb
Host smart-3805491c-37c5-4dca-8be6-ea8f903ba21d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3385510983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
3385510983
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.2378526034
Short name T1016
Test name
Test status
Simulation time 11900655 ps
CPU time 0.76 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 204188 kb
Host smart-beea0c43-30f7-41a4-befc-c11d54902a9b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378526034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.
2378526034
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.3800548761
Short name T1113
Test name
Test status
Simulation time 16475948 ps
CPU time 0.82 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 204152 kb
Host smart-697df4a3-c82b-4558-811a-26b7ffbc1441
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800548761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.
3800548761
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.3651035873
Short name T1084
Test name
Test status
Simulation time 112466187 ps
CPU time 0.73 seconds
Started Jul 06 05:03:37 PM PDT 24
Finished Jul 06 05:03:38 PM PDT 24
Peak memory 204260 kb
Host smart-f9dfbb68-efb0-40a9-8a7a-491441da2d73
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3651035873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
3651035873
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.563356600
Short name T1014
Test name
Test status
Simulation time 14687006 ps
CPU time 0.71 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 204136 kb
Host smart-48683636-397a-46b3-84d2-7f2ce95345d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563356600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.563356600
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.2286354176
Short name T1022
Test name
Test status
Simulation time 11395627 ps
CPU time 0.75 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 204252 kb
Host smart-4f9dfe6c-0bdc-4c7e-a27e-01eb73b7ce13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286354176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
2286354176
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.2169430459
Short name T1013
Test name
Test status
Simulation time 55473558 ps
CPU time 0.76 seconds
Started Jul 06 05:03:37 PM PDT 24
Finished Jul 06 05:03:38 PM PDT 24
Peak memory 204460 kb
Host smart-86c60536-dbac-4b34-accb-710eed211208
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169430459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.
2169430459
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.891324310
Short name T1041
Test name
Test status
Simulation time 27727601 ps
CPU time 0.74 seconds
Started Jul 06 05:03:36 PM PDT 24
Finished Jul 06 05:03:37 PM PDT 24
Peak memory 204452 kb
Host smart-97f7d590-f98e-4f03-a734-5ae47d080dd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=891324310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.891324310
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.3994907457
Short name T133
Test name
Test status
Simulation time 407861419 ps
CPU time 8.47 seconds
Started Jul 06 05:02:49 PM PDT 24
Finished Jul 06 05:02:58 PM PDT 24
Peak memory 207328 kb
Host smart-8211dcaf-99b8-4e9c-b136-9fd50df3fb10
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3994907457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.3994907457
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.225929150
Short name T1099
Test name
Test status
Simulation time 772181126 ps
CPU time 12.11 seconds
Started Jul 06 05:02:49 PM PDT 24
Finished Jul 06 05:03:02 PM PDT 24
Peak memory 207400 kb
Host smart-c4b73d79-5d3d-4c08-8ca1-d77f39be960f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225929150 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_bit_bash.225929150
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.2211692591
Short name T101
Test name
Test status
Simulation time 56266293 ps
CPU time 1.15 seconds
Started Jul 06 05:02:49 PM PDT 24
Finished Jul 06 05:02:50 PM PDT 24
Peak memory 217644 kb
Host smart-988b7484-ca5a-41c4-8bfc-d8a4fcfbf68e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211692591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_hw_reset.2211692591
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.3311248528
Short name T1049
Test name
Test status
Simulation time 257381669 ps
CPU time 2.7 seconds
Started Jul 06 05:02:53 PM PDT 24
Finished Jul 06 05:02:56 PM PDT 24
Peak memory 216856 kb
Host smart-2b241eb3-83aa-45fd-b352-f7cc8da3aa2e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311248528 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.3311248528
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.903753312
Short name T1067
Test name
Test status
Simulation time 122961645 ps
CPU time 2.16 seconds
Started Jul 06 05:02:48 PM PDT 24
Finished Jul 06 05:02:51 PM PDT 24
Peak memory 215708 kb
Host smart-d92edd6d-22bd-4da7-b27f-0e170dfffb37
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903753312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.903753312
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.3306852581
Short name T1050
Test name
Test status
Simulation time 17391687 ps
CPU time 0.69 seconds
Started Jul 06 05:02:49 PM PDT 24
Finished Jul 06 05:02:50 PM PDT 24
Peak memory 204264 kb
Host smart-fe98988f-9d9d-438d-9710-ab200a2bd0c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3306852581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.3
306852581
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.770330006
Short name T1092
Test name
Test status
Simulation time 122671744 ps
CPU time 1.3 seconds
Started Jul 06 05:02:50 PM PDT 24
Finished Jul 06 05:02:51 PM PDT 24
Peak memory 215708 kb
Host smart-d09b414e-1a85-40a8-bf64-c2026b56f6e0
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770330006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_
device_mem_partial_access.770330006
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.491485175
Short name T1017
Test name
Test status
Simulation time 64062117 ps
CPU time 0.66 seconds
Started Jul 06 05:03:10 PM PDT 24
Finished Jul 06 05:03:11 PM PDT 24
Peak memory 204068 kb
Host smart-bee69b08-05e8-42c4-bfa4-982b1003da7a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491485175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_mem
_walk.491485175
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.195742752
Short name T157
Test name
Test status
Simulation time 552757510 ps
CPU time 3.3 seconds
Started Jul 06 05:02:55 PM PDT 24
Finished Jul 06 05:02:58 PM PDT 24
Peak memory 215792 kb
Host smart-a4c34aa6-ae26-4ea1-93d5-53fe7d5e926a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195742752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sp
i_device_same_csr_outstanding.195742752
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.179422688
Short name T1089
Test name
Test status
Simulation time 109074077 ps
CPU time 3.01 seconds
Started Jul 06 05:02:50 PM PDT 24
Finished Jul 06 05:02:53 PM PDT 24
Peak memory 215924 kb
Host smart-7a9999d1-d84f-41b3-8850-9d2eb2d6786c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179422688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.179422688
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.2781050587
Short name T110
Test name
Test status
Simulation time 3689763506 ps
CPU time 7.78 seconds
Started Jul 06 05:02:49 PM PDT 24
Finished Jul 06 05:02:57 PM PDT 24
Peak memory 216424 kb
Host smart-2ce07e90-1715-4df6-8ea4-7681daa37ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781050587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.2781050587
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.1864445015
Short name T1106
Test name
Test status
Simulation time 14944531 ps
CPU time 0.75 seconds
Started Jul 06 05:03:36 PM PDT 24
Finished Jul 06 05:03:37 PM PDT 24
Peak memory 204252 kb
Host smart-6f77d72e-596b-46fa-b936-cd5a396de1f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864445015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
1864445015
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.2819584836
Short name T1010
Test name
Test status
Simulation time 216267356 ps
CPU time 0.77 seconds
Started Jul 06 05:03:36 PM PDT 24
Finished Jul 06 05:03:37 PM PDT 24
Peak memory 204252 kb
Host smart-ecd6ba4c-9c27-4599-a3a8-2e88eebac168
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819584836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
2819584836
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.4153945592
Short name T1026
Test name
Test status
Simulation time 15859879 ps
CPU time 0.75 seconds
Started Jul 06 05:03:42 PM PDT 24
Finished Jul 06 05:03:43 PM PDT 24
Peak memory 204284 kb
Host smart-5c2fd46f-85c8-42b3-ab69-159836170c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153945592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
4153945592
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1743388207
Short name T1083
Test name
Test status
Simulation time 26391082 ps
CPU time 0.77 seconds
Started Jul 06 05:03:42 PM PDT 24
Finished Jul 06 05:03:43 PM PDT 24
Peak memory 204268 kb
Host smart-bc4c2f21-2c86-43b9-8c12-422bbcbfc2b4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743388207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1743388207
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.2367748351
Short name T1057
Test name
Test status
Simulation time 31129833 ps
CPU time 0.75 seconds
Started Jul 06 05:03:37 PM PDT 24
Finished Jul 06 05:03:38 PM PDT 24
Peak memory 204284 kb
Host smart-60df0376-e63e-4d4c-bc97-9f7b53f3756d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367748351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
2367748351
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.3076835284
Short name T1051
Test name
Test status
Simulation time 42013399 ps
CPU time 0.76 seconds
Started Jul 06 05:03:39 PM PDT 24
Finished Jul 06 05:03:40 PM PDT 24
Peak memory 204208 kb
Host smart-c941f433-3a35-4bb4-bcd4-eb4c90d33c83
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076835284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
3076835284
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2324775255
Short name T1027
Test name
Test status
Simulation time 45839971 ps
CPU time 0.7 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:39 PM PDT 24
Peak memory 204500 kb
Host smart-8fa7681a-79ce-45c6-883c-90acb37bb2eb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324775255 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2324775255
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.2861345833
Short name T1024
Test name
Test status
Simulation time 14556699 ps
CPU time 0.76 seconds
Started Jul 06 05:03:36 PM PDT 24
Finished Jul 06 05:03:37 PM PDT 24
Peak memory 204148 kb
Host smart-2a58cad9-fac5-4652-88aa-2484a8e72155
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2861345833 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
2861345833
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.1524872086
Short name T1029
Test name
Test status
Simulation time 12958864 ps
CPU time 0.75 seconds
Started Jul 06 05:03:38 PM PDT 24
Finished Jul 06 05:03:40 PM PDT 24
Peak memory 204484 kb
Host smart-526cbca7-2553-4e8a-80a1-77e201ae27c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1524872086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.
1524872086
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3333248141
Short name T1011
Test name
Test status
Simulation time 12695369 ps
CPU time 0.7 seconds
Started Jul 06 05:03:37 PM PDT 24
Finished Jul 06 05:03:38 PM PDT 24
Peak memory 204224 kb
Host smart-6d8a2c8d-ee28-4cb1-bc2f-6ea5d9e0cb41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333248141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3333248141
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.1752273500
Short name T1128
Test name
Test status
Simulation time 200881412 ps
CPU time 1.84 seconds
Started Jul 06 05:02:54 PM PDT 24
Finished Jul 06 05:02:57 PM PDT 24
Peak memory 215844 kb
Host smart-40c60da2-c20a-47e1-b31a-2310edb045a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752273500 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.1752273500
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.3624740067
Short name T130
Test name
Test status
Simulation time 21937831 ps
CPU time 1.21 seconds
Started Jul 06 05:02:57 PM PDT 24
Finished Jul 06 05:02:58 PM PDT 24
Peak memory 214724 kb
Host smart-e85b351d-4e02-45ba-ad81-222342aba363
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624740067 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.3
624740067
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.884821276
Short name T1126
Test name
Test status
Simulation time 117096209 ps
CPU time 0.72 seconds
Started Jul 06 05:02:56 PM PDT 24
Finished Jul 06 05:02:57 PM PDT 24
Peak memory 204196 kb
Host smart-c2e87df4-54ce-4424-b4fc-e9cd8f273f55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884821276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.884821276
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.1138240010
Short name T1045
Test name
Test status
Simulation time 162046645 ps
CPU time 3.32 seconds
Started Jul 06 05:02:54 PM PDT 24
Finished Jul 06 05:02:58 PM PDT 24
Peak memory 215644 kb
Host smart-815ca6cf-d734-4a65-818d-e4387dea434a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138240010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.1138240010
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.3520413422
Short name T1082
Test name
Test status
Simulation time 488020426 ps
CPU time 3.43 seconds
Started Jul 06 05:02:56 PM PDT 24
Finished Jul 06 05:03:00 PM PDT 24
Peak memory 216916 kb
Host smart-5098ce1e-3598-4abc-a5f8-916f7847c06d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520413422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.3
520413422
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1536905767
Short name T182
Test name
Test status
Simulation time 805383642 ps
CPU time 20.04 seconds
Started Jul 06 05:02:55 PM PDT 24
Finished Jul 06 05:03:16 PM PDT 24
Peak memory 215804 kb
Host smart-5dcc45e5-1543-4210-b494-7c5ddd8b33a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1536905767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1536905767
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.1479499834
Short name T1021
Test name
Test status
Simulation time 56927183 ps
CPU time 3.68 seconds
Started Jul 06 05:03:01 PM PDT 24
Finished Jul 06 05:03:05 PM PDT 24
Peak memory 218744 kb
Host smart-35783107-c2b2-4d71-a6cc-9f6bb5873b55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479499834 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.1479499834
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.131926343
Short name T132
Test name
Test status
Simulation time 85870429 ps
CPU time 2.08 seconds
Started Jul 06 05:02:57 PM PDT 24
Finished Jul 06 05:02:59 PM PDT 24
Peak memory 206832 kb
Host smart-0b432644-dc3a-4027-9c79-5d4facf0ebe3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131926343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.131926343
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.721466029
Short name T1077
Test name
Test status
Simulation time 149761373 ps
CPU time 0.74 seconds
Started Jul 06 05:02:54 PM PDT 24
Finished Jul 06 05:02:55 PM PDT 24
Peak memory 204580 kb
Host smart-93bc28d5-94c2-412e-9778-4792961e09b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=721466029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.721466029
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1504090112
Short name T1070
Test name
Test status
Simulation time 313365321 ps
CPU time 4.17 seconds
Started Jul 06 05:02:55 PM PDT 24
Finished Jul 06 05:02:59 PM PDT 24
Peak memory 215704 kb
Host smart-c9bc978d-9e3f-4d53-8e94-b382ea3547df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504090112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1504090112
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.1275352831
Short name T79
Test name
Test status
Simulation time 294758591 ps
CPU time 3.41 seconds
Started Jul 06 05:02:54 PM PDT 24
Finished Jul 06 05:02:58 PM PDT 24
Peak memory 215952 kb
Host smart-d1da1269-9ebf-45c4-9a5e-725ddeaea398
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275352831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.1
275352831
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.1440029221
Short name T184
Test name
Test status
Simulation time 1185575255 ps
CPU time 18.86 seconds
Started Jul 06 05:02:56 PM PDT 24
Finished Jul 06 05:03:15 PM PDT 24
Peak memory 215864 kb
Host smart-1924269a-b5e9-40e2-b8a0-741a2b82fbc1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440029221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device
_tl_intg_err.1440029221
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4247952019
Short name T1058
Test name
Test status
Simulation time 371465600 ps
CPU time 2.51 seconds
Started Jul 06 05:03:00 PM PDT 24
Finished Jul 06 05:03:03 PM PDT 24
Peak memory 216880 kb
Host smart-ce9d26af-6138-4b0a-9ef8-72103fd4ce8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247952019 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4247952019
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.499012291
Short name T137
Test name
Test status
Simulation time 126159427 ps
CPU time 1.97 seconds
Started Jul 06 05:03:01 PM PDT 24
Finished Jul 06 05:03:03 PM PDT 24
Peak memory 207376 kb
Host smart-6c6447cb-7848-4b08-bac1-ce78f1b812e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=499012291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.499012291
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.2590348196
Short name T1019
Test name
Test status
Simulation time 46614350 ps
CPU time 0.73 seconds
Started Jul 06 05:03:00 PM PDT 24
Finished Jul 06 05:03:01 PM PDT 24
Peak memory 204532 kb
Host smart-dbe426b2-d98d-4340-86bc-241bce437ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2590348196 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.2
590348196
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1699689546
Short name T1044
Test name
Test status
Simulation time 424985154 ps
CPU time 4.3 seconds
Started Jul 06 05:03:01 PM PDT 24
Finished Jul 06 05:03:06 PM PDT 24
Peak memory 215808 kb
Host smart-ba66d26e-85d3-4b3c-b210-2f1ad6ba95c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699689546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1699689546
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.3032552404
Short name T1121
Test name
Test status
Simulation time 3910071288 ps
CPU time 22.22 seconds
Started Jul 06 05:03:01 PM PDT 24
Finished Jul 06 05:03:24 PM PDT 24
Peak memory 215824 kb
Host smart-4854348c-385a-4f5e-aaba-40c5a299d82c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3032552404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device
_tl_intg_err.3032552404
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.1428933089
Short name T1085
Test name
Test status
Simulation time 195491957 ps
CPU time 1.68 seconds
Started Jul 06 05:03:06 PM PDT 24
Finished Jul 06 05:03:09 PM PDT 24
Peak memory 215848 kb
Host smart-66a3605c-cd82-4ed2-a6e6-8675e0ce1de2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428933089 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.1428933089
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.2835666541
Short name T155
Test name
Test status
Simulation time 140773945 ps
CPU time 1.35 seconds
Started Jul 06 05:03:07 PM PDT 24
Finished Jul 06 05:03:09 PM PDT 24
Peak memory 215616 kb
Host smart-6138f81c-6bfe-4372-aaa9-9141be0a33ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835666541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.2
835666541
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3527089982
Short name T1012
Test name
Test status
Simulation time 43594404 ps
CPU time 0.73 seconds
Started Jul 06 05:03:08 PM PDT 24
Finished Jul 06 05:03:09 PM PDT 24
Peak memory 204276 kb
Host smart-06dcef24-9e2d-4238-b771-4f9d19f962d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527089982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
527089982
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.1279492170
Short name T1060
Test name
Test status
Simulation time 436979363 ps
CPU time 2.84 seconds
Started Jul 06 05:03:07 PM PDT 24
Finished Jul 06 05:03:10 PM PDT 24
Peak memory 215720 kb
Host smart-d592f5b0-1fb6-4ff2-be82-5cfb4ec427cd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279492170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.s
pi_device_same_csr_outstanding.1279492170
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.3397302199
Short name T115
Test name
Test status
Simulation time 744382149 ps
CPU time 4.15 seconds
Started Jul 06 05:03:02 PM PDT 24
Finished Jul 06 05:03:06 PM PDT 24
Peak memory 216932 kb
Host smart-8aebfc1f-b058-4e2e-9d9a-0bcbfcc2d3fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3397302199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.3
397302199
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.2104567249
Short name T1114
Test name
Test status
Simulation time 594056961 ps
CPU time 17.87 seconds
Started Jul 06 05:03:08 PM PDT 24
Finished Jul 06 05:03:26 PM PDT 24
Peak memory 216032 kb
Host smart-d373c664-5972-47d6-b820-a8ce0035b372
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104567249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device
_tl_intg_err.2104567249
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1955827809
Short name T1037
Test name
Test status
Simulation time 39710023 ps
CPU time 2.46 seconds
Started Jul 06 05:03:15 PM PDT 24
Finished Jul 06 05:03:18 PM PDT 24
Peak memory 216932 kb
Host smart-5d07c007-817d-486f-a2f6-3ceb648d759d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955827809 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1955827809
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.4053460063
Short name T1047
Test name
Test status
Simulation time 152938974 ps
CPU time 1.33 seconds
Started Jul 06 05:03:07 PM PDT 24
Finished Jul 06 05:03:08 PM PDT 24
Peak memory 207604 kb
Host smart-1b57a988-da24-46a3-829f-17e2928f1000
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053460063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.4
053460063
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.2538956217
Short name T1120
Test name
Test status
Simulation time 202627499 ps
CPU time 0.76 seconds
Started Jul 06 05:03:15 PM PDT 24
Finished Jul 06 05:03:17 PM PDT 24
Peak memory 204264 kb
Host smart-c7800ea9-e709-4474-b967-1dafa6985837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2538956217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.2
538956217
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.2077879171
Short name T1033
Test name
Test status
Simulation time 68932573 ps
CPU time 3.95 seconds
Started Jul 06 05:03:07 PM PDT 24
Finished Jul 06 05:03:12 PM PDT 24
Peak memory 215612 kb
Host smart-3295798d-3d87-436e-805d-f33a74408c63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077879171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.2077879171
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.3989654846
Short name T1108
Test name
Test status
Simulation time 206215629 ps
CPU time 4.6 seconds
Started Jul 06 05:03:07 PM PDT 24
Finished Jul 06 05:03:12 PM PDT 24
Peak memory 215988 kb
Host smart-347d02de-8e9f-4ba8-b0bc-4b271a6f8f2b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3989654846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.3
989654846
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.2007343267
Short name T519
Test name
Test status
Simulation time 123983464 ps
CPU time 2.39 seconds
Started Jul 06 06:39:27 PM PDT 24
Finished Jul 06 06:39:29 PM PDT 24
Peak memory 232320 kb
Host smart-b44e10b4-69b4-4ea4-8999-0649b5549d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007343267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.2007343267
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.1268121276
Short name T464
Test name
Test status
Simulation time 40927020 ps
CPU time 0.74 seconds
Started Jul 06 06:39:22 PM PDT 24
Finished Jul 06 06:39:23 PM PDT 24
Peak memory 206624 kb
Host smart-417cf750-ccd1-4592-9ebb-3d0988042141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268121276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.1268121276
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2930459679
Short name T675
Test name
Test status
Simulation time 24404592638 ps
CPU time 185.95 seconds
Started Jul 06 06:39:26 PM PDT 24
Finished Jul 06 06:42:32 PM PDT 24
Peak memory 252360 kb
Host smart-293aeede-d7bb-43ca-a6aa-5ede1acf50d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930459679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2930459679
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.2125894946
Short name T151
Test name
Test status
Simulation time 140773076264 ps
CPU time 302.5 seconds
Started Jul 06 06:39:27 PM PDT 24
Finished Jul 06 06:44:30 PM PDT 24
Peak memory 253012 kb
Host smart-00350a7e-f6e2-43d6-858b-d8249ce96a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125894946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.2125894946
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_intercept.1971486871
Short name T926
Test name
Test status
Simulation time 1265140853 ps
CPU time 8.62 seconds
Started Jul 06 06:39:42 PM PDT 24
Finished Jul 06 06:39:51 PM PDT 24
Peak memory 232756 kb
Host smart-5ad48cdf-2ce6-44a6-95fa-5aad2c21ae8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971486871 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.1971486871
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.3039215034
Short name T57
Test name
Test status
Simulation time 10987524176 ps
CPU time 55.21 seconds
Started Jul 06 06:39:27 PM PDT 24
Finished Jul 06 06:40:22 PM PDT 24
Peak memory 240956 kb
Host smart-553c2726-1810-4c92-b567-9676bc3587f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039215034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.3039215034
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.130572665
Short name T47
Test name
Test status
Simulation time 7415463847 ps
CPU time 23.35 seconds
Started Jul 06 06:39:42 PM PDT 24
Finished Jul 06 06:40:06 PM PDT 24
Peak memory 250012 kb
Host smart-fab0d273-385e-4e49-af7c-882eee7df936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130572665 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap.
130572665
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1201912301
Short name T158
Test name
Test status
Simulation time 180893693 ps
CPU time 4.02 seconds
Started Jul 06 06:39:27 PM PDT 24
Finished Jul 06 06:39:31 PM PDT 24
Peak memory 220080 kb
Host smart-6322df62-5a2f-4a1e-b6a8-8de017f22c42
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1201912301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1201912301
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.565189063
Short name T84
Test name
Test status
Simulation time 207181177 ps
CPU time 0.97 seconds
Started Jul 06 06:39:30 PM PDT 24
Finished Jul 06 06:39:31 PM PDT 24
Peak memory 236592 kb
Host smart-ab7560bf-9711-4d44-bc1b-6af10076c945
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565189063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.565189063
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.2645522469
Short name T199
Test name
Test status
Simulation time 57625414675 ps
CPU time 587.76 seconds
Started Jul 06 06:39:32 PM PDT 24
Finished Jul 06 06:49:21 PM PDT 24
Peak memory 261516 kb
Host smart-d852a309-de04-450e-a453-40ff7bf0f8a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645522469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stres
s_all.2645522469
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.776512685
Short name T30
Test name
Test status
Simulation time 2965176261 ps
CPU time 19.59 seconds
Started Jul 06 06:39:29 PM PDT 24
Finished Jul 06 06:39:49 PM PDT 24
Peak memory 216616 kb
Host smart-484a451e-b64e-4e18-af52-e351d5cc6d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776512685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.776512685
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.2299407094
Short name T660
Test name
Test status
Simulation time 15337965589 ps
CPU time 10.52 seconds
Started Jul 06 06:39:28 PM PDT 24
Finished Jul 06 06:39:39 PM PDT 24
Peak memory 216384 kb
Host smart-ccdb4be1-6da4-4bea-aefa-6d3229b82b00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299407094 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.2299407094
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.2858830380
Short name T347
Test name
Test status
Simulation time 504051642 ps
CPU time 4.33 seconds
Started Jul 06 06:39:28 PM PDT 24
Finished Jul 06 06:39:32 PM PDT 24
Peak memory 216228 kb
Host smart-35866a5a-2c73-48ac-8e9c-342b0f04c5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858830380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.2858830380
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.839216851
Short name T507
Test name
Test status
Simulation time 80651296 ps
CPU time 0.78 seconds
Started Jul 06 06:39:27 PM PDT 24
Finished Jul 06 06:39:28 PM PDT 24
Peak memory 205984 kb
Host smart-a7c4757b-0de3-49f0-80f7-7ad3fbf07d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839216851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.839216851
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.619135685
Short name T503
Test name
Test status
Simulation time 36111149 ps
CPU time 2.54 seconds
Started Jul 06 06:39:42 PM PDT 24
Finished Jul 06 06:39:45 PM PDT 24
Peak memory 232400 kb
Host smart-31323efe-08a5-4b9e-b699-e7a4b15df7a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619135685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.619135685
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.328510709
Short name T145
Test name
Test status
Simulation time 15699386 ps
CPU time 0.71 seconds
Started Jul 06 06:39:36 PM PDT 24
Finished Jul 06 06:39:37 PM PDT 24
Peak memory 205504 kb
Host smart-ed5af3ff-6787-4c89-b6c4-4ae0f528df01
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328510709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.328510709
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.100381894
Short name T258
Test name
Test status
Simulation time 51043905 ps
CPU time 2.8 seconds
Started Jul 06 06:39:34 PM PDT 24
Finished Jul 06 06:39:37 PM PDT 24
Peak memory 232652 kb
Host smart-ec82d72c-006f-4466-a7b7-75f2f4b4e3cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100381894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.100381894
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.4000624124
Short name T606
Test name
Test status
Simulation time 13241960 ps
CPU time 0.76 seconds
Started Jul 06 06:39:30 PM PDT 24
Finished Jul 06 06:39:31 PM PDT 24
Peak memory 206640 kb
Host smart-fd8f07ab-4c5e-402f-9762-2428cddef7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000624124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.4000624124
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1633866430
Short name T682
Test name
Test status
Simulation time 121575619786 ps
CPU time 116.84 seconds
Started Jul 06 06:39:35 PM PDT 24
Finished Jul 06 06:41:32 PM PDT 24
Peak memory 249228 kb
Host smart-00f1e96d-154e-442e-9425-b3b0b415d040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633866430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1633866430
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.613337020
Short name T348
Test name
Test status
Simulation time 12844045586 ps
CPU time 58.49 seconds
Started Jul 06 06:39:43 PM PDT 24
Finished Jul 06 06:40:42 PM PDT 24
Peak memory 250324 kb
Host smart-0197c83e-30fa-4422-a5d0-8907debf5684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613337020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.613337020
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.207498900
Short name T225
Test name
Test status
Simulation time 1941653365 ps
CPU time 42.02 seconds
Started Jul 06 06:39:36 PM PDT 24
Finished Jul 06 06:40:19 PM PDT 24
Peak memory 250208 kb
Host smart-fcf9663e-4ae0-438d-b709-c6b2fca749b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207498900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.
207498900
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.2094859845
Short name T245
Test name
Test status
Simulation time 3514018297 ps
CPU time 41.26 seconds
Started Jul 06 06:39:43 PM PDT 24
Finished Jul 06 06:40:24 PM PDT 24
Peak memory 249260 kb
Host smart-331985a8-c390-4176-8944-a74f6425a9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094859845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.2094859845
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.1397917610
Short name T234
Test name
Test status
Simulation time 2401532806 ps
CPU time 7.46 seconds
Started Jul 06 06:39:36 PM PDT 24
Finished Jul 06 06:39:43 PM PDT 24
Peak memory 232860 kb
Host smart-dff2e16b-5c02-4ec0-8fc9-727eb797ec3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1397917610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.1397917610
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.4274726202
Short name T881
Test name
Test status
Simulation time 19903518386 ps
CPU time 51.24 seconds
Started Jul 06 06:39:35 PM PDT 24
Finished Jul 06 06:40:26 PM PDT 24
Peak memory 232824 kb
Host smart-47a4feb8-f674-46ca-84fd-bfd005d0d48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4274726202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.4274726202
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.2754072968
Short name T640
Test name
Test status
Simulation time 419472794 ps
CPU time 3.6 seconds
Started Jul 06 06:39:43 PM PDT 24
Finished Jul 06 06:39:47 PM PDT 24
Peak memory 224456 kb
Host smart-45e450b3-d9ff-4fcb-9d52-d8f6881971a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754072968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap
.2754072968
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.2252109536
Short name T536
Test name
Test status
Simulation time 579491318 ps
CPU time 5.83 seconds
Started Jul 06 06:39:31 PM PDT 24
Finished Jul 06 06:39:37 PM PDT 24
Peak memory 224492 kb
Host smart-49c98d00-2f84-408e-aa6c-d211137696cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2252109536 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.2252109536
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.842871803
Short name T375
Test name
Test status
Simulation time 2222571096 ps
CPU time 13.53 seconds
Started Jul 06 06:39:37 PM PDT 24
Finished Jul 06 06:39:51 PM PDT 24
Peak memory 222204 kb
Host smart-166ba6fa-239f-46c2-be83-9275fa6e3be7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=842871803 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.842871803
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.1260975881
Short name T87
Test name
Test status
Simulation time 113036768 ps
CPU time 1.02 seconds
Started Jul 06 06:39:37 PM PDT 24
Finished Jul 06 06:39:39 PM PDT 24
Peak memory 235500 kb
Host smart-9ed995a8-248f-4610-8039-928223b0642b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260975881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.1260975881
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.1125405948
Short name T1001
Test name
Test status
Simulation time 8266258654 ps
CPU time 80.25 seconds
Started Jul 06 06:39:43 PM PDT 24
Finished Jul 06 06:41:03 PM PDT 24
Peak memory 250572 kb
Host smart-9da93c41-3186-45bb-9979-3c15348ca63a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1125405948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stres
s_all.1125405948
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.4002596595
Short name T579
Test name
Test status
Simulation time 1534221804 ps
CPU time 22.25 seconds
Started Jul 06 06:39:29 PM PDT 24
Finished Jul 06 06:39:52 PM PDT 24
Peak memory 216500 kb
Host smart-bda71eb7-97b1-414c-9b01-c3bfeaf65b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002596595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.4002596595
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.1590196692
Short name T453
Test name
Test status
Simulation time 828926528 ps
CPU time 3.53 seconds
Started Jul 06 06:39:32 PM PDT 24
Finished Jul 06 06:39:35 PM PDT 24
Peak memory 216204 kb
Host smart-cbdebf80-3d6a-427e-8046-e4d17c5f22aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590196692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.1590196692
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3987083287
Short name T729
Test name
Test status
Simulation time 104350051 ps
CPU time 2.17 seconds
Started Jul 06 06:39:29 PM PDT 24
Finished Jul 06 06:39:32 PM PDT 24
Peak memory 216244 kb
Host smart-d47855f3-3e5e-42c0-894f-bb816a5df207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987083287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3987083287
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.3241715214
Short name T917
Test name
Test status
Simulation time 18349592 ps
CPU time 0.7 seconds
Started Jul 06 06:39:30 PM PDT 24
Finished Jul 06 06:39:30 PM PDT 24
Peak memory 206016 kb
Host smart-4e7fe306-71f8-4e4c-aff2-687ae212fdb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241715214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.3241715214
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2634632916
Short name T758
Test name
Test status
Simulation time 2019141511 ps
CPU time 5.44 seconds
Started Jul 06 06:39:35 PM PDT 24
Finished Jul 06 06:39:41 PM PDT 24
Peak memory 232644 kb
Host smart-796fb239-1aa5-45b4-af24-3629a8b7c1ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634632916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2634632916
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3791160671
Short name T535
Test name
Test status
Simulation time 59606974 ps
CPU time 0.69 seconds
Started Jul 06 06:40:25 PM PDT 24
Finished Jul 06 06:40:26 PM PDT 24
Peak memory 204940 kb
Host smart-ba401939-7d01-4ca5-bbab-4ca90446967c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791160671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3791160671
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.1505508012
Short name T734
Test name
Test status
Simulation time 312295064 ps
CPU time 2.92 seconds
Started Jul 06 06:40:25 PM PDT 24
Finished Jul 06 06:40:28 PM PDT 24
Peak memory 224448 kb
Host smart-0e61d8b9-7334-4d53-8b7e-be22315afdcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505508012 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.1505508012
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.3067908372
Short name T93
Test name
Test status
Simulation time 16205212 ps
CPU time 0.76 seconds
Started Jul 06 06:40:20 PM PDT 24
Finished Jul 06 06:40:21 PM PDT 24
Peak memory 205584 kb
Host smart-b01b50e0-446c-48d3-b605-5ddb6ec6d4ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067908372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.3067908372
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.2932265656
Short name T309
Test name
Test status
Simulation time 15417649819 ps
CPU time 69.52 seconds
Started Jul 06 06:40:25 PM PDT 24
Finished Jul 06 06:41:35 PM PDT 24
Peak memory 256940 kb
Host smart-d4720c3c-7514-4fbb-85cc-9999a9d80d24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932265656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.2932265656
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.3336433457
Short name T720
Test name
Test status
Simulation time 9752642953 ps
CPU time 31.29 seconds
Started Jul 06 06:40:24 PM PDT 24
Finished Jul 06 06:40:55 PM PDT 24
Peak memory 231684 kb
Host smart-1eb7c0c7-8f91-4b16-ba8c-c16deb4f9956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336433457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.3336433457
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3515640120
Short name T847
Test name
Test status
Simulation time 27612498373 ps
CPU time 94.95 seconds
Started Jul 06 06:40:26 PM PDT 24
Finished Jul 06 06:42:01 PM PDT 24
Peak memory 253488 kb
Host smart-5f862249-0948-4c80-bc93-c04a79c5c4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515640120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3515640120
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.2908215720
Short name T796
Test name
Test status
Simulation time 162456220 ps
CPU time 3.26 seconds
Started Jul 06 06:40:25 PM PDT 24
Finished Jul 06 06:40:28 PM PDT 24
Peak memory 232668 kb
Host smart-59f91422-875e-4d1e-9aab-9bb23bf92b5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908215720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.2908215720
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.2035904568
Short name T473
Test name
Test status
Simulation time 47084379565 ps
CPU time 156.61 seconds
Started Jul 06 06:40:25 PM PDT 24
Finished Jul 06 06:43:02 PM PDT 24
Peak memory 249232 kb
Host smart-9ececf05-94e0-43c6-b318-ef63254d4c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035904568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.2035904568
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/10.spi_device_intercept.2452114935
Short name T277
Test name
Test status
Simulation time 600068255 ps
CPU time 5.16 seconds
Started Jul 06 06:40:20 PM PDT 24
Finished Jul 06 06:40:26 PM PDT 24
Peak memory 224512 kb
Host smart-21fa63ca-478d-4846-aefa-4ca06c1b27ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452114935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.2452114935
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.2677572899
Short name T256
Test name
Test status
Simulation time 2377395118 ps
CPU time 24.52 seconds
Started Jul 06 06:40:31 PM PDT 24
Finished Jul 06 06:40:56 PM PDT 24
Peak memory 232732 kb
Host smart-87f8a0c9-0251-4030-83f9-abe6f5d8b6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677572899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.2677572899
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.2499051559
Short name T239
Test name
Test status
Simulation time 919448723 ps
CPU time 5.26 seconds
Started Jul 06 06:40:33 PM PDT 24
Finished Jul 06 06:40:39 PM PDT 24
Peak memory 238096 kb
Host smart-141bb8de-e9fe-4b1b-b4c4-6b81ebe80f0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499051559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.2499051559
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.143273121
Short name T522
Test name
Test status
Simulation time 32527677 ps
CPU time 2.45 seconds
Started Jul 06 06:40:21 PM PDT 24
Finished Jul 06 06:40:24 PM PDT 24
Peak memory 232264 kb
Host smart-2c15b8e1-8d2f-4335-9252-5d4f463a19ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143273121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.143273121
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.1327966840
Short name T487
Test name
Test status
Simulation time 1186597103 ps
CPU time 5.3 seconds
Started Jul 06 06:40:31 PM PDT 24
Finished Jul 06 06:40:37 PM PDT 24
Peak memory 218660 kb
Host smart-337a5e98-0052-4398-9a44-38d47ae9d884
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1327966840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.1327966840
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.1514029669
Short name T168
Test name
Test status
Simulation time 8288455552 ps
CPU time 19.33 seconds
Started Jul 06 06:40:24 PM PDT 24
Finished Jul 06 06:40:44 PM PDT 24
Peak memory 224564 kb
Host smart-c8af71c1-be89-4f88-80f4-3217e4a2a39b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1514029669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.1514029669
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1710877955
Short name T456
Test name
Test status
Simulation time 2411826318 ps
CPU time 21.58 seconds
Started Jul 06 06:40:19 PM PDT 24
Finished Jul 06 06:40:41 PM PDT 24
Peak memory 220044 kb
Host smart-ed86d9c1-f1eb-4240-96f3-4e61d14df31f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710877955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1710877955
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.2889910899
Short name T744
Test name
Test status
Simulation time 46590780632 ps
CPU time 19.27 seconds
Started Jul 06 06:40:20 PM PDT 24
Finished Jul 06 06:40:40 PM PDT 24
Peak memory 216444 kb
Host smart-b856955d-0652-480f-ab12-aeac2f507416
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889910899 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.2889910899
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.267616802
Short name T527
Test name
Test status
Simulation time 669221906 ps
CPU time 3.55 seconds
Started Jul 06 06:40:20 PM PDT 24
Finished Jul 06 06:40:24 PM PDT 24
Peak memory 216196 kb
Host smart-d1406972-b634-44c5-9991-0cb3a2a3e83f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=267616802 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.267616802
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.2435361204
Short name T516
Test name
Test status
Simulation time 41327785 ps
CPU time 0.82 seconds
Started Jul 06 06:40:31 PM PDT 24
Finished Jul 06 06:40:32 PM PDT 24
Peak memory 205920 kb
Host smart-e840f0b9-001a-4524-b296-826ccf83e653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435361204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.2435361204
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.705029108
Short name T240
Test name
Test status
Simulation time 41973367237 ps
CPU time 14.83 seconds
Started Jul 06 06:40:24 PM PDT 24
Finished Jul 06 06:40:39 PM PDT 24
Peak memory 239648 kb
Host smart-93d31ec6-ed44-48bc-b11c-1bf203f57af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705029108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.705029108
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2429995314
Short name T470
Test name
Test status
Simulation time 12959103 ps
CPU time 0.71 seconds
Started Jul 06 06:40:28 PM PDT 24
Finished Jul 06 06:40:29 PM PDT 24
Peak memory 205504 kb
Host smart-67e04511-7488-4397-8d2a-502cf6bc54bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429995314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2429995314
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.1721658045
Short name T270
Test name
Test status
Simulation time 151151983 ps
CPU time 2.62 seconds
Started Jul 06 06:40:32 PM PDT 24
Finished Jul 06 06:40:35 PM PDT 24
Peak memory 232632 kb
Host smart-62ebd270-6a51-47e4-b7e1-c6f82ef76be4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721658045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.1721658045
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.1337921314
Short name T67
Test name
Test status
Simulation time 34847149 ps
CPU time 0.8 seconds
Started Jul 06 06:40:25 PM PDT 24
Finished Jul 06 06:40:26 PM PDT 24
Peak memory 206576 kb
Host smart-9a29d108-abea-4548-850b-c1de68fbf1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337921314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.1337921314
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.981903589
Short name T97
Test name
Test status
Simulation time 48980177205 ps
CPU time 183.23 seconds
Started Jul 06 06:40:30 PM PDT 24
Finished Jul 06 06:43:34 PM PDT 24
Peak memory 256244 kb
Host smart-bad0f84e-a56e-4538-8d1f-e2176271f1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981903589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.981903589
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.1085582538
Short name T65
Test name
Test status
Simulation time 6697401475 ps
CPU time 107.34 seconds
Started Jul 06 06:40:28 PM PDT 24
Finished Jul 06 06:42:16 PM PDT 24
Peak memory 265664 kb
Host smart-88500440-9120-4cb1-80d3-958f8e0d6b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1085582538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.1085582538
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.3990117164
Short name T792
Test name
Test status
Simulation time 7654784905 ps
CPU time 9.44 seconds
Started Jul 06 06:40:31 PM PDT 24
Finished Jul 06 06:40:41 PM PDT 24
Peak memory 232748 kb
Host smart-d4456e80-3876-44a4-a43e-5b6ca81495e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990117164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.3990117164
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.3313719117
Short name T411
Test name
Test status
Simulation time 20763853 ps
CPU time 0.77 seconds
Started Jul 06 06:40:27 PM PDT 24
Finished Jul 06 06:40:28 PM PDT 24
Peak memory 215816 kb
Host smart-a72e57f1-a85f-4db2-b8fa-940c752fd7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313719117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.3313719117
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_intercept.756305189
Short name T666
Test name
Test status
Simulation time 1617352161 ps
CPU time 6.17 seconds
Started Jul 06 06:40:25 PM PDT 24
Finished Jul 06 06:40:32 PM PDT 24
Peak memory 232672 kb
Host smart-f4658229-9871-4f57-92a4-bb0924f3f2df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756305189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.756305189
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.4281893360
Short name T821
Test name
Test status
Simulation time 2461477582 ps
CPU time 5.94 seconds
Started Jul 06 06:40:31 PM PDT 24
Finished Jul 06 06:40:38 PM PDT 24
Peak memory 224576 kb
Host smart-8b94db78-9703-42a8-8144-cd24e764b110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281893360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.4281893360
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.303699058
Short name T730
Test name
Test status
Simulation time 3956063898 ps
CPU time 7.02 seconds
Started Jul 06 06:40:23 PM PDT 24
Finished Jul 06 06:40:30 PM PDT 24
Peak memory 224476 kb
Host smart-9441e3d7-bb47-4f04-9d9c-ad712b87c868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303699058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swap
.303699058
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.2420858490
Short name T565
Test name
Test status
Simulation time 5466973910 ps
CPU time 20.04 seconds
Started Jul 06 06:40:26 PM PDT 24
Finished Jul 06 06:40:46 PM PDT 24
Peak memory 248484 kb
Host smart-da73cb43-0e88-4143-90bf-f261d27e88c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420858490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.2420858490
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.2886893230
Short name T685
Test name
Test status
Simulation time 2238245810 ps
CPU time 36.56 seconds
Started Jul 06 06:40:27 PM PDT 24
Finished Jul 06 06:41:03 PM PDT 24
Peak memory 238212 kb
Host smart-4cc61919-2c0a-4861-b5d3-cd770cbfc132
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886893230 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stre
ss_all.2886893230
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.540705020
Short name T460
Test name
Test status
Simulation time 4610051931 ps
CPU time 21.71 seconds
Started Jul 06 06:40:23 PM PDT 24
Finished Jul 06 06:40:45 PM PDT 24
Peak memory 216432 kb
Host smart-ce5f4e73-c051-458d-a05b-45918755f36d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540705020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.540705020
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1186185930
Short name T514
Test name
Test status
Simulation time 1889989081 ps
CPU time 6.69 seconds
Started Jul 06 06:40:25 PM PDT 24
Finished Jul 06 06:40:32 PM PDT 24
Peak memory 216188 kb
Host smart-54c6eaa4-62f0-41ca-ba68-b1ac93760e3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186185930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1186185930
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3247034280
Short name T528
Test name
Test status
Simulation time 62631595 ps
CPU time 1.34 seconds
Started Jul 06 06:40:26 PM PDT 24
Finished Jul 06 06:40:27 PM PDT 24
Peak memory 216220 kb
Host smart-472b31d0-666d-40d5-a2d2-ef16ba1f9c42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247034280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3247034280
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.3706263694
Short name T381
Test name
Test status
Simulation time 108984876 ps
CPU time 0.82 seconds
Started Jul 06 06:40:26 PM PDT 24
Finished Jul 06 06:40:27 PM PDT 24
Peak memory 205936 kb
Host smart-34bf03dd-c56b-4a0a-a5ae-e37d691198f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706263694 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.3706263694
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.3845694828
Short name T643
Test name
Test status
Simulation time 698774301 ps
CPU time 4.32 seconds
Started Jul 06 06:40:30 PM PDT 24
Finished Jul 06 06:40:35 PM PDT 24
Peak memory 224556 kb
Host smart-0df35887-03ef-42ae-9010-9e05616c7208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3845694828 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.3845694828
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.2996827820
Short name T500
Test name
Test status
Simulation time 124633930 ps
CPU time 0.7 seconds
Started Jul 06 06:40:33 PM PDT 24
Finished Jul 06 06:40:34 PM PDT 24
Peak memory 204976 kb
Host smart-0a4d6644-1ef8-4d31-83e7-73cd8c77aca9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996827820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.
2996827820
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.829115491
Short name T1
Test name
Test status
Simulation time 134124650 ps
CPU time 2.43 seconds
Started Jul 06 06:40:33 PM PDT 24
Finished Jul 06 06:40:36 PM PDT 24
Peak memory 232376 kb
Host smart-dae4de61-af32-4d55-9851-90a424d45fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829115491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.829115491
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.3764958449
Short name T639
Test name
Test status
Simulation time 14532833 ps
CPU time 0.73 seconds
Started Jul 06 06:40:30 PM PDT 24
Finished Jul 06 06:40:31 PM PDT 24
Peak memory 205920 kb
Host smart-330e1067-9da8-4dd5-b4d1-abed3a9a20a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764958449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.3764958449
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.4245011517
Short name T558
Test name
Test status
Simulation time 18008694 ps
CPU time 0.78 seconds
Started Jul 06 06:40:34 PM PDT 24
Finished Jul 06 06:40:35 PM PDT 24
Peak memory 215816 kb
Host smart-2d79a9d4-a8a9-4104-8991-af44a1324abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245011517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.4245011517
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.1216959749
Short name T968
Test name
Test status
Simulation time 81674613556 ps
CPU time 131.77 seconds
Started Jul 06 06:40:34 PM PDT 24
Finished Jul 06 06:42:47 PM PDT 24
Peak memory 249308 kb
Host smart-d407a25d-b9e6-4cdf-9304-dff12cba166f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216959749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.1216959749
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.3981303177
Short name T276
Test name
Test status
Simulation time 13105744206 ps
CPU time 47.98 seconds
Started Jul 06 06:40:34 PM PDT 24
Finished Jul 06 06:41:22 PM PDT 24
Peak memory 249652 kb
Host smart-3b2d2e50-08e8-4201-9868-3a6cf24a8a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981303177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.3981303177
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.3585914945
Short name T553
Test name
Test status
Simulation time 879892052 ps
CPU time 4.86 seconds
Started Jul 06 06:40:34 PM PDT 24
Finished Jul 06 06:40:40 PM PDT 24
Peak memory 232628 kb
Host smart-52bb01b7-01fa-4ff0-92a4-2c60aa4851b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585914945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.3585914945
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.317519717
Short name T475
Test name
Test status
Simulation time 127003882418 ps
CPU time 213 seconds
Started Jul 06 06:40:38 PM PDT 24
Finished Jul 06 06:44:11 PM PDT 24
Peak memory 249224 kb
Host smart-795911f2-a270-4162-a71d-54c9d8deeac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317519717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmds
.317519717
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.3561754913
Short name T247
Test name
Test status
Simulation time 1287284188 ps
CPU time 9.78 seconds
Started Jul 06 06:40:33 PM PDT 24
Finished Jul 06 06:40:43 PM PDT 24
Peak memory 232664 kb
Host smart-b94f4e76-c264-452c-b2e6-c1c0ad897e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561754913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.3561754913
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.750443463
Short name T263
Test name
Test status
Simulation time 227452345 ps
CPU time 3.61 seconds
Started Jul 06 06:40:32 PM PDT 24
Finished Jul 06 06:40:36 PM PDT 24
Peak memory 224440 kb
Host smart-94e562f2-ac89-4872-9514-04b343726d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=750443463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.750443463
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2739430246
Short name T354
Test name
Test status
Simulation time 1320297545 ps
CPU time 3.21 seconds
Started Jul 06 06:40:32 PM PDT 24
Finished Jul 06 06:40:36 PM PDT 24
Peak memory 224372 kb
Host smart-fd28c6e9-ab8b-4154-8013-509139a11989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739430246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2739430246
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.2084309734
Short name T269
Test name
Test status
Simulation time 454963018 ps
CPU time 4 seconds
Started Jul 06 06:40:34 PM PDT 24
Finished Jul 06 06:40:39 PM PDT 24
Peak memory 232664 kb
Host smart-13143c5b-e558-44d6-b981-28badf869c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084309734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.2084309734
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2074923308
Short name T467
Test name
Test status
Simulation time 967841165 ps
CPU time 4.51 seconds
Started Jul 06 06:40:42 PM PDT 24
Finished Jul 06 06:40:46 PM PDT 24
Peak memory 220156 kb
Host smart-4ec66cb7-dee2-4085-83cb-6085563b287b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2074923308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2074923308
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.860198123
Short name T61
Test name
Test status
Simulation time 26637365079 ps
CPU time 269.17 seconds
Started Jul 06 06:40:34 PM PDT 24
Finished Jul 06 06:45:04 PM PDT 24
Peak memory 252304 kb
Host smart-2976f5c6-b2f7-41c4-9f93-0393f19e94ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=860198123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stres
s_all.860198123
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.3159866016
Short name T714
Test name
Test status
Simulation time 1536307926 ps
CPU time 15.96 seconds
Started Jul 06 06:40:33 PM PDT 24
Finished Jul 06 06:40:49 PM PDT 24
Peak memory 216260 kb
Host smart-96cd458c-2d54-4409-b29c-200400d42c8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159866016 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.3159866016
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3159048546
Short name T448
Test name
Test status
Simulation time 8385871109 ps
CPU time 5.67 seconds
Started Jul 06 06:40:30 PM PDT 24
Finished Jul 06 06:40:36 PM PDT 24
Peak memory 216376 kb
Host smart-251bd4c3-26b9-4e09-b69a-da71504d65c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159048546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3159048546
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1663287291
Short name T617
Test name
Test status
Simulation time 1154210487 ps
CPU time 2.7 seconds
Started Jul 06 06:40:38 PM PDT 24
Finished Jul 06 06:40:41 PM PDT 24
Peak memory 216292 kb
Host smart-4c43eb11-121a-4cde-af47-d2dd30cb345c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1663287291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1663287291
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.782232141
Short name T860
Test name
Test status
Simulation time 54559791 ps
CPU time 0.88 seconds
Started Jul 06 06:40:33 PM PDT 24
Finished Jul 06 06:40:35 PM PDT 24
Peak memory 206016 kb
Host smart-49a45167-7440-4e84-8f5d-8fe106db881a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782232141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.782232141
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3767131903
Short name T3
Test name
Test status
Simulation time 22039148 ps
CPU time 0.68 seconds
Started Jul 06 06:40:41 PM PDT 24
Finished Jul 06 06:40:42 PM PDT 24
Peak memory 205536 kb
Host smart-9ee6634d-c4ef-4d89-9843-3ccc3b57d934
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767131903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3767131903
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.2293170026
Short name T692
Test name
Test status
Simulation time 312711998 ps
CPU time 3.31 seconds
Started Jul 06 06:40:40 PM PDT 24
Finished Jul 06 06:40:43 PM PDT 24
Peak memory 224460 kb
Host smart-27081108-cf1e-41c7-b838-c83132770051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293170026 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.2293170026
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.1727181682
Short name T150
Test name
Test status
Simulation time 192268319 ps
CPU time 0.77 seconds
Started Jul 06 06:40:38 PM PDT 24
Finished Jul 06 06:40:40 PM PDT 24
Peak memory 206956 kb
Host smart-31a8f4d4-8cbb-4a8c-9249-7c3e035922a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727181682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.1727181682
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.3681833275
Short name T250
Test name
Test status
Simulation time 797621419 ps
CPU time 11.2 seconds
Started Jul 06 06:40:41 PM PDT 24
Finished Jul 06 06:40:53 PM PDT 24
Peak memory 224520 kb
Host smart-5505657c-bb04-42a4-8fbd-cd9601860472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681833275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.3681833275
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.165739142
Short name T543
Test name
Test status
Simulation time 25784804762 ps
CPU time 90.16 seconds
Started Jul 06 06:40:37 PM PDT 24
Finished Jul 06 06:42:08 PM PDT 24
Peak memory 241020 kb
Host smart-e087cf1e-12c4-45fb-993f-ffb479ea69f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165739142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.165739142
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3616487449
Short name T471
Test name
Test status
Simulation time 21259178026 ps
CPU time 29.91 seconds
Started Jul 06 06:40:48 PM PDT 24
Finished Jul 06 06:41:18 PM PDT 24
Peak memory 217692 kb
Host smart-7728141e-1970-4e1d-adbd-dcb17a3717f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616487449 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3616487449
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.1787626666
Short name T328
Test name
Test status
Simulation time 385037902 ps
CPU time 14.63 seconds
Started Jul 06 06:40:40 PM PDT 24
Finished Jul 06 06:40:55 PM PDT 24
Peak memory 238888 kb
Host smart-c7187042-7c4d-4177-9245-d7f1f03d3336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787626666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.1787626666
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.1116438998
Short name T420
Test name
Test status
Simulation time 26915710124 ps
CPU time 26.09 seconds
Started Jul 06 06:40:39 PM PDT 24
Finished Jul 06 06:41:06 PM PDT 24
Peak memory 241016 kb
Host smart-ad5d06d2-dc3a-48e2-a765-3a6dfc79e641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116438998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.1116438998
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3251630784
Short name T856
Test name
Test status
Simulation time 189170255 ps
CPU time 3.53 seconds
Started Jul 06 06:40:38 PM PDT 24
Finished Jul 06 06:40:42 PM PDT 24
Peak memory 224444 kb
Host smart-bca9f953-cd7b-42ee-9022-f73cb8d71c25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251630784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3251630784
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2651467659
Short name T888
Test name
Test status
Simulation time 54705595972 ps
CPU time 43.34 seconds
Started Jul 06 06:40:42 PM PDT 24
Finished Jul 06 06:41:26 PM PDT 24
Peak memory 232852 kb
Host smart-8c90cb12-1e66-4eae-8517-edfdcc366071
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651467659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2651467659
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.886887911
Short name T566
Test name
Test status
Simulation time 32166015 ps
CPU time 2.55 seconds
Started Jul 06 06:40:37 PM PDT 24
Finished Jul 06 06:40:41 PM PDT 24
Peak memory 232336 kb
Host smart-d3b801c6-96b9-4c3a-bafd-6a83a994d6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886887911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swap
.886887911
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.2932567653
Short name T849
Test name
Test status
Simulation time 5174819349 ps
CPU time 5.72 seconds
Started Jul 06 06:40:35 PM PDT 24
Finished Jul 06 06:40:41 PM PDT 24
Peak memory 232856 kb
Host smart-757d824c-41aa-488b-911f-462dc4bf6503
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932567653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.2932567653
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3776372473
Short name T486
Test name
Test status
Simulation time 1434664569 ps
CPU time 4.88 seconds
Started Jul 06 06:40:41 PM PDT 24
Finished Jul 06 06:40:46 PM PDT 24
Peak memory 224192 kb
Host smart-3911f445-32da-4c0a-b2dd-8474c10bfece
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3776372473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3776372473
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.390864962
Short name T222
Test name
Test status
Simulation time 51214061389 ps
CPU time 264.63 seconds
Started Jul 06 06:40:39 PM PDT 24
Finished Jul 06 06:45:04 PM PDT 24
Peak memory 265080 kb
Host smart-c9a944b9-0189-48b5-8743-8673eb85f279
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390864962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stres
s_all.390864962
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.1259648839
Short name T806
Test name
Test status
Simulation time 13703293 ps
CPU time 0.7 seconds
Started Jul 06 06:40:36 PM PDT 24
Finished Jul 06 06:40:37 PM PDT 24
Peak memory 205744 kb
Host smart-da828c87-4860-4a07-9c90-11dd5b5ba8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259648839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.1259648839
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.3665921409
Short name T701
Test name
Test status
Simulation time 43618813065 ps
CPU time 11.9 seconds
Started Jul 06 06:40:36 PM PDT 24
Finished Jul 06 06:40:48 PM PDT 24
Peak memory 216440 kb
Host smart-cc485a5a-0b78-43ba-a838-46e1c392172d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665921409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.3665921409
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.1536341207
Short name T75
Test name
Test status
Simulation time 44563121 ps
CPU time 0.82 seconds
Started Jul 06 06:40:38 PM PDT 24
Finished Jul 06 06:40:39 PM PDT 24
Peak memory 207008 kb
Host smart-3bc24914-71aa-4512-bbe2-9cc049e9ea94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536341207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.1536341207
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.285174645
Short name T877
Test name
Test status
Simulation time 29346431 ps
CPU time 0.79 seconds
Started Jul 06 06:40:37 PM PDT 24
Finished Jul 06 06:40:38 PM PDT 24
Peak memory 206008 kb
Host smart-959ef39e-3414-4398-9e1d-807874fef83b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285174645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.285174645
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.3971481372
Short name T16
Test name
Test status
Simulation time 1941404864 ps
CPU time 8.69 seconds
Started Jul 06 06:40:38 PM PDT 24
Finished Jul 06 06:40:47 PM PDT 24
Peak memory 232672 kb
Host smart-ebae475f-980d-4a56-9d51-f669fa825fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971481372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.3971481372
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.313824161
Short name T914
Test name
Test status
Simulation time 13381936 ps
CPU time 0.72 seconds
Started Jul 06 06:40:44 PM PDT 24
Finished Jul 06 06:40:45 PM PDT 24
Peak memory 204992 kb
Host smart-dae13ae4-e7ab-470d-bdc5-80d4330d9c57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=313824161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.313824161
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.3116598920
Short name T483
Test name
Test status
Simulation time 1575739628 ps
CPU time 6.56 seconds
Started Jul 06 06:40:45 PM PDT 24
Finished Jul 06 06:40:51 PM PDT 24
Peak memory 224496 kb
Host smart-5cb344c8-9f33-4c46-8720-eb7360461565
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116598920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.3116598920
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.520348466
Short name T709
Test name
Test status
Simulation time 42929415 ps
CPU time 0.85 seconds
Started Jul 06 06:40:42 PM PDT 24
Finished Jul 06 06:40:43 PM PDT 24
Peak memory 206640 kb
Host smart-a05e5be2-9cfe-4a43-af65-713d31bc711c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520348466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.520348466
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.4006357967
Short name T312
Test name
Test status
Simulation time 66568589203 ps
CPU time 560.88 seconds
Started Jul 06 06:40:42 PM PDT 24
Finished Jul 06 06:50:03 PM PDT 24
Peak memory 257408 kb
Host smart-5c0ed813-7434-4dfe-9864-5e96c46b4a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4006357967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.4006357967
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.4095236162
Short name T332
Test name
Test status
Simulation time 5953886046 ps
CPU time 25.88 seconds
Started Jul 06 06:40:44 PM PDT 24
Finished Jul 06 06:41:10 PM PDT 24
Peak memory 240480 kb
Host smart-b5641446-a42b-4676-95e2-a7e67a1d219f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095236162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.4095236162
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.1980464695
Short name T899
Test name
Test status
Simulation time 18888816652 ps
CPU time 48.57 seconds
Started Jul 06 06:40:43 PM PDT 24
Finished Jul 06 06:41:32 PM PDT 24
Peak memory 224644 kb
Host smart-628e576b-3644-43da-a23f-01317f449149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980464695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmd
s.1980464695
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.691185163
Short name T71
Test name
Test status
Simulation time 20567415373 ps
CPU time 28.31 seconds
Started Jul 06 06:40:41 PM PDT 24
Finished Jul 06 06:41:10 PM PDT 24
Peak memory 224596 kb
Host smart-71d45ceb-c326-4735-b85b-1546edc07fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691185163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.691185163
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.3410711557
Short name T128
Test name
Test status
Simulation time 10395016571 ps
CPU time 28.97 seconds
Started Jul 06 06:40:41 PM PDT 24
Finished Jul 06 06:41:11 PM PDT 24
Peak memory 237384 kb
Host smart-55557b72-b911-4095-a0cf-73a41a173753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410711557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.3410711557
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.1499601066
Short name T289
Test name
Test status
Simulation time 41419746788 ps
CPU time 30.09 seconds
Started Jul 06 06:40:42 PM PDT 24
Finished Jul 06 06:41:12 PM PDT 24
Peak memory 239904 kb
Host smart-b242735c-4f51-42fb-bb36-08ab465bc087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499601066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.1499601066
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.1440967473
Short name T731
Test name
Test status
Simulation time 13474729375 ps
CPU time 10.6 seconds
Started Jul 06 06:40:41 PM PDT 24
Finished Jul 06 06:40:52 PM PDT 24
Peak memory 238212 kb
Host smart-f7f31436-6af2-44c3-98a8-d9a57daa4d79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440967473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.1440967473
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.3889204718
Short name T409
Test name
Test status
Simulation time 201402152 ps
CPU time 3.35 seconds
Started Jul 06 06:40:44 PM PDT 24
Finished Jul 06 06:40:47 PM PDT 24
Peak memory 218916 kb
Host smart-b162254e-36c5-4165-9bd2-4d475f2079d3
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3889204718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dir
ect.3889204718
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.1077777780
Short name T789
Test name
Test status
Simulation time 8527638022 ps
CPU time 29.78 seconds
Started Jul 06 06:40:48 PM PDT 24
Finished Jul 06 06:41:17 PM PDT 24
Peak memory 216584 kb
Host smart-b9a30d1f-5f8a-47a2-827e-0ba012d281ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077777780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.1077777780
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.3908138576
Short name T781
Test name
Test status
Simulation time 20745947506 ps
CPU time 8.18 seconds
Started Jul 06 06:40:45 PM PDT 24
Finished Jul 06 06:40:53 PM PDT 24
Peak memory 216356 kb
Host smart-751d4ace-ff1d-488c-b2ea-6f90495c4e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908138576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.3908138576
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2132293967
Short name T801
Test name
Test status
Simulation time 100380644 ps
CPU time 1.62 seconds
Started Jul 06 06:40:45 PM PDT 24
Finished Jul 06 06:40:46 PM PDT 24
Peak memory 216184 kb
Host smart-2a1aa466-e7e7-4e93-83a1-f6f3a10cefe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2132293967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2132293967
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.1966266922
Short name T673
Test name
Test status
Simulation time 265473540 ps
CPU time 0.91 seconds
Started Jul 06 06:40:41 PM PDT 24
Finished Jul 06 06:40:43 PM PDT 24
Peak memory 206296 kb
Host smart-00a611eb-55de-43e7-a422-d150fb7061f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966266922 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.1966266922
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.1473237796
Short name T244
Test name
Test status
Simulation time 973539751 ps
CPU time 5.5 seconds
Started Jul 06 06:40:44 PM PDT 24
Finished Jul 06 06:40:50 PM PDT 24
Peak memory 224448 kb
Host smart-5aca84fc-e6b9-492b-a119-7104b691bd40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1473237796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.1473237796
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.2952783137
Short name T663
Test name
Test status
Simulation time 38399478 ps
CPU time 0.69 seconds
Started Jul 06 06:40:45 PM PDT 24
Finished Jul 06 06:40:46 PM PDT 24
Peak memory 204928 kb
Host smart-cdc71ff2-a5fb-4e2b-9a7f-96f8e75a83df
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952783137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
2952783137
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.2901369671
Short name T597
Test name
Test status
Simulation time 1137025005 ps
CPU time 12.05 seconds
Started Jul 06 06:40:47 PM PDT 24
Finished Jul 06 06:40:59 PM PDT 24
Peak memory 232712 kb
Host smart-e7228764-e291-483e-a8e2-08316b4ce7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901369671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.2901369671
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.3095743174
Short name T465
Test name
Test status
Simulation time 57863696 ps
CPU time 0.74 seconds
Started Jul 06 06:40:46 PM PDT 24
Finished Jul 06 06:40:47 PM PDT 24
Peak memory 205884 kb
Host smart-689d72e8-e92f-4b31-87bb-8028428fef37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095743174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.3095743174
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.151354827
Short name T780
Test name
Test status
Simulation time 26141172910 ps
CPU time 17.42 seconds
Started Jul 06 06:40:45 PM PDT 24
Finished Jul 06 06:41:03 PM PDT 24
Peak memory 224644 kb
Host smart-90fff8db-387c-4708-b1d2-051266af29d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151354827 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.151354827
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.2963178017
Short name T649
Test name
Test status
Simulation time 22336229798 ps
CPU time 88.18 seconds
Started Jul 06 06:40:46 PM PDT 24
Finished Jul 06 06:42:15 PM PDT 24
Peak memory 241048 kb
Host smart-f00d82ed-104f-428c-bb4e-54799614be24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2963178017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.2963178017
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.3477753521
Short name T261
Test name
Test status
Simulation time 5754982546 ps
CPU time 79.19 seconds
Started Jul 06 06:40:47 PM PDT 24
Finished Jul 06 06:42:07 PM PDT 24
Peak memory 249268 kb
Host smart-f724b4f7-d880-4f39-bf57-14d07c7c8afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477753521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.3477753521
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.416842281
Short name T891
Test name
Test status
Simulation time 7405963949 ps
CPU time 21.1 seconds
Started Jul 06 06:40:48 PM PDT 24
Finished Jul 06 06:41:10 PM PDT 24
Peak memory 240972 kb
Host smart-e9be75c6-9fd2-413c-af55-0ecd972c00b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416842281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.416842281
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.2258377711
Short name T844
Test name
Test status
Simulation time 94141206759 ps
CPU time 250.82 seconds
Started Jul 06 06:40:46 PM PDT 24
Finished Jul 06 06:44:57 PM PDT 24
Peak memory 250616 kb
Host smart-592e116a-cacb-43a8-ab94-43aff6ee0847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258377711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.2258377711
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.1930872523
Short name T272
Test name
Test status
Simulation time 355468267 ps
CPU time 5.99 seconds
Started Jul 06 06:40:45 PM PDT 24
Finished Jul 06 06:40:51 PM PDT 24
Peak memory 232652 kb
Host smart-454510ec-8fdc-43e4-b010-55c3cc932b27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930872523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.1930872523
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.2032764260
Short name T510
Test name
Test status
Simulation time 3597793841 ps
CPU time 13.99 seconds
Started Jul 06 06:40:54 PM PDT 24
Finished Jul 06 06:41:08 PM PDT 24
Peak memory 224564 kb
Host smart-e5c2f195-9c38-49a6-92ee-099a20dc49e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2032764260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.2032764260
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.1386401941
Short name T862
Test name
Test status
Simulation time 233176180 ps
CPU time 4.2 seconds
Started Jul 06 06:40:46 PM PDT 24
Finished Jul 06 06:40:50 PM PDT 24
Peak memory 232648 kb
Host smart-b9f77240-c38c-4f5f-be47-c942ccee506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386401941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swa
p.1386401941
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.1907277239
Short name T208
Test name
Test status
Simulation time 179806084 ps
CPU time 2.13 seconds
Started Jul 06 06:40:46 PM PDT 24
Finished Jul 06 06:40:48 PM PDT 24
Peak memory 224408 kb
Host smart-5e3bb035-2a3f-43c9-ad8f-7810681e613c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907277239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.1907277239
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3439395651
Short name T550
Test name
Test status
Simulation time 4117953392 ps
CPU time 9.17 seconds
Started Jul 06 06:40:47 PM PDT 24
Finished Jul 06 06:40:56 PM PDT 24
Peak memory 223060 kb
Host smart-3756b267-5792-4b46-8c06-9f3f1e38b6c2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3439395651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3439395651
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2111525992
Short name T940
Test name
Test status
Simulation time 12373299281 ps
CPU time 110.44 seconds
Started Jul 06 06:40:45 PM PDT 24
Finished Jul 06 06:42:36 PM PDT 24
Peak memory 251400 kb
Host smart-e9f2746b-54de-4b8f-a61f-4ba4c9812eb9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111525992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2111525992
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.2748935780
Short name T659
Test name
Test status
Simulation time 2871866946 ps
CPU time 19.76 seconds
Started Jul 06 06:40:44 PM PDT 24
Finished Jul 06 06:41:04 PM PDT 24
Peak memory 216460 kb
Host smart-bf0022b0-9080-4dec-bd0d-1cf1694a9afd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748935780 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.2748935780
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.3369310238
Short name T696
Test name
Test status
Simulation time 936671400 ps
CPU time 5.98 seconds
Started Jul 06 06:40:45 PM PDT 24
Finished Jul 06 06:40:51 PM PDT 24
Peak memory 216220 kb
Host smart-89e99ad2-5ec0-4eda-9acb-fa8652e6ce96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369310238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.3369310238
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.1206146286
Short name T626
Test name
Test status
Simulation time 20682148 ps
CPU time 0.99 seconds
Started Jul 06 06:40:45 PM PDT 24
Finished Jul 06 06:40:46 PM PDT 24
Peak memory 207408 kb
Host smart-e71125af-5c15-4c3d-ac85-49d08ab8799c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206146286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.1206146286
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.326146452
Short name T611
Test name
Test status
Simulation time 55020006 ps
CPU time 0.74 seconds
Started Jul 06 06:40:49 PM PDT 24
Finished Jul 06 06:40:50 PM PDT 24
Peak memory 205940 kb
Host smart-26061685-84d7-41a7-a47f-adca971c21f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326146452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.326146452
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.1960141591
Short name T742
Test name
Test status
Simulation time 2648791835 ps
CPU time 7.2 seconds
Started Jul 06 06:40:46 PM PDT 24
Finished Jul 06 06:40:54 PM PDT 24
Peak memory 232804 kb
Host smart-2b39b4da-844c-463c-b0b7-f71ce1e5a0dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960141591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.1960141591
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1813727248
Short name T481
Test name
Test status
Simulation time 32461669 ps
CPU time 0.7 seconds
Started Jul 06 06:40:59 PM PDT 24
Finished Jul 06 06:41:00 PM PDT 24
Peak memory 205520 kb
Host smart-4a4ccd05-efe0-4858-bbad-417d09dbceca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1813727248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1813727248
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.949850985
Short name T48
Test name
Test status
Simulation time 278093501 ps
CPU time 3.13 seconds
Started Jul 06 06:40:49 PM PDT 24
Finished Jul 06 06:40:52 PM PDT 24
Peak memory 224520 kb
Host smart-b60a4ce8-2366-426d-addf-18ab9599e5a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949850985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.949850985
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1739514312
Short name T591
Test name
Test status
Simulation time 16764468 ps
CPU time 0.79 seconds
Started Jul 06 06:40:49 PM PDT 24
Finished Jul 06 06:40:50 PM PDT 24
Peak memory 206560 kb
Host smart-c8d36c66-099e-4847-8217-bf3bdd3dbfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739514312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1739514312
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.3574519202
Short name T201
Test name
Test status
Simulation time 5487717069 ps
CPU time 83.69 seconds
Started Jul 06 06:40:50 PM PDT 24
Finished Jul 06 06:42:14 PM PDT 24
Peak memory 265636 kb
Host smart-38948469-db30-4c24-89fb-50d54259aa23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3574519202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.3574519202
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.316945032
Short name T153
Test name
Test status
Simulation time 3976650039 ps
CPU time 90.8 seconds
Started Jul 06 06:40:53 PM PDT 24
Finished Jul 06 06:42:24 PM PDT 24
Peak memory 250624 kb
Host smart-ebb59df7-dbed-416b-bd1d-0cfd6f7276d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316945032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.316945032
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.31787177
Short name T200
Test name
Test status
Simulation time 48989909282 ps
CPU time 366.8 seconds
Started Jul 06 06:40:53 PM PDT 24
Finished Jul 06 06:47:00 PM PDT 24
Peak memory 257392 kb
Host smart-f64d6fc6-2f5b-4242-b4be-3615ba1962d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31787177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idle.31787177
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.337792136
Short name T694
Test name
Test status
Simulation time 352136832 ps
CPU time 6.25 seconds
Started Jul 06 06:40:50 PM PDT 24
Finished Jul 06 06:40:57 PM PDT 24
Peak memory 232712 kb
Host smart-956266ac-2e22-4c9c-a8d3-6c9298e3baaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337792136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.337792136
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.2208043228
Short name T897
Test name
Test status
Simulation time 4779162163 ps
CPU time 62.8 seconds
Started Jul 06 06:40:49 PM PDT 24
Finished Jul 06 06:41:52 PM PDT 24
Peak memory 269388 kb
Host smart-caa9a5b4-d18a-447b-926c-0e501ff00c53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208043228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.2208043228
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.2020858162
Short name T741
Test name
Test status
Simulation time 34448637 ps
CPU time 2.5 seconds
Started Jul 06 06:40:52 PM PDT 24
Finished Jul 06 06:40:55 PM PDT 24
Peak memory 232396 kb
Host smart-7bf43e69-2c83-41b7-888a-a5f9b891ef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020858162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.2020858162
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.2414589890
Short name T766
Test name
Test status
Simulation time 648637274 ps
CPU time 5.94 seconds
Started Jul 06 06:40:50 PM PDT 24
Finished Jul 06 06:40:57 PM PDT 24
Peak memory 232628 kb
Host smart-a19cff0a-2e20-4a93-a4a6-62ea5dd3366a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414589890 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.2414589890
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3460413232
Short name T871
Test name
Test status
Simulation time 4141141824 ps
CPU time 12.62 seconds
Started Jul 06 06:40:51 PM PDT 24
Finished Jul 06 06:41:04 PM PDT 24
Peak memory 224504 kb
Host smart-38f5e967-47ed-455a-a7f7-bf2c4b0f7fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460413232 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3460413232
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.3852645918
Short name T623
Test name
Test status
Simulation time 149818344 ps
CPU time 3.87 seconds
Started Jul 06 06:40:53 PM PDT 24
Finished Jul 06 06:40:58 PM PDT 24
Peak memory 235208 kb
Host smart-255e0c02-37aa-440a-8020-536aee4b6eb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852645918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.3852645918
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.2438634670
Short name T162
Test name
Test status
Simulation time 670606759 ps
CPU time 7.76 seconds
Started Jul 06 06:40:54 PM PDT 24
Finished Jul 06 06:41:02 PM PDT 24
Peak memory 222036 kb
Host smart-0f815688-5142-4118-97cd-b2d2f02289b6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2438634670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.2438634670
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.2262276187
Short name T920
Test name
Test status
Simulation time 356656492301 ps
CPU time 531.74 seconds
Started Jul 06 06:40:53 PM PDT 24
Finished Jul 06 06:49:46 PM PDT 24
Peak memory 250216 kb
Host smart-069db558-414e-4336-b303-44e3d8cde7a9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262276187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.2262276187
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.904977792
Short name T338
Test name
Test status
Simulation time 5419036372 ps
CPU time 24.11 seconds
Started Jul 06 06:40:55 PM PDT 24
Finished Jul 06 06:41:20 PM PDT 24
Peak memory 220368 kb
Host smart-8c2e6c1f-2594-4b72-9539-5b6be8f240bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=904977792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.904977792
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.440075438
Short name T906
Test name
Test status
Simulation time 182091851 ps
CPU time 1.76 seconds
Started Jul 06 06:40:53 PM PDT 24
Finished Jul 06 06:40:55 PM PDT 24
Peak memory 207884 kb
Host smart-45585877-3f84-4a75-a53e-ed774e788a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440075438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.440075438
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.1187847862
Short name T761
Test name
Test status
Simulation time 41448079 ps
CPU time 0.85 seconds
Started Jul 06 06:40:51 PM PDT 24
Finished Jul 06 06:40:52 PM PDT 24
Peak memory 206676 kb
Host smart-f312316a-b760-4850-9256-3b58b55265a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187847862 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.1187847862
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.3573243838
Short name T563
Test name
Test status
Simulation time 158976839 ps
CPU time 0.82 seconds
Started Jul 06 06:40:54 PM PDT 24
Finished Jul 06 06:40:55 PM PDT 24
Peak memory 207004 kb
Host smart-f49185dd-c8ad-43c8-8130-ea60c1d113fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573243838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.3573243838
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1478494997
Short name T538
Test name
Test status
Simulation time 596160411 ps
CPU time 3.76 seconds
Started Jul 06 06:40:50 PM PDT 24
Finished Jul 06 06:40:54 PM PDT 24
Peak memory 224472 kb
Host smart-67325acb-5e3c-4f40-9e55-832e2956744f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1478494997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1478494997
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.2583321924
Short name T595
Test name
Test status
Simulation time 14022138 ps
CPU time 0.73 seconds
Started Jul 06 06:41:00 PM PDT 24
Finished Jul 06 06:41:01 PM PDT 24
Peak memory 205512 kb
Host smart-54d8618e-b657-4054-8ddd-46a8aeba760e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583321924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.
2583321924
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.967155117
Short name T706
Test name
Test status
Simulation time 414163628 ps
CPU time 2.82 seconds
Started Jul 06 06:40:53 PM PDT 24
Finished Jul 06 06:40:56 PM PDT 24
Peak memory 232656 kb
Host smart-44f002d7-9d83-4017-936b-670f5c2915e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967155117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.967155117
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.1696306249
Short name T874
Test name
Test status
Simulation time 18380839 ps
CPU time 0.77 seconds
Started Jul 06 06:40:54 PM PDT 24
Finished Jul 06 06:40:55 PM PDT 24
Peak memory 206932 kb
Host smart-65b30b29-af23-4b97-ac8e-97216111bee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696306249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.1696306249
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.193494723
Short name T218
Test name
Test status
Simulation time 9312246940 ps
CPU time 86.95 seconds
Started Jul 06 06:40:58 PM PDT 24
Finished Jul 06 06:42:25 PM PDT 24
Peak memory 236528 kb
Host smart-9171eef6-be3b-4933-ac08-e76c4741122d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193494723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.193494723
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.1457381308
Short name T873
Test name
Test status
Simulation time 26621578052 ps
CPU time 49.31 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:41:52 PM PDT 24
Peak memory 248568 kb
Host smart-003279c7-fdeb-4a7c-9b70-58048d3f9714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457381308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.1457381308
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.4051302483
Short name T152
Test name
Test status
Simulation time 8761685437 ps
CPU time 143.45 seconds
Started Jul 06 06:40:58 PM PDT 24
Finished Jul 06 06:43:22 PM PDT 24
Peak memory 273168 kb
Host smart-011210ab-4879-49d7-a8b7-31be73b1f031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051302483 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idl
e.4051302483
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.3223505818
Short name T954
Test name
Test status
Simulation time 134326823 ps
CPU time 4.07 seconds
Started Jul 06 06:40:57 PM PDT 24
Finished Jul 06 06:41:01 PM PDT 24
Peak memory 232612 kb
Host smart-fea65108-2170-4846-9173-3f4de7be1159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223505818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.3223505818
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_intercept.2196220712
Short name T297
Test name
Test status
Simulation time 11032076707 ps
CPU time 13.49 seconds
Started Jul 06 06:40:53 PM PDT 24
Finished Jul 06 06:41:07 PM PDT 24
Peak memory 232780 kb
Host smart-99ce21c5-548c-42da-8ebc-dce92ed62e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196220712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.2196220712
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1908917099
Short name T419
Test name
Test status
Simulation time 6469232132 ps
CPU time 50.79 seconds
Started Jul 06 06:40:56 PM PDT 24
Finished Jul 06 06:41:47 PM PDT 24
Peak memory 240984 kb
Host smart-63d32b0a-9c05-40e4-9ce7-cb3092fcb905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908917099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1908917099
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.3023981322
Short name T287
Test name
Test status
Simulation time 1653794542 ps
CPU time 7.02 seconds
Started Jul 06 06:40:52 PM PDT 24
Finished Jul 06 06:41:00 PM PDT 24
Peak memory 240880 kb
Host smart-6f7b48c4-7c46-4664-9a6d-ba2cf148ef68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023981322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.3023981322
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.397075635
Short name T72
Test name
Test status
Simulation time 4941457643 ps
CPU time 8.31 seconds
Started Jul 06 06:40:59 PM PDT 24
Finished Jul 06 06:41:08 PM PDT 24
Peak memory 232768 kb
Host smart-e7855673-aa76-4d5f-96c6-07af78b89c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397075635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.397075635
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.3751356269
Short name T45
Test name
Test status
Simulation time 1462167588 ps
CPU time 7.15 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:41:10 PM PDT 24
Peak memory 220440 kb
Host smart-cc6b1e7e-11d1-4af6-a055-a95364619e59
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3751356269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.3751356269
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.3777304664
Short name T167
Test name
Test status
Simulation time 98545339206 ps
CPU time 211.69 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:44:34 PM PDT 24
Peak memory 264528 kb
Host smart-bc9de5ef-7e02-4c6d-ac6f-68b271e0d945
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777304664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.3777304664
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.3661204134
Short name T102
Test name
Test status
Simulation time 2297872237 ps
CPU time 6.05 seconds
Started Jul 06 06:40:52 PM PDT 24
Finished Jul 06 06:40:59 PM PDT 24
Peak memory 216484 kb
Host smart-63519eea-631d-400d-a92d-a767346ec085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661204134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.3661204134
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.292675438
Short name T404
Test name
Test status
Simulation time 20133814230 ps
CPU time 14.15 seconds
Started Jul 06 06:40:56 PM PDT 24
Finished Jul 06 06:41:10 PM PDT 24
Peak memory 216396 kb
Host smart-4c112487-5c9a-4b63-ab58-3c363d9c5ebc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292675438 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.292675438
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.3038396953
Short name T556
Test name
Test status
Simulation time 37100036 ps
CPU time 0.67 seconds
Started Jul 06 06:40:56 PM PDT 24
Finished Jul 06 06:40:57 PM PDT 24
Peak memory 205676 kb
Host smart-cb89c98c-17e9-403b-987a-c2bfaa8122e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038396953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.3038396953
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.2854908557
Short name T493
Test name
Test status
Simulation time 19247038 ps
CPU time 0.74 seconds
Started Jul 06 06:40:56 PM PDT 24
Finished Jul 06 06:40:57 PM PDT 24
Peak memory 206020 kb
Host smart-bde0f6ef-44be-4c41-8207-34200ec679e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854908557 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.2854908557
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.1735964023
Short name T772
Test name
Test status
Simulation time 28107714869 ps
CPU time 12.64 seconds
Started Jul 06 06:40:55 PM PDT 24
Finished Jul 06 06:41:08 PM PDT 24
Peak memory 240212 kb
Host smart-3543e40f-dde5-475b-a48c-8bd0652008f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735964023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.1735964023
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.309406228
Short name T590
Test name
Test status
Simulation time 19099570 ps
CPU time 0.75 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:41:03 PM PDT 24
Peak memory 204988 kb
Host smart-60ca681d-8644-4072-9ac0-41ce3fa09e50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=309406228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.309406228
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.735513251
Short name T997
Test name
Test status
Simulation time 439414252 ps
CPU time 5.14 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:41:07 PM PDT 24
Peak memory 232696 kb
Host smart-a676a29d-0eb7-4396-bbd1-a4b1955d73c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735513251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.735513251
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.1849548938
Short name T576
Test name
Test status
Simulation time 13799109 ps
CPU time 0.77 seconds
Started Jul 06 06:40:59 PM PDT 24
Finished Jul 06 06:41:01 PM PDT 24
Peak memory 206952 kb
Host smart-dcabb583-0793-466f-8ef6-3e4f375f9067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849548938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.1849548938
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.3764887896
Short name T996
Test name
Test status
Simulation time 193701054893 ps
CPU time 302.24 seconds
Started Jul 06 06:41:03 PM PDT 24
Finished Jul 06 06:46:06 PM PDT 24
Peak memory 249228 kb
Host smart-0741e864-d39d-4d24-afcf-0707cb1d2388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3764887896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.3764887896
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3990251794
Short name T614
Test name
Test status
Simulation time 7864233321 ps
CPU time 122.79 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:43:05 PM PDT 24
Peak memory 273592 kb
Host smart-44bf3509-5ad3-411a-8b06-877a3d9dd35a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990251794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3990251794
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.209368794
Short name T540
Test name
Test status
Simulation time 3536357050 ps
CPU time 24.95 seconds
Started Jul 06 06:41:03 PM PDT 24
Finished Jul 06 06:41:28 PM PDT 24
Peak memory 224676 kb
Host smart-e1a87aba-4e7a-446b-94fb-de3a532f357a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=209368794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idle
.209368794
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.3429842028
Short name T242
Test name
Test status
Simulation time 140149723 ps
CPU time 4.01 seconds
Started Jul 06 06:41:03 PM PDT 24
Finished Jul 06 06:41:08 PM PDT 24
Peak memory 224500 kb
Host smart-55d98a1a-7486-487c-a552-a5ff6564091b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429842028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.3429842028
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.1975744035
Short name T557
Test name
Test status
Simulation time 17666113909 ps
CPU time 101 seconds
Started Jul 06 06:41:04 PM PDT 24
Finished Jul 06 06:42:45 PM PDT 24
Peak memory 235716 kb
Host smart-9e5b30d3-1daf-45c0-9885-507eac835cc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975744035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.1975744035
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.3079272478
Short name T699
Test name
Test status
Simulation time 504105042 ps
CPU time 7.12 seconds
Started Jul 06 06:41:00 PM PDT 24
Finished Jul 06 06:41:07 PM PDT 24
Peak memory 224452 kb
Host smart-92d0515a-e94a-4dd0-be02-e861cb05a2c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3079272478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.3079272478
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.1077437794
Short name T243
Test name
Test status
Simulation time 1580244427 ps
CPU time 24.36 seconds
Started Jul 06 06:41:00 PM PDT 24
Finished Jul 06 06:41:24 PM PDT 24
Peak memory 249068 kb
Host smart-564be924-c83e-428a-883b-93c96abd4f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077437794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.1077437794
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.3594647709
Short name T53
Test name
Test status
Simulation time 6048285636 ps
CPU time 20.71 seconds
Started Jul 06 06:40:58 PM PDT 24
Finished Jul 06 06:41:19 PM PDT 24
Peak memory 240480 kb
Host smart-70189567-fa27-452d-8f93-a2e76fd8cc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594647709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.3594647709
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1355108079
Short name T197
Test name
Test status
Simulation time 1568041770 ps
CPU time 11.35 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:41:13 PM PDT 24
Peak memory 239580 kb
Host smart-fa120a13-73d0-4b35-8a25-2d36976e8161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355108079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1355108079
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3995611709
Short name T495
Test name
Test status
Simulation time 5290114852 ps
CPU time 15.17 seconds
Started Jul 06 06:41:05 PM PDT 24
Finished Jul 06 06:41:20 PM PDT 24
Peak memory 222212 kb
Host smart-9e57dca7-461f-4474-9620-95f85c99c6fa
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3995611709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3995611709
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.3444059263
Short name T921
Test name
Test status
Simulation time 5217302976 ps
CPU time 63.27 seconds
Started Jul 06 06:41:05 PM PDT 24
Finished Jul 06 06:42:09 PM PDT 24
Peak memory 250544 kb
Host smart-8dfa54a1-10d9-43a3-984f-aa313090325a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444059263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.3444059263
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3927068081
Short name T580
Test name
Test status
Simulation time 1836888217 ps
CPU time 10.93 seconds
Started Jul 06 06:40:58 PM PDT 24
Finished Jul 06 06:41:09 PM PDT 24
Peak memory 216208 kb
Host smart-f01f98c0-1d40-4908-b46d-1d8a5667141f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3927068081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3927068081
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.1233002374
Short name T991
Test name
Test status
Simulation time 12782183 ps
CPU time 0.71 seconds
Started Jul 06 06:40:58 PM PDT 24
Finished Jul 06 06:40:59 PM PDT 24
Peak memory 205724 kb
Host smart-05ae3413-5ab5-4337-9d9f-d621d3d9994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233002374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.1233002374
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.2784906350
Short name T867
Test name
Test status
Simulation time 69812367 ps
CPU time 1.56 seconds
Started Jul 06 06:41:00 PM PDT 24
Finished Jul 06 06:41:01 PM PDT 24
Peak memory 216276 kb
Host smart-6f0007c3-7327-41f8-9f34-7089e2fbbb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2784906350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.2784906350
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.1080160083
Short name T795
Test name
Test status
Simulation time 137565286 ps
CPU time 0.86 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:41:03 PM PDT 24
Peak memory 206004 kb
Host smart-f380aa90-af21-4b23-9f89-4ccfa27f33c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080160083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.1080160083
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.320091237
Short name T704
Test name
Test status
Simulation time 1582319315 ps
CPU time 6.93 seconds
Started Jul 06 06:40:57 PM PDT 24
Finished Jul 06 06:41:04 PM PDT 24
Peak memory 224504 kb
Host smart-1c41d6ef-d037-444d-aa75-858059c2daad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320091237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.320091237
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.928097265
Short name T572
Test name
Test status
Simulation time 36279036 ps
CPU time 0.72 seconds
Started Jul 06 06:41:12 PM PDT 24
Finished Jul 06 06:41:13 PM PDT 24
Peak memory 205556 kb
Host smart-b24cf8bf-b147-4a84-a2dc-b49200373941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=928097265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.928097265
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.3895523541
Short name T740
Test name
Test status
Simulation time 2220828583 ps
CPU time 6.7 seconds
Started Jul 06 06:41:08 PM PDT 24
Finished Jul 06 06:41:15 PM PDT 24
Peak memory 232696 kb
Host smart-9497e179-6b0f-4293-afae-7c76a01688a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3895523541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.3895523541
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.3370602285
Short name T353
Test name
Test status
Simulation time 45464661 ps
CPU time 0.78 seconds
Started Jul 06 06:41:03 PM PDT 24
Finished Jul 06 06:41:04 PM PDT 24
Peak memory 206608 kb
Host smart-7eb4e0b2-052c-4633-bd1c-43d7fbab17fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370602285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.3370602285
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.312055010
Short name T280
Test name
Test status
Simulation time 50077482659 ps
CPU time 136.63 seconds
Started Jul 06 06:42:12 PM PDT 24
Finished Jul 06 06:44:29 PM PDT 24
Peak memory 253380 kb
Host smart-685e4610-7fa7-4e5b-8fb0-719cf327a832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312055010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.312055010
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.759906902
Short name T846
Test name
Test status
Simulation time 9329644139 ps
CPU time 39.67 seconds
Started Jul 06 06:41:07 PM PDT 24
Finished Jul 06 06:41:47 PM PDT 24
Peak memory 250580 kb
Host smart-4d35cae7-7157-410c-a354-f809b30910a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759906902 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.759906902
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1804014224
Short name T220
Test name
Test status
Simulation time 174193719614 ps
CPU time 163.2 seconds
Started Jul 06 06:41:12 PM PDT 24
Finished Jul 06 06:43:55 PM PDT 24
Peak memory 253296 kb
Host smart-79860c15-1f74-4447-bc40-a08884be6b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804014224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1804014224
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.2237550463
Short name T301
Test name
Test status
Simulation time 36343787774 ps
CPU time 296.47 seconds
Started Jul 06 06:41:07 PM PDT 24
Finished Jul 06 06:46:03 PM PDT 24
Peak memory 264848 kb
Host smart-99c68f6f-cd06-441b-9096-ab2709dd8277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237550463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.2237550463
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.4276124920
Short name T951
Test name
Test status
Simulation time 2098562021 ps
CPU time 8.71 seconds
Started Jul 06 06:41:07 PM PDT 24
Finished Jul 06 06:41:16 PM PDT 24
Peak memory 232652 kb
Host smart-9e3469db-d5de-4a89-9f3f-f1ccd8bb07a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276124920 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.4276124920
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.3007348110
Short name T875
Test name
Test status
Simulation time 1346957702 ps
CPU time 3.56 seconds
Started Jul 06 06:41:07 PM PDT 24
Finished Jul 06 06:41:11 PM PDT 24
Peak memory 232624 kb
Host smart-3814cba4-adac-4da9-b53e-f53866739600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007348110 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.3007348110
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1433152045
Short name T620
Test name
Test status
Simulation time 426553298 ps
CPU time 5.28 seconds
Started Jul 06 06:41:08 PM PDT 24
Finished Jul 06 06:41:13 PM PDT 24
Peak memory 224424 kb
Host smart-45d7a8ae-0313-45ac-be68-67a3f2e77fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433152045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1433152045
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.12035844
Short name T922
Test name
Test status
Simulation time 10140765459 ps
CPU time 13.9 seconds
Started Jul 06 06:41:07 PM PDT 24
Finished Jul 06 06:41:22 PM PDT 24
Peak memory 224536 kb
Host smart-4a676914-a3ac-41d5-ae61-51ff4fb8efa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12035844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.12035844
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.269248840
Short name T808
Test name
Test status
Simulation time 1025813837 ps
CPU time 4.53 seconds
Started Jul 06 06:41:07 PM PDT 24
Finished Jul 06 06:41:12 PM PDT 24
Peak memory 219416 kb
Host smart-eda1cd16-73ed-4775-8796-995894ae499b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=269248840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dire
ct.269248840
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.1544609424
Short name T388
Test name
Test status
Simulation time 44907803 ps
CPU time 0.92 seconds
Started Jul 06 06:41:12 PM PDT 24
Finished Jul 06 06:41:13 PM PDT 24
Peak memory 206640 kb
Host smart-469a0110-669d-4bd3-9e1a-fd2c02344d7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1544609424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.1544609424
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.80298956
Short name T943
Test name
Test status
Simulation time 733742485 ps
CPU time 4.03 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:41:07 PM PDT 24
Peak memory 218392 kb
Host smart-9798dff5-a968-4be2-8a69-537e8319df6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80298956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.80298956
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1563900210
Short name T737
Test name
Test status
Simulation time 1041729712 ps
CPU time 2.61 seconds
Started Jul 06 06:41:03 PM PDT 24
Finished Jul 06 06:41:06 PM PDT 24
Peak memory 207856 kb
Host smart-9dd03cff-6d87-4b8e-b8c2-ba5637ce0196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563900210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1563900210
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.2987091485
Short name T702
Test name
Test status
Simulation time 131120042 ps
CPU time 1.14 seconds
Started Jul 06 06:41:06 PM PDT 24
Finished Jul 06 06:41:08 PM PDT 24
Peak memory 207908 kb
Host smart-b22de27f-eb37-43d7-b265-f27c10b8e7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987091485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.2987091485
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.286564835
Short name T406
Test name
Test status
Simulation time 17228687 ps
CPU time 0.79 seconds
Started Jul 06 06:41:02 PM PDT 24
Finished Jul 06 06:41:03 PM PDT 24
Peak memory 205980 kb
Host smart-60d88106-730a-4030-b46d-b5f509e5a829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286564835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.286564835
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.1777440612
Short name T910
Test name
Test status
Simulation time 1763445479 ps
CPU time 10.29 seconds
Started Jul 06 06:41:08 PM PDT 24
Finished Jul 06 06:41:19 PM PDT 24
Peak memory 224560 kb
Host smart-df9db9f8-ed9f-4a77-9377-444dadae71c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777440612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.1777440612
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.4008499098
Short name T827
Test name
Test status
Simulation time 172957013 ps
CPU time 0.69 seconds
Started Jul 06 06:39:40 PM PDT 24
Finished Jul 06 06:39:41 PM PDT 24
Peak memory 205772 kb
Host smart-ea278332-5af8-4a8e-abea-309a5d22b955
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008499098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.4
008499098
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.155065500
Short name T746
Test name
Test status
Simulation time 881643432 ps
CPU time 4.89 seconds
Started Jul 06 06:39:41 PM PDT 24
Finished Jul 06 06:39:46 PM PDT 24
Peak memory 232636 kb
Host smart-554bf42f-4433-479f-9d93-2d354eb3bc55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155065500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.155065500
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.279443376
Short name T25
Test name
Test status
Simulation time 39770243 ps
CPU time 0.75 seconds
Started Jul 06 06:39:41 PM PDT 24
Finished Jul 06 06:39:42 PM PDT 24
Peak memory 205600 kb
Host smart-8b52fa8a-33ea-4316-b771-379d04f943bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=279443376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.279443376
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.2816082250
Short name T221
Test name
Test status
Simulation time 42988383041 ps
CPU time 84.18 seconds
Started Jul 06 06:39:41 PM PDT 24
Finished Jul 06 06:41:06 PM PDT 24
Peak memory 249216 kb
Host smart-17797568-ecad-4d8b-accd-6eff6678d994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816082250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.2816082250
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2426055774
Short name T31
Test name
Test status
Simulation time 22042314115 ps
CPU time 88.71 seconds
Started Jul 06 06:39:37 PM PDT 24
Finished Jul 06 06:41:06 PM PDT 24
Peak memory 253488 kb
Host smart-d02f0867-654f-4f14-b7ea-5c85a1df77e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2426055774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2426055774
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2015377325
Short name T952
Test name
Test status
Simulation time 56494574794 ps
CPU time 573.77 seconds
Started Jul 06 06:39:39 PM PDT 24
Finished Jul 06 06:49:14 PM PDT 24
Peak memory 268768 kb
Host smart-f31732b8-26e2-4946-aedb-5fe9dbbc1f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2015377325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2015377325
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.3560791542
Short name T813
Test name
Test status
Simulation time 291649981 ps
CPU time 5.76 seconds
Started Jul 06 06:39:39 PM PDT 24
Finished Jul 06 06:39:46 PM PDT 24
Peak memory 224424 kb
Host smart-c3befa82-3815-4387-bcb6-f4bde107e2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560791542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.3560791542
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.4178998897
Short name T632
Test name
Test status
Simulation time 52089446100 ps
CPU time 43.04 seconds
Started Jul 06 06:39:40 PM PDT 24
Finished Jul 06 06:40:23 PM PDT 24
Peak memory 249212 kb
Host smart-ede51fa1-ce0c-41e0-bb4d-8f4010a8fd2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178998897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.4178998897
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3551542960
Short name T433
Test name
Test status
Simulation time 69483612 ps
CPU time 2.31 seconds
Started Jul 06 06:39:39 PM PDT 24
Finished Jul 06 06:39:42 PM PDT 24
Peak memory 232352 kb
Host smart-0033c826-123d-4559-909a-f1c98cff99ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551542960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3551542960
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.392306650
Short name T378
Test name
Test status
Simulation time 11163190747 ps
CPU time 27.78 seconds
Started Jul 06 06:39:39 PM PDT 24
Finished Jul 06 06:40:07 PM PDT 24
Peak memory 232744 kb
Host smart-87ca6fd1-119d-4e22-b199-ba2718b90a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392306650 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.392306650
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.1092227268
Short name T618
Test name
Test status
Simulation time 4822186039 ps
CPU time 18.6 seconds
Started Jul 06 06:39:39 PM PDT 24
Finished Jul 06 06:39:58 PM PDT 24
Peak memory 232724 kb
Host smart-c4dfd94e-0263-4438-a2da-4be91733383f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092227268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap
.1092227268
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.4098830538
Short name T51
Test name
Test status
Simulation time 10035179335 ps
CPU time 15.42 seconds
Started Jul 06 06:39:41 PM PDT 24
Finished Jul 06 06:39:57 PM PDT 24
Peak memory 235676 kb
Host smart-dfe10730-e1d6-4702-8023-03cc107c99cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098830538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.4098830538
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2485081495
Short name T2
Test name
Test status
Simulation time 491370494 ps
CPU time 3.82 seconds
Started Jul 06 06:39:39 PM PDT 24
Finished Jul 06 06:39:43 PM PDT 24
Peak memory 218900 kb
Host smart-b81e7422-122b-46e3-93fc-19763dc804f9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2485081495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2485081495
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.3315762971
Short name T693
Test name
Test status
Simulation time 42986331424 ps
CPU time 413.64 seconds
Started Jul 06 06:39:42 PM PDT 24
Finished Jul 06 06:46:36 PM PDT 24
Peak memory 268980 kb
Host smart-da558288-fd91-483e-a28f-2cfde417aaac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315762971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.3315762971
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3466876792
Short name T472
Test name
Test status
Simulation time 1929341838 ps
CPU time 4.28 seconds
Started Jul 06 06:39:38 PM PDT 24
Finished Jul 06 06:39:43 PM PDT 24
Peak memory 216440 kb
Host smart-6b2a4c06-f488-48ce-a3c3-b4d4dcaa1fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3466876792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3466876792
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.247344045
Short name T509
Test name
Test status
Simulation time 1084530470 ps
CPU time 7.06 seconds
Started Jul 06 06:39:38 PM PDT 24
Finished Jul 06 06:39:46 PM PDT 24
Peak memory 216240 kb
Host smart-c8a08492-bb8f-4a23-98d5-7f10c7aec467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=247344045 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.247344045
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.3643822378
Short name T771
Test name
Test status
Simulation time 1118626991 ps
CPU time 4.29 seconds
Started Jul 06 06:39:40 PM PDT 24
Finished Jul 06 06:39:45 PM PDT 24
Peak memory 216484 kb
Host smart-9cb28b2e-eab1-4541-8e79-803bc4fbdbb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643822378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.3643822378
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.659369716
Short name T858
Test name
Test status
Simulation time 75635256 ps
CPU time 0.91 seconds
Started Jul 06 06:39:38 PM PDT 24
Finished Jul 06 06:39:39 PM PDT 24
Peak memory 205976 kb
Host smart-3ee7a149-1a15-427d-81c2-ddaa2cb8cfb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659369716 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.659369716
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.1840295023
Short name T989
Test name
Test status
Simulation time 1085185643 ps
CPU time 7.93 seconds
Started Jul 06 06:39:39 PM PDT 24
Finished Jul 06 06:39:47 PM PDT 24
Peak memory 224408 kb
Host smart-ee436ca5-5c4f-4c26-8161-1fb9debd54df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1840295023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.1840295023
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.249087588
Short name T350
Test name
Test status
Simulation time 11929947 ps
CPU time 0.77 seconds
Started Jul 06 06:41:17 PM PDT 24
Finished Jul 06 06:41:18 PM PDT 24
Peak memory 204988 kb
Host smart-9cdc423f-34da-4b61-8d39-9d76fcaeb3fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=249087588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.249087588
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.66480608
Short name T960
Test name
Test status
Simulation time 263507640 ps
CPU time 4.59 seconds
Started Jul 06 06:41:11 PM PDT 24
Finished Jul 06 06:41:16 PM PDT 24
Peak memory 224468 kb
Host smart-90b85a12-0c4c-41a8-8948-d6733c00b7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=66480608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.66480608
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.1618844581
Short name T705
Test name
Test status
Simulation time 13435230 ps
CPU time 0.76 seconds
Started Jul 06 06:41:11 PM PDT 24
Finished Jul 06 06:41:12 PM PDT 24
Peak memory 206620 kb
Host smart-c44f15f2-5d6c-4077-bd6d-9df44008963a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1618844581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.1618844581
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.407291931
Short name T784
Test name
Test status
Simulation time 1747844286 ps
CPU time 16 seconds
Started Jul 06 06:41:17 PM PDT 24
Finished Jul 06 06:41:33 PM PDT 24
Peak memory 232664 kb
Host smart-e92f0134-4ad5-441e-be6e-21c602800fd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407291931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.407291931
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.2866357940
Short name T223
Test name
Test status
Simulation time 179185575281 ps
CPU time 335.42 seconds
Started Jul 06 06:41:16 PM PDT 24
Finished Jul 06 06:46:51 PM PDT 24
Peak memory 269076 kb
Host smart-2d46493a-b8b0-4a89-a523-e9fcc4985cac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2866357940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.2866357940
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.979331286
Short name T807
Test name
Test status
Simulation time 1767793424 ps
CPU time 8.3 seconds
Started Jul 06 06:41:23 PM PDT 24
Finished Jul 06 06:41:31 PM PDT 24
Peak memory 217708 kb
Host smart-745eec60-a83e-4055-9657-1c4d774b5f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979331286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idle
.979331286
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3882286711
Short name T331
Test name
Test status
Simulation time 4547516288 ps
CPU time 59.54 seconds
Started Jul 06 06:41:15 PM PDT 24
Finished Jul 06 06:42:15 PM PDT 24
Peak memory 232796 kb
Host smart-8b2d0774-e8ba-48e5-8d4a-020397183c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3882286711 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3882286711
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.1475176874
Short name T831
Test name
Test status
Simulation time 10539143544 ps
CPU time 53.37 seconds
Started Jul 06 06:41:16 PM PDT 24
Finished Jul 06 06:42:10 PM PDT 24
Peak memory 265372 kb
Host smart-40f5ed17-d389-4ada-873b-fb40504c01da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475176874 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.1475176874
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.2244658238
Short name T948
Test name
Test status
Simulation time 5558289061 ps
CPU time 18.98 seconds
Started Jul 06 06:41:10 PM PDT 24
Finished Jul 06 06:41:30 PM PDT 24
Peak memory 224576 kb
Host smart-8adb860f-64dd-4025-a300-2634b93c9627
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244658238 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.2244658238
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.2221742749
Short name T266
Test name
Test status
Simulation time 32918981171 ps
CPU time 54.19 seconds
Started Jul 06 06:41:13 PM PDT 24
Finished Jul 06 06:42:07 PM PDT 24
Peak memory 224592 kb
Host smart-05b0f582-1346-442b-84d5-247a0be7df36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221742749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.2221742749
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.963722300
Short name T650
Test name
Test status
Simulation time 1039302136 ps
CPU time 3.28 seconds
Started Jul 06 06:41:12 PM PDT 24
Finished Jul 06 06:41:15 PM PDT 24
Peak memory 224484 kb
Host smart-425744f1-1cdf-4835-98f7-12f17ef6a221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963722300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swap
.963722300
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2539418675
Short name T41
Test name
Test status
Simulation time 275575634 ps
CPU time 5.05 seconds
Started Jul 06 06:41:10 PM PDT 24
Finished Jul 06 06:41:15 PM PDT 24
Peak memory 224460 kb
Host smart-dae13973-9021-4b0d-ba95-ee102d395657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539418675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2539418675
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.174884778
Short name T105
Test name
Test status
Simulation time 3044597285 ps
CPU time 8.42 seconds
Started Jul 06 06:41:17 PM PDT 24
Finished Jul 06 06:41:26 PM PDT 24
Peak memory 219064 kb
Host smart-36e64c02-677f-46bb-9a2e-875b4ec36307
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=174884778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.174884778
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3442097629
Short name T848
Test name
Test status
Simulation time 14206988 ps
CPU time 0.72 seconds
Started Jul 06 06:41:13 PM PDT 24
Finished Jul 06 06:41:14 PM PDT 24
Peak memory 205748 kb
Host smart-fe53eae3-30e6-4e66-ac14-a50a5a9e0ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442097629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3442097629
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.761321161
Short name T520
Test name
Test status
Simulation time 10153145188 ps
CPU time 14.16 seconds
Started Jul 06 06:41:12 PM PDT 24
Finished Jul 06 06:41:26 PM PDT 24
Peak memory 216396 kb
Host smart-6b375faa-8f26-4b0e-81fe-0422b17a007a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761321161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.761321161
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1449919991
Short name T762
Test name
Test status
Simulation time 13687123 ps
CPU time 0.7 seconds
Started Jul 06 06:41:12 PM PDT 24
Finished Jul 06 06:41:13 PM PDT 24
Peak memory 205636 kb
Host smart-31301103-b68b-4183-a5ca-d0abd15ecebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449919991 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1449919991
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.2967833252
Short name T646
Test name
Test status
Simulation time 10907699 ps
CPU time 0.68 seconds
Started Jul 06 06:41:13 PM PDT 24
Finished Jul 06 06:41:14 PM PDT 24
Peak memory 205660 kb
Host smart-5d37d40e-2efc-4219-89dd-4ca0094a1cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967833252 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.2967833252
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.2840933724
Short name T498
Test name
Test status
Simulation time 185799127393 ps
CPU time 36.5 seconds
Started Jul 06 06:41:11 PM PDT 24
Finished Jul 06 06:41:48 PM PDT 24
Peak memory 236664 kb
Host smart-b9f91425-2936-4d51-9292-c958c21a8ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840933724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.2840933724
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.2770914835
Short name T982
Test name
Test status
Simulation time 38365500 ps
CPU time 0.7 seconds
Started Jul 06 06:41:20 PM PDT 24
Finished Jul 06 06:41:21 PM PDT 24
Peak memory 205832 kb
Host smart-2388c175-45c2-475e-9445-10e6ac856f47
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770914835 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.
2770914835
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.415228155
Short name T74
Test name
Test status
Simulation time 407928153 ps
CPU time 3.67 seconds
Started Jul 06 06:41:17 PM PDT 24
Finished Jul 06 06:41:21 PM PDT 24
Peak memory 224484 kb
Host smart-991bf19d-97b9-4c1f-a750-b75ff7e68edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415228155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.415228155
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.4043338054
Short name T677
Test name
Test status
Simulation time 21225926 ps
CPU time 0.75 seconds
Started Jul 06 06:41:17 PM PDT 24
Finished Jul 06 06:41:18 PM PDT 24
Peak memory 205872 kb
Host smart-0215bd4b-96d3-4699-89de-099cf62b7a59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4043338054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.4043338054
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.1269976859
Short name T630
Test name
Test status
Simulation time 70929626 ps
CPU time 0.77 seconds
Started Jul 06 06:41:19 PM PDT 24
Finished Jul 06 06:41:20 PM PDT 24
Peak memory 215792 kb
Host smart-bd343b4f-2cf9-4291-90d4-e412a278ad99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269976859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.1269976859
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3813895451
Short name T782
Test name
Test status
Simulation time 2702021503 ps
CPU time 29.76 seconds
Started Jul 06 06:41:21 PM PDT 24
Finished Jul 06 06:41:51 PM PDT 24
Peak memory 224712 kb
Host smart-35d08895-ec01-4227-a404-6bdc38590963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813895451 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3813895451
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.220466322
Short name T38
Test name
Test status
Simulation time 54857260673 ps
CPU time 525.63 seconds
Started Jul 06 06:41:26 PM PDT 24
Finished Jul 06 06:50:12 PM PDT 24
Peak memory 264156 kb
Host smart-a8f75473-13c1-4a1f-bd5c-46e7ea6802ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=220466322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idle
.220466322
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.1055787019
Short name T567
Test name
Test status
Simulation time 83007321 ps
CPU time 3.64 seconds
Started Jul 06 06:41:21 PM PDT 24
Finished Jul 06 06:41:25 PM PDT 24
Peak memory 232720 kb
Host smart-25bbab70-0777-41e1-847e-720dcde1206c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055787019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.1055787019
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.781052543
Short name T828
Test name
Test status
Simulation time 40382783500 ps
CPU time 265.7 seconds
Started Jul 06 06:41:19 PM PDT 24
Finished Jul 06 06:45:45 PM PDT 24
Peak memory 265604 kb
Host smart-bfc4936a-e25d-44a1-b42d-f1ebc6756e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781052543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmds
.781052543
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.3972342509
Short name T688
Test name
Test status
Simulation time 930080149 ps
CPU time 8 seconds
Started Jul 06 06:41:15 PM PDT 24
Finished Jul 06 06:41:24 PM PDT 24
Peak memory 224472 kb
Host smart-649c1a01-b303-4264-bb90-1a55ee0f6693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972342509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.3972342509
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.1579399275
Short name T975
Test name
Test status
Simulation time 2206435615 ps
CPU time 13.2 seconds
Started Jul 06 06:41:15 PM PDT 24
Finished Jul 06 06:41:29 PM PDT 24
Peak memory 238964 kb
Host smart-11d7189e-d13b-4e65-a54f-35305c76b72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579399275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.1579399275
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2517200896
Short name T596
Test name
Test status
Simulation time 968346762 ps
CPU time 6.62 seconds
Started Jul 06 06:41:16 PM PDT 24
Finished Jul 06 06:41:23 PM PDT 24
Peak memory 224444 kb
Host smart-99a53e7a-0aa6-44cc-940e-2ceb0590daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517200896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2517200896
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.2635040701
Short name T588
Test name
Test status
Simulation time 1985575290 ps
CPU time 12.93 seconds
Started Jul 06 06:41:16 PM PDT 24
Finished Jul 06 06:41:30 PM PDT 24
Peak memory 232652 kb
Host smart-e89e3ef3-5585-49d3-9f70-5b2536f63df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2635040701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.2635040701
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.4292486919
Short name T560
Test name
Test status
Simulation time 766331210 ps
CPU time 7.19 seconds
Started Jul 06 06:41:19 PM PDT 24
Finished Jul 06 06:41:26 PM PDT 24
Peak memory 220212 kb
Host smart-cb4ce4a0-5dc0-4747-82ff-59214441b162
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4292486919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dir
ect.4292486919
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2741317467
Short name T343
Test name
Test status
Simulation time 510470798 ps
CPU time 5.8 seconds
Started Jul 06 06:41:21 PM PDT 24
Finished Jul 06 06:41:27 PM PDT 24
Peak memory 216376 kb
Host smart-af89eb87-0499-478f-a310-6894b92eb706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741317467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2741317467
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2856215440
Short name T421
Test name
Test status
Simulation time 2034675877 ps
CPU time 4.55 seconds
Started Jul 06 06:41:14 PM PDT 24
Finished Jul 06 06:41:18 PM PDT 24
Peak memory 216168 kb
Host smart-10dacd4f-af6b-45db-ac74-f321809bdbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856215440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2856215440
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.2895790909
Short name T1006
Test name
Test status
Simulation time 552883888 ps
CPU time 8.62 seconds
Started Jul 06 06:41:18 PM PDT 24
Finished Jul 06 06:41:27 PM PDT 24
Peak memory 216232 kb
Host smart-76a960d4-854e-4e73-920b-835412275bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895790909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.2895790909
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.506899231
Short name T73
Test name
Test status
Simulation time 117405430 ps
CPU time 1.05 seconds
Started Jul 06 06:41:22 PM PDT 24
Finished Jul 06 06:41:24 PM PDT 24
Peak memory 207032 kb
Host smart-a223a9cd-5ce2-44c6-b778-768beba4191e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506899231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.506899231
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.2168476477
Short name T396
Test name
Test status
Simulation time 3295923908 ps
CPU time 6.47 seconds
Started Jul 06 06:41:16 PM PDT 24
Finished Jul 06 06:41:23 PM PDT 24
Peak memory 236144 kb
Host smart-36aeb306-ef94-4f80-8db7-9e8fe90e5599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168476477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.2168476477
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.1465665482
Short name T726
Test name
Test status
Simulation time 16351052 ps
CPU time 0.72 seconds
Started Jul 06 06:41:24 PM PDT 24
Finished Jul 06 06:41:25 PM PDT 24
Peak memory 205532 kb
Host smart-d0a0834f-b7b6-4939-af4b-cb14c4c571fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1465665482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
1465665482
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.2612813926
Short name T50
Test name
Test status
Simulation time 1340323331 ps
CPU time 4.13 seconds
Started Jul 06 06:41:21 PM PDT 24
Finished Jul 06 06:41:25 PM PDT 24
Peak memory 224408 kb
Host smart-4e9fdb08-9512-49d7-bc99-1d9177aa20d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612813926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.2612813926
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.2699697773
Short name T542
Test name
Test status
Simulation time 59694973 ps
CPU time 0.77 seconds
Started Jul 06 06:41:21 PM PDT 24
Finished Jul 06 06:41:22 PM PDT 24
Peak memory 206560 kb
Host smart-3ded591a-ccb1-40f3-8353-efb99509f278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2699697773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.2699697773
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.4080618395
Short name T98
Test name
Test status
Simulation time 32361828280 ps
CPU time 39.82 seconds
Started Jul 06 06:41:24 PM PDT 24
Finished Jul 06 06:42:04 PM PDT 24
Peak memory 254888 kb
Host smart-08cfca78-28eb-484c-b20f-54ce0c886c14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080618395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.4080618395
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2727407118
Short name T302
Test name
Test status
Simulation time 42279369066 ps
CPU time 139.49 seconds
Started Jul 06 06:41:25 PM PDT 24
Finished Jul 06 06:43:45 PM PDT 24
Peak memory 256888 kb
Host smart-bd49aef6-e7b8-4619-9acc-a6a0a8c880e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727407118 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2727407118
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.2978351901
Short name T62
Test name
Test status
Simulation time 136062591182 ps
CPU time 213.65 seconds
Started Jul 06 06:41:24 PM PDT 24
Finished Jul 06 06:44:58 PM PDT 24
Peak memory 249296 kb
Host smart-37793c56-45ed-42d4-80c5-48ed945901e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978351901 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.2978351901
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1917539105
Short name T333
Test name
Test status
Simulation time 6327279236 ps
CPU time 69.28 seconds
Started Jul 06 06:41:23 PM PDT 24
Finished Jul 06 06:42:33 PM PDT 24
Peak memory 240636 kb
Host smart-92dc4a17-ee97-49fe-bfc1-50f823c1d819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917539105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1917539105
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.932072863
Short name T942
Test name
Test status
Simulation time 87442691302 ps
CPU time 334.92 seconds
Started Jul 06 06:41:25 PM PDT 24
Finished Jul 06 06:47:01 PM PDT 24
Peak memory 266100 kb
Host smart-68d0d2dd-3393-4932-a648-90a9da4edcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932072863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmds
.932072863
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2237185412
Short name T554
Test name
Test status
Simulation time 518450670 ps
CPU time 5.8 seconds
Started Jul 06 06:41:19 PM PDT 24
Finished Jul 06 06:41:25 PM PDT 24
Peak memory 224420 kb
Host smart-10eb953c-42e6-4bc9-a218-f185d3649559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237185412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2237185412
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.43088551
Short name T480
Test name
Test status
Simulation time 776894238 ps
CPU time 9.66 seconds
Started Jul 06 06:41:26 PM PDT 24
Finished Jul 06 06:41:36 PM PDT 24
Peak memory 232700 kb
Host smart-ed9d34c8-ead1-4f17-b4a2-2d61a7587934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=43088551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.43088551
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.2780862542
Short name T224
Test name
Test status
Simulation time 310055938 ps
CPU time 3.38 seconds
Started Jul 06 06:41:20 PM PDT 24
Finished Jul 06 06:41:24 PM PDT 24
Peak memory 224476 kb
Host smart-aa3771e9-8bc9-4b13-b99d-1db5282a8dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780862542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.2780862542
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.61989540
Short name T444
Test name
Test status
Simulation time 890205936 ps
CPU time 4.58 seconds
Started Jul 06 06:41:21 PM PDT 24
Finished Jul 06 06:41:26 PM PDT 24
Peak memory 232704 kb
Host smart-1d487d60-2d10-417b-9db8-4e2b1a136590
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=61989540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.61989540
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.4208725668
Short name T841
Test name
Test status
Simulation time 1985214926 ps
CPU time 7.89 seconds
Started Jul 06 06:41:26 PM PDT 24
Finished Jul 06 06:41:34 PM PDT 24
Peak memory 220548 kb
Host smart-810525cb-c5ee-4344-878c-a7fed656296a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4208725668 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dir
ect.4208725668
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.2805998279
Short name T811
Test name
Test status
Simulation time 50124216 ps
CPU time 0.95 seconds
Started Jul 06 06:41:26 PM PDT 24
Finished Jul 06 06:41:27 PM PDT 24
Peak memory 207728 kb
Host smart-7020c344-fbdc-48a6-9991-a419a20e1197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805998279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.2805998279
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.3587264511
Short name T979
Test name
Test status
Simulation time 7289793821 ps
CPU time 18.98 seconds
Started Jul 06 06:41:20 PM PDT 24
Finished Jul 06 06:41:39 PM PDT 24
Peak memory 216392 kb
Host smart-22140b3a-5152-40d6-980c-7efa15cc7069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587264511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.3587264511
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.1795550624
Short name T143
Test name
Test status
Simulation time 3497235616 ps
CPU time 11.49 seconds
Started Jul 06 06:41:20 PM PDT 24
Finished Jul 06 06:41:32 PM PDT 24
Peak memory 216300 kb
Host smart-e0e6ce8c-8741-4c7f-86c9-5c8fcd67b484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795550624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.1795550624
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.1296344419
Short name T655
Test name
Test status
Simulation time 443998583 ps
CPU time 2.81 seconds
Started Jul 06 06:41:19 PM PDT 24
Finished Jul 06 06:41:22 PM PDT 24
Peak memory 216252 kb
Host smart-599d18a8-f5bc-4c50-8b4f-a63094b73e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296344419 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.1296344419
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.325001613
Short name T517
Test name
Test status
Simulation time 75977631 ps
CPU time 0.9 seconds
Started Jul 06 06:41:21 PM PDT 24
Finished Jul 06 06:41:22 PM PDT 24
Peak memory 206008 kb
Host smart-daa58d6e-47b9-4696-8194-dae75e138a73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325001613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.325001613
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.275933565
Short name T681
Test name
Test status
Simulation time 6257280775 ps
CPU time 23.26 seconds
Started Jul 06 06:41:20 PM PDT 24
Finished Jul 06 06:41:43 PM PDT 24
Peak memory 235072 kb
Host smart-1f382cbe-0184-4dcb-8bd7-43de37d50775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275933565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.275933565
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.1545905126
Short name T988
Test name
Test status
Simulation time 24838678 ps
CPU time 0.74 seconds
Started Jul 06 06:41:28 PM PDT 24
Finished Jul 06 06:41:29 PM PDT 24
Peak memory 205528 kb
Host smart-ef06a102-b8ad-48be-8d92-ef35777d3e23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545905126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
1545905126
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.3855685048
Short name T732
Test name
Test status
Simulation time 911728422 ps
CPU time 4.15 seconds
Started Jul 06 06:41:24 PM PDT 24
Finished Jul 06 06:41:28 PM PDT 24
Peak memory 224488 kb
Host smart-c7c98e75-70c9-4a2c-b618-244615daecde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855685048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.3855685048
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.404661472
Short name T423
Test name
Test status
Simulation time 21078409 ps
CPU time 0.78 seconds
Started Jul 06 06:41:24 PM PDT 24
Finished Jul 06 06:41:25 PM PDT 24
Peak memory 206948 kb
Host smart-55c2bc3b-e43b-48dc-babb-462cf57a49f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404661472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.404661472
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.240720757
Short name T96
Test name
Test status
Simulation time 3625018746 ps
CPU time 34.65 seconds
Started Jul 06 06:41:29 PM PDT 24
Finished Jul 06 06:42:04 PM PDT 24
Peak memory 237480 kb
Host smart-a99de218-a29c-43b2-98d9-9bfdc53edf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240720757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.240720757
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.3581170131
Short name T723
Test name
Test status
Simulation time 21234114400 ps
CPU time 67.05 seconds
Started Jul 06 06:41:28 PM PDT 24
Finished Jul 06 06:42:35 PM PDT 24
Peak memory 231520 kb
Host smart-e282003d-7615-4c04-b2cb-4c499922dd25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3581170131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.3581170131
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.2449498075
Short name T317
Test name
Test status
Simulation time 22309382930 ps
CPU time 124.44 seconds
Started Jul 06 06:41:30 PM PDT 24
Finished Jul 06 06:43:35 PM PDT 24
Peak memory 265568 kb
Host smart-24b0c1eb-e622-4212-aed5-2b8361c05cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449498075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idl
e.2449498075
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.1867526967
Short name T589
Test name
Test status
Simulation time 2159674257 ps
CPU time 33.29 seconds
Started Jul 06 06:41:24 PM PDT 24
Finished Jul 06 06:41:57 PM PDT 24
Peak memory 236972 kb
Host smart-f6fdeef0-5598-4849-bd19-6da7f9788ef4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867526967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.1867526967
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2859549660
Short name T103
Test name
Test status
Simulation time 7317652650 ps
CPU time 79.42 seconds
Started Jul 06 06:41:29 PM PDT 24
Finished Jul 06 06:42:48 PM PDT 24
Peak memory 257436 kb
Host smart-9aaa2e94-1d04-4224-bc77-143de04f6eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859549660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2859549660
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/23.spi_device_intercept.4135687918
Short name T216
Test name
Test status
Simulation time 1347363296 ps
CPU time 3.59 seconds
Started Jul 06 06:41:25 PM PDT 24
Finished Jul 06 06:41:29 PM PDT 24
Peak memory 232644 kb
Host smart-a6f5ce2b-6845-4056-9ad7-9b32323de34d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135687918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.4135687918
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.3717818233
Short name T876
Test name
Test status
Simulation time 5482835517 ps
CPU time 19.2 seconds
Started Jul 06 06:41:24 PM PDT 24
Finished Jul 06 06:41:43 PM PDT 24
Peak memory 240672 kb
Host smart-44a4ad50-0504-4ea5-b91b-22b094cc696c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717818233 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.3717818233
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2509349202
Short name T719
Test name
Test status
Simulation time 12770053318 ps
CPU time 19.59 seconds
Started Jul 06 06:41:24 PM PDT 24
Finished Jul 06 06:41:44 PM PDT 24
Peak memory 239532 kb
Host smart-1bb19c43-d593-4e79-a02b-34cdb2193fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509349202 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2509349202
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.286257588
Short name T674
Test name
Test status
Simulation time 1213753916 ps
CPU time 6.84 seconds
Started Jul 06 06:41:26 PM PDT 24
Finished Jul 06 06:41:33 PM PDT 24
Peak memory 232664 kb
Host smart-5a538957-6c64-4c3b-90fa-88c0a5161c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286257588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.286257588
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.3484862826
Short name T373
Test name
Test status
Simulation time 2783384382 ps
CPU time 8.63 seconds
Started Jul 06 06:41:33 PM PDT 24
Finished Jul 06 06:41:42 PM PDT 24
Peak memory 223176 kb
Host smart-2a0c2833-5269-4299-bc25-30e3fc40f041
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3484862826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.3484862826
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2349828945
Short name T172
Test name
Test status
Simulation time 25432198097 ps
CPU time 301.58 seconds
Started Jul 06 06:41:28 PM PDT 24
Finished Jul 06 06:46:30 PM PDT 24
Peak memory 266664 kb
Host smart-e482eaf3-28d7-45c9-94bd-0108b62cb3e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2349828945 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2349828945
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.1766147547
Short name T945
Test name
Test status
Simulation time 19018448488 ps
CPU time 32 seconds
Started Jul 06 06:41:26 PM PDT 24
Finished Jul 06 06:41:58 PM PDT 24
Peak memory 216432 kb
Host smart-e42aae4a-1324-4672-b5eb-c7835a4adb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766147547 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.1766147547
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.2918694637
Short name T615
Test name
Test status
Simulation time 10826909678 ps
CPU time 7.42 seconds
Started Jul 06 06:41:26 PM PDT 24
Finished Jul 06 06:41:33 PM PDT 24
Peak memory 216332 kb
Host smart-c0c7697e-6caa-4f65-8dcc-4e5f4b6caadc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918694637 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.2918694637
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.3827073804
Short name T773
Test name
Test status
Simulation time 563163144 ps
CPU time 10.52 seconds
Started Jul 06 06:41:24 PM PDT 24
Finished Jul 06 06:41:35 PM PDT 24
Peak memory 216204 kb
Host smart-162692ea-c8f5-4b08-8b05-52219c17d419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827073804 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.3827073804
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.3728486877
Short name T712
Test name
Test status
Simulation time 26639073 ps
CPU time 0.67 seconds
Started Jul 06 06:41:25 PM PDT 24
Finished Jul 06 06:41:26 PM PDT 24
Peak memory 205680 kb
Host smart-aad24b37-9dee-4281-9bc6-fc740d0a85eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728486877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.3728486877
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.1253225832
Short name T842
Test name
Test status
Simulation time 1911230449 ps
CPU time 7.07 seconds
Started Jul 06 06:41:26 PM PDT 24
Finished Jul 06 06:41:34 PM PDT 24
Peak memory 240904 kb
Host smart-b1473564-b580-4100-a54b-8b99836c46f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253225832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.1253225832
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.497489959
Short name T619
Test name
Test status
Simulation time 37114755 ps
CPU time 0.71 seconds
Started Jul 06 06:41:39 PM PDT 24
Finished Jul 06 06:41:39 PM PDT 24
Peak memory 205572 kb
Host smart-700f62e3-d054-4159-a5e3-659c3c2267ab
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497489959 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.497489959
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2282774671
Short name T476
Test name
Test status
Simulation time 392283535 ps
CPU time 3.34 seconds
Started Jul 06 06:41:31 PM PDT 24
Finished Jul 06 06:41:35 PM PDT 24
Peak memory 224468 kb
Host smart-ca5f5fd3-e337-47b0-a712-5a89a83f86d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282774671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2282774671
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.3840521370
Short name T363
Test name
Test status
Simulation time 27712113 ps
CPU time 0.78 seconds
Started Jul 06 06:41:30 PM PDT 24
Finished Jul 06 06:41:31 PM PDT 24
Peak memory 206584 kb
Host smart-fe7cce53-f063-418f-b461-4884f6b26e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840521370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.3840521370
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.2439191558
Short name T929
Test name
Test status
Simulation time 13754028168 ps
CPU time 112.29 seconds
Started Jul 06 06:41:33 PM PDT 24
Finished Jul 06 06:43:26 PM PDT 24
Peak memory 249264 kb
Host smart-65387cf1-e1a0-4192-b0d9-513552aca80c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439191558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.2439191558
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.4055184478
Short name T793
Test name
Test status
Simulation time 36855756957 ps
CPU time 266.28 seconds
Started Jul 06 06:41:32 PM PDT 24
Finished Jul 06 06:45:58 PM PDT 24
Peak memory 257496 kb
Host smart-e0b90504-c8bc-4ce6-824c-2b9a1b0feeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055184478 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idl
e.4055184478
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.1815243846
Short name T751
Test name
Test status
Simulation time 151845690 ps
CPU time 5.73 seconds
Started Jul 06 06:41:32 PM PDT 24
Finished Jul 06 06:41:38 PM PDT 24
Peak memory 249072 kb
Host smart-9d205502-14ab-4c21-8af4-40b408376a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815243846 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.1815243846
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.244127638
Short name T562
Test name
Test status
Simulation time 37972548184 ps
CPU time 154.58 seconds
Started Jul 06 06:41:32 PM PDT 24
Finished Jul 06 06:44:06 PM PDT 24
Peak memory 250176 kb
Host smart-7c3661d9-be39-4f47-81c1-8340917f918a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244127638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmds
.244127638
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.3504966918
Short name T824
Test name
Test status
Simulation time 733996055 ps
CPU time 5.92 seconds
Started Jul 06 06:41:29 PM PDT 24
Finished Jul 06 06:41:35 PM PDT 24
Peak memory 224492 kb
Host smart-6f87ed81-8b93-47d4-b3dd-f33bda8a660d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504966918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.3504966918
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.4138411642
Short name T114
Test name
Test status
Simulation time 94584422 ps
CPU time 2.12 seconds
Started Jul 06 06:41:32 PM PDT 24
Finished Jul 06 06:41:35 PM PDT 24
Peak memory 222948 kb
Host smart-ca5847a9-0340-47b0-a5f8-ab863a16c3cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138411642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.4138411642
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.3370956427
Short name T621
Test name
Test status
Simulation time 5321285225 ps
CPU time 6 seconds
Started Jul 06 06:41:33 PM PDT 24
Finished Jul 06 06:41:40 PM PDT 24
Peak memory 224584 kb
Host smart-bc2fd234-129b-495b-967c-1f5f902fb448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370956427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.3370956427
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.2012712469
Short name T518
Test name
Test status
Simulation time 703206856 ps
CPU time 2.17 seconds
Started Jul 06 06:41:30 PM PDT 24
Finished Jul 06 06:41:32 PM PDT 24
Peak memory 224080 kb
Host smart-3ca2adbc-bc4e-4b20-b269-1bc3e3e46a02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012712469 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.2012712469
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.1540543240
Short name T607
Test name
Test status
Simulation time 1938161803 ps
CPU time 20.23 seconds
Started Jul 06 06:41:32 PM PDT 24
Finished Jul 06 06:41:53 PM PDT 24
Peak memory 222636 kb
Host smart-7696d44c-a380-4de3-9ea2-b8fbc387d034
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1540543240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.1540543240
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.3483851710
Short name T24
Test name
Test status
Simulation time 3159031416 ps
CPU time 31.5 seconds
Started Jul 06 06:41:33 PM PDT 24
Finished Jul 06 06:42:05 PM PDT 24
Peak memory 241104 kb
Host smart-e7f9958c-c5d3-4261-9325-b489f21fa0c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483851710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.3483851710
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.3725955031
Short name T585
Test name
Test status
Simulation time 801382918 ps
CPU time 12.63 seconds
Started Jul 06 06:41:27 PM PDT 24
Finished Jul 06 06:41:40 PM PDT 24
Peak memory 216308 kb
Host smart-1a85174f-6e51-4110-a8ac-4aa19eb44534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725955031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.3725955031
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.1154106134
Short name T461
Test name
Test status
Simulation time 53796283286 ps
CPU time 18.93 seconds
Started Jul 06 06:41:30 PM PDT 24
Finished Jul 06 06:41:49 PM PDT 24
Peak memory 216400 kb
Host smart-06629270-8984-4d19-8bd7-fcf45ad94efe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154106134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.1154106134
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.3203927730
Short name T346
Test name
Test status
Simulation time 26402942 ps
CPU time 1 seconds
Started Jul 06 06:41:31 PM PDT 24
Finished Jul 06 06:41:32 PM PDT 24
Peak memory 207136 kb
Host smart-20f39d49-4f9f-449e-ad16-632b6a61610d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203927730 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.3203927730
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3743036616
Short name T401
Test name
Test status
Simulation time 221241792 ps
CPU time 1.02 seconds
Started Jul 06 06:41:33 PM PDT 24
Finished Jul 06 06:41:34 PM PDT 24
Peak memory 205952 kb
Host smart-1c8ec9c6-dfd6-4b6c-8247-622a96012f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3743036616 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3743036616
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.1294877722
Short name T711
Test name
Test status
Simulation time 43853684156 ps
CPU time 34.82 seconds
Started Jul 06 06:41:37 PM PDT 24
Finished Jul 06 06:42:12 PM PDT 24
Peak memory 232736 kb
Host smart-622f1ee1-7188-4c34-b169-0a3a14e68f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294877722 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.1294877722
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.102991965
Short name T955
Test name
Test status
Simulation time 15068193 ps
CPU time 0.7 seconds
Started Jul 06 06:41:37 PM PDT 24
Finished Jul 06 06:41:38 PM PDT 24
Peak memory 205000 kb
Host smart-321fb6cf-ea96-4489-92ef-a5b5f13ab9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102991965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.102991965
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.3276176734
Short name T418
Test name
Test status
Simulation time 2248556139 ps
CPU time 4.92 seconds
Started Jul 06 06:41:39 PM PDT 24
Finished Jul 06 06:41:44 PM PDT 24
Peak memory 224512 kb
Host smart-625ee54f-1276-4195-86be-ad416ca0742e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3276176734 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.3276176734
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.4093219302
Short name T390
Test name
Test status
Simulation time 15618794 ps
CPU time 0.79 seconds
Started Jul 06 06:41:33 PM PDT 24
Finished Jul 06 06:41:34 PM PDT 24
Peak memory 206628 kb
Host smart-9e2b77f6-f347-434d-8e99-545230c96c15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093219302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.4093219302
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.1772333938
Short name T394
Test name
Test status
Simulation time 5060324445 ps
CPU time 11.08 seconds
Started Jul 06 06:41:39 PM PDT 24
Finished Jul 06 06:41:50 PM PDT 24
Peak memory 235084 kb
Host smart-b9217e5d-16c4-42ed-97bd-ff2c2fa5e870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772333938 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.1772333938
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.3141052151
Short name T344
Test name
Test status
Simulation time 14887256620 ps
CPU time 16.68 seconds
Started Jul 06 06:41:36 PM PDT 24
Finished Jul 06 06:41:53 PM PDT 24
Peak memory 217532 kb
Host smart-232c133e-f496-4bf9-bc2d-bcaa3c1f5f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141052151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.3141052151
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.3475649743
Short name T854
Test name
Test status
Simulation time 2065058654 ps
CPU time 48.67 seconds
Started Jul 06 06:41:38 PM PDT 24
Finished Jul 06 06:42:27 PM PDT 24
Peak memory 240852 kb
Host smart-1088e46e-646a-4cba-94f7-a1d9e88bb5c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475649743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idl
e.3475649743
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.3129854678
Short name T953
Test name
Test status
Simulation time 599463914 ps
CPU time 13.96 seconds
Started Jul 06 06:41:35 PM PDT 24
Finished Jul 06 06:41:50 PM PDT 24
Peak memory 249092 kb
Host smart-203a1d4e-4619-487c-847a-8a566020b7e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129854678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.3129854678
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.3685624864
Short name T707
Test name
Test status
Simulation time 84104616332 ps
CPU time 183.01 seconds
Started Jul 06 06:41:39 PM PDT 24
Finished Jul 06 06:44:43 PM PDT 24
Peak memory 249880 kb
Host smart-5399ea06-fed3-4e48-bbd0-6c6c7a32da29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3685624864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.3685624864
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.3959082878
Short name T925
Test name
Test status
Simulation time 768430294 ps
CPU time 8.87 seconds
Started Jul 06 06:41:36 PM PDT 24
Finished Jul 06 06:41:45 PM PDT 24
Peak memory 224428 kb
Host smart-7db6e420-72d5-4361-a0dc-7e569de13a40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959082878 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.3959082878
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.654426796
Short name T385
Test name
Test status
Simulation time 24661219839 ps
CPU time 13.61 seconds
Started Jul 06 06:41:36 PM PDT 24
Finished Jul 06 06:41:50 PM PDT 24
Peak memory 232828 kb
Host smart-4a41fb80-5b17-41e2-95c8-226601b6bab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654426796 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.654426796
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.3090544931
Short name T285
Test name
Test status
Simulation time 4419456241 ps
CPU time 9.34 seconds
Started Jul 06 06:41:34 PM PDT 24
Finished Jul 06 06:41:43 PM PDT 24
Peak memory 232772 kb
Host smart-f859dd92-3445-4bbc-99f4-18ec92574460
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090544931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swa
p.3090544931
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.1850793610
Short name T809
Test name
Test status
Simulation time 8420650297 ps
CPU time 8.71 seconds
Started Jul 06 06:41:32 PM PDT 24
Finished Jul 06 06:41:41 PM PDT 24
Peak memory 232692 kb
Host smart-6d107c83-5118-41d4-826d-8ca6d262d88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850793610 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.1850793610
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.1428461608
Short name T885
Test name
Test status
Simulation time 125761569 ps
CPU time 4 seconds
Started Jul 06 06:41:36 PM PDT 24
Finished Jul 06 06:41:40 PM PDT 24
Peak memory 219732 kb
Host smart-b1753f05-f3fa-4e74-a2f8-9841103486d9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1428461608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.1428461608
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2967524399
Short name T413
Test name
Test status
Simulation time 11236570561 ps
CPU time 17.59 seconds
Started Jul 06 06:41:31 PM PDT 24
Finished Jul 06 06:41:49 PM PDT 24
Peak memory 217580 kb
Host smart-708d0b86-5b66-4967-b8f2-9ea49bc29932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2967524399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2967524399
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.4031924310
Short name T603
Test name
Test status
Simulation time 55976680 ps
CPU time 0.96 seconds
Started Jul 06 06:41:31 PM PDT 24
Finished Jul 06 06:41:32 PM PDT 24
Peak memory 207064 kb
Host smart-e687cf54-9289-4805-9f38-f08d9734a033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031924310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.4031924310
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.125637955
Short name T458
Test name
Test status
Simulation time 67035033 ps
CPU time 0.79 seconds
Started Jul 06 06:41:33 PM PDT 24
Finished Jul 06 06:41:34 PM PDT 24
Peak memory 205936 kb
Host smart-01988a68-f117-40e6-a4f7-a7cba673d27c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125637955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.125637955
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.1907215260
Short name T148
Test name
Test status
Simulation time 23777639 ps
CPU time 0.68 seconds
Started Jul 06 06:41:42 PM PDT 24
Finished Jul 06 06:41:43 PM PDT 24
Peak memory 205500 kb
Host smart-3633d6a8-c773-451f-97a7-45b3cf6d64fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907215260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
1907215260
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.243289139
Short name T935
Test name
Test status
Simulation time 3431067589 ps
CPU time 9.97 seconds
Started Jul 06 06:41:41 PM PDT 24
Finished Jul 06 06:41:51 PM PDT 24
Peak memory 232772 kb
Host smart-a9d58cb4-3d58-42e3-9343-87cfffa7bbba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243289139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.243289139
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.3729699334
Short name T436
Test name
Test status
Simulation time 15049534 ps
CPU time 0.76 seconds
Started Jul 06 06:41:39 PM PDT 24
Finished Jul 06 06:41:40 PM PDT 24
Peak memory 205592 kb
Host smart-0ae326e0-f4ef-46db-b4ef-1ce809598f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729699334 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.3729699334
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2754913964
Short name T39
Test name
Test status
Simulation time 7159249819 ps
CPU time 66.86 seconds
Started Jul 06 06:41:40 PM PDT 24
Finished Jul 06 06:42:47 PM PDT 24
Peak memory 265276 kb
Host smart-52f13a37-702b-42ed-aee0-cadbe84f898f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2754913964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2754913964
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.673108011
Short name T863
Test name
Test status
Simulation time 2505220869 ps
CPU time 26.17 seconds
Started Jul 06 06:41:42 PM PDT 24
Finished Jul 06 06:42:08 PM PDT 24
Peak memory 233892 kb
Host smart-ae866283-7ab6-435d-86bd-b6c17f032bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673108011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.673108011
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3842096526
Short name T63
Test name
Test status
Simulation time 60233045919 ps
CPU time 214.95 seconds
Started Jul 06 06:41:41 PM PDT 24
Finished Jul 06 06:45:16 PM PDT 24
Peak memory 267228 kb
Host smart-79fa2a09-ede5-4ca2-b08a-5fda2a598137
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842096526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3842096526
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.2191943057
Short name T68
Test name
Test status
Simulation time 709223996 ps
CPU time 8.31 seconds
Started Jul 06 06:41:40 PM PDT 24
Finished Jul 06 06:41:48 PM PDT 24
Peak memory 234748 kb
Host smart-73e8f0bd-5f22-486d-a727-7c20bef805f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191943057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.2191943057
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.455880418
Short name T886
Test name
Test status
Simulation time 1610275502 ps
CPU time 15.06 seconds
Started Jul 06 06:41:42 PM PDT 24
Finished Jul 06 06:41:58 PM PDT 24
Peak memory 224484 kb
Host smart-24ad12ed-8ab6-4c56-a2fb-c47f275346d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455880418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmds
.455880418
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.3041787910
Short name T56
Test name
Test status
Simulation time 75699924 ps
CPU time 2.98 seconds
Started Jul 06 06:41:43 PM PDT 24
Finished Jul 06 06:41:47 PM PDT 24
Peak memory 232644 kb
Host smart-83c1e64e-95c3-4b35-aa03-234a1eb2967a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041787910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.3041787910
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.1248614030
Short name T8
Test name
Test status
Simulation time 3060005374 ps
CPU time 26.69 seconds
Started Jul 06 06:41:41 PM PDT 24
Finished Jul 06 06:42:08 PM PDT 24
Peak memory 224576 kb
Host smart-9f4c6a41-219b-4259-976f-b3735aae674c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248614030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.1248614030
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.770487195
Short name T748
Test name
Test status
Simulation time 107564810 ps
CPU time 2.55 seconds
Started Jul 06 06:41:40 PM PDT 24
Finished Jul 06 06:41:43 PM PDT 24
Peak memory 224416 kb
Host smart-69e75fd5-362d-486a-8252-ce96bf0f5665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770487195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.770487195
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.938150552
Short name T900
Test name
Test status
Simulation time 573620525 ps
CPU time 6.72 seconds
Started Jul 06 06:41:38 PM PDT 24
Finished Jul 06 06:41:45 PM PDT 24
Peak memory 232680 kb
Host smart-b24d7126-11a3-4b3c-ada1-c2c1768f470d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938150552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.938150552
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.1968825752
Short name T756
Test name
Test status
Simulation time 1961788582 ps
CPU time 8.11 seconds
Started Jul 06 06:41:40 PM PDT 24
Finished Jul 06 06:41:49 PM PDT 24
Peak memory 222028 kb
Host smart-a601c3c7-414f-41c6-b7d1-6f3e98e9d73b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1968825752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.1968825752
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.4155578544
Short name T23
Test name
Test status
Simulation time 56619424264 ps
CPU time 119.86 seconds
Started Jul 06 06:41:41 PM PDT 24
Finished Jul 06 06:43:41 PM PDT 24
Peak memory 253832 kb
Host smart-230c93d4-3553-4661-806a-8cb16ca95476
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155578544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.4155578544
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.441758654
Short name T508
Test name
Test status
Simulation time 2706740576 ps
CPU time 3.38 seconds
Started Jul 06 06:41:38 PM PDT 24
Finished Jul 06 06:41:42 PM PDT 24
Peak memory 216340 kb
Host smart-93458949-031a-4c98-a921-f8dbc0f62659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441758654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.441758654
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.3954519234
Short name T812
Test name
Test status
Simulation time 707149152 ps
CPU time 2.41 seconds
Started Jul 06 06:41:36 PM PDT 24
Finished Jul 06 06:41:38 PM PDT 24
Peak memory 216236 kb
Host smart-8b2d81e3-72ae-4f47-90c4-ad27e900d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954519234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.3954519234
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.1236797530
Short name T1002
Test name
Test status
Simulation time 153860913 ps
CPU time 2.37 seconds
Started Jul 06 06:41:37 PM PDT 24
Finished Jul 06 06:41:39 PM PDT 24
Peak memory 216280 kb
Host smart-4d5e0ec9-0a4b-46b3-8962-e692df67dd47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236797530 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.1236797530
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.1642450662
Short name T698
Test name
Test status
Simulation time 49632971 ps
CPU time 0.84 seconds
Started Jul 06 06:41:40 PM PDT 24
Finished Jul 06 06:41:41 PM PDT 24
Peak memory 206028 kb
Host smart-2c6d49b7-dfa0-41a8-919c-a08fe9a60cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642450662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.1642450662
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.1605334121
Short name T622
Test name
Test status
Simulation time 1982097394 ps
CPU time 6.82 seconds
Started Jul 06 06:41:42 PM PDT 24
Finished Jul 06 06:41:49 PM PDT 24
Peak memory 240880 kb
Host smart-77dbdf5d-bb3c-48a2-be5f-1086a767723f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605334121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.1605334121
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.3508317612
Short name T815
Test name
Test status
Simulation time 13511020 ps
CPU time 0.71 seconds
Started Jul 06 06:41:44 PM PDT 24
Finished Jul 06 06:41:45 PM PDT 24
Peak memory 205456 kb
Host smart-470d7398-3ec4-4d07-8ed7-07811523c7a8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3508317612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.
3508317612
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.1388313226
Short name T645
Test name
Test status
Simulation time 1048503857 ps
CPU time 6.86 seconds
Started Jul 06 06:41:46 PM PDT 24
Finished Jul 06 06:41:53 PM PDT 24
Peak memory 224472 kb
Host smart-74a54b89-5fcf-497c-8e84-a0e76d59f6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388313226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.1388313226
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.3994895789
Short name T142
Test name
Test status
Simulation time 84514030 ps
CPU time 0.78 seconds
Started Jul 06 06:41:42 PM PDT 24
Finished Jul 06 06:41:43 PM PDT 24
Peak memory 206620 kb
Host smart-933b2b27-f092-4e83-af23-fb2cf95d7d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994895789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.3994895789
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.1070121019
Short name T386
Test name
Test status
Simulation time 42487244527 ps
CPU time 113.96 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:43:49 PM PDT 24
Peak memory 249180 kb
Host smart-ee3316fd-dab1-4bff-aa0b-5e2bc24161f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070121019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.1070121019
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.108937588
Short name T303
Test name
Test status
Simulation time 92342628107 ps
CPU time 465.69 seconds
Started Jul 06 06:41:46 PM PDT 24
Finished Jul 06 06:49:31 PM PDT 24
Peak memory 257456 kb
Host smart-ea962c07-ea44-49d3-9548-486440833d71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108937588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.108937588
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.879914176
Short name T713
Test name
Test status
Simulation time 10575062650 ps
CPU time 102.92 seconds
Started Jul 06 06:41:45 PM PDT 24
Finished Jul 06 06:43:28 PM PDT 24
Peak memory 268408 kb
Host smart-80aadd5e-2d7b-4dc6-961e-1308d6d6e21c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879914176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idle
.879914176
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.2062397325
Short name T743
Test name
Test status
Simulation time 509497769 ps
CPU time 7.68 seconds
Started Jul 06 06:41:54 PM PDT 24
Finished Jul 06 06:42:02 PM PDT 24
Peak memory 232724 kb
Host smart-f2fbb633-c660-4b0d-b5e8-c8b614cce387
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062397325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.2062397325
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.2446885870
Short name T967
Test name
Test status
Simulation time 7462297965 ps
CPU time 16.71 seconds
Started Jul 06 06:41:44 PM PDT 24
Finished Jul 06 06:42:01 PM PDT 24
Peak memory 224552 kb
Host smart-7519e68c-1e0a-4340-892f-898657951ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446885870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.2446885870
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.161042318
Short name T678
Test name
Test status
Simulation time 1960584492 ps
CPU time 15.17 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:42:11 PM PDT 24
Peak memory 232604 kb
Host smart-a10f8757-ae92-46fc-8fb3-92910caf90ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=161042318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.161042318
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.3010357043
Short name T689
Test name
Test status
Simulation time 453779921 ps
CPU time 5.18 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:42:00 PM PDT 24
Peak memory 224404 kb
Host smart-e74bbd2e-8994-4a09-b8bb-4d93c7905470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010357043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.3010357043
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.1453508453
Short name T147
Test name
Test status
Simulation time 5806616371 ps
CPU time 19.45 seconds
Started Jul 06 06:41:44 PM PDT 24
Finished Jul 06 06:42:04 PM PDT 24
Peak memory 232820 kb
Host smart-596e37a8-4a68-4d23-b8c9-d49718178846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1453508453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.1453508453
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.3316284576
Short name T919
Test name
Test status
Simulation time 447273996 ps
CPU time 3.51 seconds
Started Jul 06 06:41:45 PM PDT 24
Finished Jul 06 06:41:49 PM PDT 24
Peak memory 220168 kb
Host smart-650290df-8681-4c5f-beda-39287c61fa38
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3316284576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dir
ect.3316284576
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.3780736686
Short name T399
Test name
Test status
Simulation time 45270301775 ps
CPU time 90.14 seconds
Started Jul 06 06:41:45 PM PDT 24
Finished Jul 06 06:43:15 PM PDT 24
Peak memory 249280 kb
Host smart-c248bb2e-210e-4587-a7cb-6e68c5a2e88b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780736686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stre
ss_all.3780736686
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.3269099149
Short name T524
Test name
Test status
Simulation time 199695330 ps
CPU time 2.44 seconds
Started Jul 06 06:41:41 PM PDT 24
Finished Jul 06 06:41:44 PM PDT 24
Peak memory 217608 kb
Host smart-41e0ecd3-284b-4d65-8bcd-b93de2543805
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269099149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.3269099149
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3756583173
Short name T32
Test name
Test status
Simulation time 7209026748 ps
CPU time 4.9 seconds
Started Jul 06 06:41:42 PM PDT 24
Finished Jul 06 06:41:47 PM PDT 24
Peak memory 216384 kb
Host smart-8273740f-4fa4-408b-bd15-a97ed8b62451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756583173 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3756583173
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.1161300268
Short name T466
Test name
Test status
Simulation time 544375741 ps
CPU time 2.61 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:41:58 PM PDT 24
Peak memory 216220 kb
Host smart-4d92a27f-afbc-4ac6-ac28-8e43f7fb8883
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1161300268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.1161300268
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.1760469028
Short name T568
Test name
Test status
Simulation time 21304866 ps
CPU time 0.75 seconds
Started Jul 06 06:41:40 PM PDT 24
Finished Jul 06 06:41:42 PM PDT 24
Peak memory 205928 kb
Host smart-c6321804-bee2-421f-bb14-8895171ad326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1760469028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.1760469028
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.1294322479
Short name T290
Test name
Test status
Simulation time 3696821355 ps
CPU time 5.55 seconds
Started Jul 06 06:41:45 PM PDT 24
Finished Jul 06 06:41:51 PM PDT 24
Peak memory 232760 kb
Host smart-f942d891-a1e3-4263-8277-45e61c928e49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1294322479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.1294322479
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.716736630
Short name T624
Test name
Test status
Simulation time 45351710 ps
CPU time 0.69 seconds
Started Jul 06 06:41:50 PM PDT 24
Finished Jul 06 06:41:51 PM PDT 24
Peak memory 205776 kb
Host smart-daa17de1-4a07-421e-a468-e3f64aa37857
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716736630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.716736630
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.301955898
Short name T532
Test name
Test status
Simulation time 5366583533 ps
CPU time 9.04 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:42:05 PM PDT 24
Peak memory 224516 kb
Host smart-ed49d513-7b2c-4ab5-9b99-dce0d4ef0465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301955898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.301955898
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.1227826925
Short name T804
Test name
Test status
Simulation time 73264441 ps
CPU time 0.74 seconds
Started Jul 06 06:41:54 PM PDT 24
Finished Jul 06 06:41:55 PM PDT 24
Peak memory 205544 kb
Host smart-3052f36c-adf8-4642-88aa-f4e6719aa378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227826925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.1227826925
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2137503909
Short name T253
Test name
Test status
Simulation time 30665378917 ps
CPU time 86 seconds
Started Jul 06 06:41:53 PM PDT 24
Finished Jul 06 06:43:19 PM PDT 24
Peak memory 252100 kb
Host smart-512da06b-8eac-4a9f-9942-09985f397dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137503909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2137503909
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.3689351203
Short name T202
Test name
Test status
Simulation time 23315446924 ps
CPU time 131.05 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:44:06 PM PDT 24
Peak memory 251728 kb
Host smart-599c9632-cbef-4713-a697-453643e8d72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689351203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.3689351203
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.1456265194
Short name T203
Test name
Test status
Simulation time 14722002353 ps
CPU time 118.71 seconds
Started Jul 06 06:41:56 PM PDT 24
Finished Jul 06 06:43:55 PM PDT 24
Peak memory 257352 kb
Host smart-9cbaf5b9-ed40-4220-937d-d28020f3db60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456265194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.1456265194
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1149896001
Short name T334
Test name
Test status
Simulation time 394755234 ps
CPU time 6.06 seconds
Started Jul 06 06:41:51 PM PDT 24
Finished Jul 06 06:41:57 PM PDT 24
Peak memory 232636 kb
Host smart-5dfd1968-8d05-4c45-b76f-3ed524b5fec3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149896001 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1149896001
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.2477421317
Short name T437
Test name
Test status
Simulation time 3689421013 ps
CPU time 21.65 seconds
Started Jul 06 06:41:50 PM PDT 24
Finished Jul 06 06:42:12 PM PDT 24
Peak memory 242120 kb
Host smart-5598bc88-49dd-446e-bed8-15c9c80a3ef3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477421317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.2477421317
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1219056342
Short name T788
Test name
Test status
Simulation time 2059978960 ps
CPU time 12.06 seconds
Started Jul 06 06:41:51 PM PDT 24
Finished Jul 06 06:42:03 PM PDT 24
Peak memory 228548 kb
Host smart-5d043b70-b57f-4411-8dff-5df57cef0665
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219056342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1219056342
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.594636612
Short name T275
Test name
Test status
Simulation time 5555620913 ps
CPU time 54.56 seconds
Started Jul 06 06:41:52 PM PDT 24
Finished Jul 06 06:42:47 PM PDT 24
Peak memory 249236 kb
Host smart-ed6a27c3-195c-43d7-811c-f654b4e3666b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594636612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.594636612
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.3151262506
Short name T715
Test name
Test status
Simulation time 30747700291 ps
CPU time 13.49 seconds
Started Jul 06 06:41:50 PM PDT 24
Finished Jul 06 06:42:03 PM PDT 24
Peak memory 224612 kb
Host smart-3fae4b0b-7538-406e-9ecb-a3cd04dc365c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151262506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swa
p.3151262506
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.2473660163
Short name T810
Test name
Test status
Simulation time 1044678340 ps
CPU time 3.42 seconds
Started Jul 06 06:41:49 PM PDT 24
Finished Jul 06 06:41:53 PM PDT 24
Peak memory 224492 kb
Host smart-047e6879-b6bc-40e4-b58d-a5f569b3b374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473660163 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.2473660163
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2601385564
Short name T160
Test name
Test status
Simulation time 5665101275 ps
CPU time 12.68 seconds
Started Jul 06 06:41:50 PM PDT 24
Finished Jul 06 06:42:03 PM PDT 24
Peak memory 219240 kb
Host smart-e871cd86-264a-447c-ac11-7a88e4a8fe0b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2601385564 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2601385564
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.1511673460
Short name T17
Test name
Test status
Simulation time 138279734 ps
CPU time 1.13 seconds
Started Jul 06 06:41:52 PM PDT 24
Finished Jul 06 06:41:54 PM PDT 24
Peak memory 206836 kb
Host smart-2d2b2648-ec8c-4d6c-bb11-773081799a9a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511673460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.1511673460
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.3942189166
Short name T337
Test name
Test status
Simulation time 31636430267 ps
CPU time 40.35 seconds
Started Jul 06 06:41:49 PM PDT 24
Finished Jul 06 06:42:30 PM PDT 24
Peak memory 216348 kb
Host smart-4e4d4513-eae5-4047-8a1c-28857a3f14c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942189166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.3942189166
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.1017470324
Short name T725
Test name
Test status
Simulation time 633286821 ps
CPU time 1.86 seconds
Started Jul 06 06:41:50 PM PDT 24
Finished Jul 06 06:41:52 PM PDT 24
Peak memory 207884 kb
Host smart-75975db6-18c7-4132-b20d-bcb15c4e1c2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017470324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.1017470324
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2147964696
Short name T855
Test name
Test status
Simulation time 28028834 ps
CPU time 1.49 seconds
Started Jul 06 06:41:52 PM PDT 24
Finished Jul 06 06:41:54 PM PDT 24
Peak memory 216300 kb
Host smart-2d813c34-d086-4bc8-8a52-bf316564d8c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147964696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2147964696
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.1641175684
Short name T904
Test name
Test status
Simulation time 125457729 ps
CPU time 0.97 seconds
Started Jul 06 06:41:52 PM PDT 24
Finished Jul 06 06:41:53 PM PDT 24
Peak memory 205952 kb
Host smart-1f7d0a68-269d-4938-82ba-9effca4cd9a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641175684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.1641175684
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.579102188
Short name T274
Test name
Test status
Simulation time 2429994050 ps
CPU time 3.45 seconds
Started Jul 06 06:41:53 PM PDT 24
Finished Jul 06 06:41:57 PM PDT 24
Peak memory 224588 kb
Host smart-a98e9a97-392c-4bc1-a07c-cc14c512b0a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579102188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.579102188
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.578253440
Short name T950
Test name
Test status
Simulation time 15678619 ps
CPU time 0.74 seconds
Started Jul 06 06:42:02 PM PDT 24
Finished Jul 06 06:42:03 PM PDT 24
Peak memory 205920 kb
Host smart-b51a263a-1bdd-4c0d-be17-147bfdc3e0cc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578253440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.578253440
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.2465084925
Short name T679
Test name
Test status
Simulation time 246756495 ps
CPU time 5.21 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:42:00 PM PDT 24
Peak memory 224400 kb
Host smart-4b9a042e-8bf7-4ce3-b6a0-80fd4334f50c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465084925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.2465084925
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.2024459320
Short name T908
Test name
Test status
Simulation time 19583994 ps
CPU time 0.76 seconds
Started Jul 06 06:41:56 PM PDT 24
Finished Jul 06 06:41:57 PM PDT 24
Peak memory 206576 kb
Host smart-503650f2-84c7-486d-b640-5f4b26511dbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024459320 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.2024459320
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.3582383727
Short name T759
Test name
Test status
Simulation time 161849738667 ps
CPU time 271.33 seconds
Started Jul 06 06:42:01 PM PDT 24
Finished Jul 06 06:46:33 PM PDT 24
Peak memory 259064 kb
Host smart-a426685e-6e63-4127-a8d8-d605f002269f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582383727 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.3582383727
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.1239369339
Short name T901
Test name
Test status
Simulation time 7066704253 ps
CPU time 78.7 seconds
Started Jul 06 06:42:01 PM PDT 24
Finished Jul 06 06:43:20 PM PDT 24
Peak memory 252508 kb
Host smart-b76da2dc-d00d-44b3-b6e3-3f108071e044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239369339 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.1239369339
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.3334172823
Short name T981
Test name
Test status
Simulation time 4636301927 ps
CPU time 21.57 seconds
Started Jul 06 06:41:56 PM PDT 24
Finished Jul 06 06:42:18 PM PDT 24
Peak memory 232740 kb
Host smart-bb35ff72-c7ae-4dc3-a3d7-dc0ae8f78d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3334172823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.3334172823
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_intercept.940558568
Short name T426
Test name
Test status
Simulation time 56259290 ps
CPU time 1.96 seconds
Started Jul 06 06:41:54 PM PDT 24
Finished Jul 06 06:41:56 PM PDT 24
Peak memory 224120 kb
Host smart-48664537-1bd0-4cee-aad1-a0fbedc50f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940558568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.940558568
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.763336495
Short name T851
Test name
Test status
Simulation time 1018107797 ps
CPU time 11.71 seconds
Started Jul 06 06:41:54 PM PDT 24
Finished Jul 06 06:42:06 PM PDT 24
Peak memory 249820 kb
Host smart-26036f47-acae-4eb9-b467-a5d9892594a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763336495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.763336495
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3050800687
Short name T311
Test name
Test status
Simulation time 1284680875 ps
CPU time 10.69 seconds
Started Jul 06 06:41:52 PM PDT 24
Finished Jul 06 06:42:03 PM PDT 24
Peak memory 224464 kb
Host smart-31048672-4abd-4e61-83d8-a8d68ffb9f98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050800687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3050800687
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2696736368
Short name T575
Test name
Test status
Simulation time 1508567762 ps
CPU time 4.68 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:42:00 PM PDT 24
Peak memory 224488 kb
Host smart-d15ddb5e-241c-4dff-8018-67d7c663b0b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2696736368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2696736368
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.1626559913
Short name T574
Test name
Test status
Simulation time 156159565 ps
CPU time 4.35 seconds
Started Jul 06 06:42:00 PM PDT 24
Finished Jul 06 06:42:05 PM PDT 24
Peak memory 223200 kb
Host smart-f63d5d31-3dde-4712-9a40-6fc1dea7f5ee
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1626559913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.1626559913
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.1141574608
Short name T865
Test name
Test status
Simulation time 44695205247 ps
CPU time 230.76 seconds
Started Jul 06 06:42:00 PM PDT 24
Finished Jul 06 06:45:52 PM PDT 24
Peak memory 266604 kb
Host smart-a6ceca92-711b-452b-8b60-e1f715fd3f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141574608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stre
ss_all.1141574608
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.1092366526
Short name T930
Test name
Test status
Simulation time 290166970 ps
CPU time 3.72 seconds
Started Jul 06 06:41:52 PM PDT 24
Finished Jul 06 06:41:56 PM PDT 24
Peak memory 216524 kb
Host smart-a3f19f3c-97a5-4fd2-9060-48d2342f080f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092366526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.1092366526
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.3812693137
Short name T947
Test name
Test status
Simulation time 667204744 ps
CPU time 3.37 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:41:59 PM PDT 24
Peak memory 216264 kb
Host smart-f997aca2-bab1-41e6-b16d-7c542a24998b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812693137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.3812693137
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.3911985272
Short name T825
Test name
Test status
Simulation time 46063817 ps
CPU time 0.84 seconds
Started Jul 06 06:41:54 PM PDT 24
Finished Jul 06 06:41:55 PM PDT 24
Peak memory 206708 kb
Host smart-12107695-76ed-40de-93f9-ecbc5b0a4532
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911985272 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.3911985272
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.3561796342
Short name T852
Test name
Test status
Simulation time 33390086 ps
CPU time 0.7 seconds
Started Jul 06 06:41:55 PM PDT 24
Finished Jul 06 06:41:57 PM PDT 24
Peak memory 205680 kb
Host smart-439c373f-edac-4d3f-bfbf-7aea05b11b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561796342 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.3561796342
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.1309892345
Short name T933
Test name
Test status
Simulation time 47204669711 ps
CPU time 25.35 seconds
Started Jul 06 06:41:54 PM PDT 24
Finished Jul 06 06:42:19 PM PDT 24
Peak memory 232832 kb
Host smart-92361e20-db00-4a83-a5be-f2dfdb8beb43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309892345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.1309892345
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.1456603080
Short name T961
Test name
Test status
Simulation time 13730932 ps
CPU time 0.71 seconds
Started Jul 06 06:39:50 PM PDT 24
Finished Jul 06 06:39:51 PM PDT 24
Peak memory 205480 kb
Host smart-30a231cf-0e38-4bf3-81e0-e80c426b5a16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1456603080 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.1
456603080
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.3537979960
Short name T826
Test name
Test status
Simulation time 1325801781 ps
CPU time 3.57 seconds
Started Jul 06 06:39:43 PM PDT 24
Finished Jul 06 06:39:47 PM PDT 24
Peak memory 224468 kb
Host smart-cfc661f8-f6c1-4448-a387-19c75b11d4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537979960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.3537979960
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.285026487
Short name T397
Test name
Test status
Simulation time 46436336 ps
CPU time 0.74 seconds
Started Jul 06 06:39:41 PM PDT 24
Finished Jul 06 06:39:42 PM PDT 24
Peak memory 206912 kb
Host smart-187d00c6-893d-4f78-81e0-46e29a9f0eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285026487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.285026487
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.2453587447
Short name T501
Test name
Test status
Simulation time 1401983051 ps
CPU time 32.78 seconds
Started Jul 06 06:39:43 PM PDT 24
Finished Jul 06 06:40:16 PM PDT 24
Peak memory 249236 kb
Host smart-07ebffe3-c9d9-4e5f-9f44-ecf3d206275f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453587447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle
.2453587447
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.1969615522
Short name T11
Test name
Test status
Simulation time 10919994850 ps
CPU time 18.76 seconds
Started Jul 06 06:39:44 PM PDT 24
Finished Jul 06 06:40:03 PM PDT 24
Peak memory 240880 kb
Host smart-d5842e58-0c63-462d-a302-8179f31b085f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1969615522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.1969615522
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.1764624139
Short name T235
Test name
Test status
Simulation time 1937032284 ps
CPU time 16.37 seconds
Started Jul 06 06:39:45 PM PDT 24
Finished Jul 06 06:40:02 PM PDT 24
Peak memory 236412 kb
Host smart-b8de3d4a-afca-46aa-98de-06075d680e30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764624139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds
.1764624139
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.1890959773
Short name T708
Test name
Test status
Simulation time 3607602987 ps
CPU time 21.58 seconds
Started Jul 06 06:39:44 PM PDT 24
Finished Jul 06 06:40:05 PM PDT 24
Peak memory 232856 kb
Host smart-84aa1e21-6c59-4e8c-a963-8c19bbe658ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890959773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.1890959773
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.42961882
Short name T469
Test name
Test status
Simulation time 114291806 ps
CPU time 2.92 seconds
Started Jul 06 06:39:45 PM PDT 24
Finished Jul 06 06:39:49 PM PDT 24
Peak memory 232708 kb
Host smart-85ad54fb-2d5e-449c-837c-9393c998bbd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42961882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.42961882
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.2332464477
Short name T281
Test name
Test status
Simulation time 15655407884 ps
CPU time 10.23 seconds
Started Jul 06 06:39:44 PM PDT 24
Finished Jul 06 06:39:55 PM PDT 24
Peak memory 224592 kb
Host smart-d6778ccf-2555-462a-b7fc-c7e4aa08fe2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332464477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.2332464477
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.2425323870
Short name T496
Test name
Test status
Simulation time 12770567088 ps
CPU time 19.41 seconds
Started Jul 06 06:39:44 PM PDT 24
Finished Jul 06 06:40:04 PM PDT 24
Peak memory 240780 kb
Host smart-ebadce15-d2cc-4b8b-8a21-527b74c281a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425323870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.2425323870
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.1752746755
Short name T907
Test name
Test status
Simulation time 2473504917 ps
CPU time 11 seconds
Started Jul 06 06:39:44 PM PDT 24
Finished Jul 06 06:39:55 PM PDT 24
Peak memory 223192 kb
Host smart-c7b1dd82-d5df-471d-9840-3ec6c6a200a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1752746755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.1752746755
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.6450611
Short name T86
Test name
Test status
Simulation time 70538803 ps
CPU time 0.99 seconds
Started Jul 06 06:39:46 PM PDT 24
Finished Jul 06 06:39:48 PM PDT 24
Peak memory 235560 kb
Host smart-6ed6f454-4d87-463d-aa4f-d50f4783e9a4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=6450611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.6450611
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.2016533099
Short name T340
Test name
Test status
Simulation time 3229036281 ps
CPU time 29.67 seconds
Started Jul 06 06:39:43 PM PDT 24
Finished Jul 06 06:40:13 PM PDT 24
Peak memory 216560 kb
Host smart-b5c54a09-9400-42f6-9812-e9b35773a115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016533099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.2016533099
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3259410958
Short name T356
Test name
Test status
Simulation time 14120839580 ps
CPU time 14.42 seconds
Started Jul 06 06:39:41 PM PDT 24
Finished Jul 06 06:39:55 PM PDT 24
Peak memory 216580 kb
Host smart-a7a9d65c-bc4c-4980-be7f-d5baf1ae5fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259410958 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3259410958
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.618914289
Short name T601
Test name
Test status
Simulation time 314100229 ps
CPU time 1.84 seconds
Started Jul 06 06:39:45 PM PDT 24
Finished Jul 06 06:39:48 PM PDT 24
Peak memory 216200 kb
Host smart-00f87a43-d5b5-448a-94c5-c22155bbec40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618914289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.618914289
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.861546236
Short name T794
Test name
Test status
Simulation time 107959231 ps
CPU time 0.8 seconds
Started Jul 06 06:39:43 PM PDT 24
Finished Jul 06 06:39:45 PM PDT 24
Peak memory 206004 kb
Host smart-9814c8ee-2f07-42e4-9ee0-5ee078429467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861546236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.861546236
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.90502072
Short name T684
Test name
Test status
Simulation time 6406950725 ps
CPU time 13.45 seconds
Started Jul 06 06:39:45 PM PDT 24
Finished Jul 06 06:39:59 PM PDT 24
Peak memory 232744 kb
Host smart-ad4d81ba-df67-4ac6-af6a-2b72dd63a7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90502072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.90502072
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.4153064308
Short name T752
Test name
Test status
Simulation time 37028574 ps
CPU time 0.73 seconds
Started Jul 06 06:42:05 PM PDT 24
Finished Jul 06 06:42:07 PM PDT 24
Peak memory 205552 kb
Host smart-08cdd91e-b80f-49bb-9f62-da575fb0a426
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153064308 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
4153064308
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.1636499601
Short name T583
Test name
Test status
Simulation time 3521938724 ps
CPU time 15.39 seconds
Started Jul 06 06:42:08 PM PDT 24
Finished Jul 06 06:42:23 PM PDT 24
Peak memory 224560 kb
Host smart-7537150c-5d1b-4dff-bfdb-cd757d35ab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636499601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.1636499601
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.2424949979
Short name T779
Test name
Test status
Simulation time 34360051 ps
CPU time 0.74 seconds
Started Jul 06 06:41:58 PM PDT 24
Finished Jul 06 06:41:59 PM PDT 24
Peak memory 205608 kb
Host smart-7018d2af-6218-45cd-b782-a56113582554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424949979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.2424949979
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.1046115410
Short name T251
Test name
Test status
Simulation time 1845556779 ps
CPU time 43.06 seconds
Started Jul 06 06:42:07 PM PDT 24
Finished Jul 06 06:42:50 PM PDT 24
Peak memory 251604 kb
Host smart-b548cb6a-2faf-42db-a962-e6ee573bd05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046115410 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.1046115410
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.3069193450
Short name T798
Test name
Test status
Simulation time 5474741526 ps
CPU time 51.24 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:58 PM PDT 24
Peak memory 249216 kb
Host smart-105a4b16-5868-4853-832b-0b186f707d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069193450 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.3069193450
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.1704067990
Short name T760
Test name
Test status
Simulation time 10588866888 ps
CPU time 28.93 seconds
Started Jul 06 06:42:04 PM PDT 24
Finished Jul 06 06:42:33 PM PDT 24
Peak memory 224660 kb
Host smart-93e1c7b5-37aa-4163-9df9-1aceef7a1270
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704067990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.1704067990
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.201205187
Short name T368
Test name
Test status
Simulation time 1451784064 ps
CPU time 8.39 seconds
Started Jul 06 06:42:07 PM PDT 24
Finished Jul 06 06:42:15 PM PDT 24
Peak memory 224492 kb
Host smart-8e56eb3d-908e-4f36-b961-0b261b7a4633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201205187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.201205187
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.576358736
Short name T192
Test name
Test status
Simulation time 44329143387 ps
CPU time 68.85 seconds
Started Jul 06 06:42:04 PM PDT 24
Finished Jul 06 06:43:13 PM PDT 24
Peak memory 255344 kb
Host smart-1b120fd5-2833-4e54-a76b-908f85e2fb72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576358736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmds
.576358736
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.1825170309
Short name T972
Test name
Test status
Simulation time 663732907 ps
CPU time 8.94 seconds
Started Jul 06 06:41:59 PM PDT 24
Finished Jul 06 06:42:08 PM PDT 24
Peak memory 224408 kb
Host smart-3ec172aa-7655-4d40-a864-fbb42965f971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825170309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.1825170309
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.2083434935
Short name T604
Test name
Test status
Simulation time 6393983532 ps
CPU time 47.68 seconds
Started Jul 06 06:42:00 PM PDT 24
Finished Jul 06 06:42:48 PM PDT 24
Peak memory 232852 kb
Host smart-e4b67844-b481-4872-8022-04fe62260842
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083434935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.2083434935
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.1750341092
Short name T934
Test name
Test status
Simulation time 75370632 ps
CPU time 2.23 seconds
Started Jul 06 06:42:01 PM PDT 24
Finished Jul 06 06:42:04 PM PDT 24
Peak memory 224108 kb
Host smart-dc59e37e-b74d-40ed-a2f6-6a6d9190287a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1750341092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.1750341092
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.2393713198
Short name T765
Test name
Test status
Simulation time 64266022 ps
CPU time 2.23 seconds
Started Jul 06 06:41:59 PM PDT 24
Finished Jul 06 06:42:02 PM PDT 24
Peak memory 224376 kb
Host smart-cce1abc9-7eee-4f00-a19c-73dfda4edb68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393713198 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.2393713198
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.1530301567
Short name T159
Test name
Test status
Simulation time 1888420025 ps
CPU time 7.14 seconds
Started Jul 06 06:42:10 PM PDT 24
Finished Jul 06 06:42:17 PM PDT 24
Peak memory 222112 kb
Host smart-7336f6c2-3d30-4bdc-887d-1dda7a3ee899
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1530301567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dir
ect.1530301567
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1695512688
Short name T359
Test name
Test status
Simulation time 2292015249 ps
CPU time 3.84 seconds
Started Jul 06 06:41:59 PM PDT 24
Finished Jul 06 06:42:04 PM PDT 24
Peak memory 216328 kb
Host smart-3657922e-e1de-4c2e-bba9-063213aec950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1695512688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1695512688
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.2626889011
Short name T457
Test name
Test status
Simulation time 830833593 ps
CPU time 2.93 seconds
Started Jul 06 06:42:01 PM PDT 24
Finished Jul 06 06:42:04 PM PDT 24
Peak memory 216236 kb
Host smart-ed478f15-546b-4552-805e-9b3acfccd561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626889011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.2626889011
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2862871395
Short name T599
Test name
Test status
Simulation time 37424432 ps
CPU time 1.8 seconds
Started Jul 06 06:42:02 PM PDT 24
Finished Jul 06 06:42:04 PM PDT 24
Peak memory 216216 kb
Host smart-cc4f95c9-af9c-41b8-9dfe-1985087ae0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862871395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2862871395
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.505571411
Short name T608
Test name
Test status
Simulation time 128174267 ps
CPU time 0.75 seconds
Started Jul 06 06:41:59 PM PDT 24
Finished Jul 06 06:42:00 PM PDT 24
Peak memory 206004 kb
Host smart-0c356ef9-4d75-41c9-8f2b-4f7ccbad823d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505571411 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.505571411
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.1654821195
Short name T976
Test name
Test status
Simulation time 891165833 ps
CPU time 7.34 seconds
Started Jul 06 06:42:02 PM PDT 24
Finished Jul 06 06:42:10 PM PDT 24
Peak memory 224444 kb
Host smart-b12f6586-ba6a-4c97-a723-257812ae55e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654821195 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.1654821195
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.1995131142
Short name T416
Test name
Test status
Simulation time 42211474 ps
CPU time 0.74 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:07 PM PDT 24
Peak memory 205512 kb
Host smart-56fa324d-5b93-47a4-b2c2-c23a68eac96f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995131142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
1995131142
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3006966482
Short name T750
Test name
Test status
Simulation time 49695370 ps
CPU time 2.75 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:09 PM PDT 24
Peak memory 232684 kb
Host smart-b2b46a43-1305-42bd-8c99-b06e70c614c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006966482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3006966482
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.2389605318
Short name T839
Test name
Test status
Simulation time 40493363 ps
CPU time 0.77 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:07 PM PDT 24
Peak memory 206636 kb
Host smart-58bdd4e1-515b-4ba1-b33b-b45e97a6075b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389605318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.2389605318
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.338148471
Short name T547
Test name
Test status
Simulation time 23262810415 ps
CPU time 218.72 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:45:45 PM PDT 24
Peak memory 249312 kb
Host smart-adb2591f-3c49-4e04-bb80-cdfff0f90686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338148471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.338148471
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.1278632829
Short name T916
Test name
Test status
Simulation time 4578779545 ps
CPU time 51.22 seconds
Started Jul 06 06:42:05 PM PDT 24
Finished Jul 06 06:42:57 PM PDT 24
Peak memory 249264 kb
Host smart-86b93c42-dbea-43e8-9680-774e1e48d433
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1278632829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idl
e.1278632829
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.2406202956
Short name T246
Test name
Test status
Simulation time 317139209 ps
CPU time 6.61 seconds
Started Jul 06 06:42:10 PM PDT 24
Finished Jul 06 06:42:18 PM PDT 24
Peak memory 232784 kb
Host smart-e5acea54-e2de-4571-8f36-3b39410e183e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406202956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.2406202956
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.3301032000
Short name T189
Test name
Test status
Simulation time 22083453077 ps
CPU time 105.32 seconds
Started Jul 06 06:42:07 PM PDT 24
Finished Jul 06 06:43:53 PM PDT 24
Peak memory 249588 kb
Host smart-7207746d-9099-4c0d-8359-7c72e5a812f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301032000 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.3301032000
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3528933714
Short name T859
Test name
Test status
Simulation time 39444942478 ps
CPU time 34.56 seconds
Started Jul 06 06:42:05 PM PDT 24
Finished Jul 06 06:42:40 PM PDT 24
Peak memory 224632 kb
Host smart-72254a2c-aecc-470a-8892-8d09e0acdeb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528933714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3528933714
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.3137219459
Short name T279
Test name
Test status
Simulation time 831077562 ps
CPU time 18.88 seconds
Started Jul 06 06:42:08 PM PDT 24
Finished Jul 06 06:42:27 PM PDT 24
Peak memory 251396 kb
Host smart-12d75028-75bc-4fd7-b20d-f8657556c4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137219459 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.3137219459
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1178544136
Short name T46
Test name
Test status
Simulation time 9253413437 ps
CPU time 15.52 seconds
Started Jul 06 06:42:05 PM PDT 24
Finished Jul 06 06:42:21 PM PDT 24
Peak memory 240576 kb
Host smart-376e18c4-a1e7-4a68-895f-ed10d0048d15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178544136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1178544136
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.3601490797
Short name T175
Test name
Test status
Simulation time 2263104091 ps
CPU time 7.38 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:14 PM PDT 24
Peak memory 240652 kb
Host smart-3aeb5065-188c-4145-901b-fa22c451094f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601490797 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.3601490797
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.1966768715
Short name T985
Test name
Test status
Simulation time 2561397174 ps
CPU time 16.39 seconds
Started Jul 06 06:42:08 PM PDT 24
Finished Jul 06 06:42:24 PM PDT 24
Peak memory 219116 kb
Host smart-308ce969-4b4f-4c72-a43b-182a3ee71a0d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1966768715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.1966768715
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2092804098
Short name T965
Test name
Test status
Simulation time 1758256080 ps
CPU time 9.39 seconds
Started Jul 06 06:42:04 PM PDT 24
Finished Jul 06 06:42:14 PM PDT 24
Peak memory 216292 kb
Host smart-a1d4ed20-caa8-4d07-bdf6-24d898a08663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092804098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2092804098
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3543659747
Short name T647
Test name
Test status
Simulation time 2095806525 ps
CPU time 7.45 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:14 PM PDT 24
Peak memory 216212 kb
Host smart-992bb2ed-16bc-4134-a136-cebb54ba193a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543659747 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3543659747
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.1256163420
Short name T407
Test name
Test status
Simulation time 25169817 ps
CPU time 0.68 seconds
Started Jul 06 06:42:10 PM PDT 24
Finished Jul 06 06:42:11 PM PDT 24
Peak memory 205688 kb
Host smart-50bafc15-8f4b-43bb-84a6-f97e191511aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256163420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.1256163420
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.1418312217
Short name T450
Test name
Test status
Simulation time 22327092 ps
CPU time 0.81 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:07 PM PDT 24
Peak memory 205912 kb
Host smart-cfbb13a3-7642-4b59-a210-5cf1a045a322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418312217 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.1418312217
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.1985552748
Short name T892
Test name
Test status
Simulation time 6430808468 ps
CPU time 12.48 seconds
Started Jul 06 06:42:08 PM PDT 24
Finished Jul 06 06:42:21 PM PDT 24
Peak memory 240140 kb
Host smart-e77b2776-1499-473e-ae72-4ccd7ef81072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985552748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.1985552748
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.55848280
Short name T735
Test name
Test status
Simulation time 14098453 ps
CPU time 0.74 seconds
Started Jul 06 06:42:13 PM PDT 24
Finished Jul 06 06:42:14 PM PDT 24
Peak memory 204984 kb
Host smart-87241704-57f7-4aa7-87f6-6288845ea520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55848280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.55848280
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.2196107915
Short name T494
Test name
Test status
Simulation time 154297110 ps
CPU time 2.98 seconds
Started Jul 06 06:42:14 PM PDT 24
Finished Jul 06 06:42:18 PM PDT 24
Peak memory 224396 kb
Host smart-b28210a4-3b5c-42a3-8d8d-a6c45894d7e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196107915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.2196107915
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.3604692115
Short name T616
Test name
Test status
Simulation time 13193514 ps
CPU time 0.75 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:07 PM PDT 24
Peak memory 205900 kb
Host smart-1002c629-16d1-4aa9-849b-617a2db1bae2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604692115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.3604692115
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2609783580
Short name T54
Test name
Test status
Simulation time 9527581185 ps
CPU time 42.86 seconds
Started Jul 06 06:42:10 PM PDT 24
Finished Jul 06 06:42:54 PM PDT 24
Peak memory 251184 kb
Host smart-26e20b03-e135-4cf1-ac86-bca35c6c6713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609783580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2609783580
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.1143867832
Short name T642
Test name
Test status
Simulation time 3951793509 ps
CPU time 5.64 seconds
Started Jul 06 06:42:11 PM PDT 24
Finished Jul 06 06:42:17 PM PDT 24
Peak memory 219368 kb
Host smart-449b706b-cac8-4c53-915d-45e9e7bc0092
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143867832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.1143867832
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.4127661627
Short name T66
Test name
Test status
Simulation time 88453549 ps
CPU time 3.68 seconds
Started Jul 06 06:42:18 PM PDT 24
Finished Jul 06 06:42:22 PM PDT 24
Peak memory 232712 kb
Host smart-84c6ea7b-8fc4-4f7a-93b3-40c33eff2024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4127661627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.4127661627
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.477115921
Short name T415
Test name
Test status
Simulation time 66456688 ps
CPU time 0.87 seconds
Started Jul 06 06:42:12 PM PDT 24
Finished Jul 06 06:42:14 PM PDT 24
Peak memory 215952 kb
Host smart-af134016-a042-4e3d-8be5-76519417c42f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477115921 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmds
.477115921
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.2304441611
Short name T451
Test name
Test status
Simulation time 2434667927 ps
CPU time 21.74 seconds
Started Jul 06 06:42:12 PM PDT 24
Finished Jul 06 06:42:34 PM PDT 24
Peak memory 232756 kb
Host smart-1ba04497-b366-4bc5-a3bb-470ce86e021a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304441611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.2304441611
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3108285671
Short name T573
Test name
Test status
Simulation time 723981541 ps
CPU time 4.13 seconds
Started Jul 06 06:42:11 PM PDT 24
Finished Jul 06 06:42:16 PM PDT 24
Peak memory 224468 kb
Host smart-866bb33f-d126-42ea-bb61-279c49859e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108285671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3108285671
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.530016105
Short name T775
Test name
Test status
Simulation time 298269116 ps
CPU time 2.17 seconds
Started Jul 06 06:42:11 PM PDT 24
Finished Jul 06 06:42:14 PM PDT 24
Peak memory 232404 kb
Host smart-041a9c0f-6628-47fd-b969-0af831f92aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530016105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swap
.530016105
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.1155885632
Short name T905
Test name
Test status
Simulation time 16774408428 ps
CPU time 17.47 seconds
Started Jul 06 06:42:15 PM PDT 24
Finished Jul 06 06:42:33 PM PDT 24
Peak memory 232848 kb
Host smart-7aa67cb7-6c86-4def-b093-132d4b603097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155885632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.1155885632
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.3926626764
Short name T879
Test name
Test status
Simulation time 963965326 ps
CPU time 11.82 seconds
Started Jul 06 06:42:12 PM PDT 24
Finished Jul 06 06:42:24 PM PDT 24
Peak memory 219268 kb
Host smart-6e701dca-f51a-4ed1-bfb2-cd12f47a0493
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3926626764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dir
ect.3926626764
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.1774246720
Short name T774
Test name
Test status
Simulation time 124045457 ps
CPU time 0.99 seconds
Started Jul 06 06:42:29 PM PDT 24
Finished Jul 06 06:42:31 PM PDT 24
Peak memory 207576 kb
Host smart-5f8ada9d-94da-4d4a-a23b-7c1d6910efa1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1774246720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.1774246720
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1077227721
Short name T339
Test name
Test status
Simulation time 1329298699 ps
CPU time 7.05 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:13 PM PDT 24
Peak memory 216216 kb
Host smart-1d30c117-ab0b-439d-b4a0-04b70221f3a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077227721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1077227721
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.2077642158
Short name T763
Test name
Test status
Simulation time 11830186808 ps
CPU time 5.91 seconds
Started Jul 06 06:42:07 PM PDT 24
Finished Jul 06 06:42:13 PM PDT 24
Peak memory 217156 kb
Host smart-e5311fb1-daa3-4cdb-8e5b-32f39ce20613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077642158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.2077642158
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.568112021
Short name T683
Test name
Test status
Simulation time 181816942 ps
CPU time 1.74 seconds
Started Jul 06 06:42:05 PM PDT 24
Finished Jul 06 06:42:08 PM PDT 24
Peak memory 216192 kb
Host smart-2c413a74-c45b-47fb-8ed3-30a8414ed523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=568112021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.568112021
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.1477942228
Short name T768
Test name
Test status
Simulation time 58762817 ps
CPU time 0.75 seconds
Started Jul 06 06:42:06 PM PDT 24
Finished Jul 06 06:42:07 PM PDT 24
Peak memory 205936 kb
Host smart-a8f25f36-2db1-48a9-994d-e3e684920b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477942228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.1477942228
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.1612553149
Short name T822
Test name
Test status
Simulation time 639475170 ps
CPU time 5.7 seconds
Started Jul 06 06:42:15 PM PDT 24
Finished Jul 06 06:42:21 PM PDT 24
Peak memory 224424 kb
Host smart-992ddc14-b2c0-4123-9b83-314290ff03c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612553149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.1612553149
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.771292556
Short name T479
Test name
Test status
Simulation time 20573626 ps
CPU time 0.72 seconds
Started Jul 06 06:42:17 PM PDT 24
Finished Jul 06 06:42:18 PM PDT 24
Peak memory 204976 kb
Host smart-7befdce7-10b9-4c31-bf7e-1d50e10405e0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771292556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.771292556
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.3029995741
Short name T978
Test name
Test status
Simulation time 357142539 ps
CPU time 3.7 seconds
Started Jul 06 06:42:15 PM PDT 24
Finished Jul 06 06:42:19 PM PDT 24
Peak memory 232704 kb
Host smart-20347e83-adf3-4115-8b36-71bbae1d510c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029995741 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.3029995741
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.3441875391
Short name T400
Test name
Test status
Simulation time 28233548 ps
CPU time 0.81 seconds
Started Jul 06 06:42:14 PM PDT 24
Finished Jul 06 06:42:15 PM PDT 24
Peak memory 205584 kb
Host smart-3909d859-e0d0-4993-8e3a-a05708702caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441875391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.3441875391
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.1629736764
Short name T207
Test name
Test status
Simulation time 93833508315 ps
CPU time 165.85 seconds
Started Jul 06 06:42:22 PM PDT 24
Finished Jul 06 06:45:08 PM PDT 24
Peak memory 249192 kb
Host smart-626ead4c-8957-48d6-a1fd-8b8fe9ce2104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629736764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.1629736764
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.1081473863
Short name T36
Test name
Test status
Simulation time 20674348540 ps
CPU time 105.03 seconds
Started Jul 06 06:42:17 PM PDT 24
Finished Jul 06 06:44:02 PM PDT 24
Peak memory 257472 kb
Host smart-460e2a11-4584-477b-8fb0-d2f0a4558ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081473863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.1081473863
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.2776493187
Short name T661
Test name
Test status
Simulation time 11770251285 ps
CPU time 51.91 seconds
Started Jul 06 06:42:16 PM PDT 24
Finished Jul 06 06:43:09 PM PDT 24
Peak memory 249436 kb
Host smart-8af3a830-af2c-4988-bed6-c8ac147264cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776493187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idl
e.2776493187
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.2575127317
Short name T837
Test name
Test status
Simulation time 1242784799 ps
CPU time 11.79 seconds
Started Jul 06 06:42:17 PM PDT 24
Finished Jul 06 06:42:29 PM PDT 24
Peak memory 240856 kb
Host smart-966feb79-4411-4ad2-87c8-99ad8c6bd511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575127317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.2575127317
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.2766001877
Short name T352
Test name
Test status
Simulation time 12818229 ps
CPU time 0.76 seconds
Started Jul 06 06:42:17 PM PDT 24
Finished Jul 06 06:42:19 PM PDT 24
Peak memory 215816 kb
Host smart-260c156a-5a58-4959-8d9e-a259b3b3568e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2766001877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.2766001877
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.432954102
Short name T840
Test name
Test status
Simulation time 299762487 ps
CPU time 3.13 seconds
Started Jul 06 06:42:11 PM PDT 24
Finished Jul 06 06:42:15 PM PDT 24
Peak memory 232716 kb
Host smart-e2b7052b-ce64-419b-abba-a8e0c691f88d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432954102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.432954102
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3855716092
Short name T676
Test name
Test status
Simulation time 3426571438 ps
CPU time 12.02 seconds
Started Jul 06 06:42:14 PM PDT 24
Finished Jul 06 06:42:27 PM PDT 24
Peak memory 232784 kb
Host smart-5abf8f16-67e0-4683-ba7d-5c34fc8ee543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855716092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3855716092
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.1362696765
Short name T322
Test name
Test status
Simulation time 383568575 ps
CPU time 3.57 seconds
Started Jul 06 06:42:12 PM PDT 24
Finished Jul 06 06:42:16 PM PDT 24
Peak memory 232688 kb
Host smart-6a0c9d94-932b-4ac0-b3bd-8585ea9d34da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362696765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.1362696765
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3903000348
Short name T259
Test name
Test status
Simulation time 2370515161 ps
CPU time 8.29 seconds
Started Jul 06 06:42:10 PM PDT 24
Finished Jul 06 06:42:19 PM PDT 24
Peak memory 224492 kb
Host smart-c5577cb6-b1a3-467a-9e33-3c41eaae9d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903000348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3903000348
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.811690744
Short name T526
Test name
Test status
Simulation time 6922907748 ps
CPU time 10.76 seconds
Started Jul 06 06:42:17 PM PDT 24
Finished Jul 06 06:42:28 PM PDT 24
Peak memory 220564 kb
Host smart-e468a104-35eb-44fb-8088-25be22556116
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=811690744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dire
ct.811690744
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3904548534
Short name T341
Test name
Test status
Simulation time 8316922535 ps
CPU time 44.09 seconds
Started Jul 06 06:42:14 PM PDT 24
Finished Jul 06 06:42:59 PM PDT 24
Peak memory 216312 kb
Host smart-fcf2506b-ab64-4e56-8c4e-d64feeb0686c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904548534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3904548534
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.1129745856
Short name T446
Test name
Test status
Simulation time 1785370698 ps
CPU time 5.16 seconds
Started Jul 06 06:42:12 PM PDT 24
Finished Jul 06 06:42:18 PM PDT 24
Peak memory 216276 kb
Host smart-51ae5dd4-986b-4c7d-8a87-017e1a5ff66b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129745856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.1129745856
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.2792469141
Short name T146
Test name
Test status
Simulation time 157301588 ps
CPU time 2.39 seconds
Started Jul 06 06:42:14 PM PDT 24
Finished Jul 06 06:42:17 PM PDT 24
Peak memory 216260 kb
Host smart-5348d288-c193-48a1-905d-2a0dd62e6c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792469141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.2792469141
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3323895759
Short name T357
Test name
Test status
Simulation time 90911783 ps
CPU time 0.95 seconds
Started Jul 06 06:42:12 PM PDT 24
Finished Jul 06 06:42:14 PM PDT 24
Peak memory 206456 kb
Host smart-cd20027b-f5ab-477a-b58e-dce95c410859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323895759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3323895759
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3001312057
Short name T298
Test name
Test status
Simulation time 3235557058 ps
CPU time 10.21 seconds
Started Jul 06 06:42:16 PM PDT 24
Finished Jul 06 06:42:26 PM PDT 24
Peak memory 229184 kb
Host smart-610f15d4-f1a3-419d-b59c-a8d9cf1a5400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001312057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3001312057
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.1775689373
Short name T497
Test name
Test status
Simulation time 58464589 ps
CPU time 0.78 seconds
Started Jul 06 06:42:22 PM PDT 24
Finished Jul 06 06:42:23 PM PDT 24
Peak memory 205524 kb
Host smart-48bcb8d4-83db-4c7f-9383-8823fb20e55f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775689373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
1775689373
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.3906727380
Short name T818
Test name
Test status
Simulation time 527321318 ps
CPU time 6.24 seconds
Started Jul 06 06:42:21 PM PDT 24
Finished Jul 06 06:42:28 PM PDT 24
Peak memory 224492 kb
Host smart-956fc5ec-75a7-451f-92f1-8d6e25f1628b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3906727380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.3906727380
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.4009502283
Short name T924
Test name
Test status
Simulation time 17876395 ps
CPU time 0.76 seconds
Started Jul 06 06:42:16 PM PDT 24
Finished Jul 06 06:42:17 PM PDT 24
Peak memory 206920 kb
Host smart-a2ad94ea-dee0-4bac-b1db-2a1f25cf61b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009502283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.4009502283
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.3919943183
Short name T284
Test name
Test status
Simulation time 469437507 ps
CPU time 9.23 seconds
Started Jul 06 06:42:25 PM PDT 24
Finished Jul 06 06:42:35 PM PDT 24
Peak memory 232688 kb
Host smart-dd949180-1cac-419e-a161-00ba5c59c73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919943183 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.3919943183
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3772448867
Short name T306
Test name
Test status
Simulation time 17417126264 ps
CPU time 216.88 seconds
Started Jul 06 06:42:22 PM PDT 24
Finished Jul 06 06:45:59 PM PDT 24
Peak memory 265624 kb
Host smart-9ede0211-c0f5-4de6-8a13-2e959d7f5b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772448867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3772448867
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.1523431170
Short name T561
Test name
Test status
Simulation time 14017708899 ps
CPU time 129.65 seconds
Started Jul 06 06:42:23 PM PDT 24
Finished Jul 06 06:44:33 PM PDT 24
Peak memory 268888 kb
Host smart-f0d24850-8926-42c1-9b88-ebc838581e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523431170 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.1523431170
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.320996940
Short name T325
Test name
Test status
Simulation time 6756962542 ps
CPU time 22.86 seconds
Started Jul 06 06:42:21 PM PDT 24
Finished Jul 06 06:42:44 PM PDT 24
Peak memory 224572 kb
Host smart-b413d330-c073-4526-a512-b88ce9a2725c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320996940 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.320996940
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.621754884
Short name T60
Test name
Test status
Simulation time 6146118566 ps
CPU time 78.11 seconds
Started Jul 06 06:42:23 PM PDT 24
Finished Jul 06 06:43:41 PM PDT 24
Peak memory 250336 kb
Host smart-19eb82ab-c8f9-4276-a54a-b9cfb8131a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621754884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmds
.621754884
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.1827807242
Short name T455
Test name
Test status
Simulation time 23794946074 ps
CPU time 17.38 seconds
Started Jul 06 06:42:17 PM PDT 24
Finished Jul 06 06:42:34 PM PDT 24
Peak memory 232788 kb
Host smart-cd58e1a4-536a-4d28-be42-472d02226b72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827807242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.1827807242
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.3536178640
Short name T993
Test name
Test status
Simulation time 285209523 ps
CPU time 2.11 seconds
Started Jul 06 06:42:23 PM PDT 24
Finished Jul 06 06:42:25 PM PDT 24
Peak memory 218580 kb
Host smart-329c6b04-b49c-4225-a856-03f8c5b668e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536178640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.3536178640
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.899354914
Short name T980
Test name
Test status
Simulation time 27544753660 ps
CPU time 24.64 seconds
Started Jul 06 06:42:15 PM PDT 24
Finished Jul 06 06:42:40 PM PDT 24
Peak memory 239964 kb
Host smart-4efa8dc2-e437-40a6-b0aa-9714f94de8db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899354914 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swap
.899354914
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.1995356560
Short name T249
Test name
Test status
Simulation time 2217603584 ps
CPU time 6.78 seconds
Started Jul 06 06:42:19 PM PDT 24
Finished Jul 06 06:42:26 PM PDT 24
Peak memory 232800 kb
Host smart-a866e98f-5fb2-4dda-8ac3-0a0286bf11b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995356560 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.1995356560
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.2380539029
Short name T817
Test name
Test status
Simulation time 3869980088 ps
CPU time 8.23 seconds
Started Jul 06 06:42:22 PM PDT 24
Finished Jul 06 06:42:30 PM PDT 24
Peak memory 220476 kb
Host smart-03a4911b-e98f-4865-b63d-8ee9cd33c84a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2380539029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dir
ect.2380539029
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1889377346
Short name T653
Test name
Test status
Simulation time 6596082586 ps
CPU time 19.61 seconds
Started Jul 06 06:42:24 PM PDT 24
Finished Jul 06 06:42:44 PM PDT 24
Peak memory 232820 kb
Host smart-017d3c8e-6a99-4520-9fb2-eac1f672355e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889377346 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1889377346
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.1572250857
Short name T790
Test name
Test status
Simulation time 7859416435 ps
CPU time 20.81 seconds
Started Jul 06 06:42:17 PM PDT 24
Finished Jul 06 06:42:38 PM PDT 24
Peak memory 218008 kb
Host smart-cc816f7b-6bd6-4612-bd83-5eca4265b600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1572250857 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.1572250857
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.1961770588
Short name T600
Test name
Test status
Simulation time 6087407856 ps
CPU time 20.57 seconds
Started Jul 06 06:42:18 PM PDT 24
Finished Jul 06 06:42:39 PM PDT 24
Peak memory 216280 kb
Host smart-3bc16f55-68c0-42af-afb5-2e737ed9e1b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961770588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.1961770588
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.4154567915
Short name T428
Test name
Test status
Simulation time 351767774 ps
CPU time 6.12 seconds
Started Jul 06 06:42:16 PM PDT 24
Finished Jul 06 06:42:23 PM PDT 24
Peak memory 216236 kb
Host smart-fc42ca8c-b0bf-4705-8a9a-2119fde555b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154567915 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.4154567915
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2680402680
Short name T6
Test name
Test status
Simulation time 91542471 ps
CPU time 0.8 seconds
Started Jul 06 06:42:19 PM PDT 24
Finished Jul 06 06:42:20 PM PDT 24
Peak memory 206012 kb
Host smart-7d087df2-398c-4868-ad51-322725080cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680402680 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2680402680
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1697951441
Short name T868
Test name
Test status
Simulation time 832540334 ps
CPU time 7.97 seconds
Started Jul 06 06:42:22 PM PDT 24
Finished Jul 06 06:42:30 PM PDT 24
Peak memory 232692 kb
Host smart-05478fe0-0a74-4651-98c7-70e75fc6913d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697951441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1697951441
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.3513829918
Short name T438
Test name
Test status
Simulation time 46560614 ps
CPU time 0.7 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:42:32 PM PDT 24
Peak memory 205516 kb
Host smart-8e17cbe0-b822-4077-acc7-e7b5b0686970
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513829918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
3513829918
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.4212864175
Short name T422
Test name
Test status
Simulation time 111502339 ps
CPU time 2.69 seconds
Started Jul 06 06:42:26 PM PDT 24
Finished Jul 06 06:42:29 PM PDT 24
Peak memory 224512 kb
Host smart-081f0927-4bfe-4adf-bd1a-c325032db0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212864175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.4212864175
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.3548774305
Short name T928
Test name
Test status
Simulation time 38711613 ps
CPU time 0.75 seconds
Started Jul 06 06:42:21 PM PDT 24
Finished Jul 06 06:42:23 PM PDT 24
Peak memory 205556 kb
Host smart-c4bab4c5-48f8-48e2-94ea-87cc28de4a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548774305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.3548774305
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.3904582933
Short name T691
Test name
Test status
Simulation time 61615829302 ps
CPU time 55.01 seconds
Started Jul 06 06:42:32 PM PDT 24
Finished Jul 06 06:43:28 PM PDT 24
Peak memory 237220 kb
Host smart-6958ed02-c963-40ed-a1ad-232bf147fc2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904582933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.3904582933
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.603034788
Short name T957
Test name
Test status
Simulation time 8482768634 ps
CPU time 95.9 seconds
Started Jul 06 06:42:27 PM PDT 24
Finished Jul 06 06:44:03 PM PDT 24
Peak memory 257456 kb
Host smart-55e7d2ed-d541-4d29-9cbd-08daa5cd2596
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603034788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.603034788
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.2834009537
Short name T686
Test name
Test status
Simulation time 29273191185 ps
CPU time 99.78 seconds
Started Jul 06 06:42:28 PM PDT 24
Finished Jul 06 06:44:08 PM PDT 24
Peak memory 252860 kb
Host smart-497bced5-8283-4af0-bf3d-ad998bbfeec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834009537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.2834009537
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.1872815193
Short name T651
Test name
Test status
Simulation time 2133251399 ps
CPU time 14.55 seconds
Started Jul 06 06:42:27 PM PDT 24
Finished Jul 06 06:42:42 PM PDT 24
Peak memory 224456 kb
Host smart-be413f24-b685-4852-bf3e-7a1ae8c004e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872815193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.1872815193
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.3228129607
Short name T320
Test name
Test status
Simulation time 202924550580 ps
CPU time 317.36 seconds
Started Jul 06 06:42:27 PM PDT 24
Finished Jul 06 06:47:44 PM PDT 24
Peak memory 265592 kb
Host smart-3154a5a6-2ce6-4b2b-8a5c-0a8731b475f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228129607 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.3228129607
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2418940057
Short name T255
Test name
Test status
Simulation time 802174138 ps
CPU time 6.6 seconds
Started Jul 06 06:42:21 PM PDT 24
Finished Jul 06 06:42:28 PM PDT 24
Peak memory 232604 kb
Host smart-b785e8c8-7bdd-42b8-8a4c-eee1382a75e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418940057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2418940057
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.4289043489
Short name T238
Test name
Test status
Simulation time 9751809745 ps
CPU time 23.41 seconds
Started Jul 06 06:42:27 PM PDT 24
Finished Jul 06 06:42:51 PM PDT 24
Peak memory 224596 kb
Host smart-ba02de40-4da3-452c-8329-08844b6b40ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289043489 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.4289043489
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.1744014391
Short name T710
Test name
Test status
Simulation time 525296147 ps
CPU time 3.14 seconds
Started Jul 06 06:42:25 PM PDT 24
Finished Jul 06 06:42:29 PM PDT 24
Peak memory 224452 kb
Host smart-ab37d688-a91e-4916-8270-4d5684c2eeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744014391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swa
p.1744014391
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.2269106682
Short name T845
Test name
Test status
Simulation time 2271818896 ps
CPU time 9.35 seconds
Started Jul 06 06:42:26 PM PDT 24
Finished Jul 06 06:42:36 PM PDT 24
Peak memory 233900 kb
Host smart-bf3ca694-8bde-4ad7-b481-c7582dbf246e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269106682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.2269106682
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.467718088
Short name T717
Test name
Test status
Simulation time 548986278 ps
CPU time 6.86 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:42:39 PM PDT 24
Peak memory 222512 kb
Host smart-821e5e69-727d-4648-9f44-875efff3ffb8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=467718088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dire
ct.467718088
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2405230830
Short name T634
Test name
Test status
Simulation time 9737058728 ps
CPU time 66.72 seconds
Started Jul 06 06:42:27 PM PDT 24
Finished Jul 06 06:43:34 PM PDT 24
Peak memory 255372 kb
Host smart-ea9e3606-141e-4c80-acdf-6481c542f9bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405230830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2405230830
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3073505582
Short name T384
Test name
Test status
Simulation time 3305332248 ps
CPU time 6.81 seconds
Started Jul 06 06:42:22 PM PDT 24
Finished Jul 06 06:42:29 PM PDT 24
Peak memory 216388 kb
Host smart-3d5c1632-373a-4543-80aa-37021bf2f0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073505582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3073505582
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.3333855368
Short name T431
Test name
Test status
Simulation time 17732436702 ps
CPU time 17.65 seconds
Started Jul 06 06:42:21 PM PDT 24
Finished Jul 06 06:42:39 PM PDT 24
Peak memory 216376 kb
Host smart-ab4e094e-889b-46d0-8cf7-7d209bad5ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333855368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.3333855368
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.4146310627
Short name T716
Test name
Test status
Simulation time 42810217 ps
CPU time 1.6 seconds
Started Jul 06 06:42:26 PM PDT 24
Finished Jul 06 06:42:28 PM PDT 24
Peak memory 216264 kb
Host smart-9a2255a1-9b80-4761-b234-6a4fcc22e273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4146310627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.4146310627
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.2219507177
Short name T391
Test name
Test status
Simulation time 90426155 ps
CPU time 0.83 seconds
Started Jul 06 06:42:20 PM PDT 24
Finished Jul 06 06:42:21 PM PDT 24
Peak memory 206352 kb
Host smart-3b6c21bb-52e5-4433-8691-77e0ba2574c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2219507177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.2219507177
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.2713033319
Short name T299
Test name
Test status
Simulation time 1674815549 ps
CPU time 5.81 seconds
Started Jul 06 06:42:27 PM PDT 24
Finished Jul 06 06:42:33 PM PDT 24
Peak memory 232660 kb
Host smart-47f651f9-2d3c-41b1-99fb-92fd32a902d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713033319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.2713033319
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.3992125079
Short name T424
Test name
Test status
Simulation time 43382296 ps
CPU time 0.77 seconds
Started Jul 06 06:42:30 PM PDT 24
Finished Jul 06 06:42:31 PM PDT 24
Peak memory 205544 kb
Host smart-cc341363-d060-4874-80eb-b9824a63a6a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992125079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
3992125079
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.3960973678
Short name T379
Test name
Test status
Simulation time 950900658 ps
CPU time 4.13 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:42:36 PM PDT 24
Peak memory 224472 kb
Host smart-3dd33fd4-efb9-40f6-8914-e0cdd48c5365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960973678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.3960973678
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.3521844497
Short name T963
Test name
Test status
Simulation time 19495425 ps
CPU time 0.79 seconds
Started Jul 06 06:42:30 PM PDT 24
Finished Jul 06 06:42:32 PM PDT 24
Peak memory 206952 kb
Host smart-6eb576a0-4a8a-45e4-bb1c-b6dac31c68c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3521844497 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.3521844497
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.2523946693
Short name T592
Test name
Test status
Simulation time 13229434544 ps
CPU time 54.95 seconds
Started Jul 06 06:42:33 PM PDT 24
Finished Jul 06 06:43:28 PM PDT 24
Peak memory 257348 kb
Host smart-c9db732d-b54d-4b7f-8e90-d62d327e8da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523946693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.2523946693
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3902310277
Short name T970
Test name
Test status
Simulation time 13834067066 ps
CPU time 19.24 seconds
Started Jul 06 06:42:30 PM PDT 24
Finished Jul 06 06:42:49 PM PDT 24
Peak memory 219672 kb
Host smart-a9716aeb-d460-41d7-8146-2fe3de411f87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902310277 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3902310277
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4004526020
Short name T990
Test name
Test status
Simulation time 47518597589 ps
CPU time 158.95 seconds
Started Jul 06 06:42:32 PM PDT 24
Finished Jul 06 06:45:11 PM PDT 24
Peak memory 253904 kb
Host smart-59bfdf07-16ce-4b0f-b0cc-e8329f5955f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004526020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4004526020
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.4101315017
Short name T370
Test name
Test status
Simulation time 538784209 ps
CPU time 5.87 seconds
Started Jul 06 06:42:27 PM PDT 24
Finished Jul 06 06:42:33 PM PDT 24
Peak memory 238724 kb
Host smart-61726cad-6e31-4a4d-a5da-02fc12ac469f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101315017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.4101315017
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1218752299
Short name T946
Test name
Test status
Simulation time 925730196 ps
CPU time 4.51 seconds
Started Jul 06 06:42:26 PM PDT 24
Finished Jul 06 06:42:30 PM PDT 24
Peak memory 224696 kb
Host smart-c2e824f2-5d5e-4e3d-90b1-edd510952810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218752299 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1218752299
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.3417522759
Short name T265
Test name
Test status
Simulation time 11278340042 ps
CPU time 23.28 seconds
Started Jul 06 06:42:26 PM PDT 24
Finished Jul 06 06:42:49 PM PDT 24
Peak memory 232824 kb
Host smart-3c40fdb9-58fe-4a41-a409-55462aef708c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417522759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.3417522759
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.3279966289
Short name T959
Test name
Test status
Simulation time 6203985107 ps
CPU time 8.96 seconds
Started Jul 06 06:42:29 PM PDT 24
Finished Jul 06 06:42:38 PM PDT 24
Peak memory 224596 kb
Host smart-b0a35d5f-4e72-4322-9b9d-78b0f766123f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279966289 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swa
p.3279966289
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.4086024205
Short name T769
Test name
Test status
Simulation time 2397650410 ps
CPU time 3.82 seconds
Started Jul 06 06:42:27 PM PDT 24
Finished Jul 06 06:42:31 PM PDT 24
Peak memory 232788 kb
Host smart-bab92351-b57c-4e2b-953f-a21e1f71ebbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4086024205 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.4086024205
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.2170684336
Short name T569
Test name
Test status
Simulation time 1126001000 ps
CPU time 14.43 seconds
Started Jul 06 06:42:30 PM PDT 24
Finished Jul 06 06:42:45 PM PDT 24
Peak memory 222156 kb
Host smart-f1574a5b-70ff-4f30-93c3-178793b98621
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2170684336 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.2170684336
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1545254968
Short name T544
Test name
Test status
Simulation time 129428074230 ps
CPU time 34.8 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:43:07 PM PDT 24
Peak memory 216324 kb
Host smart-6f04f8e2-3c80-454f-a0e1-83ca6e28ac8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545254968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1545254968
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.338901099
Short name T983
Test name
Test status
Simulation time 666067080 ps
CPU time 5.03 seconds
Started Jul 06 06:42:26 PM PDT 24
Finished Jul 06 06:42:31 PM PDT 24
Peak memory 216216 kb
Host smart-6a78f489-561d-4325-8254-6e98eecf0a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338901099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.338901099
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.4160831589
Short name T654
Test name
Test status
Simulation time 57566757 ps
CPU time 1.03 seconds
Started Jul 06 06:42:29 PM PDT 24
Finished Jul 06 06:42:30 PM PDT 24
Peak memory 207024 kb
Host smart-3c894de2-6427-4f45-a8d2-feb0f633b96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160831589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.4160831589
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2659459768
Short name T739
Test name
Test status
Simulation time 21912658 ps
CPU time 0.77 seconds
Started Jul 06 06:42:30 PM PDT 24
Finished Jul 06 06:42:31 PM PDT 24
Peak memory 206008 kb
Host smart-6e1ef120-07ea-4568-b939-82ae34e65585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2659459768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2659459768
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.2989735293
Short name T268
Test name
Test status
Simulation time 848057892 ps
CPU time 5.49 seconds
Started Jul 06 06:42:27 PM PDT 24
Finished Jul 06 06:42:33 PM PDT 24
Peak memory 232692 kb
Host smart-bcbf5dae-2423-4d2f-9dfa-b2cb3fa2f814
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989735293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.2989735293
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3733626960
Short name T896
Test name
Test status
Simulation time 15856383 ps
CPU time 0.73 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:42:32 PM PDT 24
Peak memory 205508 kb
Host smart-48f9ee4d-4aa7-40eb-b366-1874116d17ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733626960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3733626960
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.3458009119
Short name T832
Test name
Test status
Simulation time 336572013 ps
CPU time 2.94 seconds
Started Jul 06 06:42:33 PM PDT 24
Finished Jul 06 06:42:36 PM PDT 24
Peak memory 224436 kb
Host smart-022c348b-bbd7-4711-8667-fa56bbdc1616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458009119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.3458009119
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.60848421
Short name T559
Test name
Test status
Simulation time 37332833 ps
CPU time 0.82 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:42:33 PM PDT 24
Peak memory 206612 kb
Host smart-5afa5e15-8c29-4d86-8c56-f2b2c46147ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60848421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.60848421
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.3324412748
Short name T1007
Test name
Test status
Simulation time 203523365313 ps
CPU time 353.17 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:48:25 PM PDT 24
Peak memory 254768 kb
Host smart-dbbaf673-6f7f-4ac4-8874-728f28698f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324412748 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.3324412748
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.129126458
Short name T799
Test name
Test status
Simulation time 147398155165 ps
CPU time 94.57 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:44:06 PM PDT 24
Peak memory 248308 kb
Host smart-76a4842b-a14b-437c-acf4-ba7fef9f8054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129126458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idle
.129126458
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.3850362175
Short name T1003
Test name
Test status
Simulation time 810514093 ps
CPU time 9.79 seconds
Started Jul 06 06:42:30 PM PDT 24
Finished Jul 06 06:42:40 PM PDT 24
Peak memory 240312 kb
Host smart-c1158b19-da37-4071-8535-66af2134c851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850362175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.3850362175
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3185851653
Short name T866
Test name
Test status
Simulation time 172498666614 ps
CPU time 276.49 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:47:09 PM PDT 24
Peak memory 252924 kb
Host smart-aa751a85-c850-4f50-b4f3-3cbb4c65c748
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185851653 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3185851653
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.474631136
Short name T816
Test name
Test status
Simulation time 6695130333 ps
CPU time 17.5 seconds
Started Jul 06 06:42:33 PM PDT 24
Finished Jul 06 06:42:51 PM PDT 24
Peak memory 232780 kb
Host smart-9d50e4c2-39dc-4cf8-9220-dab9095a6caa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=474631136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.474631136
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.3026792898
Short name T546
Test name
Test status
Simulation time 49460559649 ps
CPU time 97.89 seconds
Started Jul 06 06:42:33 PM PDT 24
Finished Jul 06 06:44:11 PM PDT 24
Peak memory 224588 kb
Host smart-9ef8ff0b-0264-42b6-8d4f-326730207dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026792898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.3026792898
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.4205925286
Short name T13
Test name
Test status
Simulation time 462123719 ps
CPU time 3.68 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:42:36 PM PDT 24
Peak memory 232704 kb
Host smart-3c09f0b0-addd-4b4d-abf3-aec1efefe105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4205925286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.4205925286
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.3826843107
Short name T937
Test name
Test status
Simulation time 353337777 ps
CPU time 2.31 seconds
Started Jul 06 06:42:32 PM PDT 24
Finished Jul 06 06:42:35 PM PDT 24
Peak memory 224436 kb
Host smart-82225a3d-d516-47ed-bf64-8d35867f5e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826843107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.3826843107
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.3113595375
Short name T58
Test name
Test status
Simulation time 416980982 ps
CPU time 3.83 seconds
Started Jul 06 06:42:32 PM PDT 24
Finished Jul 06 06:42:37 PM PDT 24
Peak memory 222612 kb
Host smart-10866418-38e2-439f-b11b-d18cb1d97a8e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3113595375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dir
ect.3113595375
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.1014921951
Short name T586
Test name
Test status
Simulation time 178293287 ps
CPU time 0.98 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:42:33 PM PDT 24
Peak memory 206764 kb
Host smart-93b59278-cd96-4edb-a93a-b3984f71cdfa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1014921951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.1014921951
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3066647051
Short name T803
Test name
Test status
Simulation time 19209823 ps
CPU time 0.72 seconds
Started Jul 06 06:42:33 PM PDT 24
Finished Jul 06 06:42:34 PM PDT 24
Peak memory 205744 kb
Host smart-f695a716-39e2-4b3c-8683-b6bf08cacb3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3066647051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3066647051
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.2830633432
Short name T754
Test name
Test status
Simulation time 5615167523 ps
CPU time 17.01 seconds
Started Jul 06 06:42:32 PM PDT 24
Finished Jul 06 06:42:50 PM PDT 24
Peak memory 216320 kb
Host smart-c587bd0e-9070-4511-a301-5cd7412960b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830633432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.2830633432
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.1607609520
Short name T670
Test name
Test status
Simulation time 43153729 ps
CPU time 0.67 seconds
Started Jul 06 06:42:32 PM PDT 24
Finished Jul 06 06:42:33 PM PDT 24
Peak memory 205644 kb
Host smart-93d48202-095d-4cbb-b714-f5ff127f6279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607609520 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.1607609520
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.2976996983
Short name T408
Test name
Test status
Simulation time 40878345 ps
CPU time 0.85 seconds
Started Jul 06 06:42:30 PM PDT 24
Finished Jul 06 06:42:31 PM PDT 24
Peak memory 205984 kb
Host smart-7788427b-100e-4068-9cbe-a89d40dfe68a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976996983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.2976996983
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.3514309570
Short name T894
Test name
Test status
Simulation time 1723154259 ps
CPU time 6.51 seconds
Started Jul 06 06:42:30 PM PDT 24
Finished Jul 06 06:42:37 PM PDT 24
Peak memory 224552 kb
Host smart-4bfb9603-b366-44ca-a971-b08c3943b2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514309570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.3514309570
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.3775917385
Short name T403
Test name
Test status
Simulation time 13300109 ps
CPU time 0.75 seconds
Started Jul 06 06:42:40 PM PDT 24
Finished Jul 06 06:42:41 PM PDT 24
Peak memory 205000 kb
Host smart-1970e53e-441a-411c-ab63-d30207707bcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3775917385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.
3775917385
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1960135096
Short name T628
Test name
Test status
Simulation time 1973926497 ps
CPU time 17.8 seconds
Started Jul 06 06:42:37 PM PDT 24
Finished Jul 06 06:42:55 PM PDT 24
Peak memory 224452 kb
Host smart-4e9e7220-e68c-40d7-abe2-379afa325b0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960135096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1960135096
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.2187100452
Short name T814
Test name
Test status
Simulation time 115145356 ps
CPU time 0.76 seconds
Started Jul 06 06:42:31 PM PDT 24
Finished Jul 06 06:42:32 PM PDT 24
Peak memory 206624 kb
Host smart-ffdbf6b6-fca3-4888-bc00-4dd1299b060a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187100452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.2187100452
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2267835550
Short name T785
Test name
Test status
Simulation time 6313083760 ps
CPU time 57.4 seconds
Started Jul 06 06:42:34 PM PDT 24
Finished Jul 06 06:43:32 PM PDT 24
Peak memory 249192 kb
Host smart-8258e84c-00bb-404e-9dbb-3995dd3756fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267835550 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2267835550
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.3408568283
Short name T728
Test name
Test status
Simulation time 4611600695 ps
CPU time 74.31 seconds
Started Jul 06 06:42:36 PM PDT 24
Finished Jul 06 06:43:51 PM PDT 24
Peak memory 253088 kb
Host smart-9120341a-69c4-4a23-bb8c-25d55a0f88f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408568283 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.3408568283
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.1336489499
Short name T820
Test name
Test status
Simulation time 817160918 ps
CPU time 4.98 seconds
Started Jul 06 06:42:35 PM PDT 24
Finished Jul 06 06:42:41 PM PDT 24
Peak memory 232640 kb
Host smart-146c8da3-c9fd-4f07-a8c9-5cbb2b81c53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1336489499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.1336489499
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.3202481740
Short name T1000
Test name
Test status
Simulation time 79445875805 ps
CPU time 115.74 seconds
Started Jul 06 06:42:39 PM PDT 24
Finished Jul 06 06:44:35 PM PDT 24
Peak memory 255684 kb
Host smart-22138cab-d2ae-4d41-97c4-3a6dc7dff47b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202481740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.3202481740
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.1945734685
Short name T273
Test name
Test status
Simulation time 1945406264 ps
CPU time 8.35 seconds
Started Jul 06 06:42:36 PM PDT 24
Finished Jul 06 06:42:45 PM PDT 24
Peak memory 232664 kb
Host smart-44a693c9-1938-4df2-b08a-d8d767261ccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945734685 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.1945734685
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.1191069893
Short name T770
Test name
Test status
Simulation time 5208987510 ps
CPU time 47.3 seconds
Started Jul 06 06:42:36 PM PDT 24
Finished Jul 06 06:43:24 PM PDT 24
Peak memory 249200 kb
Host smart-7031e042-a281-4c9d-aa6f-50f58c9f7190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1191069893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.1191069893
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.4155802343
Short name T949
Test name
Test status
Simulation time 24495326106 ps
CPU time 18.3 seconds
Started Jul 06 06:42:38 PM PDT 24
Finished Jul 06 06:42:57 PM PDT 24
Peak memory 229112 kb
Host smart-63ceb68d-9e07-43dc-b532-43ff5f525728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155802343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.4155802343
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3366951368
Short name T230
Test name
Test status
Simulation time 1531778055 ps
CPU time 9.01 seconds
Started Jul 06 06:42:37 PM PDT 24
Finished Jul 06 06:42:46 PM PDT 24
Peak memory 224516 kb
Host smart-fb109d97-3162-4d02-a852-dc2c1c74a37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366951368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3366951368
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.301057969
Short name T938
Test name
Test status
Simulation time 163181996 ps
CPU time 3.47 seconds
Started Jul 06 06:42:35 PM PDT 24
Finished Jul 06 06:42:39 PM PDT 24
Peak memory 223548 kb
Host smart-8bab7f94-fbe1-40b4-8418-c08ad006ca7d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=301057969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_dire
ct.301057969
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.1667006503
Short name T635
Test name
Test status
Simulation time 242905673 ps
CPU time 1.02 seconds
Started Jul 06 06:42:35 PM PDT 24
Finished Jul 06 06:42:36 PM PDT 24
Peak memory 207748 kb
Host smart-5e864b32-6aff-4b79-b140-4e772132016f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667006503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.1667006503
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.3609964601
Short name T541
Test name
Test status
Simulation time 29739686788 ps
CPU time 16.09 seconds
Started Jul 06 06:42:35 PM PDT 24
Finished Jul 06 06:42:52 PM PDT 24
Peak memory 216296 kb
Host smart-adc600f5-d0c9-434f-bd6d-71cd3f12d0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3609964601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.3609964601
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.190998946
Short name T668
Test name
Test status
Simulation time 2788749417 ps
CPU time 2.18 seconds
Started Jul 06 06:42:36 PM PDT 24
Finished Jul 06 06:42:39 PM PDT 24
Peak memory 208020 kb
Host smart-ac247eac-ecf5-4fb7-84d8-bd9c65ef2c77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=190998946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.190998946
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.1768028047
Short name T664
Test name
Test status
Simulation time 18064189 ps
CPU time 0.75 seconds
Started Jul 06 06:42:38 PM PDT 24
Finished Jul 06 06:42:39 PM PDT 24
Peak memory 205980 kb
Host smart-73e41443-619a-4d16-bcf6-244e155a3598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768028047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.1768028047
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.3149625642
Short name T797
Test name
Test status
Simulation time 23578396 ps
CPU time 0.76 seconds
Started Jul 06 06:42:41 PM PDT 24
Finished Jul 06 06:42:42 PM PDT 24
Peak memory 205940 kb
Host smart-3ab1e962-cc8a-44c7-bc85-ef8730c8f694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149625642 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.3149625642
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.512844439
Short name T548
Test name
Test status
Simulation time 23795633248 ps
CPU time 20.73 seconds
Started Jul 06 06:42:37 PM PDT 24
Finished Jul 06 06:42:58 PM PDT 24
Peak memory 232756 kb
Host smart-ad0b8fae-7643-48bb-a6a9-496c729cc84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512844439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.512844439
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.1269809351
Short name T387
Test name
Test status
Simulation time 42356216 ps
CPU time 0.7 seconds
Started Jul 06 06:42:39 PM PDT 24
Finished Jul 06 06:42:40 PM PDT 24
Peak memory 205772 kb
Host smart-06061235-d581-43ad-becd-cedfc7b8ca09
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269809351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
1269809351
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.2497482517
Short name T376
Test name
Test status
Simulation time 1196543388 ps
CPU time 10.05 seconds
Started Jul 06 06:42:41 PM PDT 24
Finished Jul 06 06:42:52 PM PDT 24
Peak memory 232680 kb
Host smart-2ea6bfa0-027d-4057-961d-1e2e612a624d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497482517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.2497482517
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.358896817
Short name T764
Test name
Test status
Simulation time 18054103 ps
CPU time 0.82 seconds
Started Jul 06 06:42:41 PM PDT 24
Finished Jul 06 06:42:43 PM PDT 24
Peak memory 206952 kb
Host smart-4da979db-419d-4974-9f66-8fe56f149b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358896817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.358896817
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.2895973618
Short name T193
Test name
Test status
Simulation time 180758664220 ps
CPU time 133.6 seconds
Started Jul 06 06:42:40 PM PDT 24
Finished Jul 06 06:44:54 PM PDT 24
Peak memory 250240 kb
Host smart-85a28e0d-174a-4631-92ba-d3b97e74d9e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895973618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.2895973618
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.1921578395
Short name T447
Test name
Test status
Simulation time 18145101673 ps
CPU time 143.44 seconds
Started Jul 06 06:42:42 PM PDT 24
Finished Jul 06 06:45:06 PM PDT 24
Peak memory 247992 kb
Host smart-033a9ae6-a4eb-4947-8e9c-eb11a395ff5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921578395 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.1921578395
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.1142655926
Short name T229
Test name
Test status
Simulation time 368325871983 ps
CPU time 830.63 seconds
Started Jul 06 06:42:46 PM PDT 24
Finished Jul 06 06:56:37 PM PDT 24
Peak memory 264800 kb
Host smart-6abfff3f-b0ac-4f55-b0de-950eae66785b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142655926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idl
e.1142655926
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.4080001177
Short name T367
Test name
Test status
Simulation time 122005408 ps
CPU time 2.35 seconds
Started Jul 06 06:42:44 PM PDT 24
Finished Jul 06 06:42:47 PM PDT 24
Peak memory 224496 kb
Host smart-0778784e-a4b7-4160-8049-2f18b81f82b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080001177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.4080001177
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.2898122691
Short name T414
Test name
Test status
Simulation time 19111723776 ps
CPU time 150.69 seconds
Started Jul 06 06:42:41 PM PDT 24
Finished Jul 06 06:45:13 PM PDT 24
Peak memory 257260 kb
Host smart-47dc495a-32e3-4931-a16e-6c04cb672fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898122691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmd
s.2898122691
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/39.spi_device_intercept.594650234
Short name T389
Test name
Test status
Simulation time 6052114647 ps
CPU time 4.53 seconds
Started Jul 06 06:42:41 PM PDT 24
Finished Jul 06 06:42:46 PM PDT 24
Peak memory 224524 kb
Host smart-ea8d5900-fa5c-4f2a-8307-cd63b7890515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594650234 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.594650234
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.497065764
Short name T652
Test name
Test status
Simulation time 9221964490 ps
CPU time 34.99 seconds
Started Jul 06 06:42:41 PM PDT 24
Finished Jul 06 06:43:17 PM PDT 24
Peak memory 232872 kb
Host smart-4bb81fe6-5810-4a7a-ab17-ef6785477992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497065764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.497065764
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.2730298482
Short name T850
Test name
Test status
Simulation time 1989421787 ps
CPU time 9.27 seconds
Started Jul 06 06:42:40 PM PDT 24
Finished Jul 06 06:42:50 PM PDT 24
Peak memory 232572 kb
Host smart-0a3feb5b-2364-4b7f-a2ad-1399398d019a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730298482 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.2730298482
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.3908317788
Short name T971
Test name
Test status
Simulation time 36191048439 ps
CPU time 20.58 seconds
Started Jul 06 06:42:40 PM PDT 24
Finished Jul 06 06:43:01 PM PDT 24
Peak memory 232776 kb
Host smart-38ce66a3-d73e-479b-9e3a-1261f7baf37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908317788 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.3908317788
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.2808115647
Short name T648
Test name
Test status
Simulation time 1363490310 ps
CPU time 8.96 seconds
Started Jul 06 06:42:42 PM PDT 24
Finished Jul 06 06:42:51 PM PDT 24
Peak memory 218312 kb
Host smart-3d3691b1-d256-463d-a69d-97059e65d929
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2808115647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.2808115647
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.3519934531
Short name T21
Test name
Test status
Simulation time 185808438 ps
CPU time 0.93 seconds
Started Jul 06 06:42:41 PM PDT 24
Finished Jul 06 06:42:43 PM PDT 24
Peak memory 207512 kb
Host smart-b855d659-8dde-4d1c-ac92-ea87f06f7e9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519934531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stre
ss_all.3519934531
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.3924263066
Short name T435
Test name
Test status
Simulation time 7327796475 ps
CPU time 20.41 seconds
Started Jul 06 06:42:41 PM PDT 24
Finished Jul 06 06:43:02 PM PDT 24
Peak memory 216432 kb
Host smart-c642b3ff-e641-48a3-80e3-57c5511c8901
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924263066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.3924263066
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.560230939
Short name T903
Test name
Test status
Simulation time 13618627 ps
CPU time 0.77 seconds
Started Jul 06 06:42:45 PM PDT 24
Finished Jul 06 06:42:46 PM PDT 24
Peak memory 205664 kb
Host smart-5290e2de-6789-4640-873c-aab9f8f7e941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560230939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.560230939
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.611109017
Short name T987
Test name
Test status
Simulation time 907378443 ps
CPU time 1.79 seconds
Started Jul 06 06:42:38 PM PDT 24
Finished Jul 06 06:42:41 PM PDT 24
Peak memory 216260 kb
Host smart-fb9dc7b6-d20a-4b1e-ac52-dbb3de93755f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611109017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.611109017
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.3375510401
Short name T658
Test name
Test status
Simulation time 13393180 ps
CPU time 0.72 seconds
Started Jul 06 06:42:40 PM PDT 24
Finished Jul 06 06:42:41 PM PDT 24
Peak memory 206012 kb
Host smart-cd43339b-c35d-4cf6-839f-d115ee3cc0e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375510401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.3375510401
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.4219137655
Short name T49
Test name
Test status
Simulation time 4788891098 ps
CPU time 8.55 seconds
Started Jul 06 06:42:43 PM PDT 24
Finished Jul 06 06:42:52 PM PDT 24
Peak memory 224544 kb
Host smart-ce07e954-055d-40ca-ade0-04f7e28487b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219137655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.4219137655
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.43012190
Short name T783
Test name
Test status
Simulation time 58088553 ps
CPU time 0.67 seconds
Started Jul 06 06:39:52 PM PDT 24
Finished Jul 06 06:39:53 PM PDT 24
Peak memory 204988 kb
Host smart-d0fb2c1c-552b-4011-a140-28e8c9d17044
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43012190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.43012190
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.343065987
Short name T371
Test name
Test status
Simulation time 5253054778 ps
CPU time 15.66 seconds
Started Jul 06 06:39:51 PM PDT 24
Finished Jul 06 06:40:06 PM PDT 24
Peak memory 232880 kb
Host smart-37658249-499c-405e-b4a3-dc654a91ed22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343065987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.343065987
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.104463179
Short name T555
Test name
Test status
Simulation time 23441125 ps
CPU time 0.76 seconds
Started Jul 06 06:39:48 PM PDT 24
Finished Jul 06 06:39:49 PM PDT 24
Peak memory 206616 kb
Host smart-c6295505-4da0-4277-be46-12198ddb14a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104463179 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.104463179
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.541976180
Short name T321
Test name
Test status
Simulation time 277077595616 ps
CPU time 471.71 seconds
Started Jul 06 06:39:53 PM PDT 24
Finished Jul 06 06:47:45 PM PDT 24
Peak memory 265072 kb
Host smart-28ad131c-62ec-4d29-9547-891c2c1a412b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541976180 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.541976180
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.203456091
Short name T55
Test name
Test status
Simulation time 30378955957 ps
CPU time 276.34 seconds
Started Jul 06 06:39:52 PM PDT 24
Finished Jul 06 06:44:29 PM PDT 24
Peak memory 268020 kb
Host smart-1332932d-04f9-434c-bae2-411748ac7a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203456091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle.
203456091
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.1047560443
Short name T330
Test name
Test status
Simulation time 566865939 ps
CPU time 16.3 seconds
Started Jul 06 06:39:52 PM PDT 24
Finished Jul 06 06:40:09 PM PDT 24
Peak memory 240616 kb
Host smart-caa17be4-bcf9-49ac-a71c-d3dee48e62ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047560443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.1047560443
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.1503078810
Short name T12
Test name
Test status
Simulation time 11581938299 ps
CPU time 116.73 seconds
Started Jul 06 06:39:51 PM PDT 24
Finished Jul 06 06:41:48 PM PDT 24
Peak memory 257360 kb
Host smart-f6da58a5-ecc9-458b-8319-b8e87bbeb6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503078810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds
.1503078810
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.563109109
Short name T219
Test name
Test status
Simulation time 4442416468 ps
CPU time 10.24 seconds
Started Jul 06 06:39:50 PM PDT 24
Finished Jul 06 06:40:01 PM PDT 24
Peak memory 232792 kb
Host smart-706156a9-94a9-4969-96b0-46f05fa121fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563109109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.563109109
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.1434053721
Short name T882
Test name
Test status
Simulation time 12545019937 ps
CPU time 136.66 seconds
Started Jul 06 06:39:52 PM PDT 24
Finished Jul 06 06:42:09 PM PDT 24
Peak memory 234948 kb
Host smart-e5dd3a2e-8516-4dfa-8fd0-abd2c8b30c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1434053721 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.1434053721
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.3097152165
Short name T474
Test name
Test status
Simulation time 8735345314 ps
CPU time 12.61 seconds
Started Jul 06 06:39:48 PM PDT 24
Finished Jul 06 06:40:01 PM PDT 24
Peak memory 232780 kb
Host smart-49be449e-8b3d-45b1-a2f5-6f67a15f2807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3097152165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap
.3097152165
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1058760753
Short name T212
Test name
Test status
Simulation time 7817272443 ps
CPU time 23.96 seconds
Started Jul 06 06:39:47 PM PDT 24
Finished Jul 06 06:40:11 PM PDT 24
Peak memory 240964 kb
Host smart-a6178aa5-e05f-427a-860e-c203e4127fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058760753 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1058760753
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.689958120
Short name T441
Test name
Test status
Simulation time 2958182303 ps
CPU time 9.85 seconds
Started Jul 06 06:39:53 PM PDT 24
Finished Jul 06 06:40:03 PM PDT 24
Peak memory 219744 kb
Host smart-b84bcefd-ecd1-4434-8ead-a484b14d08b7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=689958120 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_direc
t.689958120
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2970067054
Short name T85
Test name
Test status
Simulation time 423911590 ps
CPU time 1.19 seconds
Started Jul 06 06:39:50 PM PDT 24
Finished Jul 06 06:39:52 PM PDT 24
Peak memory 237628 kb
Host smart-e390f2d4-22c9-42b8-a996-89489df0a47a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970067054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2970067054
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.1244865312
Short name T170
Test name
Test status
Simulation time 41455080224 ps
CPU time 291.72 seconds
Started Jul 06 06:39:52 PM PDT 24
Finished Jul 06 06:44:44 PM PDT 24
Peak memory 270208 kb
Host smart-3a4e492e-15a7-43ec-8ef5-ca1e1e2a75e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244865312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stres
s_all.1244865312
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3258189091
Short name T721
Test name
Test status
Simulation time 1172937764 ps
CPU time 9.87 seconds
Started Jul 06 06:39:46 PM PDT 24
Finished Jul 06 06:39:56 PM PDT 24
Peak memory 218992 kb
Host smart-73ce0710-914f-4c97-8d8c-c1caa174a8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258189091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3258189091
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.2126004461
Short name T369
Test name
Test status
Simulation time 87881611 ps
CPU time 1.12 seconds
Started Jul 06 06:39:46 PM PDT 24
Finished Jul 06 06:39:47 PM PDT 24
Peak memory 207892 kb
Host smart-c032cd89-86af-40da-b4aa-d652618ae647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126004461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.2126004461
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.464261986
Short name T962
Test name
Test status
Simulation time 1199144152 ps
CPU time 8.43 seconds
Started Jul 06 06:39:47 PM PDT 24
Finished Jul 06 06:39:56 PM PDT 24
Peak memory 216160 kb
Host smart-0e233e2f-2990-44f0-b6d6-86a1e3abc397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=464261986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.464261986
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.353139845
Short name T95
Test name
Test status
Simulation time 226108553 ps
CPU time 0.85 seconds
Started Jul 06 06:39:46 PM PDT 24
Finished Jul 06 06:39:48 PM PDT 24
Peak memory 205964 kb
Host smart-472f96ac-9eec-4783-aaff-25aa2551e022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353139845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.353139845
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.3553358098
Short name T502
Test name
Test status
Simulation time 4595996416 ps
CPU time 14.96 seconds
Started Jul 06 06:39:53 PM PDT 24
Finished Jul 06 06:40:09 PM PDT 24
Peak memory 232768 kb
Host smart-675e93e6-e3cf-4921-8cba-f5c4c292b951
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553358098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.3553358098
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.3245578702
Short name T511
Test name
Test status
Simulation time 13367479 ps
CPU time 0.7 seconds
Started Jul 06 06:42:46 PM PDT 24
Finished Jul 06 06:42:47 PM PDT 24
Peak memory 205000 kb
Host smart-335cab41-c86d-4616-bfe0-8c8c9fa08e54
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245578702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
3245578702
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.708518392
Short name T776
Test name
Test status
Simulation time 72782311 ps
CPU time 2.55 seconds
Started Jul 06 06:42:48 PM PDT 24
Finished Jul 06 06:42:51 PM PDT 24
Peak memory 232680 kb
Host smart-13239075-d641-4cda-a854-05dd83779a35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708518392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.708518392
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.3979259354
Short name T361
Test name
Test status
Simulation time 15549116 ps
CPU time 0.78 seconds
Started Jul 06 06:42:39 PM PDT 24
Finished Jul 06 06:42:40 PM PDT 24
Peak memory 206876 kb
Host smart-10515c47-b751-4141-84f5-df539398ab85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3979259354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.3979259354
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.1242575751
Short name T669
Test name
Test status
Simulation time 6911826474 ps
CPU time 39.15 seconds
Started Jul 06 06:42:47 PM PDT 24
Finished Jul 06 06:43:27 PM PDT 24
Peak memory 252700 kb
Host smart-7a9a8ad2-a309-44b5-bf4e-a3a85db7597a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242575751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.1242575751
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.3598904034
Short name T318
Test name
Test status
Simulation time 22053628260 ps
CPU time 100.04 seconds
Started Jul 06 06:42:50 PM PDT 24
Finished Jul 06 06:44:30 PM PDT 24
Peak memory 253256 kb
Host smart-d2166b06-7af3-4da8-b9d8-4262e8ac3c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598904034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.3598904034
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1633705562
Short name T295
Test name
Test status
Simulation time 21981180784 ps
CPU time 47.21 seconds
Started Jul 06 06:42:45 PM PDT 24
Finished Jul 06 06:43:32 PM PDT 24
Peak memory 233920 kb
Host smart-e5fab653-7054-4815-977b-4a5ef138b226
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1633705562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1633705562
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.3810295561
Short name T578
Test name
Test status
Simulation time 2637928716 ps
CPU time 5.71 seconds
Started Jul 06 06:42:48 PM PDT 24
Finished Jul 06 06:42:54 PM PDT 24
Peak memory 224508 kb
Host smart-eee7c5b9-6dd4-4a99-a976-d078b6c52ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810295561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.3810295561
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.999397666
Short name T194
Test name
Test status
Simulation time 19038010555 ps
CPU time 95.21 seconds
Started Jul 06 06:42:44 PM PDT 24
Finished Jul 06 06:44:20 PM PDT 24
Peak memory 254684 kb
Host smart-c4ebde3c-0e7f-48dc-bf6b-9bcefa9bb073
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=999397666 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds
.999397666
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.124784897
Short name T605
Test name
Test status
Simulation time 1171824994 ps
CPU time 14.83 seconds
Started Jul 06 06:42:45 PM PDT 24
Finished Jul 06 06:43:00 PM PDT 24
Peak memory 224508 kb
Host smart-e2452802-bb72-42de-a731-7047ec7d67a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=124784897 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.124784897
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.567407433
Short name T986
Test name
Test status
Simulation time 1547409082 ps
CPU time 11.62 seconds
Started Jul 06 06:42:44 PM PDT 24
Finished Jul 06 06:42:56 PM PDT 24
Peak memory 224548 kb
Host smart-3b47fc17-156b-4688-b2a7-2590fc615190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=567407433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.567407433
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.2387793108
Short name T323
Test name
Test status
Simulation time 2381806073 ps
CPU time 11.49 seconds
Started Jul 06 06:42:45 PM PDT 24
Finished Jul 06 06:42:57 PM PDT 24
Peak memory 240832 kb
Host smart-7d92beee-911d-42af-bc99-1049f3411195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387793108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swa
p.2387793108
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.1221977624
Short name T577
Test name
Test status
Simulation time 3681308599 ps
CPU time 9.34 seconds
Started Jul 06 06:42:43 PM PDT 24
Finished Jul 06 06:42:53 PM PDT 24
Peak memory 232712 kb
Host smart-de1323eb-b80c-407b-bc0c-67b36cf1e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221977624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.1221977624
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.1835170529
Short name T593
Test name
Test status
Simulation time 376287346 ps
CPU time 3.71 seconds
Started Jul 06 06:42:49 PM PDT 24
Finished Jul 06 06:42:53 PM PDT 24
Peak memory 222684 kb
Host smart-0b6167d5-5a27-48c1-b886-877529e32dc9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1835170529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dir
ect.1835170529
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.3999785051
Short name T173
Test name
Test status
Simulation time 14779887213 ps
CPU time 237.78 seconds
Started Jul 06 06:42:45 PM PDT 24
Finished Jul 06 06:46:43 PM PDT 24
Peak memory 265680 kb
Host smart-13a52595-ecf8-4141-91b2-8f5d5d35472c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999785051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.3999785051
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.2767757211
Short name T994
Test name
Test status
Simulation time 1592190335 ps
CPU time 24.36 seconds
Started Jul 06 06:42:45 PM PDT 24
Finished Jul 06 06:43:09 PM PDT 24
Peak memory 216268 kb
Host smart-775d2a62-e2e5-4967-bc09-45531d4c647b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2767757211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.2767757211
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3497871651
Short name T374
Test name
Test status
Simulation time 4964817265 ps
CPU time 5.33 seconds
Started Jul 06 06:42:42 PM PDT 24
Finished Jul 06 06:42:48 PM PDT 24
Peak memory 216336 kb
Host smart-fe822412-4711-450c-ae0c-7ae39c771c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497871651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3497871651
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.2481889367
Short name T345
Test name
Test status
Simulation time 935258184 ps
CPU time 1.4 seconds
Started Jul 06 06:42:48 PM PDT 24
Finished Jul 06 06:42:50 PM PDT 24
Peak memory 216164 kb
Host smart-5fcb460d-2f9e-4c3e-b97b-91c597d2aa0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481889367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.2481889367
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.3799631597
Short name T521
Test name
Test status
Simulation time 61245831 ps
CPU time 0.88 seconds
Started Jul 06 06:42:46 PM PDT 24
Finished Jul 06 06:42:47 PM PDT 24
Peak memory 205980 kb
Host smart-509de9db-400a-4283-b134-f44d0bd5b8a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799631597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.3799631597
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.1551315842
Short name T491
Test name
Test status
Simulation time 2046680902 ps
CPU time 6.95 seconds
Started Jul 06 06:42:49 PM PDT 24
Finished Jul 06 06:42:57 PM PDT 24
Peak memory 232676 kb
Host smart-e41421ec-3504-4227-99a2-caca21f67b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551315842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.1551315842
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.946795005
Short name T631
Test name
Test status
Simulation time 21005470 ps
CPU time 0.73 seconds
Started Jul 06 06:42:52 PM PDT 24
Finished Jul 06 06:42:53 PM PDT 24
Peak memory 204952 kb
Host smart-4ceb3763-afe2-44ef-8114-a54225bc370b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946795005 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.946795005
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1141377276
Short name T755
Test name
Test status
Simulation time 394846387 ps
CPU time 2.2 seconds
Started Jul 06 06:42:48 PM PDT 24
Finished Jul 06 06:42:51 PM PDT 24
Peak memory 224060 kb
Host smart-493305d1-720f-40d0-a95c-5ab02e1d578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141377276 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1141377276
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.705339791
Short name T392
Test name
Test status
Simulation time 58834278 ps
CPU time 0.76 seconds
Started Jul 06 06:42:46 PM PDT 24
Finished Jul 06 06:42:47 PM PDT 24
Peak memory 206600 kb
Host smart-b35e1b6a-043e-4d08-a06d-0c7cf8666ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705339791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.705339791
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.373608284
Short name T767
Test name
Test status
Simulation time 45066171080 ps
CPU time 171.69 seconds
Started Jul 06 06:42:55 PM PDT 24
Finished Jul 06 06:45:47 PM PDT 24
Peak memory 249484 kb
Host smart-dc7b54df-f1d9-4d7e-a9f9-ec49c4b11b79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373608284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.373608284
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.2114721719
Short name T718
Test name
Test status
Simulation time 99603067899 ps
CPU time 502.49 seconds
Started Jul 06 06:42:49 PM PDT 24
Finished Jul 06 06:51:12 PM PDT 24
Peak memory 263928 kb
Host smart-fcc2852f-1ada-412c-b5ea-5287de31a90a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2114721719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.2114721719
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.1536416158
Short name T637
Test name
Test status
Simulation time 69650028106 ps
CPU time 138.24 seconds
Started Jul 06 06:42:53 PM PDT 24
Finished Jul 06 06:45:11 PM PDT 24
Peak memory 255292 kb
Host smart-1c9ef93d-6643-4a4a-b339-5087eb2573b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1536416158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.1536416158
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1259970035
Short name T425
Test name
Test status
Simulation time 27132377535 ps
CPU time 12.26 seconds
Started Jul 06 06:42:49 PM PDT 24
Finished Jul 06 06:43:02 PM PDT 24
Peak memory 232768 kb
Host smart-01aec13b-6bfb-4e18-87b6-dcac7ce44dbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259970035 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1259970035
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.112121768
Short name T195
Test name
Test status
Simulation time 316244991981 ps
CPU time 380.99 seconds
Started Jul 06 06:42:51 PM PDT 24
Finished Jul 06 06:49:12 PM PDT 24
Peak memory 271780 kb
Host smart-d150142f-3577-4d0c-a234-c549a824bed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112121768 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmds
.112121768
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.524372821
Short name T791
Test name
Test status
Simulation time 148663135 ps
CPU time 4.77 seconds
Started Jul 06 06:42:53 PM PDT 24
Finished Jul 06 06:42:58 PM PDT 24
Peak memory 232608 kb
Host smart-72f2f440-2def-4543-8f66-70a15727e2bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524372821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.524372821
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.273559624
Short name T777
Test name
Test status
Simulation time 613418475 ps
CPU time 7.67 seconds
Started Jul 06 06:42:54 PM PDT 24
Finished Jul 06 06:43:02 PM PDT 24
Peak memory 232652 kb
Host smart-cf2b6e3c-0c33-4c9f-9aa3-f71468475ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=273559624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.273559624
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.2625327881
Short name T228
Test name
Test status
Simulation time 17818476116 ps
CPU time 15.39 seconds
Started Jul 06 06:42:52 PM PDT 24
Finished Jul 06 06:43:07 PM PDT 24
Peak memory 232772 kb
Host smart-2862ada9-4766-4210-b17c-cb2b304f8cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625327881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.2625327881
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.306877325
Short name T267
Test name
Test status
Simulation time 67021179 ps
CPU time 2.35 seconds
Started Jul 06 06:42:49 PM PDT 24
Finished Jul 06 06:42:52 PM PDT 24
Peak memory 232684 kb
Host smart-2589a6ec-c254-464a-954a-fbfe703cf5f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306877325 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.306877325
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.2099267641
Short name T380
Test name
Test status
Simulation time 1385034735 ps
CPU time 9.01 seconds
Started Jul 06 06:42:50 PM PDT 24
Finished Jul 06 06:42:59 PM PDT 24
Peak memory 222812 kb
Host smart-9ae12564-0603-4b44-b6f2-6e9715ff4495
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2099267641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dir
ect.2099267641
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3416435062
Short name T627
Test name
Test status
Simulation time 64062536268 ps
CPU time 305.86 seconds
Started Jul 06 06:42:51 PM PDT 24
Finished Jul 06 06:47:57 PM PDT 24
Peak memory 251480 kb
Host smart-1d3fd5c4-4e5c-4305-8637-10899f23f26c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416435062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3416435062
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.1736214631
Short name T417
Test name
Test status
Simulation time 12682032664 ps
CPU time 25.89 seconds
Started Jul 06 06:42:45 PM PDT 24
Finished Jul 06 06:43:11 PM PDT 24
Peak memory 216412 kb
Host smart-644a705c-81ba-47d9-8f27-130ef63a5583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1736214631 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.1736214631
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.2591350681
Short name T89
Test name
Test status
Simulation time 9886607258 ps
CPU time 18.68 seconds
Started Jul 06 06:42:45 PM PDT 24
Finished Jul 06 06:43:04 PM PDT 24
Peak memory 216336 kb
Host smart-9917b5ae-407d-49e3-9da9-e127532686d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591350681 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.2591350681
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.3776539085
Short name T91
Test name
Test status
Simulation time 55578443 ps
CPU time 3.29 seconds
Started Jul 06 06:42:50 PM PDT 24
Finished Jul 06 06:42:54 PM PDT 24
Peak memory 216236 kb
Host smart-c6b1863b-6011-48c0-9927-bcd1a0f1e272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776539085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.3776539085
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.2127584808
Short name T393
Test name
Test status
Simulation time 46634313 ps
CPU time 0.71 seconds
Started Jul 06 06:42:45 PM PDT 24
Finished Jul 06 06:42:46 PM PDT 24
Peak memory 205960 kb
Host smart-ffbab217-753f-408b-a755-556ca910b218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2127584808 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.2127584808
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.493567166
Short name T254
Test name
Test status
Simulation time 705819788 ps
CPU time 3.59 seconds
Started Jul 06 06:42:49 PM PDT 24
Finished Jul 06 06:42:52 PM PDT 24
Peak memory 224504 kb
Host smart-e71dd9a8-a103-4450-b54c-271cfd07e3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=493567166 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.493567166
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.3132454654
Short name T459
Test name
Test status
Simulation time 14226948 ps
CPU time 0.74 seconds
Started Jul 06 06:43:00 PM PDT 24
Finished Jul 06 06:43:01 PM PDT 24
Peak memory 205528 kb
Host smart-6cd2d966-695a-4db6-9c44-bd1a3d99d493
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132454654 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
3132454654
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.990299966
Short name T468
Test name
Test status
Simulation time 810524024 ps
CPU time 4.97 seconds
Started Jul 06 06:42:53 PM PDT 24
Finished Jul 06 06:42:58 PM PDT 24
Peak memory 232724 kb
Host smart-136912c5-fc75-4967-a696-912069693be1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990299966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.990299966
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.3742802865
Short name T753
Test name
Test status
Simulation time 118711738 ps
CPU time 0.73 seconds
Started Jul 06 06:42:52 PM PDT 24
Finished Jul 06 06:42:53 PM PDT 24
Peak memory 206920 kb
Host smart-ec171735-fd5e-4483-9a89-a661c319ccb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742802865 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.3742802865
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.3674980820
Short name T802
Test name
Test status
Simulation time 11242736656 ps
CPU time 112.61 seconds
Started Jul 06 06:42:55 PM PDT 24
Finished Jul 06 06:44:48 PM PDT 24
Peak memory 254096 kb
Host smart-3774bb3d-d151-45b4-bcd3-e7e4a9ec9e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674980820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.3674980820
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.1642958142
Short name T262
Test name
Test status
Simulation time 5185606839 ps
CPU time 96 seconds
Started Jul 06 06:43:01 PM PDT 24
Finished Jul 06 06:44:37 PM PDT 24
Peak memory 265696 kb
Host smart-816813ef-93e9-46d3-a21a-2b7ed894760a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642958142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.1642958142
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.2741832359
Short name T662
Test name
Test status
Simulation time 4770433808 ps
CPU time 67.29 seconds
Started Jul 06 06:42:53 PM PDT 24
Finished Jul 06 06:44:01 PM PDT 24
Peak memory 249312 kb
Host smart-07962678-0e02-49f1-9cf6-f03ba2279b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741832359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.2741832359
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.2233666044
Short name T531
Test name
Test status
Simulation time 3061366478 ps
CPU time 4.57 seconds
Started Jul 06 06:42:54 PM PDT 24
Finished Jul 06 06:42:59 PM PDT 24
Peak memory 224592 kb
Host smart-ad947fda-5f4a-47e1-810c-442da9d8b8d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233666044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.2233666044
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.438641869
Short name T40
Test name
Test status
Simulation time 2801950094 ps
CPU time 39.89 seconds
Started Jul 06 06:43:00 PM PDT 24
Finished Jul 06 06:43:40 PM PDT 24
Peak memory 249352 kb
Host smart-a1856864-6d1f-4943-bac2-b81d01b7cac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438641869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmds
.438641869
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.1061919417
Short name T292
Test name
Test status
Simulation time 172017722 ps
CPU time 3.97 seconds
Started Jul 06 06:42:50 PM PDT 24
Finished Jul 06 06:42:55 PM PDT 24
Peak memory 232720 kb
Host smart-e4c68c2c-5d89-4a21-b9d7-ce798fdf7454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061919417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.1061919417
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.1841647321
Short name T362
Test name
Test status
Simulation time 6352247124 ps
CPU time 12.92 seconds
Started Jul 06 06:42:55 PM PDT 24
Finished Jul 06 06:43:09 PM PDT 24
Peak memory 232736 kb
Host smart-db14e30c-7a13-4915-8bf5-c48b4dfba1ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841647321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.1841647321
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.4231796064
Short name T463
Test name
Test status
Simulation time 971491048 ps
CPU time 8.35 seconds
Started Jul 06 06:42:53 PM PDT 24
Finished Jul 06 06:43:01 PM PDT 24
Peak memory 232604 kb
Host smart-7a5003ad-1315-4d2c-b53d-7b6eb86d57e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231796064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.4231796064
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.2420640140
Short name T512
Test name
Test status
Simulation time 286323124 ps
CPU time 3.18 seconds
Started Jul 06 06:42:50 PM PDT 24
Finished Jul 06 06:42:53 PM PDT 24
Peak memory 232624 kb
Host smart-1828d7ed-a901-42b7-9543-c3abd7197955
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420640140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.2420640140
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.391551786
Short name T641
Test name
Test status
Simulation time 3438493552 ps
CPU time 6.17 seconds
Started Jul 06 06:42:54 PM PDT 24
Finished Jul 06 06:43:01 PM PDT 24
Peak memory 223280 kb
Host smart-55288c12-cd48-4d40-ad90-aeb7ec3b7400
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=391551786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dire
ct.391551786
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.1559437083
Short name T377
Test name
Test status
Simulation time 1613450640 ps
CPU time 8.66 seconds
Started Jul 06 06:42:50 PM PDT 24
Finished Jul 06 06:42:59 PM PDT 24
Peak memory 216220 kb
Host smart-ab7da11f-7628-45f8-a47a-4ab4192ee04b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559437083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.1559437083
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.3903758439
Short name T594
Test name
Test status
Simulation time 8366371012 ps
CPU time 20.8 seconds
Started Jul 06 06:42:49 PM PDT 24
Finished Jul 06 06:43:10 PM PDT 24
Peak memory 216248 kb
Host smart-b7d3ab8f-d8b5-4e5e-99e3-e119fffd6096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903758439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.3903758439
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.2053594362
Short name T700
Test name
Test status
Simulation time 443746199 ps
CPU time 6.29 seconds
Started Jul 06 06:42:51 PM PDT 24
Finished Jul 06 06:42:58 PM PDT 24
Peak memory 216196 kb
Host smart-d4266a09-10ad-4052-9d38-439f22b306f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053594362 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.2053594362
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.1261932036
Short name T530
Test name
Test status
Simulation time 29433122 ps
CPU time 0.83 seconds
Started Jul 06 06:42:49 PM PDT 24
Finished Jul 06 06:42:50 PM PDT 24
Peak memory 205988 kb
Host smart-5eb1dcc6-1d80-4121-9e52-d8830946255e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1261932036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.1261932036
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.2796412888
Short name T690
Test name
Test status
Simulation time 766846504 ps
CPU time 4.97 seconds
Started Jul 06 06:42:53 PM PDT 24
Finished Jul 06 06:42:58 PM PDT 24
Peak memory 232696 kb
Host smart-a8c4910f-b177-4e91-9bf6-d09ec7942b77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796412888 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.2796412888
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3115458444
Short name T944
Test name
Test status
Simulation time 13479829 ps
CPU time 0.72 seconds
Started Jul 06 06:42:58 PM PDT 24
Finished Jul 06 06:42:59 PM PDT 24
Peak memory 204976 kb
Host smart-1424f5d8-17d1-4486-ac0d-0a7b13a1d712
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115458444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3115458444
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2840621995
Short name T296
Test name
Test status
Simulation time 940698618 ps
CPU time 11.23 seconds
Started Jul 06 06:42:56 PM PDT 24
Finished Jul 06 06:43:07 PM PDT 24
Peak memory 232668 kb
Host smart-403b4fd1-47c6-453d-b443-2439c22270bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840621995 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2840621995
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.1186854263
Short name T805
Test name
Test status
Simulation time 19898196 ps
CPU time 0.77 seconds
Started Jul 06 06:42:55 PM PDT 24
Finished Jul 06 06:42:56 PM PDT 24
Peak memory 206624 kb
Host smart-c78dd85a-6d9f-4f84-94ac-a66b99865a4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1186854263 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.1186854263
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.4173476791
Short name T878
Test name
Test status
Simulation time 2532442440 ps
CPU time 42.63 seconds
Started Jul 06 06:42:57 PM PDT 24
Finished Jul 06 06:43:40 PM PDT 24
Peak memory 240996 kb
Host smart-3d7cce25-bf56-41c3-953d-1bc3390135db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4173476791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.4173476791
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.1273384491
Short name T738
Test name
Test status
Simulation time 23903522322 ps
CPU time 141.85 seconds
Started Jul 06 06:43:01 PM PDT 24
Finished Jul 06 06:45:24 PM PDT 24
Peak memory 256828 kb
Host smart-00acad0d-7ff1-45ba-8bf5-846d0a3c6fe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273384491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.1273384491
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.3150575439
Short name T282
Test name
Test status
Simulation time 7343278286 ps
CPU time 70.61 seconds
Started Jul 06 06:43:00 PM PDT 24
Finished Jul 06 06:44:11 PM PDT 24
Peak memory 248624 kb
Host smart-5b9645a1-f712-4849-8ba9-03f916043f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150575439 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.3150575439
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.1804486503
Short name T999
Test name
Test status
Simulation time 521549216 ps
CPU time 6.48 seconds
Started Jul 06 06:43:00 PM PDT 24
Finished Jul 06 06:43:07 PM PDT 24
Peak memory 234552 kb
Host smart-af98eaba-4656-4ffd-bb36-59ef20d9779c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1804486503 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.1804486503
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.3551969919
Short name T956
Test name
Test status
Simulation time 6839994221 ps
CPU time 26.92 seconds
Started Jul 06 06:43:01 PM PDT 24
Finished Jul 06 06:43:29 PM PDT 24
Peak memory 240936 kb
Host smart-93b3a95f-5aeb-44fd-8367-b3be360fb465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551969919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.3551969919
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.1195242624
Short name T587
Test name
Test status
Simulation time 2724606418 ps
CPU time 22.98 seconds
Started Jul 06 06:43:00 PM PDT 24
Finished Jul 06 06:43:24 PM PDT 24
Peak memory 229284 kb
Host smart-f295c644-5734-443a-8a01-bb7030bb8caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1195242624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.1195242624
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.3454394634
Short name T872
Test name
Test status
Simulation time 495428528 ps
CPU time 6.11 seconds
Started Jul 06 06:42:55 PM PDT 24
Finished Jul 06 06:43:02 PM PDT 24
Peak memory 224388 kb
Host smart-7b862cf2-dda7-42be-9828-e934587b9307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3454394634 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.3454394634
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.807841456
Short name T286
Test name
Test status
Simulation time 296868627 ps
CPU time 2.95 seconds
Started Jul 06 06:42:53 PM PDT 24
Finished Jul 06 06:42:56 PM PDT 24
Peak memory 224512 kb
Host smart-7154cea4-07d2-4ca9-8783-499f7bf9e54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=807841456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swap
.807841456
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.1256154824
Short name T602
Test name
Test status
Simulation time 1701346929 ps
CPU time 5.47 seconds
Started Jul 06 06:42:55 PM PDT 24
Finished Jul 06 06:43:00 PM PDT 24
Peak memory 224416 kb
Host smart-b6f2284d-9af5-4aeb-b7e1-afbac4f3ea18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1256154824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.1256154824
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.1349267787
Short name T884
Test name
Test status
Simulation time 2355213694 ps
CPU time 9.54 seconds
Started Jul 06 06:42:58 PM PDT 24
Finished Jul 06 06:43:08 PM PDT 24
Peak memory 222180 kb
Host smart-f0232879-8c40-43a0-837d-3d34124fb30c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1349267787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.1349267787
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.1159051093
Short name T59
Test name
Test status
Simulation time 2259802050 ps
CPU time 12.99 seconds
Started Jul 06 06:43:01 PM PDT 24
Finished Jul 06 06:43:14 PM PDT 24
Peak memory 219560 kb
Host smart-ad30504b-37ef-48ec-98c0-0ff5312cfef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159051093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.1159051093
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2007244611
Short name T429
Test name
Test status
Simulation time 986190458 ps
CPU time 3.02 seconds
Started Jul 06 06:42:56 PM PDT 24
Finished Jul 06 06:42:59 PM PDT 24
Peak memory 216240 kb
Host smart-519f8a92-54a8-4d4e-96e1-9bccd87abbb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007244611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2007244611
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.1072875176
Short name T539
Test name
Test status
Simulation time 146591296 ps
CPU time 0.95 seconds
Started Jul 06 06:42:55 PM PDT 24
Finished Jul 06 06:42:56 PM PDT 24
Peak memory 206980 kb
Host smart-80020aec-bdcb-43ee-9316-fac623422b01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072875176 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.1072875176
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.3050591069
Short name T506
Test name
Test status
Simulation time 50988168 ps
CPU time 0.7 seconds
Started Jul 06 06:43:00 PM PDT 24
Finished Jul 06 06:43:02 PM PDT 24
Peak memory 205940 kb
Host smart-d23fd36d-529a-42a1-9096-a3a9bac4f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050591069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.3050591069
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.873809018
Short name T853
Test name
Test status
Simulation time 13708320917 ps
CPU time 23.21 seconds
Started Jul 06 06:42:55 PM PDT 24
Finished Jul 06 06:43:19 PM PDT 24
Peak memory 232788 kb
Host smart-ce72a4cd-3fdd-49e9-a00d-4caa514cdfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873809018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.873809018
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.1050355856
Short name T819
Test name
Test status
Simulation time 15448187 ps
CPU time 0.74 seconds
Started Jul 06 06:43:04 PM PDT 24
Finished Jul 06 06:43:05 PM PDT 24
Peak memory 204968 kb
Host smart-182a6c59-fba6-42f9-b0b1-5fb221441c98
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050355856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
1050355856
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.1973038314
Short name T383
Test name
Test status
Simulation time 1101398392 ps
CPU time 5.05 seconds
Started Jul 06 06:43:02 PM PDT 24
Finished Jul 06 06:43:08 PM PDT 24
Peak memory 224532 kb
Host smart-8d070b8e-2f55-4256-a0c5-d22766ed28bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973038314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.1973038314
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.3223388265
Short name T351
Test name
Test status
Simulation time 48384265 ps
CPU time 0.76 seconds
Started Jul 06 06:42:58 PM PDT 24
Finished Jul 06 06:42:59 PM PDT 24
Peak memory 206928 kb
Host smart-874353a3-c442-43da-9e48-baf4562e4ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223388265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.3223388265
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.1680289648
Short name T838
Test name
Test status
Simulation time 11749322133 ps
CPU time 156.48 seconds
Started Jul 06 06:43:04 PM PDT 24
Finished Jul 06 06:45:41 PM PDT 24
Peak memory 265384 kb
Host smart-30aa2171-1415-45f3-bb1d-3ad272cb228f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680289648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.1680289648
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.189731393
Short name T727
Test name
Test status
Simulation time 8507176530 ps
CPU time 43.05 seconds
Started Jul 06 06:43:03 PM PDT 24
Finished Jul 06 06:43:46 PM PDT 24
Peak memory 238040 kb
Host smart-23765fc0-3513-449d-bb69-bcb494863ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189731393 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.189731393
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.477678174
Short name T680
Test name
Test status
Simulation time 24037307360 ps
CPU time 238.45 seconds
Started Jul 06 06:43:03 PM PDT 24
Finished Jul 06 06:47:02 PM PDT 24
Peak memory 256920 kb
Host smart-6c11d773-28a9-4363-8302-50ef37065a23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477678174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idle
.477678174
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.2031776151
Short name T489
Test name
Test status
Simulation time 1663749869 ps
CPU time 20.03 seconds
Started Jul 06 06:43:05 PM PDT 24
Finished Jul 06 06:43:25 PM PDT 24
Peak memory 250340 kb
Host smart-c994fbc2-d9f2-4be2-819b-90b535771a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2031776151 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.2031776151
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3481439742
Short name T484
Test name
Test status
Simulation time 65804428 ps
CPU time 0.79 seconds
Started Jul 06 06:43:03 PM PDT 24
Finished Jul 06 06:43:04 PM PDT 24
Peak memory 215804 kb
Host smart-9d4ba1be-98a2-4aaf-9291-8cfbdf2761f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481439742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3481439742
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.4288871391
Short name T504
Test name
Test status
Simulation time 1573956101 ps
CPU time 6.92 seconds
Started Jul 06 06:42:59 PM PDT 24
Finished Jul 06 06:43:06 PM PDT 24
Peak memory 224412 kb
Host smart-a8a1fb5d-01ef-4627-a370-86383784c4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288871391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.4288871391
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.1923114566
Short name T293
Test name
Test status
Simulation time 651240724 ps
CPU time 8.49 seconds
Started Jul 06 06:42:58 PM PDT 24
Finished Jul 06 06:43:07 PM PDT 24
Peak memory 256992 kb
Host smart-f214552d-6166-41ad-a4fe-da7f4ff9d27f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923114566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.1923114566
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2124551684
Short name T830
Test name
Test status
Simulation time 843266612 ps
CPU time 4.68 seconds
Started Jul 06 06:42:59 PM PDT 24
Finished Jul 06 06:43:04 PM PDT 24
Peak memory 232652 kb
Host smart-5237e294-d0a8-45de-a97a-1804b0bc6e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124551684 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2124551684
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.3634542905
Short name T260
Test name
Test status
Simulation time 1682553220 ps
CPU time 5.03 seconds
Started Jul 06 06:43:00 PM PDT 24
Finished Jul 06 06:43:06 PM PDT 24
Peak memory 239664 kb
Host smart-dbdb0490-59e4-4c88-9791-cfeb12a3c5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634542905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.3634542905
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.1649309249
Short name T360
Test name
Test status
Simulation time 4308465915 ps
CPU time 9.99 seconds
Started Jul 06 06:43:04 PM PDT 24
Finished Jul 06 06:43:14 PM PDT 24
Peak memory 219364 kb
Host smart-faf2c0e9-f62c-42ee-80c8-cbe35d5e9c56
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1649309249 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dir
ect.1649309249
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.4066250049
Short name T34
Test name
Test status
Simulation time 75045742553 ps
CPU time 276.35 seconds
Started Jul 06 06:43:06 PM PDT 24
Finished Jul 06 06:47:42 PM PDT 24
Peak memory 269400 kb
Host smart-7ee912d0-7104-4e49-a551-bf6da169a262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066250049 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.4066250049
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.2261302136
Short name T749
Test name
Test status
Simulation time 912223796 ps
CPU time 9.91 seconds
Started Jul 06 06:42:59 PM PDT 24
Finished Jul 06 06:43:09 PM PDT 24
Peak memory 216308 kb
Host smart-01b32e6e-fbc0-449d-9793-1d8aa9bb5555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261302136 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.2261302136
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.2036712282
Short name T33
Test name
Test status
Simulation time 4606860871 ps
CPU time 6.27 seconds
Started Jul 06 06:43:00 PM PDT 24
Finished Jul 06 06:43:07 PM PDT 24
Peak memory 216300 kb
Host smart-122803d6-9bc7-4bc2-80e0-804edc1406c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036712282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.2036712282
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1335322978
Short name T787
Test name
Test status
Simulation time 58347512 ps
CPU time 0.78 seconds
Started Jul 06 06:42:59 PM PDT 24
Finished Jul 06 06:43:00 PM PDT 24
Peak memory 206032 kb
Host smart-e80a068b-40ef-4aaf-aede-207b28ee3915
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335322978 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1335322978
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.3186243675
Short name T402
Test name
Test status
Simulation time 104579645 ps
CPU time 0.86 seconds
Started Jul 06 06:42:59 PM PDT 24
Finished Jul 06 06:43:00 PM PDT 24
Peak memory 206420 kb
Host smart-9a3ad412-4ab5-4f61-8e83-0b6358606b13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186243675 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.3186243675
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1714157718
Short name T231
Test name
Test status
Simulation time 190276350 ps
CPU time 4.25 seconds
Started Jul 06 06:43:05 PM PDT 24
Finished Jul 06 06:43:10 PM PDT 24
Peak memory 232664 kb
Host smart-8830c536-4a22-43f3-baf4-b0324f26b0d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714157718 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1714157718
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.4186934801
Short name T931
Test name
Test status
Simulation time 39281769 ps
CPU time 0.72 seconds
Started Jul 06 06:43:09 PM PDT 24
Finished Jul 06 06:43:10 PM PDT 24
Peak memory 204988 kb
Host smart-f226f6b9-c445-4c5e-bf40-3d9912fbc208
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4186934801 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
4186934801
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.3637086678
Short name T889
Test name
Test status
Simulation time 2018667141 ps
CPU time 6.42 seconds
Started Jul 06 06:43:10 PM PDT 24
Finished Jul 06 06:43:17 PM PDT 24
Peak memory 224444 kb
Host smart-36eba24a-bc53-4aaa-ae78-cd23c067e3ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3637086678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.3637086678
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.1151926491
Short name T462
Test name
Test status
Simulation time 38902500 ps
CPU time 0.76 seconds
Started Jul 06 06:43:04 PM PDT 24
Finished Jul 06 06:43:05 PM PDT 24
Peak memory 206612 kb
Host smart-33846ab3-dc54-4718-bd28-0a8d34c692d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151926491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.1151926491
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3591046444
Short name T525
Test name
Test status
Simulation time 12123064108 ps
CPU time 100.17 seconds
Started Jul 06 06:43:09 PM PDT 24
Finished Jul 06 06:44:49 PM PDT 24
Peak memory 254416 kb
Host smart-4fec0115-2270-4224-9d7b-3ceb1fd18b17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591046444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3591046444
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.1178322754
Short name T887
Test name
Test status
Simulation time 32663807299 ps
CPU time 232.51 seconds
Started Jul 06 06:43:14 PM PDT 24
Finished Jul 06 06:47:07 PM PDT 24
Peak memory 249552 kb
Host smart-d3e2c520-a36e-4cf0-976c-ca6b32e56796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178322754 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.1178322754
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.425384960
Short name T551
Test name
Test status
Simulation time 1812158839 ps
CPU time 44.84 seconds
Started Jul 06 06:43:10 PM PDT 24
Finished Jul 06 06:43:55 PM PDT 24
Peak memory 250172 kb
Host smart-626f2fed-38d0-4a8f-b12a-4170008279df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425384960 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.425384960
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.3394344856
Short name T144
Test name
Test status
Simulation time 77705246 ps
CPU time 2.68 seconds
Started Jul 06 06:43:08 PM PDT 24
Finished Jul 06 06:43:11 PM PDT 24
Peak memory 224496 kb
Host smart-6a2239f5-488b-4677-a71d-4ee8e236caa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394344856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.3394344856
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2644866322
Short name T598
Test name
Test status
Simulation time 1933105275 ps
CPU time 11.09 seconds
Started Jul 06 06:43:11 PM PDT 24
Finished Jul 06 06:43:23 PM PDT 24
Peak memory 232728 kb
Host smart-b8149b18-17dd-4176-9211-6583c198379c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644866322 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2644866322
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.237467814
Short name T836
Test name
Test status
Simulation time 1104415194 ps
CPU time 5.88 seconds
Started Jul 06 06:43:11 PM PDT 24
Finished Jul 06 06:43:17 PM PDT 24
Peak memory 218924 kb
Host smart-56116b75-d751-4fb0-a528-2017b37ab551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237467814 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.237467814
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.2263917257
Short name T1004
Test name
Test status
Simulation time 4596296162 ps
CPU time 9.63 seconds
Started Jul 06 06:43:09 PM PDT 24
Finished Jul 06 06:43:19 PM PDT 24
Peak memory 232820 kb
Host smart-8a8dd481-05fe-4ef7-92eb-267c44a08917
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263917257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swa
p.2263917257
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.2221762966
Short name T434
Test name
Test status
Simulation time 55632324680 ps
CPU time 19.91 seconds
Started Jul 06 06:43:10 PM PDT 24
Finished Jul 06 06:43:30 PM PDT 24
Peak memory 240632 kb
Host smart-304da5a6-b6cd-4783-b273-0a96fd24fec7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2221762966 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.2221762966
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3262360943
Short name T927
Test name
Test status
Simulation time 1344334067 ps
CPU time 3.75 seconds
Started Jul 06 06:43:10 PM PDT 24
Finished Jul 06 06:43:14 PM PDT 24
Peak memory 219384 kb
Host smart-937bdab0-313a-4b7a-9d93-515cd74a054d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3262360943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3262360943
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.948199969
Short name T300
Test name
Test status
Simulation time 16570067269 ps
CPU time 91.92 seconds
Started Jul 06 06:43:11 PM PDT 24
Finished Jul 06 06:44:43 PM PDT 24
Peak memory 265284 kb
Host smart-e7509c8c-638b-4bea-bb81-225b063879df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948199969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stres
s_all.948199969
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.3422335597
Short name T342
Test name
Test status
Simulation time 746928007 ps
CPU time 4.86 seconds
Started Jul 06 06:43:03 PM PDT 24
Finished Jul 06 06:43:08 PM PDT 24
Peak memory 216220 kb
Host smart-bb420162-32aa-4c0d-b2be-0c2a9e9251fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422335597 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.3422335597
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.2218177785
Short name T405
Test name
Test status
Simulation time 637354164 ps
CPU time 3.85 seconds
Started Jul 06 06:43:05 PM PDT 24
Finished Jul 06 06:43:09 PM PDT 24
Peak memory 216220 kb
Host smart-741db075-ac1a-4c5d-852c-370765985544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218177785 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.2218177785
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.3370156644
Short name T537
Test name
Test status
Simulation time 283903887 ps
CPU time 0.96 seconds
Started Jul 06 06:43:10 PM PDT 24
Finished Jul 06 06:43:11 PM PDT 24
Peak memory 207912 kb
Host smart-f7e7215d-339c-4514-8d97-cba52aa2b7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370156644 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.3370156644
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.1859551860
Short name T571
Test name
Test status
Simulation time 20954567 ps
CPU time 0.79 seconds
Started Jul 06 06:43:04 PM PDT 24
Finished Jul 06 06:43:05 PM PDT 24
Peak memory 205976 kb
Host smart-df5c32e5-bc20-4e89-8e10-7b8f073ba49b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859551860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.1859551860
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.1891604575
Short name T177
Test name
Test status
Simulation time 8502788009 ps
CPU time 4.82 seconds
Started Jul 06 06:43:07 PM PDT 24
Finished Jul 06 06:43:12 PM PDT 24
Peak memory 232752 kb
Host smart-ac556348-0f25-4026-b841-4a0b56ad7acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891604575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.1891604575
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.4022097537
Short name T94
Test name
Test status
Simulation time 12526889 ps
CPU time 0.76 seconds
Started Jul 06 06:43:16 PM PDT 24
Finished Jul 06 06:43:17 PM PDT 24
Peak memory 205868 kb
Host smart-1974b010-73fb-474d-804d-2f62cb1737ca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4022097537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
4022097537
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.881760630
Short name T271
Test name
Test status
Simulation time 1225994285 ps
CPU time 8.17 seconds
Started Jul 06 06:43:08 PM PDT 24
Finished Jul 06 06:43:17 PM PDT 24
Peak memory 232672 kb
Host smart-175cdd2f-d6f9-47c2-be7c-9ee835158585
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881760630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.881760630
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.4135193441
Short name T349
Test name
Test status
Simulation time 16686787 ps
CPU time 0.74 seconds
Started Jul 06 06:43:09 PM PDT 24
Finished Jul 06 06:43:10 PM PDT 24
Peak memory 205568 kb
Host smart-f0219237-03af-4137-af3c-24222c86dbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4135193441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.4135193441
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.1880980307
Short name T778
Test name
Test status
Simulation time 2801081692 ps
CPU time 31.22 seconds
Started Jul 06 06:43:13 PM PDT 24
Finished Jul 06 06:43:45 PM PDT 24
Peak memory 241004 kb
Host smart-cce90184-d715-4777-b310-b93d0d688af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880980307 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.1880980307
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3335386442
Short name T745
Test name
Test status
Simulation time 11058865451 ps
CPU time 186.22 seconds
Started Jul 06 06:43:07 PM PDT 24
Finished Jul 06 06:46:14 PM PDT 24
Peak memory 257084 kb
Host smart-da3f1656-e6bd-4c06-a747-28666aca539a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335386442 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3335386442
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.1503004293
Short name T890
Test name
Test status
Simulation time 5831063524 ps
CPU time 39.32 seconds
Started Jul 06 06:43:09 PM PDT 24
Finished Jul 06 06:43:48 PM PDT 24
Peak memory 235372 kb
Host smart-7a3f5393-ecf3-40ff-8bea-811be28c28c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503004293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.1503004293
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.3021485309
Short name T534
Test name
Test status
Simulation time 15039826 ps
CPU time 0.76 seconds
Started Jul 06 06:43:09 PM PDT 24
Finished Jul 06 06:43:10 PM PDT 24
Peak memory 215820 kb
Host smart-f71eee58-8903-4079-8e50-e06a7754fc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021485309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.3021485309
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.423281660
Short name T633
Test name
Test status
Simulation time 2201582727 ps
CPU time 13.46 seconds
Started Jul 06 06:43:13 PM PDT 24
Finished Jul 06 06:43:27 PM PDT 24
Peak memory 232748 kb
Host smart-e21a91e6-23f1-44a7-9e42-d03c80702c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423281660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.423281660
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.438123162
Short name T482
Test name
Test status
Simulation time 678723978 ps
CPU time 14.3 seconds
Started Jul 06 06:43:08 PM PDT 24
Finished Jul 06 06:43:23 PM PDT 24
Peak memory 232732 kb
Host smart-60b5a20c-12c5-4023-8660-76b6bd736d9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438123162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.438123162
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.2055140227
Short name T319
Test name
Test status
Simulation time 1304373997 ps
CPU time 4.73 seconds
Started Jul 06 06:43:14 PM PDT 24
Finished Jul 06 06:43:19 PM PDT 24
Peak memory 224464 kb
Host smart-352697d3-2425-4d21-be75-03a385ff8312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055140227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.2055140227
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.4054426208
Short name T995
Test name
Test status
Simulation time 1502102752 ps
CPU time 3.31 seconds
Started Jul 06 06:43:07 PM PDT 24
Finished Jul 06 06:43:11 PM PDT 24
Peak memory 224432 kb
Host smart-992006be-58b0-4f7c-b084-7f0101f235ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054426208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.4054426208
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.2808254577
Short name T515
Test name
Test status
Simulation time 15788544149 ps
CPU time 15.92 seconds
Started Jul 06 06:43:08 PM PDT 24
Finished Jul 06 06:43:24 PM PDT 24
Peak memory 219308 kb
Host smart-a5352ee9-799a-46e7-b1b5-3e49131278b1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2808254577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.2808254577
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.2661639143
Short name T984
Test name
Test status
Simulation time 59722982 ps
CPU time 1.05 seconds
Started Jul 06 06:43:16 PM PDT 24
Finished Jul 06 06:43:17 PM PDT 24
Peak memory 206868 kb
Host smart-19f34a4c-d531-4a45-9d1e-d48f8f9908c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661639143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stre
ss_all.2661639143
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.505897193
Short name T69
Test name
Test status
Simulation time 156132712976 ps
CPU time 43.12 seconds
Started Jul 06 06:43:11 PM PDT 24
Finished Jul 06 06:43:54 PM PDT 24
Peak memory 216336 kb
Host smart-7a568ee4-bb6e-485b-b5be-b28dde4b446f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505897193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.505897193
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.1825899383
Short name T893
Test name
Test status
Simulation time 1041236272 ps
CPU time 1.74 seconds
Started Jul 06 06:43:07 PM PDT 24
Finished Jul 06 06:43:09 PM PDT 24
Peak memory 207932 kb
Host smart-ef2606b8-0a49-4b52-8144-e183f9809ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825899383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.1825899383
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.3505305893
Short name T724
Test name
Test status
Simulation time 14595963 ps
CPU time 0.76 seconds
Started Jul 06 06:43:10 PM PDT 24
Finished Jul 06 06:43:11 PM PDT 24
Peak memory 206468 kb
Host smart-9964cc70-d2ee-497e-9e99-477004b28e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505305893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.3505305893
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.1124576476
Short name T365
Test name
Test status
Simulation time 85233323 ps
CPU time 0.76 seconds
Started Jul 06 06:43:10 PM PDT 24
Finished Jul 06 06:43:11 PM PDT 24
Peak memory 206004 kb
Host smart-671f22b3-e46e-4b81-a81d-1f403c368936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124576476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.1124576476
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.1143434515
Short name T490
Test name
Test status
Simulation time 11555399118 ps
CPU time 10.66 seconds
Started Jul 06 06:43:11 PM PDT 24
Finished Jul 06 06:43:21 PM PDT 24
Peak memory 224616 kb
Host smart-d12c9809-f00b-4fb5-a230-047e12cbbfd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1143434515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.1143434515
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.1056742243
Short name T77
Test name
Test status
Simulation time 12229025 ps
CPU time 0.75 seconds
Started Jul 06 06:43:17 PM PDT 24
Finished Jul 06 06:43:18 PM PDT 24
Peak memory 205528 kb
Host smart-57ecee86-1e77-4862-b2b5-f0965722acd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056742243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
1056742243
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.2061261841
Short name T733
Test name
Test status
Simulation time 3428112233 ps
CPU time 7.48 seconds
Started Jul 06 06:43:13 PM PDT 24
Finished Jul 06 06:43:21 PM PDT 24
Peak memory 224556 kb
Host smart-d35aeae7-0a97-4f38-b1d9-e429bec62fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061261841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.2061261841
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2925209555
Short name T5
Test name
Test status
Simulation time 39723544 ps
CPU time 0.74 seconds
Started Jul 06 06:43:15 PM PDT 24
Finished Jul 06 06:43:16 PM PDT 24
Peak memory 206920 kb
Host smart-7be85a72-1741-40e2-b92f-a69a575caba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925209555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2925209555
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.4268856389
Short name T294
Test name
Test status
Simulation time 4128408655 ps
CPU time 82.67 seconds
Started Jul 06 06:43:15 PM PDT 24
Finished Jul 06 06:44:38 PM PDT 24
Peak memory 264396 kb
Host smart-58ca65ba-c47a-432c-a5a4-702f561a9d53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268856389 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.4268856389
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3811167895
Short name T248
Test name
Test status
Simulation time 3131792625 ps
CPU time 37.18 seconds
Started Jul 06 06:43:14 PM PDT 24
Finished Jul 06 06:43:52 PM PDT 24
Peak memory 237408 kb
Host smart-39b3c013-3bf7-42d8-86ea-433cdb3eadaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3811167895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3811167895
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.2572676380
Short name T936
Test name
Test status
Simulation time 3439302057 ps
CPU time 41.41 seconds
Started Jul 06 06:43:13 PM PDT 24
Finished Jul 06 06:43:55 PM PDT 24
Peak memory 257472 kb
Host smart-8eeab1af-72c3-4e9e-9d64-bfa063fa3ca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572676380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.2572676380
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1936377457
Short name T178
Test name
Test status
Simulation time 181723001 ps
CPU time 2.71 seconds
Started Jul 06 06:43:12 PM PDT 24
Finished Jul 06 06:43:15 PM PDT 24
Peak memory 224452 kb
Host smart-bad54a22-672b-4407-857c-a6fc3a0bd6ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1936377457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1936377457
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2883413165
Short name T823
Test name
Test status
Simulation time 49979958161 ps
CPU time 145.68 seconds
Started Jul 06 06:43:16 PM PDT 24
Finished Jul 06 06:45:42 PM PDT 24
Peak memory 249228 kb
Host smart-1efcb864-4812-45b2-a683-22d8d7a75516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883413165 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2883413165
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.4277931164
Short name T449
Test name
Test status
Simulation time 1057603837 ps
CPU time 10.44 seconds
Started Jul 06 06:43:14 PM PDT 24
Finished Jul 06 06:43:25 PM PDT 24
Peak memory 232724 kb
Host smart-68b416aa-bb7e-4f29-b93d-4561ab4a1da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4277931164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.4277931164
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.3311087219
Short name T833
Test name
Test status
Simulation time 972458196 ps
CPU time 14.58 seconds
Started Jul 06 06:43:15 PM PDT 24
Finished Jul 06 06:43:30 PM PDT 24
Peak memory 233760 kb
Host smart-58125599-7a41-4a11-a98a-c620d8841fc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311087219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.3311087219
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.495317841
Short name T291
Test name
Test status
Simulation time 969037972 ps
CPU time 3.45 seconds
Started Jul 06 06:43:17 PM PDT 24
Finished Jul 06 06:43:20 PM PDT 24
Peak memory 224448 kb
Host smart-0ee51423-124c-4267-80c7-7e7f4708b3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495317841 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.495317841
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.1189381983
Short name T176
Test name
Test status
Simulation time 7035702471 ps
CPU time 14 seconds
Started Jul 06 06:43:16 PM PDT 24
Finished Jul 06 06:43:30 PM PDT 24
Peak memory 224596 kb
Host smart-cb540e63-a881-4be5-8273-3dd34ad3fcfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189381983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.1189381983
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.1497247943
Short name T923
Test name
Test status
Simulation time 2423485066 ps
CPU time 8.17 seconds
Started Jul 06 06:43:17 PM PDT 24
Finished Jul 06 06:43:25 PM PDT 24
Peak memory 219036 kb
Host smart-3b5c5305-afb3-400a-b501-64410ecf1a1f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1497247943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.1497247943
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.2389214326
Short name T169
Test name
Test status
Simulation time 76907755981 ps
CPU time 674.69 seconds
Started Jul 06 06:43:15 PM PDT 24
Finished Jul 06 06:54:30 PM PDT 24
Peak memory 273816 kb
Host smart-48b55b3b-7c7e-4c49-b446-568df1d531fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389214326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.2389214326
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.109251324
Short name T398
Test name
Test status
Simulation time 3533435268 ps
CPU time 19.29 seconds
Started Jul 06 06:43:14 PM PDT 24
Finished Jul 06 06:43:34 PM PDT 24
Peak memory 217524 kb
Host smart-32faeef8-711b-4722-af6a-f61c0a10f4f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109251324 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.109251324
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1535324697
Short name T382
Test name
Test status
Simulation time 1256166146 ps
CPU time 7.21 seconds
Started Jul 06 06:43:14 PM PDT 24
Finished Jul 06 06:43:22 PM PDT 24
Peak memory 216256 kb
Host smart-73380bc0-2ad1-4c8d-802b-5009cf954bd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1535324697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1535324697
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.887290345
Short name T445
Test name
Test status
Simulation time 63030977 ps
CPU time 1.66 seconds
Started Jul 06 06:43:13 PM PDT 24
Finished Jul 06 06:43:14 PM PDT 24
Peak memory 216208 kb
Host smart-730a6288-67d9-454f-be7b-514869daca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887290345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.887290345
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.1484312155
Short name T697
Test name
Test status
Simulation time 840810701 ps
CPU time 1.01 seconds
Started Jul 06 06:43:14 PM PDT 24
Finished Jul 06 06:43:15 PM PDT 24
Peak memory 206268 kb
Host smart-023cde8e-ba70-475b-b5a8-7597241b767b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484312155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.1484312155
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.1110968177
Short name T757
Test name
Test status
Simulation time 72821484 ps
CPU time 2.79 seconds
Started Jul 06 06:43:17 PM PDT 24
Finished Jul 06 06:43:20 PM PDT 24
Peak memory 232696 kb
Host smart-4e48b272-5ad5-4f30-8d80-635cf8284096
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110968177 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.1110968177
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.2744337932
Short name T667
Test name
Test status
Simulation time 14066741 ps
CPU time 0.67 seconds
Started Jul 06 06:43:22 PM PDT 24
Finished Jul 06 06:43:22 PM PDT 24
Peak memory 205548 kb
Host smart-75b8a183-0506-430a-8c22-bf854efabebc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744337932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
2744337932
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.1461846193
Short name T545
Test name
Test status
Simulation time 65646249 ps
CPU time 2.1 seconds
Started Jul 06 06:43:19 PM PDT 24
Finished Jul 06 06:43:22 PM PDT 24
Peak memory 224068 kb
Host smart-5b0eae77-baf2-4378-8c3b-b5e28048fdc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461846193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.1461846193
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1031263058
Short name T26
Test name
Test status
Simulation time 88975890 ps
CPU time 0.76 seconds
Started Jul 06 06:43:15 PM PDT 24
Finished Jul 06 06:43:16 PM PDT 24
Peak memory 206580 kb
Host smart-691a1ec7-1140-4c67-91d9-36129a06ffef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031263058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1031263058
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.3730173394
Short name T581
Test name
Test status
Simulation time 17002417809 ps
CPU time 122.01 seconds
Started Jul 06 06:43:21 PM PDT 24
Finished Jul 06 06:45:23 PM PDT 24
Peak memory 249372 kb
Host smart-41f04bf4-0cf5-4a81-810c-39c15c511d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730173394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.3730173394
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.162116712
Short name T549
Test name
Test status
Simulation time 5991443389 ps
CPU time 14.95 seconds
Started Jul 06 06:43:19 PM PDT 24
Finished Jul 06 06:43:34 PM PDT 24
Peak memory 224520 kb
Host smart-2a8ad1e7-0650-4ea7-b32d-6f069867d12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162116712 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.162116712
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.2313054356
Short name T308
Test name
Test status
Simulation time 2023933783 ps
CPU time 12.56 seconds
Started Jul 06 06:43:19 PM PDT 24
Finished Jul 06 06:43:32 PM PDT 24
Peak memory 240872 kb
Host smart-d30dbfd0-02f3-4213-a8d8-3979a8a494b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313054356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.2313054356
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.3236962279
Short name T324
Test name
Test status
Simulation time 301044505 ps
CPU time 9.27 seconds
Started Jul 06 06:43:21 PM PDT 24
Finished Jul 06 06:43:31 PM PDT 24
Peak memory 240876 kb
Host smart-029a256c-739d-40e9-8bbd-438f228903f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236962279 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.3236962279
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.545117851
Short name T477
Test name
Test status
Simulation time 1430508814 ps
CPU time 7.03 seconds
Started Jul 06 06:43:20 PM PDT 24
Finished Jul 06 06:43:27 PM PDT 24
Peak memory 227864 kb
Host smart-2c4ab559-839d-43bb-ad20-986e15102679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=545117851 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmds
.545117851
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.2477979153
Short name T958
Test name
Test status
Simulation time 697351747 ps
CPU time 6.36 seconds
Started Jul 06 06:43:21 PM PDT 24
Finished Jul 06 06:43:28 PM PDT 24
Peak memory 232636 kb
Host smart-298fa3f8-3932-4efd-80d8-7795a1526176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477979153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.2477979153
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.3151771472
Short name T227
Test name
Test status
Simulation time 517408446 ps
CPU time 8.1 seconds
Started Jul 06 06:43:20 PM PDT 24
Finished Jul 06 06:43:28 PM PDT 24
Peak memory 232688 kb
Host smart-0a2fadfd-4957-4acb-92b5-afe0958893a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151771472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.3151771472
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.2706202737
Short name T695
Test name
Test status
Simulation time 2095352386 ps
CPU time 6.86 seconds
Started Jul 06 06:43:21 PM PDT 24
Finished Jul 06 06:43:28 PM PDT 24
Peak memory 240444 kb
Host smart-a44ee073-04f5-4256-b32f-82b1f9a255ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706202737 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swa
p.2706202737
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.2806046744
Short name T636
Test name
Test status
Simulation time 104167969 ps
CPU time 2.84 seconds
Started Jul 06 06:43:21 PM PDT 24
Finished Jul 06 06:43:24 PM PDT 24
Peak memory 232644 kb
Host smart-4f0dddd9-ea55-47ee-94fc-67e39eeac019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806046744 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.2806046744
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2028702018
Short name T911
Test name
Test status
Simulation time 3671505184 ps
CPU time 14.18 seconds
Started Jul 06 06:43:22 PM PDT 24
Finished Jul 06 06:43:37 PM PDT 24
Peak memory 222208 kb
Host smart-21bdd82a-072f-4f3d-a5bf-d34a951b326b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2028702018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2028702018
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.3932836394
Short name T665
Test name
Test status
Simulation time 703358156 ps
CPU time 0.99 seconds
Started Jul 06 06:43:20 PM PDT 24
Finished Jul 06 06:43:21 PM PDT 24
Peak memory 207604 kb
Host smart-fae37dff-d68f-4303-a2d7-af8f4967e02b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932836394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.3932836394
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.1202409306
Short name T609
Test name
Test status
Simulation time 2004583967 ps
CPU time 4.89 seconds
Started Jul 06 06:43:21 PM PDT 24
Finished Jul 06 06:43:26 PM PDT 24
Peak memory 216232 kb
Host smart-42283694-8e35-4a7f-a6b3-64b03e7c0706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1202409306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.1202409306
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.2606415988
Short name T432
Test name
Test status
Simulation time 332366957 ps
CPU time 1.61 seconds
Started Jul 06 06:43:20 PM PDT 24
Finished Jul 06 06:43:22 PM PDT 24
Peak memory 206984 kb
Host smart-9159fa94-a400-452d-9024-6abc8bcd9af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606415988 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.2606415988
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.432347359
Short name T835
Test name
Test status
Simulation time 1478118575 ps
CPU time 3.39 seconds
Started Jul 06 06:43:22 PM PDT 24
Finished Jul 06 06:43:26 PM PDT 24
Peak memory 216236 kb
Host smart-5c643004-c826-42f3-99e9-ecf19f16f40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432347359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.432347359
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.2529623976
Short name T671
Test name
Test status
Simulation time 21225924 ps
CPU time 0.76 seconds
Started Jul 06 06:43:19 PM PDT 24
Finished Jul 06 06:43:20 PM PDT 24
Peak memory 205992 kb
Host smart-a2f94bed-2cad-4bc2-a494-9b3bb37d006e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529623976 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.2529623976
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.275381608
Short name T241
Test name
Test status
Simulation time 56748457359 ps
CPU time 40.6 seconds
Started Jul 06 06:43:21 PM PDT 24
Finished Jul 06 06:44:01 PM PDT 24
Peak memory 240008 kb
Host smart-5cde13e4-e880-4c29-8873-eddcdf4049d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275381608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.275381608
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.2086313705
Short name T412
Test name
Test status
Simulation time 31529741 ps
CPU time 0.72 seconds
Started Jul 06 06:43:27 PM PDT 24
Finished Jul 06 06:43:28 PM PDT 24
Peak memory 205880 kb
Host smart-5e76bd72-6052-4bcd-9c7e-ba4bdfd2d4bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086313705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.
2086313705
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.655462484
Short name T485
Test name
Test status
Simulation time 299933480 ps
CPU time 2.82 seconds
Started Jul 06 06:43:31 PM PDT 24
Finished Jul 06 06:43:35 PM PDT 24
Peak memory 224544 kb
Host smart-5595a95c-83bc-4539-8428-03fe47838ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=655462484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.655462484
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.1745365861
Short name T570
Test name
Test status
Simulation time 47042845 ps
CPU time 0.75 seconds
Started Jul 06 06:43:20 PM PDT 24
Finished Jul 06 06:43:21 PM PDT 24
Peak memory 205852 kb
Host smart-e0dc98ef-eef0-4c3c-b8ab-cf47ec599fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745365861 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.1745365861
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.2087775204
Short name T964
Test name
Test status
Simulation time 12744819515 ps
CPU time 95.83 seconds
Started Jul 06 06:43:26 PM PDT 24
Finished Jul 06 06:45:02 PM PDT 24
Peak memory 255364 kb
Host smart-30c06d91-bd50-4407-9193-34d5db9e9d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087775204 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.2087775204
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.2989149866
Short name T206
Test name
Test status
Simulation time 2096706590 ps
CPU time 44.64 seconds
Started Jul 06 06:43:26 PM PDT 24
Finished Jul 06 06:44:11 PM PDT 24
Peak memory 241016 kb
Host smart-9f9e31e3-be89-4a67-b287-bfa788608fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989149866 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.2989149866
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.132157070
Short name T638
Test name
Test status
Simulation time 2595384743 ps
CPU time 43.55 seconds
Started Jul 06 06:43:31 PM PDT 24
Finished Jul 06 06:44:15 PM PDT 24
Peak memory 241008 kb
Host smart-8f47d2a8-490e-4122-aab2-95daf923d42b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=132157070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.132157070
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2216177529
Short name T327
Test name
Test status
Simulation time 662674462 ps
CPU time 12.12 seconds
Started Jul 06 06:43:27 PM PDT 24
Finished Jul 06 06:43:39 PM PDT 24
Peak memory 240864 kb
Host smart-7225bf47-5cd2-4062-8b54-bcfa77c553dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216177529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2216177529
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1270127771
Short name T107
Test name
Test status
Simulation time 131090635 ps
CPU time 3.61 seconds
Started Jul 06 06:43:25 PM PDT 24
Finished Jul 06 06:43:29 PM PDT 24
Peak memory 232668 kb
Host smart-01b9218f-be77-43d9-b91a-bd4f011729b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270127771 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1270127771
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.1040254477
Short name T883
Test name
Test status
Simulation time 2419582530 ps
CPU time 29.09 seconds
Started Jul 06 06:43:25 PM PDT 24
Finished Jul 06 06:43:55 PM PDT 24
Peak memory 232824 kb
Host smart-10ff1328-be36-4b64-b732-c4f5a4b5ab23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040254477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.1040254477
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.28479926
Short name T313
Test name
Test status
Simulation time 11392977525 ps
CPU time 29.84 seconds
Started Jul 06 06:43:25 PM PDT 24
Finished Jul 06 06:43:55 PM PDT 24
Peak memory 232792 kb
Host smart-fac6a090-7a29-4232-a8a2-20f80b3f85b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28479926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swap.28479926
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.3552240790
Short name T909
Test name
Test status
Simulation time 452421399 ps
CPU time 4.99 seconds
Started Jul 06 06:43:26 PM PDT 24
Finished Jul 06 06:43:31 PM PDT 24
Peak memory 232632 kb
Host smart-a883eae3-2aa6-423a-91a7-2659de8ab9c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3552240790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.3552240790
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.4132987660
Short name T932
Test name
Test status
Simulation time 1828737223 ps
CPU time 25.22 seconds
Started Jul 06 06:43:29 PM PDT 24
Finished Jul 06 06:43:54 PM PDT 24
Peak memory 220556 kb
Host smart-a83dd575-5a49-47a5-a62f-84822059ca49
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4132987660 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.4132987660
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.2678527485
Short name T523
Test name
Test status
Simulation time 203235330 ps
CPU time 0.99 seconds
Started Jul 06 06:43:25 PM PDT 24
Finished Jul 06 06:43:27 PM PDT 24
Peak memory 207440 kb
Host smart-b54380aa-9b61-445f-bc3b-4444874ee3ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678527485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stre
ss_all.2678527485
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.3918787595
Short name T687
Test name
Test status
Simulation time 7946750847 ps
CPU time 23.41 seconds
Started Jul 06 06:43:20 PM PDT 24
Finished Jul 06 06:43:44 PM PDT 24
Peak memory 216252 kb
Host smart-5ffc8e90-fffa-409f-9c04-5a2f4cd61fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918787595 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.3918787595
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.321489989
Short name T10
Test name
Test status
Simulation time 19509954 ps
CPU time 0.83 seconds
Started Jul 06 06:43:25 PM PDT 24
Finished Jul 06 06:43:26 PM PDT 24
Peak memory 206676 kb
Host smart-d98b79f3-52c3-445c-b1d9-f24b2ce5691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321489989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.321489989
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3795140626
Short name T657
Test name
Test status
Simulation time 56900635 ps
CPU time 0.74 seconds
Started Jul 06 06:43:26 PM PDT 24
Finished Jul 06 06:43:27 PM PDT 24
Peak memory 205980 kb
Host smart-b3f177ea-5fe7-4ddd-9802-e5516055d981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795140626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3795140626
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1328199825
Short name T869
Test name
Test status
Simulation time 45588600456 ps
CPU time 9.86 seconds
Started Jul 06 06:43:25 PM PDT 24
Finished Jul 06 06:43:36 PM PDT 24
Peak memory 224576 kb
Host smart-a07bcad8-fc24-4d16-a380-bed7355d5992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328199825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1328199825
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3654770418
Short name T736
Test name
Test status
Simulation time 39303256 ps
CPU time 0.76 seconds
Started Jul 06 06:39:58 PM PDT 24
Finished Jul 06 06:39:59 PM PDT 24
Peak memory 204964 kb
Host smart-a4690a58-02ac-4000-a656-4735882e8878
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654770418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
654770418
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.303109106
Short name T257
Test name
Test status
Simulation time 78937236 ps
CPU time 2.41 seconds
Started Jul 06 06:39:55 PM PDT 24
Finished Jul 06 06:39:57 PM PDT 24
Peak memory 232676 kb
Host smart-8c70e5a5-11ba-4249-834d-635cc4711e06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303109106 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.303109106
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.3238579465
Short name T505
Test name
Test status
Simulation time 48576397 ps
CPU time 0.75 seconds
Started Jul 06 06:39:54 PM PDT 24
Finished Jul 06 06:39:55 PM PDT 24
Peak memory 205536 kb
Host smart-c373f011-7295-43b9-838b-a43b21779869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3238579465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.3238579465
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3303240962
Short name T440
Test name
Test status
Simulation time 14777004865 ps
CPU time 14.57 seconds
Started Jul 06 06:39:56 PM PDT 24
Finished Jul 06 06:40:11 PM PDT 24
Peak memory 236184 kb
Host smart-dab64599-6826-4ee7-833b-fc73370c63db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3303240962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3303240962
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.802119267
Short name T310
Test name
Test status
Simulation time 61739194291 ps
CPU time 144.85 seconds
Started Jul 06 06:39:55 PM PDT 24
Finished Jul 06 06:42:20 PM PDT 24
Peak memory 250240 kb
Host smart-6fb7ce6a-4d58-4483-9948-5d1668db5efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802119267 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.802119267
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.288077923
Short name T198
Test name
Test status
Simulation time 2713145811 ps
CPU time 50.52 seconds
Started Jul 06 06:39:58 PM PDT 24
Finished Jul 06 06:40:49 PM PDT 24
Peak memory 236988 kb
Host smart-7b78d640-963e-4430-8d92-7dce51499ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288077923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle.
288077923
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.3875814019
Short name T941
Test name
Test status
Simulation time 766307853 ps
CPU time 19.04 seconds
Started Jul 06 06:39:57 PM PDT 24
Finished Jul 06 06:40:16 PM PDT 24
Peak memory 232660 kb
Host smart-7b09fa62-563d-4eb7-b6b0-def5f5ad23ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3875814019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.3875814019
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.1571246055
Short name T196
Test name
Test status
Simulation time 350580972890 ps
CPU time 198.99 seconds
Started Jul 06 06:39:55 PM PDT 24
Finished Jul 06 06:43:14 PM PDT 24
Peak memory 265156 kb
Host smart-a70ed48d-d7f8-468c-af9b-2ab4ef0077d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571246055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.1571246055
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3682961537
Short name T880
Test name
Test status
Simulation time 7303981852 ps
CPU time 11.81 seconds
Started Jul 06 06:39:56 PM PDT 24
Finished Jul 06 06:40:08 PM PDT 24
Peak memory 224484 kb
Host smart-1619afc0-3915-4b36-b528-3f2ab9632896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682961537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3682961537
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.1907918498
Short name T939
Test name
Test status
Simulation time 3224766937 ps
CPU time 19.92 seconds
Started Jul 06 06:39:55 PM PDT 24
Finished Jul 06 06:40:15 PM PDT 24
Peak memory 240948 kb
Host smart-d837759a-bbb5-4b38-a26b-787352df4f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907918498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.1907918498
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.2539561664
Short name T478
Test name
Test status
Simulation time 6069187823 ps
CPU time 7.54 seconds
Started Jul 06 06:39:52 PM PDT 24
Finished Jul 06 06:40:00 PM PDT 24
Peak memory 232772 kb
Host smart-1ea0b874-2855-4182-98ea-4d1114fd6d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539561664 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.2539561664
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.2623629242
Short name T974
Test name
Test status
Simulation time 3452005654 ps
CPU time 7.52 seconds
Started Jul 06 06:39:52 PM PDT 24
Finished Jul 06 06:40:00 PM PDT 24
Peak memory 232720 kb
Host smart-011cca87-0f42-40fe-8902-05dc5de64ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623629242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.2623629242
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.2776204315
Short name T644
Test name
Test status
Simulation time 1740044078 ps
CPU time 9.78 seconds
Started Jul 06 06:39:54 PM PDT 24
Finished Jul 06 06:40:04 PM PDT 24
Peak memory 222080 kb
Host smart-9a42ff7f-4e98-428d-b7cc-72b1955c7104
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2776204315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.2776204315
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1237318401
Short name T191
Test name
Test status
Simulation time 37145736634 ps
CPU time 227.02 seconds
Started Jul 06 06:39:53 PM PDT 24
Finished Jul 06 06:43:41 PM PDT 24
Peak memory 271280 kb
Host smart-75f0bbd4-6d06-4594-9685-a48061753c94
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237318401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1237318401
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.2947138302
Short name T488
Test name
Test status
Simulation time 3173832322 ps
CPU time 26.22 seconds
Started Jul 06 06:39:52 PM PDT 24
Finished Jul 06 06:40:19 PM PDT 24
Peak memory 216380 kb
Host smart-0d7337df-94db-4526-a33e-c19fcf6154c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947138302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.2947138302
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.2730650274
Short name T358
Test name
Test status
Simulation time 16141045 ps
CPU time 0.75 seconds
Started Jul 06 06:39:50 PM PDT 24
Finished Jul 06 06:39:51 PM PDT 24
Peak memory 205696 kb
Host smart-d8d5b5eb-f0cc-4f3d-bb1c-a00ea7ef167c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730650274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.2730650274
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.1321779691
Short name T656
Test name
Test status
Simulation time 427870023 ps
CPU time 2.79 seconds
Started Jul 06 06:39:53 PM PDT 24
Finished Jul 06 06:39:56 PM PDT 24
Peak memory 216264 kb
Host smart-6882dd40-bbb8-485d-a8e2-1336a9774422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321779691 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.1321779691
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.1671948097
Short name T864
Test name
Test status
Simulation time 61229623 ps
CPU time 0.82 seconds
Started Jul 06 06:39:53 PM PDT 24
Finished Jul 06 06:39:55 PM PDT 24
Peak memory 205976 kb
Host smart-b98e9f74-17c0-4d76-8b84-caf0fc0746fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671948097 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.1671948097
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.3730984023
Short name T108
Test name
Test status
Simulation time 12300693716 ps
CPU time 14.75 seconds
Started Jul 06 06:39:54 PM PDT 24
Finished Jul 06 06:40:09 PM PDT 24
Peak memory 224640 kb
Host smart-03bd03df-90d1-418a-830a-360e3754a545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730984023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.3730984023
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.2184192856
Short name T513
Test name
Test status
Simulation time 13063377 ps
CPU time 0.72 seconds
Started Jul 06 06:39:59 PM PDT 24
Finished Jul 06 06:40:00 PM PDT 24
Peak memory 204988 kb
Host smart-aaf6ca00-10de-48d8-8a2b-c9712fe9aa80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184192856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.2
184192856
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1058249663
Short name T870
Test name
Test status
Simulation time 3062275878 ps
CPU time 16.45 seconds
Started Jul 06 06:40:01 PM PDT 24
Finished Jul 06 06:40:18 PM PDT 24
Peak memory 224608 kb
Host smart-582c9648-7652-460d-be37-1fe21230961b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058249663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1058249663
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.2981130486
Short name T27
Test name
Test status
Simulation time 40063510 ps
CPU time 0.78 seconds
Started Jul 06 06:39:55 PM PDT 24
Finished Jul 06 06:39:56 PM PDT 24
Peak memory 206604 kb
Host smart-9e264ac2-4380-4055-abf2-e77ce83674f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981130486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.2981130486
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.1099719040
Short name T315
Test name
Test status
Simulation time 5122682484 ps
CPU time 21.11 seconds
Started Jul 06 06:40:01 PM PDT 24
Finished Jul 06 06:40:22 PM PDT 24
Peak memory 232816 kb
Host smart-e79b24f8-a9a9-4587-8c1f-579c1911e430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099719040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.1099719040
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.3088494678
Short name T913
Test name
Test status
Simulation time 35387185900 ps
CPU time 137.5 seconds
Started Jul 06 06:40:00 PM PDT 24
Finished Jul 06 06:42:18 PM PDT 24
Peak memory 239176 kb
Host smart-9770dfba-2820-497f-95ec-594f49988ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088494678 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.3088494678
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.3896113141
Short name T213
Test name
Test status
Simulation time 2493147242 ps
CPU time 51.12 seconds
Started Jul 06 06:40:00 PM PDT 24
Finished Jul 06 06:40:51 PM PDT 24
Peak memory 249284 kb
Host smart-6cfe1a3a-bb72-4509-bf8f-3b2de94e782e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896113141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.3896113141
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.202594187
Short name T366
Test name
Test status
Simulation time 828354084 ps
CPU time 4.14 seconds
Started Jul 06 06:39:59 PM PDT 24
Finished Jul 06 06:40:03 PM PDT 24
Peak memory 224472 kb
Host smart-8a41bc85-e8d3-41bd-9fc4-3ae411fd3476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202594187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.202594187
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.1963124366
Short name T584
Test name
Test status
Simulation time 4917687422 ps
CPU time 17.94 seconds
Started Jul 06 06:40:00 PM PDT 24
Finished Jul 06 06:40:18 PM PDT 24
Peak memory 236668 kb
Host smart-c3e3fd94-65c0-4e0d-9de3-af993424783c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963124366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds
.1963124366
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.2922800575
Short name T233
Test name
Test status
Simulation time 1169950831 ps
CPU time 4.99 seconds
Started Jul 06 06:40:01 PM PDT 24
Finished Jul 06 06:40:06 PM PDT 24
Peak memory 232616 kb
Host smart-f5241e61-5078-4ed4-9dd2-45be2083683f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922800575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.2922800575
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.583488989
Short name T902
Test name
Test status
Simulation time 352116745 ps
CPU time 7.57 seconds
Started Jul 06 06:39:59 PM PDT 24
Finished Jul 06 06:40:07 PM PDT 24
Peak memory 232648 kb
Host smart-44403351-5d0b-425c-86f9-4db03a7193b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583488989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.583488989
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.63400826
Short name T35
Test name
Test status
Simulation time 7612192485 ps
CPU time 10.28 seconds
Started Jul 06 06:40:01 PM PDT 24
Finished Jul 06 06:40:12 PM PDT 24
Peak memory 232692 kb
Host smart-72c706a3-8bd1-4d27-96be-16458a14b3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63400826 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.63400826
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.417999119
Short name T829
Test name
Test status
Simulation time 14668318781 ps
CPU time 32.58 seconds
Started Jul 06 06:39:59 PM PDT 24
Finished Jul 06 06:40:32 PM PDT 24
Peak memory 224644 kb
Host smart-b248fec5-c559-445d-a6fe-fec7c01de483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417999119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.417999119
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.3053317128
Short name T161
Test name
Test status
Simulation time 57181804 ps
CPU time 3.16 seconds
Started Jul 06 06:40:01 PM PDT 24
Finished Jul 06 06:40:04 PM PDT 24
Peak memory 219364 kb
Host smart-ec43730e-7477-4c04-8d87-49e6847d78bc
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3053317128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_dire
ct.3053317128
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.1372397404
Short name T174
Test name
Test status
Simulation time 2420263157 ps
CPU time 18.77 seconds
Started Jul 06 06:39:59 PM PDT 24
Finished Jul 06 06:40:18 PM PDT 24
Peak memory 224564 kb
Host smart-04f1f216-88cc-481d-a798-e3e515219943
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372397404 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stres
s_all.1372397404
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3520774656
Short name T629
Test name
Test status
Simulation time 17264390545 ps
CPU time 49.62 seconds
Started Jul 06 06:39:55 PM PDT 24
Finished Jul 06 06:40:45 PM PDT 24
Peak memory 221844 kb
Host smart-8857f152-aef3-4812-b4d9-d0ecabb16677
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520774656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3520774656
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.566746461
Short name T442
Test name
Test status
Simulation time 5745408864 ps
CPU time 7.94 seconds
Started Jul 06 06:39:53 PM PDT 24
Finished Jul 06 06:40:01 PM PDT 24
Peak memory 216296 kb
Host smart-8046e996-6e52-497f-a9a2-9d9c84faf1b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566746461 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.566746461
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3532219772
Short name T395
Test name
Test status
Simulation time 93940124 ps
CPU time 1.64 seconds
Started Jul 06 06:40:01 PM PDT 24
Finished Jul 06 06:40:03 PM PDT 24
Peak memory 207984 kb
Host smart-e23a7b34-a2ae-443c-b707-a28742eb30c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532219772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3532219772
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2444275948
Short name T1008
Test name
Test status
Simulation time 224960514 ps
CPU time 1.05 seconds
Started Jul 06 06:39:56 PM PDT 24
Finished Jul 06 06:39:57 PM PDT 24
Peak memory 205964 kb
Host smart-c20d90b4-1d75-41e7-a799-6f6958f42996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2444275948 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2444275948
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.1827305559
Short name T918
Test name
Test status
Simulation time 6140623487 ps
CPU time 10.24 seconds
Started Jul 06 06:40:01 PM PDT 24
Finished Jul 06 06:40:11 PM PDT 24
Peak memory 232796 kb
Host smart-f7152e85-23c7-45e5-840e-e0ade7fd4562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827305559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.1827305559
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4283351488
Short name T78
Test name
Test status
Simulation time 13448195 ps
CPU time 0.72 seconds
Started Jul 06 06:40:10 PM PDT 24
Finished Jul 06 06:40:11 PM PDT 24
Peak memory 205532 kb
Host smart-f11b0e2a-1471-44c2-804a-578e79c00352
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283351488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
283351488
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2197271990
Short name T499
Test name
Test status
Simulation time 111102528 ps
CPU time 2.25 seconds
Started Jul 06 06:40:02 PM PDT 24
Finished Jul 06 06:40:05 PM PDT 24
Peak memory 223888 kb
Host smart-b73ef7d4-21d4-4519-bbec-dc82ebab9d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197271990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2197271990
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2198711939
Short name T564
Test name
Test status
Simulation time 170369525 ps
CPU time 0.74 seconds
Started Jul 06 06:39:58 PM PDT 24
Finished Jul 06 06:39:59 PM PDT 24
Peak memory 205568 kb
Host smart-42f4cf87-e5ff-442c-9e0a-e92236a14b22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2198711939 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2198711939
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.566583360
Short name T552
Test name
Test status
Simulation time 77077775325 ps
CPU time 119.51 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:42:17 PM PDT 24
Peak memory 249160 kb
Host smart-0d3117bb-6ecd-4716-b929-54a701e0e07b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566583360 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.566583360
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2324799219
Short name T43
Test name
Test status
Simulation time 25954138749 ps
CPU time 240.93 seconds
Started Jul 06 06:40:09 PM PDT 24
Finished Jul 06 06:44:10 PM PDT 24
Peak memory 257412 kb
Host smart-68550aa5-b39b-4e05-9ae9-494569f5c907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324799219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2324799219
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.2934075812
Short name T969
Test name
Test status
Simulation time 62856066678 ps
CPU time 314.21 seconds
Started Jul 06 06:40:10 PM PDT 24
Finished Jul 06 06:45:24 PM PDT 24
Peak memory 266664 kb
Host smart-fc492cf8-8229-4406-b57b-e7f438d0635b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934075812 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle
.2934075812
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2579595525
Short name T443
Test name
Test status
Simulation time 583619533 ps
CPU time 7.23 seconds
Started Jul 06 06:40:07 PM PDT 24
Finished Jul 06 06:40:15 PM PDT 24
Peak memory 224512 kb
Host smart-2a078cc4-f7ad-41ea-86c5-0f5089f3c8fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579595525 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2579595525
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.3381447894
Short name T612
Test name
Test status
Simulation time 6242506976 ps
CPU time 66.78 seconds
Started Jul 06 06:40:08 PM PDT 24
Finished Jul 06 06:41:15 PM PDT 24
Peak memory 264720 kb
Host smart-30d25f67-8373-47e7-9040-8fa84dbd7833
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381447894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds
.3381447894
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.3414573563
Short name T492
Test name
Test status
Simulation time 15314804106 ps
CPU time 28.24 seconds
Started Jul 06 06:40:03 PM PDT 24
Finished Jul 06 06:40:32 PM PDT 24
Peak memory 224640 kb
Host smart-fb3daddd-de1d-498e-8b78-07f420eb03e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414573563 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.3414573563
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1419415102
Short name T786
Test name
Test status
Simulation time 31358888 ps
CPU time 2 seconds
Started Jul 06 06:40:04 PM PDT 24
Finished Jul 06 06:40:06 PM PDT 24
Peak memory 224124 kb
Host smart-5e42016d-051c-4d09-86b3-52a0c2aec602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419415102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1419415102
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.4092580544
Short name T992
Test name
Test status
Simulation time 1511927620 ps
CPU time 6.15 seconds
Started Jul 06 06:40:03 PM PDT 24
Finished Jul 06 06:40:10 PM PDT 24
Peak memory 238404 kb
Host smart-ec7ea8f5-3743-4619-9254-381bb4ec072b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092580544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.4092580544
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2711562884
Short name T861
Test name
Test status
Simulation time 1313029067 ps
CPU time 5.46 seconds
Started Jul 06 06:40:03 PM PDT 24
Finished Jul 06 06:40:08 PM PDT 24
Peak memory 224524 kb
Host smart-9a594586-56e4-42f0-a8b4-9e1b706402dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711562884 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2711562884
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.2442987297
Short name T915
Test name
Test status
Simulation time 800952642 ps
CPU time 5.89 seconds
Started Jul 06 06:40:06 PM PDT 24
Finished Jul 06 06:40:13 PM PDT 24
Peak memory 222468 kb
Host smart-74c4b2de-4e88-4ebe-82db-a8d109e8ded8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2442987297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_dire
ct.2442987297
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.4161818599
Short name T19
Test name
Test status
Simulation time 43062370 ps
CPU time 1 seconds
Started Jul 06 06:40:09 PM PDT 24
Finished Jul 06 06:40:10 PM PDT 24
Peak memory 206936 kb
Host smart-1b1dc415-4a0f-4666-b61a-1831241535ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161818599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.4161818599
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2793316661
Short name T336
Test name
Test status
Simulation time 7116531210 ps
CPU time 20.98 seconds
Started Jul 06 06:40:00 PM PDT 24
Finished Jul 06 06:40:22 PM PDT 24
Peak memory 216392 kb
Host smart-9bcf6955-c869-4e41-8186-2e38e5c3bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793316661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2793316661
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2256700397
Short name T92
Test name
Test status
Simulation time 409686672 ps
CPU time 2.94 seconds
Started Jul 06 06:40:02 PM PDT 24
Finished Jul 06 06:40:05 PM PDT 24
Peak memory 216144 kb
Host smart-d2b8941d-51b1-4147-b4e2-3463096f5d31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2256700397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2256700397
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3257983103
Short name T613
Test name
Test status
Simulation time 28811696 ps
CPU time 0.67 seconds
Started Jul 06 06:39:59 PM PDT 24
Finished Jul 06 06:40:00 PM PDT 24
Peak memory 205648 kb
Host smart-9dfcf605-6b61-4083-9938-dd071b23b2e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257983103 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3257983103
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1862371611
Short name T430
Test name
Test status
Simulation time 118571057 ps
CPU time 0.86 seconds
Started Jul 06 06:40:02 PM PDT 24
Finished Jul 06 06:40:03 PM PDT 24
Peak memory 206976 kb
Host smart-de860ed3-c882-4740-a0b3-80ffb89fa250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862371611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1862371611
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2803685006
Short name T237
Test name
Test status
Simulation time 13754260380 ps
CPU time 10.47 seconds
Started Jul 06 06:40:04 PM PDT 24
Finished Jul 06 06:40:15 PM PDT 24
Peak memory 224584 kb
Host smart-684afa66-ef73-4948-92fb-e839fcb9962d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803685006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2803685006
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.983151829
Short name T427
Test name
Test status
Simulation time 80477169 ps
CPU time 0.7 seconds
Started Jul 06 06:40:14 PM PDT 24
Finished Jul 06 06:40:16 PM PDT 24
Peak memory 204988 kb
Host smart-e84661cb-6b9c-45f6-8200-22c15d911952
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983151829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.983151829
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.2178381070
Short name T76
Test name
Test status
Simulation time 1768085285 ps
CPU time 7.09 seconds
Started Jul 06 06:40:11 PM PDT 24
Finished Jul 06 06:40:18 PM PDT 24
Peak memory 232660 kb
Host smart-9711e209-6c79-4cdc-8b45-0b20127af1c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178381070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.2178381070
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.1697755239
Short name T364
Test name
Test status
Simulation time 13678396 ps
CPU time 0.8 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:40:19 PM PDT 24
Peak memory 206600 kb
Host smart-d805208a-f4d4-4c94-92c2-abc2fa179ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697755239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.1697755239
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.2507711382
Short name T215
Test name
Test status
Simulation time 110813772312 ps
CPU time 225.67 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:44:04 PM PDT 24
Peak memory 264992 kb
Host smart-f6b0821f-db4e-4b5a-97ed-901f97414a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507711382 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.2507711382
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3110524471
Short name T64
Test name
Test status
Simulation time 5368995931 ps
CPU time 125.41 seconds
Started Jul 06 06:40:12 PM PDT 24
Finished Jul 06 06:42:17 PM PDT 24
Peak memory 249212 kb
Host smart-adb58ef8-8511-466a-9bad-793e21735c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110524471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3110524471
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.533246900
Short name T9
Test name
Test status
Simulation time 105278725 ps
CPU time 0.86 seconds
Started Jul 06 06:40:12 PM PDT 24
Finished Jul 06 06:40:13 PM PDT 24
Peak memory 217048 kb
Host smart-19f1cd19-7469-4125-91e1-2d5f3d2fcac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533246900 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle.
533246900
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.3994685986
Short name T335
Test name
Test status
Simulation time 1084598422 ps
CPU time 11.06 seconds
Started Jul 06 06:40:11 PM PDT 24
Finished Jul 06 06:40:22 PM PDT 24
Peak memory 232708 kb
Host smart-b5894091-eaad-4810-8700-269c155bd060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3994685986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.3994685986
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.63461437
Short name T205
Test name
Test status
Simulation time 90191610926 ps
CPU time 599.06 seconds
Started Jul 06 06:40:12 PM PDT 24
Finished Jul 06 06:50:11 PM PDT 24
Peak memory 288188 kb
Host smart-6dbf2579-e1f6-4207-9143-dd4a27674a1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63461437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds.63461437
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.949201203
Short name T977
Test name
Test status
Simulation time 2011760708 ps
CPU time 6.54 seconds
Started Jul 06 06:40:09 PM PDT 24
Finished Jul 06 06:40:16 PM PDT 24
Peak memory 232676 kb
Host smart-627cd709-aad1-467a-87f7-882231bd047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949201203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.949201203
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.3920805186
Short name T90
Test name
Test status
Simulation time 687990629 ps
CPU time 4.31 seconds
Started Jul 06 06:40:07 PM PDT 24
Finished Jul 06 06:40:12 PM PDT 24
Peak memory 227684 kb
Host smart-bec13b68-d744-4075-8d35-2d21743ba90d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920805186 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.3920805186
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.2329225162
Short name T834
Test name
Test status
Simulation time 453577024 ps
CPU time 2.33 seconds
Started Jul 06 06:40:10 PM PDT 24
Finished Jul 06 06:40:13 PM PDT 24
Peak memory 224412 kb
Host smart-ed7698e3-f757-4ec7-9080-e48a47326fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2329225162 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap
.2329225162
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2014463008
Short name T15
Test name
Test status
Simulation time 255618095 ps
CPU time 2.63 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:40:20 PM PDT 24
Peak memory 224412 kb
Host smart-f40b256a-836f-4ca1-8c0e-1ae5ccaa523f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014463008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2014463008
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.195938487
Short name T800
Test name
Test status
Simulation time 1858002142 ps
CPU time 13.27 seconds
Started Jul 06 06:40:11 PM PDT 24
Finished Jul 06 06:40:25 PM PDT 24
Peak memory 220328 kb
Host smart-a0ca6ae0-a254-45ab-8828-866d2629da5f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=195938487 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.195938487
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.2413205435
Short name T166
Test name
Test status
Simulation time 13783845533 ps
CPU time 137.78 seconds
Started Jul 06 06:40:12 PM PDT 24
Finished Jul 06 06:42:30 PM PDT 24
Peak memory 241420 kb
Host smart-02966cfb-d19f-41ca-a8ac-10d4664de3e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2413205435 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.2413205435
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.757723555
Short name T582
Test name
Test status
Simulation time 4113183977 ps
CPU time 13.33 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:40:31 PM PDT 24
Peak memory 216340 kb
Host smart-1f35c2cc-7d13-4f38-99b7-9281a9337a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=757723555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.757723555
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.519193877
Short name T998
Test name
Test status
Simulation time 3946693233 ps
CPU time 6.59 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:40:24 PM PDT 24
Peak memory 216276 kb
Host smart-c06498fe-2f42-42c2-95a4-2d1cc4352642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519193877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.519193877
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.2422379885
Short name T533
Test name
Test status
Simulation time 1768188678 ps
CPU time 2.43 seconds
Started Jul 06 06:40:10 PM PDT 24
Finished Jul 06 06:40:13 PM PDT 24
Peak memory 216228 kb
Host smart-7d9a0801-403f-41f5-9cb7-29e55a4e9335
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422379885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.2422379885
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.869410532
Short name T454
Test name
Test status
Simulation time 37844882 ps
CPU time 0.86 seconds
Started Jul 06 06:40:09 PM PDT 24
Finished Jul 06 06:40:10 PM PDT 24
Peak memory 207028 kb
Host smart-8ab4f5ae-9b8d-41aa-ac2a-5b3033ce0e0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869410532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.869410532
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.2373223573
Short name T703
Test name
Test status
Simulation time 3681791744 ps
CPU time 14.18 seconds
Started Jul 06 06:40:08 PM PDT 24
Finished Jul 06 06:40:22 PM PDT 24
Peak memory 240904 kb
Host smart-9a83d3b6-ebd8-4aab-a0ce-a5e71529707b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373223573 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.2373223573
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3352311357
Short name T439
Test name
Test status
Simulation time 21105263 ps
CPU time 0.7 seconds
Started Jul 06 06:40:21 PM PDT 24
Finished Jul 06 06:40:23 PM PDT 24
Peak memory 204984 kb
Host smart-990ace95-9751-4353-8a53-1a3bf33539c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352311357 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
352311357
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1054312394
Short name T410
Test name
Test status
Simulation time 36653893 ps
CPU time 2.43 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:40:20 PM PDT 24
Peak memory 232652 kb
Host smart-7567d888-0b14-42f7-bb27-fdb888fe2c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1054312394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1054312394
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2618768534
Short name T966
Test name
Test status
Simulation time 40868864 ps
CPU time 0.72 seconds
Started Jul 06 06:40:15 PM PDT 24
Finished Jul 06 06:40:16 PM PDT 24
Peak memory 205564 kb
Host smart-c414ec73-c042-4621-978a-05601efb7707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618768534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2618768534
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.2724489420
Short name T1005
Test name
Test status
Simulation time 21022380885 ps
CPU time 89.1 seconds
Started Jul 06 06:40:22 PM PDT 24
Finished Jul 06 06:41:52 PM PDT 24
Peak memory 249200 kb
Host smart-f4a11bf2-24b2-4ec7-bd8b-312dd1bd15b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724489420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.2724489420
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.2008223182
Short name T843
Test name
Test status
Simulation time 12913283939 ps
CPU time 66.53 seconds
Started Jul 06 06:40:19 PM PDT 24
Finished Jul 06 06:41:26 PM PDT 24
Peak memory 249288 kb
Host smart-d1dc30f4-2cd7-4b70-8830-111ffa9abea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008223182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.2008223182
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.2179672414
Short name T88
Test name
Test status
Simulation time 1861755324 ps
CPU time 27.34 seconds
Started Jul 06 06:40:33 PM PDT 24
Finished Jul 06 06:41:01 PM PDT 24
Peak memory 240392 kb
Host smart-b905a6f5-9bd5-4211-9b23-a7d1eeec7dfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179672414 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.2179672414
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.1925646947
Short name T672
Test name
Test status
Simulation time 367744269 ps
CPU time 5.02 seconds
Started Jul 06 06:40:14 PM PDT 24
Finished Jul 06 06:40:19 PM PDT 24
Peak memory 224784 kb
Host smart-c1b6aadf-d9ac-4679-aeb4-abf9a1f5f18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925646947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.1925646947
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.1773148367
Short name T912
Test name
Test status
Simulation time 21926448890 ps
CPU time 72.55 seconds
Started Jul 06 06:40:31 PM PDT 24
Finished Jul 06 06:41:44 PM PDT 24
Peak memory 240964 kb
Host smart-3cbca81d-477b-40b3-a493-0af528f1527e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773148367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.1773148367
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2003733635
Short name T898
Test name
Test status
Simulation time 3691674111 ps
CPU time 27.57 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:40:45 PM PDT 24
Peak memory 232752 kb
Host smart-5a3ca99a-5293-4dde-82d6-4f8d38f7810b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2003733635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2003733635
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.2834697517
Short name T452
Test name
Test status
Simulation time 11189355449 ps
CPU time 61.97 seconds
Started Jul 06 06:40:16 PM PDT 24
Finished Jul 06 06:41:18 PM PDT 24
Peak memory 240756 kb
Host smart-25aaf2a9-4abf-4633-a633-9e558d1b3ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2834697517 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.2834697517
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.1487682575
Short name T895
Test name
Test status
Simulation time 1857530613 ps
CPU time 3.44 seconds
Started Jul 06 06:40:18 PM PDT 24
Finished Jul 06 06:40:22 PM PDT 24
Peak memory 224484 kb
Host smart-01d90283-d04e-4b2f-874f-2edb61ae4ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487682575 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap
.1487682575
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.3096339965
Short name T264
Test name
Test status
Simulation time 4528403889 ps
CPU time 13.37 seconds
Started Jul 06 06:40:19 PM PDT 24
Finished Jul 06 06:40:33 PM PDT 24
Peak memory 232756 kb
Host smart-6b926ed1-3fed-40d4-a136-c9f485133a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096339965 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.3096339965
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.4213535134
Short name T747
Test name
Test status
Simulation time 2110799229 ps
CPU time 10.92 seconds
Started Jul 06 06:40:33 PM PDT 24
Finished Jul 06 06:40:44 PM PDT 24
Peak memory 220372 kb
Host smart-1eac5fb3-2def-47e8-897f-031a142adff7
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4213535134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.4213535134
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.2158339275
Short name T288
Test name
Test status
Simulation time 78447818275 ps
CPU time 588.96 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:50:06 PM PDT 24
Peak memory 273672 kb
Host smart-cfcb8b47-1755-495a-bb3b-d463b7e37704
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158339275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.2158339275
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3450366648
Short name T28
Test name
Test status
Simulation time 2186911872 ps
CPU time 19.3 seconds
Started Jul 06 06:40:18 PM PDT 24
Finished Jul 06 06:40:37 PM PDT 24
Peak memory 216252 kb
Host smart-100c3c02-cbba-4cfd-936d-264806892da6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450366648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3450366648
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.204586933
Short name T529
Test name
Test status
Simulation time 5687639921 ps
CPU time 5.06 seconds
Started Jul 06 06:40:17 PM PDT 24
Finished Jul 06 06:40:23 PM PDT 24
Peak memory 216320 kb
Host smart-9cc51d93-57fd-4c64-ac73-14c202eb1fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204586933 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.204586933
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.4083191690
Short name T722
Test name
Test status
Simulation time 64908293 ps
CPU time 1.93 seconds
Started Jul 06 06:40:18 PM PDT 24
Finished Jul 06 06:40:20 PM PDT 24
Peak memory 216252 kb
Host smart-d09a0bd7-50d3-4c52-b714-cae498fcd15b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4083191690 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.4083191690
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.3835549253
Short name T625
Test name
Test status
Simulation time 438959326 ps
CPU time 0.83 seconds
Started Jul 06 06:40:14 PM PDT 24
Finished Jul 06 06:40:16 PM PDT 24
Peak memory 206024 kb
Host smart-f3a378a1-e302-405a-9eea-66c616ca1750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3835549253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.3835549253
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.3890658672
Short name T278
Test name
Test status
Simulation time 721983603 ps
CPU time 2.99 seconds
Started Jul 06 06:40:19 PM PDT 24
Finished Jul 06 06:40:22 PM PDT 24
Peak memory 224412 kb
Host smart-4df06720-ac5e-43ea-b7c5-528d2472ca29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890658672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.3890658672
Directory /workspace/9.spi_device_upload/latest
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