Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2447561	1			T1	1		T2	1005		T3	1
all_values[1]	2447561	1			T1	1		T2	1005		T3	1
all_values[2]	2447561	1			T1	1		T2	1005		T3	1
all_values[3]	2447561	1			T1	1		T2	1005		T3	1
all_values[4]	2447561	1			T1	1		T2	1005		T3	1
all_values[5]	2447561	1			T1	1		T2	1005		T3	1
all_values[6]	2447561	1			T1	1		T2	1005		T3	1
all_values[7]	2447561	1			T1	1		T2	1005		T3	1

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19443116

1

T1

8

T2

8040

T3

8

auto[1]

137372

1

T13

44

T14

85

T15

33

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

19556272

1

T1

8

T2

8040

T3

8

auto[1]

24216

1

T33

51

T34

23

T13

228

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2435447	1			T1	1		T2	1005		T3	1
all_values[0]	auto[0]	auto[1]	11618	1			T33	19		T34	15		T13	106
all_values[0]	auto[1]	auto[0]	295	1			T13	6		T14	8		T15	5
all_values[0]	auto[1]	auto[1]	201	1			T13	1		T14	7		T15	2
all_values[1]	auto[0]	auto[0]	2414407	1			T1	1		T2	1005		T3	1
all_values[1]	auto[0]	auto[1]	7129	1			T33	19		T34	4		T13	93
all_values[1]	auto[1]	auto[0]	25710	1			T13	3		T14	9		T15	2
all_values[1]	auto[1]	auto[1]	315	1			T13	2		T14	3		T15	2
all_values[2]	auto[0]	auto[0]	2416881	1			T1	1		T2	1005		T3	1
all_values[2]	auto[0]	auto[1]	2753	1			T33	13		T34	4		T13	7
all_values[2]	auto[1]	auto[0]	27614	1			T13	2		T14	9		T15	1
all_values[2]	auto[1]	auto[1]	313	1			T13	2		T14	4		T15	2
all_values[3]	auto[0]	auto[0]	2421383	1			T1	1		T2	1005		T3	1
all_values[3]	auto[0]	auto[1]	188	1			T14	4		T15	1		T17	1
all_values[3]	auto[1]	auto[0]	25779	1			T13	4		T14	2		T17	25496
all_values[3]	auto[1]	auto[1]	211	1			T13	1		T14	1		T15	2
all_values[4]	auto[0]	auto[0]	2419607	1			T1	1		T2	1005		T3	1
all_values[4]	auto[0]	auto[1]	161	1			T13	1		T14	9		T19	3
all_values[4]	auto[1]	auto[0]	27589	1			T13	6		T14	4		T15	2
all_values[4]	auto[1]	auto[1]	204	1			T13	1		T14	5		T15	5
all_values[5]	auto[0]	auto[0]	2446719	1			T1	1		T2	1005		T3	1
all_values[5]	auto[0]	auto[1]	176	1			T13	2		T14	1		T15	2
all_values[5]	auto[1]	auto[0]	497	1			T13	1		T14	6		T15	1
all_values[5]	auto[1]	auto[1]	169	1			T13	5		T14	4		T15	1
all_values[6]	auto[0]	auto[0]	2444912	1			T1	1		T2	1005		T3	1
all_values[6]	auto[0]	auto[1]	166	1			T13	3		T14	4		T15	4
all_values[6]	auto[1]	auto[0]	2265	1			T13	3		T14	9		T15	1
all_values[6]	auto[1]	auto[1]	218	1			T13	3		T14	2		T15	2
all_values[7]	auto[0]	auto[0]	2421397	1			T1	1		T2	1005		T3	1
all_values[7]	auto[0]	auto[1]	172	1			T14	1		T15	1		T19	5
all_values[7]	auto[1]	auto[0]	25770	1			T13	3		T14	4		T15	4
all_values[7]	auto[1]	auto[1]	222	1			T13	1		T14	8		T15	1