Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31043	1			T3	10		T5	2		T9	84
auto[SpiFlashAddrCfg]	7236	1			T1	1		T6	1		T7	2
auto[SpiFlashAddr3b]	8628	1			T5	2		T6	3		T9	61
auto[SpiFlashAddr4b]	7260	1			T1	2		T4	1		T5	6

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31683

1

T1

3

T3

10

T4

1

auto[1]

22484

1

T5

10

T9

105

T11

7

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

29463

1

T3

10

T5

6

T6

2

auto[1]

24704

1

T1

3

T4

1

T5

4

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	35278	1			T3	10		T9	108		T11	9
values[1]	1119	1			T9	3		T11	2		T12	5
values[2]	1357	1			T5	4		T9	17		T12	7
values[3]	1414	1			T9	15		T12	8		T40	2
values[4]	1356	1			T9	6		T12	10		T33	13
values[5]	1468	1			T4	1		T9	7		T11	4
values[6]	1433	1			T9	10		T12	13		T40	2
values[7]	1336	1			T5	2		T9	22		T12	8
values[8]	9406	1			T1	3		T5	4		T6	4

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

26193

1

T3

10

T5

10

T7

2

auto[1]

27974

1

T1

3

T4

1

T6

4

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

51151

1

T1

3

T3

10

T4

1

write

3016

1

T9

21

T11

2

T12

13

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18350

1

T1

3

T3

10

T5

2

valids[0x1]

35817

1

T4

1

T5

8

T6

2

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1532	1			T9	6		T12	9		T44	4
internal_process_ops[0x5a]	1528	1			T9	8		T11	1		T12	8
internal_process_ops[0x05]	17476	1			T9	10		T12	9		T40	88
internal_process_ops[0x35]	1559	1			T9	12		T11	2		T12	5
internal_process_ops[0x15]	1482	1			T9	7		T12	8		T44	6
internal_process_ops[0x03]	1038	1			T5	2		T7	2		T8	1
internal_process_ops[0x0b]	1002	1			T4	1		T6	2		T9	8
internal_process_ops[0x3b]	976	1			T6	1		T9	12		T12	3
internal_process_ops[0x6b]	941	1			T8	1		T9	6		T33	7
internal_process_ops[0xbb]	876	1			T1	1		T9	11		T12	4
internal_process_ops[0xeb]	969	1			T1	2		T6	1		T9	9

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

52699

1

T1

3

T3

10

T4

1

auto[1]

1468

1

T9

11

T11

2

T12

12

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

51949

1

T1

3

T3

10

T4

1

auto[1]

2218

1

T9

17

T11

1

T12

8

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

8426

1

T3

10

T9

57

T44

10

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4992

1

T5

2

T9

23

T33

120

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1942

1

T7

2

T9

30

T40

8

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1648

1

T9

31

T33

23

T34

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2273

1

T9

33

T33

36

T39

2

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1987

1

T5

2

T9

18

T33

30

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1800

1

T9

24

T40

4

T33

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1677

1

T5

6

T9

23

T33

30

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

96

1

T14

2

T42

3

T18

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

86

1

T33

1

T43

1

T47

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T9

2

T33

1

T34

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

102

1

T9

2

T33

1

T42

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

107

1

T9

2

T33

1

T34

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

79

1

T9

1

T34

3

T14

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

77

1

T9

1

T42

2

T15

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

99

1

T9

2

T14

4

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

120

1

T9

2

T33

6

T39

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

82

1

T9

5

T33

4

T34

2

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

81

1

T9

3

T33

5

T42

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

93

1

T42

1

T15

2

T43

6

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T40

2

T33

2

T14

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

66

1

T9

1

T33

3

T42

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

70

1

T42

3

T172

1

T173

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

87

1

T34

1

T42

2

T43

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10804

1

T11

7

T12

53

T41

266

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

6065

1

T11

1

T12

34

T41

51

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1519

1

T1

1

T6

1

T12

16

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1365

1

T12

26

T41

7

T13

2

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

1849

1

T6

3

T11

5

T12

15

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1758

1

T11

4

T12

26

T41

10

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1538

1

T1

2

T4

1

T8

2

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1508

1

T12

19

T41

19

T13

9

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

93

1

T13

2

T37

2

T92

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

81

1

T12

1

T25

2

T174

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

85

1

T92

3

T175

3

T176

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

128

1

T41

1

T29

1

T37

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

88

1

T41

2

T25

2

T29

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

105

1

T12

2

T13

1

T37

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

128

1

T41

2

T13

3

T92

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

79

1

T12

3

T25

1

T37

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

113

1

T41

2

T37

3

T15

3

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

91

1

T12

1

T37

1

T92

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

94

1

T37

1

T92

1

T14

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

87

1

T11

2

T12

1

T14

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

118

1

T12

1

T41

4

T13

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

89

1

T13

2

T25

1

T14

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

75

1

T29

3

T37

3

T92

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

114

1

T12

4

T41

2

T13

3

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3559	1			T3	10		T9	31		T33	41
auto[0]	values[0]	valids[0x1]	12471	1			T9	77		T44	10		T40	90
auto[0]	values[1]	valids[0x1]	546	1			T9	3		T33	15		T34	1
auto[0]	values[2]	valids[0x0]	458	1			T9	8		T33	12		T34	3
auto[0]	values[2]	valids[0x1]	273	1			T5	4		T9	9		T33	2
auto[0]	values[3]	valids[0x0]	493	1			T9	8		T40	2		T33	3
auto[0]	values[3]	valids[0x1]	259	1			T9	7		T33	2		T34	2
auto[0]	values[4]	valids[0x0]	434	1			T9	2		T33	8		T34	5
auto[0]	values[4]	valids[0x1]	261	1			T9	4		T33	5		T34	1
auto[0]	values[5]	valids[0x0]	524	1			T9	4		T33	5		T34	5
auto[0]	values[5]	valids[0x1]	302	1			T9	3		T33	3		T34	3
auto[0]	values[6]	valids[0x0]	517	1			T9	8		T40	2		T33	5
auto[0]	values[6]	valids[0x1]	271	1			T9	2		T33	3		T42	2
auto[0]	values[7]	valids[0x0]	450	1			T5	2		T9	13		T33	7
auto[0]	values[7]	valids[0x1]	288	1			T9	9		T33	3		T34	2
auto[0]	values[8]	valids[0x0]	3171	1			T9	50		T40	8		T33	50
auto[0]	values[8]	valids[0x1]	1916	1			T5	4		T7	2		T9	22
auto[1]	values[0]	valids[0x0]	3949	1			T11	4		T12	46		T41	29
auto[1]	values[0]	valids[0x1]	15299	1			T11	5		T12	64		T41	306
auto[1]	values[1]	valids[0x1]	573	1			T11	2		T12	5		T41	5
auto[1]	values[2]	valids[0x0]	367	1			T12	6		T41	1		T13	2
auto[1]	values[2]	valids[0x1]	259	1			T12	1		T41	6		T13	1
auto[1]	values[3]	valids[0x0]	347	1			T12	4		T41	2		T13	2
auto[1]	values[3]	valids[0x1]	315	1			T12	4		T41	4		T13	2
auto[1]	values[4]	valids[0x0]	396	1			T12	7		T41	6		T13	2
auto[1]	values[4]	valids[0x1]	265	1			T12	3		T41	1		T13	2
auto[1]	values[5]	valids[0x0]	421	1			T11	4		T12	10		T13	1
auto[1]	values[5]	valids[0x1]	221	1			T4	1		T12	2		T41	2
auto[1]	values[6]	valids[0x0]	391	1			T12	2		T41	4		T13	2
auto[1]	values[6]	valids[0x1]	254	1			T12	11		T41	3		T29	1
auto[1]	values[7]	valids[0x0]	333	1			T12	4		T13	2		T25	1
auto[1]	values[7]	valids[0x1]	265	1			T12	4		T41	1		T25	2
auto[1]	values[8]	valids[0x0]	2540	1			T1	3		T6	2		T8	1
auto[1]	values[8]	valids[0x1]	1779	1			T6	2		T8	1		T11	1