Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3060723

1

T1

18976

T3

315

T4

15005

auto[1]

22680

1

T9

614

T11

6

T12

60

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

801411

1

T1

18976

T3

315

T4

15005

auto[1]

2281992

1

T9

13340

T11

640

T12

7957

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	563645	1			T1	372		T3	118		T4	3295
auto[524288:1048575]	325827	1			T1	3360		T3	48		T8	4
auto[1048576:1572863]	367574	1			T1	7673		T6	8143		T9	4
auto[1572864:2097151]	387240	1			T3	49		T4	9593		T6	7719
auto[2097152:2621439]	428654	1			T1	3		T3	93		T4	1564
auto[2621440:3145727]	358914	1			T1	3146		T9	1872		T12	559
auto[3145728:3670015]	340994	1			T1	783		T3	6		T4	552
auto[3670016:4194303]	310555	1			T1	3639		T3	1		T4	1

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2314916

1

T1

22

T3

19

T4

16

auto[1]

768487

1

T1

18954

T3

296

T4

14989

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2645887

1

T1

18976

T3

314

T4

15005

auto[1]

437516

1

T3

1

T9

4041

T12

1632

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	165191	1			T1	372		T3	118		T4	3295
auto[0]	auto[0]	auto[0:524287]	auto[1]	334812	1			T9	1534		T11	512		T12	1028
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	84710	1			T1	3360		T3	47		T8	4
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	189595	1			T9	1470		T12	1200		T33	12
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	83434	1			T1	7673		T6	8143		T9	4
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	227169	1			T12	256		T33	4800		T41	522
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	110688	1			T3	49		T4	9593		T6	7719
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	222461	1			T9	2487		T12	2395		T33	3735
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	93691	1			T1	3		T3	93		T4	1564
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	252404	1			T9	1		T12	1283		T33	129
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	89107	1			T1	3146		T9	59		T12	26
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	222711	1			T9	1478		T33	4798		T41	198
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	91885	1			T1	783		T3	6		T4	552
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	199088	1			T9	522		T12	256		T33	2160
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	68299	1			T1	3639		T3	1		T4	1
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	191671	1			T9	1455		T11	128		T33	1153
auto[0]	auto[1]	auto[0:524287]	auto[0]	2786	1			T12	2		T41	2		T34	2
auto[0]	auto[1]	auto[0:524287]	auto[1]	57778	1			T34	2325		T29	1		T175	1
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	816	1			T3	1		T12	17		T33	4
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	48019	1			T12	257		T33	791		T25	2234
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	672	1			T12	3		T34	3		T29	3
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	53194	1			T34	2399		T29	771		T37	258
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	803	1			T12	26		T33	1		T25	6
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	50638	1			T12	512		T25	260		T29	2331
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	2714	1			T9	5		T33	5		T29	1
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	77096	1			T33	391		T92	256		T14	257
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	969	1			T9	42		T12	14		T33	2
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	43679	1			T9	256		T12	491		T33	256
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	627	1			T9	32		T12	19		T33	1
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	46553	1			T9	3669		T12	256		T33	256
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	1292	1			T12	7		T41	1		T174	5
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	46171	1			T37	263		T14	256		T176	370
auto[1]	auto[0]	auto[0:524287]	auto[0]	436	1			T9	10		T11	6		T12	7
auto[1]	auto[0]	auto[0:524287]	auto[1]	2199	1			T40	86		T33	42		T41	12
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	358	1			T12	10		T33	4		T41	1
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1921	1			T33	35		T41	31		T13	2
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	317	1			T12	3		T41	7		T34	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	2357	1			T41	91		T34	2		T25	19
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	449	1			T9	42		T41	2		T13	2
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	1795	1			T9	259		T41	63		T13	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	393	1			T9	22		T12	6		T33	1
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	1832	1			T33	2		T41	12		T25	6
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	298	1			T33	1		T14	2		T15	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1632	1			T33	7		T14	2		T15	8
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	389	1			T9	6		T12	4		T33	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	1884	1			T12	2		T33	7		T41	33
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	399	1			T9	29		T33	1		T41	1
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2312	1			T9	209		T41	7		T34	3
auto[1]	auto[1]	auto[0:524287]	auto[0]	85	1			T29	1		T174	6		T204	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	358	1			T29	1		T204	6		T176	25
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	80	1			T174	3		T37	2		T14	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	328	1			T15	12		T175	86		T47	3
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	60	1			T34	1		T37	2		T15	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	371	1			T34	4		T37	1		T15	8
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	92	1			T25	4		T14	2		T15	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	314	1			T25	56		T14	2		T15	27
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	88	1			T14	1		T42	6		T200	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	436	1			T14	1		T200	53		T47	10
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	105	1			T9	37		T12	7		T29	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	413	1			T12	21		T15	17		T250	16
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	93	1			T37	1		T48	1		T173	1
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	475	1			T48	14		T173	14		T199	2
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	85	1			T37	1		T92	3		T42	9
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	326	1			T42	5		T48	25		T172	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1864491	1			T1	22		T3	18		T4	16
auto[0]	auto[0]	auto[1]	762425	1			T1	18954		T3	296		T4	14989
auto[0]	auto[1]	auto[0]	428420	1			T3	1		T9	4004		T12	1604
auto[0]	auto[1]	auto[1]	5387	1			T25	1		T15	1		T251	62
auto[1]	auto[0]	auto[0]	18426	1			T9	568		T11	5		T12	27
auto[1]	auto[0]	auto[1]	545	1			T9	9		T11	1		T12	5
auto[1]	auto[1]	auto[0]	3579	1			T9	35		T12	27		T34	5
auto[1]	auto[1]	auto[1]	130	1			T9	2		T12	1		T25	1