Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2447561	1			T1	1		T2	1005		T3	1
all_pins[1]	2447561	1			T1	1		T2	1005		T3	1
all_pins[2]	2447561	1			T1	1		T2	1005		T3	1
all_pins[3]	2447561	1			T1	1		T2	1005		T3	1
all_pins[4]	2447561	1			T1	1		T2	1005		T3	1
all_pins[5]	2447561	1			T1	1		T2	1005		T3	1
all_pins[6]	2447561	1			T1	1		T2	1005		T3	1
all_pins[7]	2447561	1			T1	1		T2	1005		T3	1

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	19576881	1			T1	8		T2	8040		T3	8
values[0x1]	3607	1			T13	16		T14	34		T15	17
transitions[0x0=>0x1]	3108	1			T13	14		T14	28		T15	10
transitions[0x1=>0x0]	3124	1			T13	15		T14	28		T15	10

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2447360	1			T1	1		T2	1005		T3	1
all_pins[0]	values[0x1]	201	1			T13	1		T14	7		T15	2
all_pins[0]	transitions[0x0=>0x1]	146	1			T13	1		T14	5		T17	1
all_pins[0]	transitions[0x1=>0x0]	269	1			T13	2		T14	1		T17	116
all_pins[1]	values[0x0]	2447237	1			T1	1		T2	1005		T3	1
all_pins[1]	values[0x1]	324	1			T13	2		T14	3		T15	2
all_pins[1]	transitions[0x0=>0x1]	196	1			T13	2		T14	3		T15	2
all_pins[1]	transitions[0x1=>0x0]	192	1			T13	2		T14	4		T15	2
all_pins[2]	values[0x0]	2447241	1			T1	1		T2	1005		T3	1
all_pins[2]	values[0x1]	320	1			T13	2		T14	4		T15	2
all_pins[2]	transitions[0x0=>0x1]	262	1			T13	2		T14	4		T15	1
all_pins[2]	transitions[0x1=>0x0]	153	1			T13	1		T14	1		T15	1
all_pins[3]	values[0x0]	2447350	1			T1	1		T2	1005		T3	1
all_pins[3]	values[0x1]	211	1			T13	1		T14	1		T15	2
all_pins[3]	transitions[0x0=>0x1]	160	1			T13	1		T14	1		T18	3
all_pins[3]	transitions[0x1=>0x0]	153	1			T13	1		T14	5		T15	3
all_pins[4]	values[0x0]	2447357	1			T1	1		T2	1005		T3	1
all_pins[4]	values[0x1]	204	1			T13	1		T14	5		T15	5
all_pins[4]	transitions[0x0=>0x1]	168	1			T14	3		T15	4		T17	2
all_pins[4]	transitions[0x1=>0x0]	133	1			T13	4		T14	2		T17	1
all_pins[5]	values[0x0]	2447392	1			T1	1		T2	1005		T3	1
all_pins[5]	values[0x1]	169	1			T13	5		T14	4		T15	1
all_pins[5]	transitions[0x0=>0x1]	126	1			T13	5		T14	4		T15	1
all_pins[5]	transitions[0x1=>0x0]	1913	1			T13	3		T14	2		T15	2
all_pins[6]	values[0x0]	2445605	1			T1	1		T2	1005		T3	1
all_pins[6]	values[0x1]	1956	1			T13	3		T14	2		T15	2
all_pins[6]	transitions[0x0=>0x1]	1894	1			T13	3		T14	2		T15	1
all_pins[6]	transitions[0x1=>0x0]	160	1			T13	1		T14	8		T17	1
all_pins[7]	values[0x0]	2447339	1			T1	1		T2	1005		T3	1
all_pins[7]	values[0x1]	222	1			T13	1		T14	8		T15	1
all_pins[7]	transitions[0x0=>0x1]	156	1			T14	6		T15	1		T19	2
all_pins[7]	transitions[0x1=>0x0]	151	1			T13	1		T14	5		T15	2