Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

15195

1

T3

10

T7

2

T9

155

auto[1]

10998

1

T5

10

T9

105

T33

210

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3380	1			T7	2		T9	40		T33	81
values[1]	3631	1			T9	20		T33	151		T39	15
values[2]	2710	1			T9	40		T33	44		T34	20
values[3]	3302	1			T9	60		T33	28		T34	23
values[4]	2991	1			T5	10		T9	20		T44	10
values[5]	3121	1			T3	10		T9	20		T33	20
values[6]	3841	1			T9	60		T40	104		T33	40
values[7]	3217	1			T34	49		T23	20		T45	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3016	1			T9	20		T34	20		T14	21
values[1]	2867	1			T9	40		T33	84		T39	15
values[2]	3641	1			T5	10		T9	20		T33	86
values[3]	3124	1			T9	40		T44	10		T33	21
values[4]	3219	1			T7	2		T40	104		T33	20
values[5]	3218	1			T9	80		T33	45		T34	20
values[6]	3626	1			T3	10		T9	60		T33	88
values[7]	3482	1			T33	40		T34	23		T14	20

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	296	1			T14	16		T252	2		T199	12
auto[0]	values[0]	values[1]	325	1			T33	12		T42	13		T199	17
auto[0]	values[0]	values[2]	319	1			T253	6		T172	10		T199	40
auto[0]	values[0]	values[3]	134	1			T33	15		T83	9		T254	6
auto[0]	values[0]	values[4]	208	1			T7	2		T33	12		T34	9
auto[0]	values[0]	values[5]	201	1			T83	5		T247	9		T245	12
auto[0]	values[0]	values[6]	237	1			T9	27		T33	9		T255	16
auto[0]	values[0]	values[7]	290	1			T15	34		T191	14		T256	15
auto[0]	values[1]	values[0]	333	1			T216	15		T246	8		T219	21
auto[0]	values[1]	values[1]	209	1			T39	15		T112	24		T46	10
auto[0]	values[1]	values[2]	327	1			T33	12		T46	10		T43	9
auto[0]	values[1]	values[3]	233	1			T9	11		T111	8		T197	10
auto[0]	values[1]	values[4]	243	1			T228	20		T208	10		T54	18
auto[0]	values[1]	values[5]	192	1			T33	23		T42	15		T47	8
auto[0]	values[1]	values[6]	270	1			T43	23		T18	21		T199	19
auto[0]	values[1]	values[7]	266	1			T33	13		T43	9		T48	13
auto[0]	values[2]	values[0]	215	1			T83	7		T131	13		T193	14
auto[0]	values[2]	values[1]	238	1			T33	13		T83	18		T194	8
auto[0]	values[2]	values[2]	107	1			T34	9		T83	10		T191	13
auto[0]	values[2]	values[3]	111	1			T96	2		T42	15		T195	13
auto[0]	values[2]	values[4]	182	1			T47	22		T173	12		T231	20
auto[0]	values[2]	values[5]	230	1			T9	20		T46	10		T248	12
auto[0]	values[2]	values[6]	210	1			T251	4		T43	12		T172	16
auto[0]	values[2]	values[7]	259	1			T42	10		T199	15		T191	12
auto[0]	values[3]	values[0]	205	1			T9	12		T172	12		T186	12
auto[0]	values[3]	values[1]	201	1			T9	17		T199	18		T229	16
auto[0]	values[3]	values[2]	199	1			T14	11		T186	11		T220	11
auto[0]	values[3]	values[3]	289	1			T257	28		T197	62		T258	20
auto[0]	values[3]	values[4]	163	1			T26	12		T43	12		T48	8
auto[0]	values[3]	values[5]	242	1			T9	12		T259	4		T83	14
auto[0]	values[3]	values[6]	326	1			T33	9		T224	14		T197	37
auto[0]	values[3]	values[7]	265	1			T34	12		T14	8		T48	57
auto[0]	values[4]	values[0]	179	1			T42	11		T197	29		T245	38
auto[0]	values[4]	values[1]	100	1			T186	9		T231	15		T156	14
auto[0]	values[4]	values[2]	202	1			T172	14		T219	18		T193	16
auto[0]	values[4]	values[3]	220	1			T44	10		T197	10		T231	20
auto[0]	values[4]	values[4]	236	1			T43	11		T199	21		T247	11
auto[0]	values[4]	values[5]	209	1			T9	10		T42	11		T46	13
auto[0]	values[4]	values[6]	341	1			T33	16		T173	92		T260	8
auto[0]	values[4]	values[7]	230	1			T48	20		T261	8		T203	10
auto[0]	values[5]	values[0]	163	1			T172	11		T173	27		T216	13
auto[0]	values[5]	values[1]	127	1			T15	15		T219	14		T247	13
auto[0]	values[5]	values[2]	252	1			T9	11		T42	11		T199	9
auto[0]	values[5]	values[3]	229	1			T43	12		T48	10		T131	17
auto[0]	values[5]	values[4]	348	1			T47	20		T186	16		T195	137
auto[0]	values[5]	values[5]	167	1			T262	2		T199	9		T191	13
auto[0]	values[5]	values[6]	264	1			T3	10		T33	11		T42	12
auto[0]	values[5]	values[7]	196	1			T15	16		T46	7		T43	15
auto[0]	values[6]	values[0]	147	1			T48	9		T199	12		T81	6
auto[0]	values[6]	values[1]	312	1			T9	13		T33	15		T201	16
auto[0]	values[6]	values[2]	454	1			T34	13		T43	28		T216	8
auto[0]	values[6]	values[3]	340	1			T9	13		T227	24		T42	17
auto[0]	values[6]	values[4]	212	1			T40	104		T167	8		T186	14
auto[0]	values[6]	values[5]	218	1			T34	14		T263	2		T43	5
auto[0]	values[6]	values[6]	240	1			T9	9		T83	27		T245	16
auto[0]	values[6]	values[7]	382	1			T33	14		T244	16		T43	12
auto[0]	values[7]	values[0]	348	1			T34	17		T42	14		T47	26
auto[0]	values[7]	values[1]	155	1			T23	20		T196	16		T186	9
auto[0]	values[7]	values[2]	133	1			T14	10		T83	10		T205	11
auto[0]	values[7]	values[3]	306	1			T42	10		T235	59		T199	13
auto[0]	values[7]	values[4]	235	1			T45	20		T90	8		T156	9
auto[0]	values[7]	values[5]	290	1			T173	22		T191	12		T245	96
auto[0]	values[7]	values[6]	161	1			T34	20		T215	8		T48	13
auto[0]	values[7]	values[7]	274	1			T264	38		T170	12		T265	4
auto[1]	values[0]	values[0]	124	1			T14	5		T199	11		T131	9
auto[1]	values[0]	values[1]	110	1			T33	8		T42	7		T199	12
auto[1]	values[0]	values[2]	260	1			T172	10		T199	18		T83	9
auto[1]	values[0]	values[3]	126	1			T33	6		T83	33		T203	10
auto[1]	values[0]	values[4]	153	1			T33	8		T34	11		T42	13
auto[1]	values[0]	values[5]	270	1			T83	21		T247	11		T245	74
auto[1]	values[0]	values[6]	149	1			T9	13		T33	11		T197	8
auto[1]	values[0]	values[7]	178	1			T15	11		T191	6		T256	5
auto[1]	values[1]	values[0]	186	1			T216	9		T219	5		T186	11
auto[1]	values[1]	values[1]	162	1			T46	10		T220	10		T230	9
auto[1]	values[1]	values[2]	325	1			T33	74		T46	49		T43	11
auto[1]	values[1]	values[3]	201	1			T9	9		T197	27		T130	18
auto[1]	values[1]	values[4]	122	1			T54	8		T155	6		T238	13
auto[1]	values[1]	values[5]	125	1			T33	22		T42	5		T47	12
auto[1]	values[1]	values[6]	240	1			T43	17		T18	6		T199	7
auto[1]	values[1]	values[7]	197	1			T33	7		T43	11		T48	12
auto[1]	values[2]	values[0]	193	1			T83	13		T131	7		T193	6
auto[1]	values[2]	values[1]	187	1			T33	31		T83	2		T131	11
auto[1]	values[2]	values[2]	124	1			T34	11		T83	36		T191	7
auto[1]	values[2]	values[3]	67	1			T42	5		T195	7		T156	20
auto[1]	values[2]	values[4]	77	1			T47	4		T173	8		T231	7
auto[1]	values[2]	values[5]	265	1			T9	20		T46	16		T205	7
auto[1]	values[2]	values[6]	136	1			T43	8		T172	8		T193	10
auto[1]	values[2]	values[7]	109	1			T42	10		T199	7		T191	8
auto[1]	values[3]	values[0]	129	1			T9	8		T172	8		T186	8
auto[1]	values[3]	values[1]	81	1			T9	3		T199	2		T156	7
auto[1]	values[3]	values[2]	205	1			T14	10		T186	9		T220	9
auto[1]	values[3]	values[3]	202	1			T197	9		T131	33		T256	11
auto[1]	values[3]	values[4]	296	1			T43	8		T48	191		T266	8
auto[1]	values[3]	values[5]	165	1			T9	8		T83	9		T156	13
auto[1]	values[3]	values[6]	147	1			T33	19		T224	6		T197	9
auto[1]	values[3]	values[7]	187	1			T34	11		T14	12		T48	5
auto[1]	values[4]	values[0]	118	1			T42	9		T197	6		T245	4
auto[1]	values[4]	values[1]	88	1			T225	16		T186	11		T231	11
auto[1]	values[4]	values[2]	188	1			T5	10		T172	6		T219	7
auto[1]	values[4]	values[3]	115	1			T197	11		T267	6		T231	5
auto[1]	values[4]	values[4]	123	1			T43	9		T199	8		T247	9
auto[1]	values[4]	values[5]	253	1			T9	10		T42	9		T46	7
auto[1]	values[4]	values[6]	239	1			T33	4		T173	11		T83	10
auto[1]	values[4]	values[7]	150	1			T48	8		T203	10		T134	4
auto[1]	values[5]	values[0]	132	1			T172	9		T173	13		T216	8
auto[1]	values[5]	values[1]	173	1			T15	12		T219	6		T247	7
auto[1]	values[5]	values[2]	158	1			T9	9		T42	9		T199	11
auto[1]	values[5]	values[3]	128	1			T43	8		T48	10		T131	9
auto[1]	values[5]	values[4]	324	1			T232	20		T47	91		T268	8
auto[1]	values[5]	values[5]	161	1			T199	11		T191	7		T256	6
auto[1]	values[5]	values[6]	193	1			T33	9		T42	8		T47	13
auto[1]	values[5]	values[7]	106	1			T15	10		T46	13		T43	5
auto[1]	values[6]	values[0]	98	1			T48	12		T199	8		T269	11
auto[1]	values[6]	values[1]	279	1			T9	7		T33	5		T199	10
auto[1]	values[6]	values[2]	197	1			T34	7		T43	12		T216	23
auto[1]	values[6]	values[3]	123	1			T9	7		T42	3		T48	8
auto[1]	values[6]	values[4]	122	1			T186	6		T270	12		T237	14
auto[1]	values[6]	values[5]	127	1			T34	6		T43	15		T205	11
auto[1]	values[6]	values[6]	296	1			T9	11		T271	4		T83	9
auto[1]	values[6]	values[7]	294	1			T33	6		T43	8		T48	13
auto[1]	values[7]	values[0]	150	1			T34	3		T42	6		T47	5
auto[1]	values[7]	values[1]	120	1			T186	11		T193	11		T155	8
auto[1]	values[7]	values[2]	191	1			T14	20		T83	10		T205	23
auto[1]	values[7]	values[3]	300	1			T42	10		T199	7		T272	26
auto[1]	values[7]	values[4]	175	1			T156	11		T273	3		T274	24
auto[1]	values[7]	values[5]	103	1			T173	13		T191	8		T245	1
auto[1]	values[7]	values[6]	177	1			T34	9		T48	7		T83	29
auto[1]	values[7]	values[7]	99	1			T219	15		T205	8		T230	10