Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	370	1			T9	4		T33	4		T34	3
auto[ReadAddrCrossIntoMailbox]	245	1			T9	5		T33	5		T34	2
auto[ReadAddrCrossOutOfMailbox]	283	1			T9	5		T14	4		T42	2
auto[ReadAddrCrossAllMailbox]	197	1			T9	3		T33	2		T34	2
auto[ReadAddrOutsideMailbox]	3151	1			T5	2		T7	2		T9	41

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2090

1

T5

1

T7

1

T9

27

auto[1]

2156

1

T5

1

T7

1

T9

31

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	760	1			T5	2		T7	2		T9	12
read_ops[0x0b]	735	1			T9	8		T33	11		T34	9
read_ops[0x3b]	726	1			T9	12		T33	14		T34	7
read_ops[0x6b]	701	1			T9	6		T33	7		T34	8
read_ops[0xbb]	620	1			T9	11		T33	12		T34	2
read_ops[0xeb]	704	1			T9	9		T33	3		T39	2

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T90	1		T244	2		T172	2
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T33	1		T34	1		T42	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	20	1			T9	1		T33	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T33	1		T15	1		T43	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	18	1			T9	1		T43	1		T219	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T14	1		T42	1		T15	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T9	2		T199	1		T219	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T9	1		T34	1		T48	2
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	277	1			T5	1		T7	1		T9	6
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	296	1			T5	1		T7	1		T9	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	42	1			T9	1		T34	1		T14	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T9	1		T43	1		T173	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	14	1			T15	1		T199	1		T231	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	21	1			T34	1		T197	1		T193	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	19	1			T47	2		T199	1		T197	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T15	1		T43	1		T48	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	16	1			T33	1		T43	1		T191	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	21	1			T43	1		T216	1		T197	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	263	1			T9	1		T33	7		T34	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	282	1			T9	5		T33	3		T34	5
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	35	1			T244	1		T48	1		T173	1
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	40	1			T9	1		T33	2		T34	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T48	1		T172	1		T191	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	33	1			T9	1		T33	1		T34	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	30	1			T9	1		T173	2		T83	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	23	1			T9	1		T43	1		T47	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T15	1		T46	1		T191	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	19	1			T42	2		T43	1		T83	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	270	1			T9	3		T33	6		T34	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	238	1			T9	5		T33	5		T34	4
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	27	1			T240	2		T173	1		T131	1
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T9	1		T15	1		T43	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	23	1			T46	1		T173	1		T197	2
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	17	1			T9	1		T43	2		T205	2
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	21	1			T14	1		T46	1		T43	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T9	2		T48	1		T246	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	14	1			T216	2		T83	1		T219	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	16	1			T33	1		T34	1		T199	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	267	1			T33	5		T34	4		T26	2
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	261	1			T9	2		T33	1		T34	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	26	1			T33	1		T42	1		T244	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	14	1			T244	2		T240	1		T197	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	17	1			T33	2		T222	1		T203	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T9	1		T46	1		T131	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T172	1		T240	2		T219	3
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	27	1			T46	1		T240	2		T199	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T216	1		T197	1		T205	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	11	1			T15	1		T197	1		T131	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	216	1			T9	7		T33	3		T34	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	244	1			T9	3		T33	6		T34	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	24	1			T42	1		T46	1		T240	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	26	1			T42	1		T15	1		T43	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	18	1			T172	1		T240	1		T199	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	24	1			T9	1		T240	1		T199	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	17	1			T43	1		T216	1		T197	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	26	1			T14	2		T42	1		T173	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	15	1			T47	1		T240	1		T246	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	17	1			T42	1		T43	1		T240	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	268	1			T9	4		T33	1		T39	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	269	1			T9	4		T33	2		T39	1