Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	825	1			T13	10		T14	17		T15	7
all_values[1]	825	1			T13	10		T14	17		T15	7
all_values[2]	825	1			T13	10		T14	17		T15	7
all_values[3]	825	1			T13	10		T14	17		T15	7
all_values[4]	825	1			T13	10		T14	17		T15	7
all_values[5]	825	1			T13	10		T14	17		T15	7
all_values[6]	825	1			T13	10		T14	17		T15	7
all_values[7]	825	1			T13	10		T14	17		T15	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3390

1

T13

41

T14

68

T15

28

auto[1]

3210

1

T13

39

T14

68

T15

28

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2657

1

T13

38

T14

57

T15

17

auto[1]

3943

1

T13

42

T14

79

T15

39

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3782

1

T13

45

T14

82

T15

31

auto[1]

2818

1

T13

35

T14

54

T15

25

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	153	1			T13	3		T14	2		T15	2
all_values[0]	auto[0]	auto[0]	auto[1]	87	1			T14	2		T19	1		T20	3
all_values[0]	auto[0]	auto[1]	auto[0]	132	1			T13	3		T14	4		T15	2
all_values[0]	auto[0]	auto[1]	auto[1]	85	1			T13	1		T14	2		T15	1
all_values[0]	auto[1]	auto[0]	auto[1]	187	1			T13	2		T14	1		T15	1
all_values[0]	auto[1]	auto[1]	auto[1]	181	1			T13	1		T14	6		T15	1
all_values[1]	auto[0]	auto[0]	auto[0]	168	1			T13	3		T14	4		T15	2
all_values[1]	auto[0]	auto[0]	auto[1]	74	1			T19	4		T20	1		T21	3
all_values[1]	auto[0]	auto[1]	auto[0]	156	1			T13	1		T14	4		T17	1
all_values[1]	auto[0]	auto[1]	auto[1]	79	1			T14	1		T15	2		T17	1
all_values[1]	auto[1]	auto[0]	auto[1]	170	1			T13	5		T14	3		T15	3
all_values[1]	auto[1]	auto[1]	auto[1]	178	1			T13	1		T14	5		T17	2
all_values[2]	auto[0]	auto[0]	auto[0]	165	1			T13	2		T14	4		T18	1
all_values[2]	auto[0]	auto[0]	auto[1]	75	1			T15	1		T18	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[0]	127	1			T13	1		T14	3		T17	2
all_values[2]	auto[0]	auto[1]	auto[1]	94	1			T13	3		T14	4		T15	2
all_values[2]	auto[1]	auto[0]	auto[1]	188	1			T13	2		T14	2		T15	2
all_values[2]	auto[1]	auto[1]	auto[1]	176	1			T13	2		T14	4		T15	2
all_values[3]	auto[0]	auto[0]	auto[0]	165	1			T13	5		T14	8		T15	2
all_values[3]	auto[0]	auto[0]	auto[1]	78	1			T13	1		T14	2		T15	1
all_values[3]	auto[0]	auto[1]	auto[0]	129	1			T13	2		T14	1		T17	1
all_values[3]	auto[0]	auto[1]	auto[1]	77	1			T18	1		T19	1		T20	1
all_values[3]	auto[1]	auto[0]	auto[1]	204	1			T14	5		T15	2		T17	1
all_values[3]	auto[1]	auto[1]	auto[1]	172	1			T13	2		T14	1		T15	2
all_values[4]	auto[0]	auto[0]	auto[0]	176	1			T13	2		T18	1		T19	4
all_values[4]	auto[0]	auto[0]	auto[1]	58	1			T14	5		T15	1		T21	2
all_values[4]	auto[0]	auto[1]	auto[0]	159	1			T13	3		T14	1		T17	1
all_values[4]	auto[0]	auto[1]	auto[1]	95	1			T14	3		T15	2		T17	1
all_values[4]	auto[1]	auto[0]	auto[1]	167	1			T13	3		T14	4		T15	2
all_values[4]	auto[1]	auto[1]	auto[1]	170	1			T13	2		T14	4		T15	2
all_values[5]	auto[0]	auto[0]	auto[0]	269	1			T13	2		T14	6		T15	2
all_values[5]	auto[0]	auto[1]	auto[0]	211	1			T13	1		T14	6		T15	2
all_values[5]	auto[1]	auto[0]	auto[1]	176	1			T14	1		T15	1		T18	3
all_values[5]	auto[1]	auto[1]	auto[1]	169	1			T13	7		T14	4		T15	2
all_values[6]	auto[0]	auto[0]	auto[0]	173	1			T13	1		T14	4		T18	2
all_values[6]	auto[0]	auto[0]	auto[1]	59	1			T14	1		T15	1		T17	1
all_values[6]	auto[0]	auto[1]	auto[0]	155	1			T13	1		T14	4		T15	1
all_values[6]	auto[0]	auto[1]	auto[1]	100	1			T13	1		T15	2		T19	2
all_values[6]	auto[1]	auto[0]	auto[1]	170	1			T13	5		T14	5		T15	2
all_values[6]	auto[1]	auto[1]	auto[1]	168	1			T13	2		T14	3		T15	1
all_values[7]	auto[0]	auto[0]	auto[0]	197	1			T13	5		T14	6		T15	2
all_values[7]	auto[0]	auto[0]	auto[1]	67	1			T14	1		T19	2		T20	3
all_values[7]	auto[0]	auto[1]	auto[0]	122	1			T13	3		T15	2		T17	2
all_values[7]	auto[0]	auto[1]	auto[1]	97	1			T13	1		T14	4		T15	1
all_values[7]	auto[1]	auto[0]	auto[1]	164	1			T14	2		T15	1		T19	8
all_values[7]	auto[1]	auto[1]	auto[1]	178	1			T13	1		T14	4		T15	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal