Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1782

1

T2

10

T10

18

T31

7

auto[1]

1830

1

T2

6

T10

11

T31

7

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1819

1

T2

12

T31

14

T33

6

auto[1]

1793

1

T2

4

T10

29

T33

1

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2871

1

T2

10

T10

29

T31

6

auto[1]

741

1

T2

6

T31

8

T33

3

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	716	1			T2	3		T10	6		T31	1
valid[1]	714	1			T2	3		T10	6		T31	1
valid[2]	765	1			T2	1		T10	8		T31	4
valid[3]	739	1			T2	3		T10	3		T31	3
valid[4]	678	1			T2	6		T10	6		T31	5

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	114	1			T2	1		T31	1		T13	3
auto[0]	auto[0]	valid[0]	auto[1]	165	1			T10	3		T14	1		T330	6
auto[0]	auto[0]	valid[1]	auto[0]	108	1			T2	1		T33	1		T34	1
auto[0]	auto[0]	valid[1]	auto[1]	195	1			T10	5		T25	1		T88	1
auto[0]	auto[0]	valid[2]	auto[0]	109	1			T2	1		T31	1		T13	1
auto[0]	auto[0]	valid[2]	auto[1]	181	1			T10	4		T88	1		T14	2
auto[0]	auto[0]	valid[3]	auto[0]	92	1			T13	1		T24	2		T29	1
auto[0]	auto[0]	valid[3]	auto[1]	194	1			T10	2		T33	1		T29	1
auto[0]	auto[0]	valid[4]	auto[0]	88	1			T2	1		T31	1		T13	2
auto[0]	auto[0]	valid[4]	auto[1]	181	1			T2	3		T10	4		T34	2
auto[0]	auto[1]	valid[0]	auto[0]	111	1			T33	1		T34	1		T13	1
auto[0]	auto[1]	valid[0]	auto[1]	177	1			T10	3		T34	2		T89	2
auto[0]	auto[1]	valid[1]	auto[0]	113	1			T2	1		T31	1		T34	1
auto[0]	auto[1]	valid[1]	auto[1]	156	1			T10	1		T34	1		T88	2
auto[0]	auto[1]	valid[2]	auto[0]	134	1			T13	2		T24	3		T25	2
auto[0]	auto[1]	valid[2]	auto[1]	191	1			T10	4		T88	1		T89	3
auto[0]	auto[1]	valid[3]	auto[0]	112	1			T31	2		T13	2		T24	1
auto[0]	auto[1]	valid[3]	auto[1]	192	1			T2	1		T10	1		T88	1
auto[0]	auto[1]	valid[4]	auto[0]	97	1			T2	1		T33	1		T24	1
auto[0]	auto[1]	valid[4]	auto[1]	161	1			T10	2		T37	1		T88	3
auto[1]	auto[0]	valid[0]	auto[0]	71	1			T2	1		T34	1		T15	1
auto[1]	auto[0]	valid[1]	auto[0]	62	1			T2	1		T24	1		T29	1
auto[1]	auto[0]	valid[2]	auto[0]	77	1			T31	2		T33	1		T24	1
auto[1]	auto[0]	valid[3]	auto[0]	71	1			T2	1		T33	1		T34	2
auto[1]	auto[0]	valid[4]	auto[0]	74	1			T31	2		T13	2		T25	2
auto[1]	auto[1]	valid[0]	auto[0]	78	1			T2	1		T33	1		T25	1
auto[1]	auto[1]	valid[1]	auto[0]	80	1			T34	1		T14	1		T200	1
auto[1]	auto[1]	valid[2]	auto[0]	73	1			T31	1		T34	1		T13	1
auto[1]	auto[1]	valid[3]	auto[0]	78	1			T2	1		T31	1		T34	2
auto[1]	auto[1]	valid[4]	auto[0]	77	1			T2	1		T31	2		T34	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal