Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	21	0	21	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_transfer_size	7	0	7	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_transfer_size_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	21	0	21	100.00	100	1	1	0

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

45141

1

T2

387

T30

10

T31

228

auto[1]

18284

1

T2

30

T10

256

T33

34

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

46796

1

T2

273

T10

256

T30

5

auto[1]

16629

1

T2

144

T30

5

T31

91

---

Summary for Variable cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	7	0	7	100.00

User Defined Bins for cp_transfer_size

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
others[0]	32477	1			T2	211		T10	140		T30	4
others[1]	5365	1			T2	25		T10	18		T30	1
others[2]	5376	1			T2	32		T10	21		T30	2
others[3]	6056	1			T2	35		T10	22		T31	18
interest[1]	3588	1			T2	38		T10	19		T30	2
interest[4]	21326	1			T2	127		T10	93		T30	3
interest[64]	10563	1			T2	76		T10	36		T30	1

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_is_hw_return cp_transfer_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	21	0	21	100.00
Automatically Generated Cross Bins	21	0	21	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_is_hw_return	cp_transfer_size	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	others[0]	14648	1			T2	121		T30	1		T31	72
auto[0]	auto[0]	others[1]	2390	1			T2	15		T30	1		T31	19
auto[0]	auto[0]	others[2]	2373	1			T2	22		T30	1		T31	10
auto[0]	auto[0]	others[3]	2733	1			T2	20		T31	9		T33	5
auto[0]	auto[0]	interest[1]	1585	1			T2	21		T30	2		T31	7
auto[0]	auto[0]	interest[4]	9512	1			T2	72		T30	1		T31	48
auto[0]	auto[0]	interest[64]	4783	1			T2	44		T31	20		T33	11
auto[0]	auto[1]	others[0]	9402	1			T2	15		T10	140		T33	19
auto[0]	auto[1]	others[1]	1577	1			T2	1		T10	18		T33	2
auto[0]	auto[1]	others[2]	1603	1			T2	4		T10	21		T33	4
auto[0]	auto[1]	others[3]	1722	1			T2	1		T10	22		T33	2
auto[0]	auto[1]	interest[1]	1025	1			T2	5		T10	19		T33	2
auto[0]	auto[1]	interest[4]	6328	1			T2	7		T10	93		T33	11
auto[0]	auto[1]	interest[64]	2955	1			T2	4		T10	36		T33	5
auto[1]	auto[0]	others[0]	8427	1			T2	75		T30	3		T31	47
auto[1]	auto[0]	others[1]	1398	1			T2	9		T31	12		T33	3
auto[1]	auto[0]	others[2]	1400	1			T2	6		T30	1		T31	5
auto[1]	auto[0]	others[3]	1601	1			T2	14		T31	9		T33	4
auto[1]	auto[0]	interest[1]	978	1			T2	12		T31	5		T33	3
auto[1]	auto[0]	interest[4]	5486	1			T2	48		T30	2		T31	30
auto[1]	auto[0]	interest[64]	2825	1			T2	28		T30	1		T31	13

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal