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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.04 98.38 93.99 98.62 89.36 97.19 95.45 99.26


Total test records in report: 1131
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T1022 /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.150465658 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:40 PM PDT 24 218379525 ps
T1023 /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.187667119 Jul 07 05:26:49 PM PDT 24 Jul 07 05:26:51 PM PDT 24 39325992 ps
T105 /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1833920228 Jul 07 05:26:53 PM PDT 24 Jul 07 05:26:55 PM PDT 24 127523763 ps
T121 /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3985904436 Jul 07 05:26:33 PM PDT 24 Jul 07 05:27:07 PM PDT 24 1065328507 ps
T106 /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4207264954 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:40 PM PDT 24 34158611 ps
T101 /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.276337603 Jul 07 05:26:28 PM PDT 24 Jul 07 05:26:32 PM PDT 24 98915914 ps
T1024 /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3189801422 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:55 PM PDT 24 13760005 ps
T1025 /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2710296772 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:39 PM PDT 24 10914544 ps
T1026 /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1485424152 Jul 07 05:26:32 PM PDT 24 Jul 07 05:26:37 PM PDT 24 1771930515 ps
T151 /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1023464180 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:42 PM PDT 24 146376606 ps
T152 /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3728224163 Jul 07 05:26:38 PM PDT 24 Jul 07 05:26:44 PM PDT 24 493400637 ps
T122 /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2832356406 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:38 PM PDT 24 102846929 ps
T1027 /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2824751328 Jul 07 05:26:20 PM PDT 24 Jul 07 05:26:44 PM PDT 24 1466149514 ps
T153 /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2441363974 Jul 07 05:26:32 PM PDT 24 Jul 07 05:26:36 PM PDT 24 108626223 ps
T1028 /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1786608090 Jul 07 05:26:46 PM PDT 24 Jul 07 05:26:47 PM PDT 24 13318376 ps
T1029 /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3582394751 Jul 07 05:26:45 PM PDT 24 Jul 07 05:26:46 PM PDT 24 28369479 ps
T1030 /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1148897104 Jul 07 05:26:33 PM PDT 24 Jul 07 05:26:39 PM PDT 24 2409761456 ps
T1031 /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2513578128 Jul 07 05:26:46 PM PDT 24 Jul 07 05:26:47 PM PDT 24 56764634 ps
T180 /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.846652625 Jul 07 05:26:37 PM PDT 24 Jul 07 05:27:02 PM PDT 24 791080821 ps
T1032 /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3059982594 Jul 07 05:26:41 PM PDT 24 Jul 07 05:26:49 PM PDT 24 216371937 ps
T123 /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1382365554 Jul 07 05:26:35 PM PDT 24 Jul 07 05:26:40 PM PDT 24 60577298 ps
T1033 /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1398450210 Jul 07 05:26:47 PM PDT 24 Jul 07 05:26:49 PM PDT 24 23819774 ps
T1034 /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1367810567 Jul 07 05:26:39 PM PDT 24 Jul 07 05:26:41 PM PDT 24 29367577 ps
T1035 /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3461918063 Jul 07 05:26:40 PM PDT 24 Jul 07 05:26:42 PM PDT 24 101375357 ps
T154 /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1510441203 Jul 07 05:26:33 PM PDT 24 Jul 07 05:26:35 PM PDT 24 127151625 ps
T1036 /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1163880329 Jul 07 05:26:43 PM PDT 24 Jul 07 05:26:45 PM PDT 24 25497093 ps
T1037 /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3260960430 Jul 07 05:26:35 PM PDT 24 Jul 07 05:26:38 PM PDT 24 29480443 ps
T1038 /workspace/coverage/cover_reg_top/6.spi_device_intr_test.861253535 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:39 PM PDT 24 16372043 ps
T102 /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.382930124 Jul 07 05:26:32 PM PDT 24 Jul 07 05:26:37 PM PDT 24 398331622 ps
T183 /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.139648312 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:44 PM PDT 24 1512184845 ps
T1039 /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3162452540 Jul 07 05:26:38 PM PDT 24 Jul 07 05:26:40 PM PDT 24 26020152 ps
T181 /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1205195558 Jul 07 05:26:37 PM PDT 24 Jul 07 05:26:58 PM PDT 24 710528391 ps
T1040 /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2732957986 Jul 07 05:26:47 PM PDT 24 Jul 07 05:26:48 PM PDT 24 23218193 ps
T1041 /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2194591839 Jul 07 05:26:33 PM PDT 24 Jul 07 05:26:36 PM PDT 24 39826013 ps
T1042 /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2816602491 Jul 07 05:26:32 PM PDT 24 Jul 07 05:26:34 PM PDT 24 16650010 ps
T178 /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.279160321 Jul 07 05:26:30 PM PDT 24 Jul 07 05:26:52 PM PDT 24 3442186011 ps
T185 /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2029690345 Jul 07 05:26:38 PM PDT 24 Jul 07 05:26:55 PM PDT 24 2902146564 ps
T1043 /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2819550052 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:39 PM PDT 24 170107994 ps
T1044 /workspace/coverage/cover_reg_top/33.spi_device_intr_test.7502072 Jul 07 05:26:45 PM PDT 24 Jul 07 05:26:46 PM PDT 24 63079167 ps
T1045 /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3316587551 Jul 07 05:26:28 PM PDT 24 Jul 07 05:26:29 PM PDT 24 21525343 ps
T1046 /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4066793781 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:43 PM PDT 24 1047656607 ps
T86 /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.89523518 Jul 07 05:26:31 PM PDT 24 Jul 07 05:26:33 PM PDT 24 129699710 ps
T1047 /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2593283224 Jul 07 05:26:29 PM PDT 24 Jul 07 05:26:30 PM PDT 24 52309682 ps
T1048 /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3720616858 Jul 07 05:26:28 PM PDT 24 Jul 07 05:26:29 PM PDT 24 20920263 ps
T1049 /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3692162714 Jul 07 05:26:24 PM PDT 24 Jul 07 05:26:29 PM PDT 24 1018779150 ps
T1050 /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.873715301 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:42 PM PDT 24 555332778 ps
T1051 /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3516926062 Jul 07 05:26:40 PM PDT 24 Jul 07 05:26:44 PM PDT 24 351590809 ps
T1052 /workspace/coverage/cover_reg_top/5.spi_device_intr_test.670654947 Jul 07 05:26:32 PM PDT 24 Jul 07 05:26:34 PM PDT 24 62823604 ps
T1053 /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2293325943 Jul 07 05:26:40 PM PDT 24 Jul 07 05:26:44 PM PDT 24 1176773581 ps
T1054 /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4215762587 Jul 07 05:26:35 PM PDT 24 Jul 07 05:26:40 PM PDT 24 87073566 ps
T1055 /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4189876836 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:41 PM PDT 24 33662982 ps
T1056 /workspace/coverage/cover_reg_top/38.spi_device_intr_test.750337309 Jul 07 05:26:56 PM PDT 24 Jul 07 05:26:58 PM PDT 24 16905577 ps
T1057 /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3269993491 Jul 07 05:26:37 PM PDT 24 Jul 07 05:26:39 PM PDT 24 41362812 ps
T1058 /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2010947550 Jul 07 05:26:37 PM PDT 24 Jul 07 05:26:42 PM PDT 24 366457253 ps
T1059 /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3522805752 Jul 07 05:26:47 PM PDT 24 Jul 07 05:26:51 PM PDT 24 95124802 ps
T1060 /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3424754713 Jul 07 05:26:40 PM PDT 24 Jul 07 05:26:42 PM PDT 24 61809615 ps
T1061 /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.520481174 Jul 07 05:26:24 PM PDT 24 Jul 07 05:26:28 PM PDT 24 406358953 ps
T1062 /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2266518662 Jul 07 05:26:32 PM PDT 24 Jul 07 05:26:47 PM PDT 24 15006423061 ps
T1063 /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2330517742 Jul 07 05:26:38 PM PDT 24 Jul 07 05:26:44 PM PDT 24 65281165 ps
T1064 /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4154041186 Jul 07 05:26:39 PM PDT 24 Jul 07 05:26:44 PM PDT 24 109831106 ps
T1065 /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4114979909 Jul 07 05:26:31 PM PDT 24 Jul 07 05:26:34 PM PDT 24 324263241 ps
T1066 /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1818962588 Jul 07 05:26:30 PM PDT 24 Jul 07 05:26:32 PM PDT 24 701725667 ps
T1067 /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1413309193 Jul 07 05:26:33 PM PDT 24 Jul 07 05:26:36 PM PDT 24 25924232 ps
T1068 /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3107975209 Jul 07 05:26:31 PM PDT 24 Jul 07 05:26:34 PM PDT 24 447030868 ps
T1069 /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3279438630 Jul 07 05:26:42 PM PDT 24 Jul 07 05:26:46 PM PDT 24 45622487 ps
T1070 /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.981298740 Jul 07 05:26:37 PM PDT 24 Jul 07 05:26:41 PM PDT 24 195580604 ps
T1071 /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2721762292 Jul 07 05:26:38 PM PDT 24 Jul 07 05:26:42 PM PDT 24 227023912 ps
T1072 /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1178695075 Jul 07 05:26:30 PM PDT 24 Jul 07 05:26:36 PM PDT 24 519552650 ps
T1073 /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2764889401 Jul 07 05:26:35 PM PDT 24 Jul 07 05:26:53 PM PDT 24 4325948735 ps
T179 /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.732415709 Jul 07 05:26:42 PM PDT 24 Jul 07 05:26:56 PM PDT 24 407246031 ps
T1074 /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4006637568 Jul 07 05:26:37 PM PDT 24 Jul 07 05:26:40 PM PDT 24 13241027 ps
T1075 /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2986607059 Jul 07 05:26:37 PM PDT 24 Jul 07 05:26:43 PM PDT 24 576088253 ps
T1076 /workspace/coverage/cover_reg_top/11.spi_device_intr_test.455768701 Jul 07 05:26:46 PM PDT 24 Jul 07 05:26:47 PM PDT 24 187286715 ps
T1077 /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3892012994 Jul 07 05:26:37 PM PDT 24 Jul 07 05:26:41 PM PDT 24 793846238 ps
T1078 /workspace/coverage/cover_reg_top/34.spi_device_intr_test.328494570 Jul 07 05:26:55 PM PDT 24 Jul 07 05:27:01 PM PDT 24 10738411 ps
T1079 /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1012082790 Jul 07 05:26:39 PM PDT 24 Jul 07 05:26:41 PM PDT 24 43398240 ps
T1080 /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4123124552 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:39 PM PDT 24 248377840 ps
T1081 /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2753229412 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:40 PM PDT 24 146141440 ps
T1082 /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1830504524 Jul 07 05:26:31 PM PDT 24 Jul 07 05:26:40 PM PDT 24 432593192 ps
T1083 /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3646857652 Jul 07 05:26:41 PM PDT 24 Jul 07 05:26:44 PM PDT 24 129852421 ps
T1084 /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1199691347 Jul 07 05:26:38 PM PDT 24 Jul 07 05:26:42 PM PDT 24 220132912 ps
T1085 /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3427653275 Jul 07 05:26:43 PM PDT 24 Jul 07 05:26:44 PM PDT 24 200516300 ps
T1086 /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1453296490 Jul 07 05:26:35 PM PDT 24 Jul 07 05:26:41 PM PDT 24 585262168 ps
T1087 /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4036589979 Jul 07 05:26:41 PM PDT 24 Jul 07 05:26:45 PM PDT 24 213999314 ps
T1088 /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3189089589 Jul 07 05:26:40 PM PDT 24 Jul 07 05:26:42 PM PDT 24 20275973 ps
T1089 /workspace/coverage/cover_reg_top/9.spi_device_intr_test.229957182 Jul 07 05:26:39 PM PDT 24 Jul 07 05:26:42 PM PDT 24 45239464 ps
T1090 /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4181654146 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:37 PM PDT 24 327248180 ps
T1091 /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.897500554 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:55 PM PDT 24 293252994 ps
T1092 /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1486670319 Jul 07 05:26:51 PM PDT 24 Jul 07 05:26:55 PM PDT 24 1367228419 ps
T1093 /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2951358630 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:36 PM PDT 24 37748956 ps
T1094 /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.821600239 Jul 07 05:26:42 PM PDT 24 Jul 07 05:26:51 PM PDT 24 303120012 ps
T1095 /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3478592840 Jul 07 05:26:39 PM PDT 24 Jul 07 05:26:44 PM PDT 24 383012149 ps
T184 /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.298315809 Jul 07 05:26:43 PM PDT 24 Jul 07 05:26:59 PM PDT 24 2770065553 ps
T1096 /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3933014728 Jul 07 05:27:01 PM PDT 24 Jul 07 05:27:02 PM PDT 24 34144792 ps
T1097 /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1548325840 Jul 07 05:26:45 PM PDT 24 Jul 07 05:26:47 PM PDT 24 18000039 ps
T1098 /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4247886262 Jul 07 05:26:35 PM PDT 24 Jul 07 05:26:39 PM PDT 24 144688338 ps
T1099 /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2624759157 Jul 07 05:26:52 PM PDT 24 Jul 07 05:26:54 PM PDT 24 11366736 ps
T1100 /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.965569587 Jul 07 05:26:32 PM PDT 24 Jul 07 05:26:55 PM PDT 24 1207378247 ps
T1101 /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3371280148 Jul 07 05:26:42 PM PDT 24 Jul 07 05:26:44 PM PDT 24 30206682 ps
T1102 /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3179502916 Jul 07 05:26:27 PM PDT 24 Jul 07 05:26:48 PM PDT 24 1587764524 ps
T1103 /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1932624212 Jul 07 05:26:44 PM PDT 24 Jul 07 05:26:45 PM PDT 24 16505223 ps
T1104 /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1019411472 Jul 07 05:26:46 PM PDT 24 Jul 07 05:26:52 PM PDT 24 24956958 ps
T1105 /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2489943832 Jul 07 05:26:33 PM PDT 24 Jul 07 05:26:37 PM PDT 24 420715468 ps
T1106 /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2250772998 Jul 07 05:26:41 PM PDT 24 Jul 07 05:26:45 PM PDT 24 358729469 ps
T1107 /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3845077895 Jul 07 05:26:41 PM PDT 24 Jul 07 05:26:43 PM PDT 24 27152251 ps
T1108 /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.246628749 Jul 07 05:26:29 PM PDT 24 Jul 07 05:26:32 PM PDT 24 178319783 ps
T1109 /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2419284849 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:41 PM PDT 24 103525569 ps
T1110 /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2661397537 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:42 PM PDT 24 561070848 ps
T1111 /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3733028485 Jul 07 05:26:41 PM PDT 24 Jul 07 05:26:46 PM PDT 24 1978290056 ps
T1112 /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3824994870 Jul 07 05:26:38 PM PDT 24 Jul 07 05:26:41 PM PDT 24 32880566 ps
T1113 /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3493310953 Jul 07 05:26:40 PM PDT 24 Jul 07 05:26:44 PM PDT 24 297736296 ps
T1114 /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2412348672 Jul 07 05:26:44 PM PDT 24 Jul 07 05:26:45 PM PDT 24 34388120 ps
T1115 /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1909966309 Jul 07 05:26:41 PM PDT 24 Jul 07 05:26:43 PM PDT 24 54187472 ps
T1116 /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2420271570 Jul 07 05:26:40 PM PDT 24 Jul 07 05:26:46 PM PDT 24 248888295 ps
T1117 /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2120264231 Jul 07 05:26:40 PM PDT 24 Jul 07 05:26:46 PM PDT 24 1404867667 ps
T1118 /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1441704831 Jul 07 05:26:54 PM PDT 24 Jul 07 05:26:56 PM PDT 24 26404354 ps
T1119 /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1012455457 Jul 07 05:26:30 PM PDT 24 Jul 07 05:26:31 PM PDT 24 13680039 ps
T1120 /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2932981772 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:41 PM PDT 24 84134994 ps
T1121 /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.459619562 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:38 PM PDT 24 66044305 ps
T1122 /workspace/coverage/cover_reg_top/48.spi_device_intr_test.801217647 Jul 07 05:26:42 PM PDT 24 Jul 07 05:26:44 PM PDT 24 46007250 ps
T1123 /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1172646423 Jul 07 05:26:34 PM PDT 24 Jul 07 05:26:38 PM PDT 24 74583503 ps
T1124 /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3739834305 Jul 07 05:26:37 PM PDT 24 Jul 07 05:26:40 PM PDT 24 11554434 ps
T1125 /workspace/coverage/cover_reg_top/22.spi_device_intr_test.304853088 Jul 07 05:26:41 PM PDT 24 Jul 07 05:26:43 PM PDT 24 12690689 ps
T1126 /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3464197326 Jul 07 05:26:49 PM PDT 24 Jul 07 05:26:53 PM PDT 24 409387953 ps
T1127 /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1449801383 Jul 07 05:26:40 PM PDT 24 Jul 07 05:26:43 PM PDT 24 71241045 ps
T87 /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.117624662 Jul 07 05:26:38 PM PDT 24 Jul 07 05:26:41 PM PDT 24 24469052 ps
T1128 /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4030985717 Jul 07 05:26:37 PM PDT 24 Jul 07 05:26:42 PM PDT 24 108049186 ps
T1129 /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.954292011 Jul 07 05:26:39 PM PDT 24 Jul 07 05:26:47 PM PDT 24 332528188 ps
T1130 /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1934781275 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:40 PM PDT 24 216063155 ps
T1131 /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.530187073 Jul 07 05:26:38 PM PDT 24 Jul 07 05:26:43 PM PDT 24 474215702 ps
T177 /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2119635354 Jul 07 05:26:36 PM PDT 24 Jul 07 05:26:43 PM PDT 24 144257792 ps

Test location /workspace/coverage/default/23.spi_device_flash_mode_ignore_cmds.2735034493
Short name T9
Test name
Test status
Simulation time 7544136040 ps
CPU time 84.64 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:30:52 PM PDT 24
Peak memory 257028 kb
Host smart-abe20dfd-a1f7-4229-bd97-78b2d065bae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735034493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode_ignore_cmd
s.2735034493
Directory /workspace/23.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm_min_idle.2369796885
Short name T34
Test name
Test status
Simulation time 16454121033 ps
CPU time 131.28 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:32:24 PM PDT 24
Peak memory 251920 kb
Host smart-daf862c5-9638-432f-a328-abc112c8879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369796885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm_min_idl
e.2369796885
Directory /workspace/34.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_stress_all.2215778917
Short name T15
Test name
Test status
Simulation time 70759181498 ps
CPU time 196.72 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:32:47 PM PDT 24
Peak memory 267640 kb
Host smart-c07fdb4c-a1d1-47f8-b498-1cbe1c9eb1ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215778917 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_stre
ss_all.2215778917
Directory /workspace/20.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_intg_err.1492965636
Short name T95
Test name
Test status
Simulation time 1488639675 ps
CPU time 8.67 seconds
Started Jul 07 05:26:30 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 216224 kb
Host smart-adb25b92-e09a-4492-b655-0a1bde0b1af8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492965636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device
_tl_intg_err.1492965636
Directory /workspace/5.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/47.spi_device_stress_all.1977286501
Short name T14
Test name
Test status
Simulation time 209242278103 ps
CPU time 470.49 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:38:34 PM PDT 24
Peak memory 265652 kb
Host smart-abcd560a-034d-47b7-a975-3330c8cec0df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977286501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_stre
ss_all.1977286501
Directory /workspace/47.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm.310859098
Short name T204
Test name
Test status
Simulation time 19997610025 ps
CPU time 83.58 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:31:41 PM PDT 24
Peak memory 250344 kb
Host smart-83215cc6-6627-4e0f-9855-72ec9b7cd7c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310859098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm.310859098
Directory /workspace/33.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_ram_cfg.3296776158
Short name T68
Test name
Test status
Simulation time 30882528 ps
CPU time 0.73 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 216068 kb
Host smart-79af3b65-471c-4dfc-ab29-b48a2980725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3296776158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_ram_cfg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_ram_cfg.3296776158
Directory /workspace/0.spi_device_ram_cfg/latest

Test location /workspace/coverage/default/1.spi_device_stress_all.572463670
Short name T156
Test name
Test status
Simulation time 8014906923 ps
CPU time 206.93 seconds
Started Jul 07 05:28:30 PM PDT 24
Finished Jul 07 05:31:58 PM PDT 24
Peak memory 283340 kb
Host smart-4b40474f-3d52-4633-a43b-77a22dd57615
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572463670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_stress
_all.572463670
Directory /workspace/1.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm_min_idle.1631253083
Short name T33
Test name
Test status
Simulation time 424459449109 ps
CPU time 449.66 seconds
Started Jul 07 05:30:22 PM PDT 24
Finished Jul 07 05:37:52 PM PDT 24
Peak memory 265648 kb
Host smart-cb406429-93e9-4a1e-897e-bae2d07780d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631253083 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm_min_idl
e.1631253083
Directory /workspace/42.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_errors.2995340069
Short name T94
Test name
Test status
Simulation time 197413927 ps
CPU time 4.47 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 215808 kb
Host smart-9b353b22-b98d-42df-bee4-2adbb789945c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2995340069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_tl_errors.2
995340069
Directory /workspace/9.spi_device_tl_errors/latest

Test location /workspace/coverage/default/8.spi_device_flash_all.1158850746
Short name T199
Test name
Test status
Simulation time 68942598351 ps
CPU time 288.27 seconds
Started Jul 07 05:29:01 PM PDT 24
Finished Jul 07 05:33:50 PM PDT 24
Peak memory 255128 kb
Host smart-6c9514e6-5a2a-4c46-bcee-395fb670d341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158850746 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_all.1158850746
Directory /workspace/8.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_sec_cm.3554221328
Short name T69
Test name
Test status
Simulation time 68876038 ps
CPU time 1.03 seconds
Started Jul 07 05:28:33 PM PDT 24
Finished Jul 07 05:28:34 PM PDT 24
Peak memory 236564 kb
Host smart-28153c7f-324c-4ff6-b728-216985b410b0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3554221328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_sec_cm.3554221328
Directory /workspace/2.spi_device_sec_cm/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode.2568629009
Short name T4
Test name
Test status
Simulation time 14605792034 ps
CPU time 46.29 seconds
Started Jul 07 05:29:05 PM PDT 24
Finished Jul 07 05:29:53 PM PDT 24
Peak memory 232748 kb
Host smart-b6ef28c3-42ca-4eda-8ae4-6bb3b578e916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2568629009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode.2568629009
Directory /workspace/8.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm_min_idle.3680238980
Short name T193
Test name
Test status
Simulation time 11779021480 ps
CPU time 130.88 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:32:24 PM PDT 24
Peak memory 262100 kb
Host smart-c956cb4b-afff-42b3-bd14-d6d9c8e25ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680238980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm_min_idl
e.3680238980
Directory /workspace/41.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_stress_all.2250977570
Short name T231
Test name
Test status
Simulation time 42152632985 ps
CPU time 450.49 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:36:53 PM PDT 24
Peak memory 270616 kb
Host smart-8d1968fb-c085-4a80-8efc-1101381a3323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250977570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_stre
ss_all.2250977570
Directory /workspace/19.spi_device_stress_all/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_rw.2344162891
Short name T113
Test name
Test status
Simulation time 83456818 ps
CPU time 2.17 seconds
Started Jul 07 05:26:44 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 207528 kb
Host smart-ade03991-f098-4671-b432-7892b244097c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2344162891 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_rw.
2344162891
Directory /workspace/13.spi_device_csr_rw/latest

Test location /workspace/coverage/default/29.spi_device_stress_all.217929280
Short name T155
Test name
Test status
Simulation time 3717320882 ps
CPU time 99.31 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:31:38 PM PDT 24
Peak memory 256616 kb
Host smart-bfb750b7-854a-45a1-9e14-744ec17f4791
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217929280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_stres
s_all.217929280
Directory /workspace/29.spi_device_stress_all/latest

Test location /workspace/coverage/default/48.spi_device_stress_all.2342831515
Short name T13
Test name
Test status
Simulation time 20440715396 ps
CPU time 192.02 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:33:55 PM PDT 24
Peak memory 249300 kb
Host smart-ecbaf500-b9ff-4652-a135-07323b0e3b2e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342831515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_stre
ss_all.2342831515
Directory /workspace/48.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode_ignore_cmds.525942069
Short name T186
Test name
Test status
Simulation time 15122394283 ps
CPU time 102.39 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:32:00 PM PDT 24
Peak memory 272396 kb
Host smart-aa0874d1-9deb-40a8-a6fd-1fe8560e8de1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525942069 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode_ignore_cmds
.525942069
Directory /workspace/39.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_flash_and_tpm.3425002138
Short name T273
Test name
Test status
Simulation time 173655441025 ps
CPU time 336.93 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:35:44 PM PDT 24
Peak memory 265768 kb
Host smart-a4a17d2b-197b-459a-983d-076f34dddb2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425002138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_and_tpm.3425002138
Directory /workspace/34.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode_ignore_cmds.3437171506
Short name T43
Test name
Test status
Simulation time 39539000976 ps
CPU time 278.02 seconds
Started Jul 07 05:29:38 PM PDT 24
Finished Jul 07 05:34:16 PM PDT 24
Peak memory 265664 kb
Host smart-14c667f2-76e7-4af9-b960-8eeb8190bf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437171506 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode_ignore_cmd
s.3437171506
Directory /workspace/22.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm_min_idle.2623846892
Short name T290
Test name
Test status
Simulation time 7156483102 ps
CPU time 144.95 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:32:36 PM PDT 24
Peak memory 266880 kb
Host smart-4d61da8b-f270-4dff-965b-698a0c150827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623846892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm_min_idl
e.2623846892
Directory /workspace/37.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/41.spi_device_flash_and_tpm.3056099413
Short name T38
Test name
Test status
Simulation time 43739242230 ps
CPU time 468.31 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:38:05 PM PDT 24
Peak memory 265636 kb
Host smart-52755892-b881-49e6-8e2b-ee41661b2d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056099413 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_and_tpm.3056099413
Directory /workspace/41.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm_min_idle.3887386456
Short name T135
Test name
Test status
Simulation time 42402987436 ps
CPU time 148.69 seconds
Started Jul 07 05:30:06 PM PDT 24
Finished Jul 07 05:32:35 PM PDT 24
Peak memory 273824 kb
Host smart-5f67a763-1c6c-4253-92c4-7ea46c533cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3887386456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm_min_idl
e.3887386456
Directory /workspace/32.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm.649259155
Short name T25
Test name
Test status
Simulation time 18485256657 ps
CPU time 76.61 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:31:17 PM PDT 24
Peak memory 255376 kb
Host smart-b3ae66b2-11aa-474b-9d2f-c2b36b743ecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649259155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm.649259155
Directory /workspace/30.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_intg_err.279160321
Short name T178
Test name
Test status
Simulation time 3442186011 ps
CPU time 21.1 seconds
Started Jul 07 05:26:30 PM PDT 24
Finished Jul 07 05:26:52 PM PDT 24
Peak memory 215828 kb
Host smart-7066c343-223f-460c-950d-f3c1b9e163c8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279160321 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_
tl_intg_err.279160321
Directory /workspace/6.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/6.spi_device_stress_all.705287519
Short name T307
Test name
Test status
Simulation time 173461455311 ps
CPU time 458.83 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:36:18 PM PDT 24
Peak memory 264888 kb
Host smart-d661774a-fb25-47e4-88cd-1584dc46dd4f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705287519 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_stress
_all.705287519
Directory /workspace/6.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_alert_test.474372566
Short name T64
Test name
Test status
Simulation time 14570000 ps
CPU time 0.74 seconds
Started Jul 07 05:29:15 PM PDT 24
Finished Jul 07 05:29:16 PM PDT 24
Peak memory 205552 kb
Host smart-0c4ddbb5-89bc-42cd-a60e-844abf5da9d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=474372566 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_alert_test.474372566
Directory /workspace/12.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm.2006282418
Short name T205
Test name
Test status
Simulation time 61230820176 ps
CPU time 226.1 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:32:43 PM PDT 24
Peak memory 253656 kb
Host smart-c082cc2b-c879-4679-a289-d3592aed7b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2006282418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm.2006282418
Directory /workspace/2.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode.3375948652
Short name T311
Test name
Test status
Simulation time 478088983 ps
CPU time 7.02 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:34 PM PDT 24
Peak memory 232696 kb
Host smart-d122aea6-0886-4ff6-b0f8-c56bb2ad4470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3375948652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode.3375948652
Directory /workspace/20.spi_device_flash_mode/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_errors.2119635354
Short name T177
Test name
Test status
Simulation time 144257792 ps
CPU time 4.43 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 215976 kb
Host smart-58fcc593-dc51-433e-b9d4-acb15078d534
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119635354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_tl_errors.2
119635354
Directory /workspace/8.spi_device_tl_errors/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm.4125225792
Short name T230
Test name
Test status
Simulation time 127100797931 ps
CPU time 334.24 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:34:52 PM PDT 24
Peak memory 257452 kb
Host smart-793511c4-fb66-497f-903e-f16db0d4ece9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125225792 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm.4125225792
Directory /workspace/17.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/17.spi_device_flash_and_tpm_min_idle.534010257
Short name T331
Test name
Test status
Simulation time 198225263724 ps
CPU time 415.14 seconds
Started Jul 07 05:29:16 PM PDT 24
Finished Jul 07 05:36:12 PM PDT 24
Peak memory 269372 kb
Host smart-d3e9c0e8-b7f9-422e-afa1-bcbdc77c1d19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534010257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_and_tpm_min_idle
.534010257
Directory /workspace/17.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm.4010450580
Short name T195
Test name
Test status
Simulation time 10296365954 ps
CPU time 110.89 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:31:11 PM PDT 24
Peak memory 264912 kb
Host smart-6f7aa4f3-0258-4629-8d6f-8dae0f1c162c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010450580 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm.4010450580
Directory /workspace/19.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_intg_err.897500554
Short name T1091
Test name
Test status
Simulation time 293252994 ps
CPU time 18.83 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 215776 kb
Host smart-a1ef7760-cc3c-4319-9cdd-f8e299aba25c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897500554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device
_tl_intg_err.897500554
Directory /workspace/10.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_all.1287425182
Short name T291
Test name
Test status
Simulation time 36806168841 ps
CPU time 289.12 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:33:44 PM PDT 24
Peak memory 256728 kb
Host smart-a72bbeb7-e713-446b-a727-efc99a17b432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287425182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_all.1287425182
Directory /workspace/1.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm.2520186967
Short name T37
Test name
Test status
Simulation time 52296444612 ps
CPU time 271.8 seconds
Started Jul 07 05:29:16 PM PDT 24
Finished Jul 07 05:33:48 PM PDT 24
Peak memory 249292 kb
Host smart-538efc1d-a0fd-4164-bace-0f7159154315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520186967 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm.2520186967
Directory /workspace/14.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode.984864576
Short name T314
Test name
Test status
Simulation time 174129154 ps
CPU time 9.97 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 237096 kb
Host smart-886c9796-5a4c-49cd-a569-d612e803fd68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984864576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode.984864576
Directory /workspace/14.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_read_buffer_direct.3613794480
Short name T28
Test name
Test status
Simulation time 337408404 ps
CPU time 4.69 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:27 PM PDT 24
Peak memory 220352 kb
Host smart-43976da0-02c9-4268-b44f-45fff29a699f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3613794480 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_read_buffer_dir
ect.3613794480
Directory /workspace/18.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_intg_err.903548158
Short name T65
Test name
Test status
Simulation time 565347933 ps
CPU time 14.97 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 215928 kb
Host smart-e39279fd-6f91-42dd-9e9b-28b39854c807
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903548158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_
tl_intg_err.903548158
Directory /workspace/0.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_intg_err.2029690345
Short name T185
Test name
Test status
Simulation time 2902146564 ps
CPU time 14.86 seconds
Started Jul 07 05:26:38 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 215640 kb
Host smart-5e926a04-bd76-4030-a30e-636bc966cafa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029690345 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_devic
e_tl_intg_err.2029690345
Directory /workspace/12.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm.709873689
Short name T47
Test name
Test status
Simulation time 19061634433 ps
CPU time 114.38 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:30:45 PM PDT 24
Peak memory 265664 kb
Host smart-4a1e6c50-b085-4961-ad43-2c8671faebce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709873689 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm.709873689
Directory /workspace/1.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode_ignore_cmds.3240450371
Short name T304
Test name
Test status
Simulation time 8054973199 ps
CPU time 56.36 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 262664 kb
Host smart-842ad6b6-d708-4215-b07c-f004322022ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240450371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode_ignore_cmd
s.3240450371
Directory /workspace/10.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm.408435656
Short name T885
Test name
Test status
Simulation time 10962268367 ps
CPU time 166.24 seconds
Started Jul 07 05:29:02 PM PDT 24
Finished Jul 07 05:31:49 PM PDT 24
Peak memory 267600 kb
Host smart-71b49d52-84af-4597-9841-3479e30541f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408435656 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm.408435656
Directory /workspace/11.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode_ignore_cmds.1789342167
Short name T766
Test name
Test status
Simulation time 151960583452 ps
CPU time 250.37 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:33:29 PM PDT 24
Peak memory 257372 kb
Host smart-cb1d2bcb-8c4a-4e0a-ba24-9648c2740d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789342167 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode_ignore_cmd
s.1789342167
Directory /workspace/11.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm_min_idle.2649800916
Short name T285
Test name
Test status
Simulation time 31262366263 ps
CPU time 316.53 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:34:44 PM PDT 24
Peak memory 266316 kb
Host smart-848b5683-0103-4ad8-964c-474b67d402e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649800916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm_min_idl
e.2649800916
Directory /workspace/18.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm.1938608927
Short name T284
Test name
Test status
Simulation time 50600822265 ps
CPU time 198.21 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:33:09 PM PDT 24
Peak memory 272284 kb
Host smart-7e55eb4f-cabf-403e-bfb5-e5d5b5dc18b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938608927 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm.1938608927
Directory /workspace/26.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm.2099623490
Short name T218
Test name
Test status
Simulation time 524221435470 ps
CPU time 328.63 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:35:24 PM PDT 24
Peak memory 263356 kb
Host smart-f41bcb80-6101-436a-871b-fb6629ae79f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099623490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm.2099623490
Directory /workspace/31.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_pass_addr_payload_swap.76485292
Short name T49
Test name
Test status
Simulation time 488007257 ps
CPU time 2.3 seconds
Started Jul 07 05:29:10 PM PDT 24
Finished Jul 07 05:29:12 PM PDT 24
Peak memory 224492 kb
Host smart-718cbbf5-fd67-4bdb-9b62-454255bde72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76485292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_addr_payload_swap.76485292
Directory /workspace/15.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_tl_errors.1361497908
Short name T98
Test name
Test status
Simulation time 49593860 ps
CPU time 3.1 seconds
Started Jul 07 05:26:24 PM PDT 24
Finished Jul 07 05:26:28 PM PDT 24
Peak memory 216992 kb
Host smart-dd35df6f-b170-4657-9da7-ba3dd5ddd836
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1361497908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_tl_errors.1
361497908
Directory /workspace/0.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_hw_reset.89523518
Short name T86
Test name
Test status
Simulation time 129699710 ps
CPU time 1.25 seconds
Started Jul 07 05:26:31 PM PDT 24
Finished Jul 07 05:26:33 PM PDT 24
Peak memory 207420 kb
Host smart-73f0896f-1bac-425c-bcc7-96fc447e5a5e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89523518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_co
mmon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_
hw_reset.89523518
Directory /workspace/3.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_aliasing.4111923608
Short name T118
Test name
Test status
Simulation time 624615173 ps
CPU time 16.18 seconds
Started Jul 07 05:26:29 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 215684 kb
Host smart-bb82f50f-e6f6-4023-80a6-e5e981377c12
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111923608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_aliasing.4111923608
Directory /workspace/0.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_bit_bash.2266518662
Short name T1062
Test name
Test status
Simulation time 15006423061 ps
CPU time 14.61 seconds
Started Jul 07 05:26:32 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 207540 kb
Host smart-96542aa4-ee85-43d0-9fcd-ae3c3068966e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266518662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_bit_bash.2266518662
Directory /workspace/0.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_hw_reset.1510441203
Short name T154
Test name
Test status
Simulation time 127151625 ps
CPU time 1.2 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:35 PM PDT 24
Peak memory 207396 kb
Host smart-3281a18d-98a8-474c-8e38-b910f18a017a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510441203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_cs
r_hw_reset.1510441203
Directory /workspace/0.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_mem_rw_with_rand_reset.2709124891
Short name T93
Test name
Test status
Simulation time 523615167 ps
CPU time 3.86 seconds
Started Jul 07 05:26:26 PM PDT 24
Finished Jul 07 05:26:30 PM PDT 24
Peak memory 217800 kb
Host smart-1944b47a-1d3d-431d-a79b-9642b0cb69e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709124891 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_mem_rw_with_rand_reset.2709124891
Directory /workspace/0.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_csr_rw.4114979909
Short name T1065
Test name
Test status
Simulation time 324263241 ps
CPU time 2.47 seconds
Started Jul 07 05:26:31 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 207332 kb
Host smart-6f1fc1fa-b566-4f33-942e-ded389acd57a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4114979909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_csr_rw.4
114979909
Directory /workspace/0.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_intr_test.1367810567
Short name T1034
Test name
Test status
Simulation time 29367577 ps
CPU time 0.73 seconds
Started Jul 07 05:26:39 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 204528 kb
Host smart-fd49ed63-2e99-4713-a8be-47c8bdbe6e0b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1367810567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_intr_test.1
367810567
Directory /workspace/0.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_partial_access.1172646423
Short name T1123
Test name
Test status
Simulation time 74583503 ps
CPU time 1.27 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:38 PM PDT 24
Peak memory 215660 kb
Host smart-50e7cf79-0ce9-477b-833a-6ac7b9e7e54b
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172646423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi
_device_mem_partial_access.1172646423
Directory /workspace/0.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_mem_walk.3316587551
Short name T1045
Test name
Test status
Simulation time 21525343 ps
CPU time 0.7 seconds
Started Jul 07 05:26:28 PM PDT 24
Finished Jul 07 05:26:29 PM PDT 24
Peak memory 204416 kb
Host smart-334fbf5e-4fe2-4195-aae8-259d5c64407c
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316587551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.spi_device_me
m_walk.3316587551
Directory /workspace/0.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/0.spi_device_same_csr_outstanding.1485424152
Short name T1026
Test name
Test status
Simulation time 1771930515 ps
CPU time 4.02 seconds
Started Jul 07 05:26:32 PM PDT 24
Finished Jul 07 05:26:37 PM PDT 24
Peak memory 215788 kb
Host smart-d5c30133-c34e-4229-b46e-bd3b732b6913
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485424152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.s
pi_device_same_csr_outstanding.1485424152
Directory /workspace/0.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_aliasing.878202477
Short name T114
Test name
Test status
Simulation time 365264318 ps
CPU time 7.88 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 207484 kb
Host smart-d1905236-0476-4c01-915f-2cabee2819aa
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878202477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr
_aliasing.878202477
Directory /workspace/1.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_bit_bash.2824751328
Short name T1027
Test name
Test status
Simulation time 1466149514 ps
CPU time 23.18 seconds
Started Jul 07 05:26:20 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 207464 kb
Host smart-b5f9edad-55fc-4458-b182-4769405e6262
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824751328 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_bit_bash.2824751328
Directory /workspace/1.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_hw_reset.1942005317
Short name T85
Test name
Test status
Simulation time 64462810 ps
CPU time 1.19 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 207488 kb
Host smart-09f70eac-8a90-42a2-8bb4-9c85883ebeb3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942005317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_cs
r_hw_reset.1942005317
Directory /workspace/1.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_mem_rw_with_rand_reset.520481174
Short name T1061
Test name
Test status
Simulation time 406358953 ps
CPU time 2.99 seconds
Started Jul 07 05:26:24 PM PDT 24
Finished Jul 07 05:26:28 PM PDT 24
Peak memory 216836 kb
Host smart-568109fa-8027-4ccc-b146-24ba6b2f46ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520481174 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 1.spi_device_csr_mem_rw_with_rand_reset.520481174
Directory /workspace/1.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_csr_rw.3107975209
Short name T1068
Test name
Test status
Simulation time 447030868 ps
CPU time 2.73 seconds
Started Jul 07 05:26:31 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 215608 kb
Host smart-922fa61f-1ead-4fef-8971-eeea8925cc73
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107975209 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_csr_rw.3
107975209
Directory /workspace/1.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_intr_test.2593283224
Short name T1047
Test name
Test status
Simulation time 52309682 ps
CPU time 0.74 seconds
Started Jul 07 05:26:29 PM PDT 24
Finished Jul 07 05:26:30 PM PDT 24
Peak memory 204088 kb
Host smart-0cc911ad-b7a2-4a96-9b2e-9aa580a61999
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593283224 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_intr_test.2
593283224
Directory /workspace/1.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_partial_access.246628749
Short name T1108
Test name
Test status
Simulation time 178319783 ps
CPU time 1.91 seconds
Started Jul 07 05:26:29 PM PDT 24
Finished Jul 07 05:26:32 PM PDT 24
Peak memory 215748 kb
Host smart-85867651-737d-48d0-885b-08f368e2e9df
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246628749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=sp
i_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_
device_mem_partial_access.246628749
Directory /workspace/1.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_mem_walk.298684843
Short name T1013
Test name
Test status
Simulation time 12521745 ps
CPU time 0.65 seconds
Started Jul 07 05:26:29 PM PDT 24
Finished Jul 07 05:26:30 PM PDT 24
Peak memory 204032 kb
Host smart-e99634bd-a4b9-42b9-876b-c9b64b7ae846
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298684843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_mem
_walk.298684843
Directory /workspace/1.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_same_csr_outstanding.3981257514
Short name T139
Test name
Test status
Simulation time 255640540 ps
CPU time 3.79 seconds
Started Jul 07 05:26:27 PM PDT 24
Finished Jul 07 05:26:31 PM PDT 24
Peak memory 215788 kb
Host smart-d4c3b1c0-98be-4029-bebd-5fd48de334a4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981257514 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.s
pi_device_same_csr_outstanding.3981257514
Directory /workspace/1.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_errors.3692162714
Short name T1049
Test name
Test status
Simulation time 1018779150 ps
CPU time 5 seconds
Started Jul 07 05:26:24 PM PDT 24
Finished Jul 07 05:26:29 PM PDT 24
Peak memory 215956 kb
Host smart-bbf4a8d6-df0a-424b-b091-0bd1d3686357
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692162714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device_tl_errors.3
692162714
Directory /workspace/1.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.spi_device_tl_intg_err.3630110975
Short name T108
Test name
Test status
Simulation time 2293245182 ps
CPU time 7.97 seconds
Started Jul 07 05:26:30 PM PDT 24
Finished Jul 07 05:26:38 PM PDT 24
Peak memory 216172 kb
Host smart-0a1d0c40-18ce-403c-a63a-9b10f0538b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3630110975 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.spi_device
_tl_intg_err.3630110975
Directory /workspace/1.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_mem_rw_with_rand_reset.1023464180
Short name T151
Test name
Test status
Simulation time 146376606 ps
CPU time 3.75 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 217528 kb
Host smart-5946af51-2d63-4d0c-938d-44c5da31b924
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023464180 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_mem_rw_with_rand_reset.1023464180
Directory /workspace/10.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_csr_rw.207677298
Short name T116
Test name
Test status
Simulation time 269891796 ps
CPU time 1.95 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 207480 kb
Host smart-da460716-8791-43cc-a9d8-76546abaa2ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207677298 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_csr_rw.207677298
Directory /workspace/10.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_intr_test.1834352408
Short name T1020
Test name
Test status
Simulation time 45107916 ps
CPU time 0.73 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:37 PM PDT 24
Peak memory 204248 kb
Host smart-5c925c59-2693-424d-ad18-6af89e3dbc81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834352408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_intr_test.
1834352408
Directory /workspace/10.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_same_csr_outstanding.1934781275
Short name T1130
Test name
Test status
Simulation time 216063155 ps
CPU time 1.75 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 207484 kb
Host smart-e8e3799d-4b7b-428d-9927-11eb288ac57a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934781275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
spi_device_same_csr_outstanding.1934781275
Directory /workspace/10.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.spi_device_tl_errors.741374366
Short name T97
Test name
Test status
Simulation time 66703752 ps
CPU time 4.27 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 215960 kb
Host smart-a8829747-ca5e-49a5-92b6-8cd4ffc580f9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741374366 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.spi_device_tl_errors.741374366
Directory /workspace/10.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_mem_rw_with_rand_reset.4215762587
Short name T1054
Test name
Test status
Simulation time 87073566 ps
CPU time 2.71 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 216844 kb
Host smart-04162699-1c0c-441f-8504-bb904f8aab45
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4215762587 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_mem_rw_with_rand_reset.4215762587
Directory /workspace/11.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_csr_rw.3677041523
Short name T140
Test name
Test status
Simulation time 26170684 ps
CPU time 1.64 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 207420 kb
Host smart-de045c2c-52e8-4f76-9dc8-83db007dc28d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677041523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_csr_rw.
3677041523
Directory /workspace/11.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_intr_test.455768701
Short name T1076
Test name
Test status
Simulation time 187286715 ps
CPU time 0.8 seconds
Started Jul 07 05:26:46 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 204572 kb
Host smart-20cd3df9-9145-4c7a-8838-08177878df11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=455768701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_intr_test.455768701
Directory /workspace/11.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_same_csr_outstanding.2330517742
Short name T1063
Test name
Test status
Simulation time 65281165 ps
CPU time 3.79 seconds
Started Jul 07 05:26:38 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 215712 kb
Host smart-3d136290-ae32-465a-84b4-383a9cba3c82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330517742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
spi_device_same_csr_outstanding.2330517742
Directory /workspace/11.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_errors.954292011
Short name T1129
Test name
Test status
Simulation time 332528188 ps
CPU time 6.02 seconds
Started Jul 07 05:26:39 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 215928 kb
Host smart-b994909c-c314-42eb-ae2c-c8d3978d642f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954292011 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_device_tl_errors.954292011
Directory /workspace/11.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.spi_device_tl_intg_err.1205195558
Short name T181
Test name
Test status
Simulation time 710528391 ps
CPU time 18.87 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 223860 kb
Host smart-6eb308f8-1e26-4bbe-9d72-d3a1aabb311e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1205195558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.spi_devic
e_tl_intg_err.1205195558
Directory /workspace/11.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_mem_rw_with_rand_reset.1148897104
Short name T1030
Test name
Test status
Simulation time 2409761456 ps
CPU time 3.71 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 217688 kb
Host smart-e0cd2523-dcf7-41d9-9f69-6141bbad2bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148897104 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_mem_rw_with_rand_reset.1148897104
Directory /workspace/12.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_csr_rw.459619562
Short name T1121
Test name
Test status
Simulation time 66044305 ps
CPU time 1.87 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:38 PM PDT 24
Peak memory 215704 kb
Host smart-cdbd0a25-304d-4b7a-8a00-6c671365d697
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459619562 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_csr_rw.459619562
Directory /workspace/12.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_intr_test.1012082790
Short name T1079
Test name
Test status
Simulation time 43398240 ps
CPU time 0.7 seconds
Started Jul 07 05:26:39 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 204544 kb
Host smart-ed0e59ce-c4cd-4393-b02b-f1796b37485e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012082790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_intr_test.
1012082790
Directory /workspace/12.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_same_csr_outstanding.1199691347
Short name T1084
Test name
Test status
Simulation time 220132912 ps
CPU time 2.01 seconds
Started Jul 07 05:26:38 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 215760 kb
Host smart-d5c3e32c-85ff-4bda-8ba9-d4e9207915c5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199691347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
spi_device_same_csr_outstanding.1199691347
Directory /workspace/12.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.spi_device_tl_errors.2721762292
Short name T1071
Test name
Test status
Simulation time 227023912 ps
CPU time 1.88 seconds
Started Jul 07 05:26:38 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 217088 kb
Host smart-e3dbb44f-d714-4b18-909f-419a37d4d997
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721762292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.spi_device_tl_errors.
2721762292
Directory /workspace/12.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_csr_mem_rw_with_rand_reset.2932981772
Short name T1120
Test name
Test status
Simulation time 84134994 ps
CPU time 2.53 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 216808 kb
Host smart-620afa1f-9553-4617-968b-2e612eaf7796
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2932981772 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 13.spi_device_csr_mem_rw_with_rand_reset.2932981772
Directory /workspace/13.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_intr_test.3260960430
Short name T1037
Test name
Test status
Simulation time 29480443 ps
CPU time 0.77 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:38 PM PDT 24
Peak memory 204168 kb
Host smart-f12f5e5e-cc21-45a9-8f2a-bb13a99e003d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3260960430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_intr_test.
3260960430
Directory /workspace/13.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_same_csr_outstanding.4030985717
Short name T1128
Test name
Test status
Simulation time 108049186 ps
CPU time 1.94 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 207504 kb
Host smart-1adcc057-6440-4c7f-aa3c-0c2cbaf10ab0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030985717 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
spi_device_same_csr_outstanding.4030985717
Directory /workspace/13.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_errors.2558836157
Short name T100
Test name
Test status
Simulation time 532370952 ps
CPU time 3.95 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 215908 kb
Host smart-3e068276-0c06-46d4-b777-0f93b588ee83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558836157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device_tl_errors.
2558836157
Directory /workspace/13.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.spi_device_tl_intg_err.456555116
Short name T104
Test name
Test status
Simulation time 1131006545 ps
CPU time 24.44 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:27:07 PM PDT 24
Peak memory 216068 kb
Host smart-82cf7a18-1968-40ac-a7e8-09a82785a339
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456555116 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.spi_device
_tl_intg_err.456555116
Directory /workspace/13.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_mem_rw_with_rand_reset.3279438630
Short name T1069
Test name
Test status
Simulation time 45622487 ps
CPU time 2.95 seconds
Started Jul 07 05:26:42 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 216876 kb
Host smart-6eefd9d2-d394-4c52-824b-5ba41df0a25f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279438630 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_mem_rw_with_rand_reset.3279438630
Directory /workspace/14.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_csr_rw.3478592840
Short name T1095
Test name
Test status
Simulation time 383012149 ps
CPU time 2.74 seconds
Started Jul 07 05:26:39 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 215700 kb
Host smart-41ef741a-d9c2-4a32-b70d-2f5858fbde6f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478592840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_csr_rw.
3478592840
Directory /workspace/14.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_intr_test.2710296772
Short name T1025
Test name
Test status
Simulation time 10914544 ps
CPU time 0.71 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 204268 kb
Host smart-d147c19c-b80b-4e1a-a3db-f602bd7c1dce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710296772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_intr_test.
2710296772
Directory /workspace/14.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_same_csr_outstanding.2753229412
Short name T1081
Test name
Test status
Simulation time 146141440 ps
CPU time 1.97 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 215628 kb
Host smart-1b98951e-2db8-49a7-a501-d4d2bf12dab6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2753229412 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
spi_device_same_csr_outstanding.2753229412
Directory /workspace/14.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_errors.919293594
Short name T99
Test name
Test status
Simulation time 322986179 ps
CPU time 2.21 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 215868 kb
Host smart-41243972-957f-458f-a5bd-eef682985835
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919293594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device_tl_errors.919293594
Directory /workspace/14.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.spi_device_tl_intg_err.981758924
Short name T109
Test name
Test status
Simulation time 1240873635 ps
CPU time 7.59 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:50 PM PDT 24
Peak memory 215748 kb
Host smart-d1b2084b-2bca-4e56-be60-874617cb64c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981758924 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.spi_device
_tl_intg_err.981758924
Directory /workspace/14.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_mem_rw_with_rand_reset.3728224163
Short name T152
Test name
Test status
Simulation time 493400637 ps
CPU time 4.21 seconds
Started Jul 07 05:26:38 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 217380 kb
Host smart-b4631e1a-ea93-454c-86ab-088f096c2896
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728224163 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_mem_rw_with_rand_reset.3728224163
Directory /workspace/15.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_csr_rw.2293325943
Short name T1053
Test name
Test status
Simulation time 1176773581 ps
CPU time 2.73 seconds
Started Jul 07 05:26:40 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 215672 kb
Host smart-0baa5fce-21c8-4fb1-913e-314a553696b6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2293325943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_csr_rw.
2293325943
Directory /workspace/15.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_intr_test.3461918063
Short name T1035
Test name
Test status
Simulation time 101375357 ps
CPU time 0.7 seconds
Started Jul 07 05:26:40 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 204592 kb
Host smart-a868355c-9118-4fef-880a-1577e300343c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461918063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_intr_test.
3461918063
Directory /workspace/15.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_same_csr_outstanding.2420271570
Short name T1116
Test name
Test status
Simulation time 248888295 ps
CPU time 4.11 seconds
Started Jul 07 05:26:40 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 215720 kb
Host smart-134740b2-1771-41ee-9ec6-f4e31fcd26c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2420271570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
spi_device_same_csr_outstanding.2420271570
Directory /workspace/15.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_errors.3733028485
Short name T1111
Test name
Test status
Simulation time 1978290056 ps
CPU time 4.05 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 216012 kb
Host smart-378313fc-65a6-4064-a98f-27c9f7784a8d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733028485 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device_tl_errors.
3733028485
Directory /workspace/15.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.spi_device_tl_intg_err.732415709
Short name T179
Test name
Test status
Simulation time 407246031 ps
CPU time 13.08 seconds
Started Jul 07 05:26:42 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 215696 kb
Host smart-1f770eb9-e0cf-4163-a05b-91cb15cb6268
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732415709 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.spi_device
_tl_intg_err.732415709
Directory /workspace/15.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_mem_rw_with_rand_reset.2010947550
Short name T1058
Test name
Test status
Simulation time 366457253 ps
CPU time 3.04 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 218128 kb
Host smart-d040cc1a-ba90-4f03-94fd-284bd2ae1494
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2010947550 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_mem_rw_with_rand_reset.2010947550
Directory /workspace/16.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_csr_rw.3646857652
Short name T1083
Test name
Test status
Simulation time 129852421 ps
CPU time 1.35 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 215632 kb
Host smart-3b31de6d-6dba-4e91-8b9f-adcae3d366b2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3646857652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_csr_rw.
3646857652
Directory /workspace/16.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_intr_test.579184720
Short name T1012
Test name
Test status
Simulation time 23259072 ps
CPU time 0.75 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 204284 kb
Host smart-832779a2-0737-4562-bff8-698d08fa70cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579184720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_intr_test.579184720
Directory /workspace/16.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_same_csr_outstanding.530187073
Short name T1131
Test name
Test status
Simulation time 474215702 ps
CPU time 3.11 seconds
Started Jul 07 05:26:38 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 215772 kb
Host smart-d58a8646-78c1-4593-ab1b-20846888fce8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=530187073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.s
pi_device_same_csr_outstanding.530187073
Directory /workspace/16.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_errors.3827233923
Short name T67
Test name
Test status
Simulation time 213852600 ps
CPU time 1.81 seconds
Started Jul 07 05:26:48 PM PDT 24
Finished Jul 07 05:26:50 PM PDT 24
Peak memory 215976 kb
Host smart-1fbdbd5d-75ba-4d1c-b248-83b93c0b6603
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3827233923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device_tl_errors.
3827233923
Directory /workspace/16.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.spi_device_tl_intg_err.298315809
Short name T184
Test name
Test status
Simulation time 2770065553 ps
CPU time 15.19 seconds
Started Jul 07 05:26:43 PM PDT 24
Finished Jul 07 05:26:59 PM PDT 24
Peak memory 215752 kb
Host smart-6bc9f5c3-e9df-4573-9b7f-3e5c7fa47927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298315809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.spi_device
_tl_intg_err.298315809
Directory /workspace/16.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_mem_rw_with_rand_reset.3516926062
Short name T1051
Test name
Test status
Simulation time 351590809 ps
CPU time 2.6 seconds
Started Jul 07 05:26:40 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 217000 kb
Host smart-8331901a-06ca-40b6-967c-40ec40919bdd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516926062 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_mem_rw_with_rand_reset.3516926062
Directory /workspace/17.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_csr_rw.3892012994
Short name T1077
Test name
Test status
Simulation time 793846238 ps
CPU time 1.41 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 215624 kb
Host smart-bc1f4def-d15e-4527-804b-0015a6faee8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892012994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_csr_rw.
3892012994
Directory /workspace/17.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_intr_test.3162452540
Short name T1039
Test name
Test status
Simulation time 26020152 ps
CPU time 0.72 seconds
Started Jul 07 05:26:38 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 204604 kb
Host smart-355727e9-05d0-4d19-85e0-6ab812cc2506
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162452540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_intr_test.
3162452540
Directory /workspace/17.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_same_csr_outstanding.3464197326
Short name T1126
Test name
Test status
Simulation time 409387953 ps
CPU time 2.89 seconds
Started Jul 07 05:26:49 PM PDT 24
Finished Jul 07 05:26:53 PM PDT 24
Peak memory 215724 kb
Host smart-4256fbc2-2d12-4753-aaec-de3c5aa83f77
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464197326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
spi_device_same_csr_outstanding.3464197326
Directory /workspace/17.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_errors.2120264231
Short name T1117
Test name
Test status
Simulation time 1404867667 ps
CPU time 4.72 seconds
Started Jul 07 05:26:40 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 215968 kb
Host smart-b97ec9ca-9b95-49d1-9aaa-c1c5b33415eb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120264231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_device_tl_errors.
2120264231
Directory /workspace/17.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.spi_device_tl_intg_err.3637233592
Short name T66
Test name
Test status
Simulation time 105364732 ps
CPU time 6.85 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 215700 kb
Host smart-f8116584-2406-4ce1-a96b-4db8d8918242
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637233592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.spi_devic
e_tl_intg_err.3637233592
Directory /workspace/17.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_mem_rw_with_rand_reset.1486670319
Short name T1092
Test name
Test status
Simulation time 1367228419 ps
CPU time 3.45 seconds
Started Jul 07 05:26:51 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 218552 kb
Host smart-debc59ad-bdcf-417d-8b05-5b422b125b84
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486670319 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_mem_rw_with_rand_reset.1486670319
Directory /workspace/18.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_csr_rw.2250772998
Short name T1106
Test name
Test status
Simulation time 358729469 ps
CPU time 2.4 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 215556 kb
Host smart-39d4ded7-8658-4c85-8510-ec0fa85d11a5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2250772998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_csr_rw.
2250772998
Directory /workspace/18.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_intr_test.3427653275
Short name T1085
Test name
Test status
Simulation time 200516300 ps
CPU time 0.7 seconds
Started Jul 07 05:26:43 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 204852 kb
Host smart-282e9cb4-09d1-4a6d-9bf1-cb9c24a7b9f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427653275 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_intr_test.
3427653275
Directory /workspace/18.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_same_csr_outstanding.50700657
Short name T141
Test name
Test status
Simulation time 158460476 ps
CPU time 2.68 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 215704 kb
Host smart-15146080-67ec-4781-a65e-973183e1042e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50700657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sp
i_device_same_csr_outstanding.50700657
Directory /workspace/18.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_errors.1833920228
Short name T105
Test name
Test status
Simulation time 127523763 ps
CPU time 2.11 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 215992 kb
Host smart-358a755c-612e-47ec-909a-3fbd499969d4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833920228 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device_tl_errors.
1833920228
Directory /workspace/18.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.spi_device_tl_intg_err.821600239
Short name T1094
Test name
Test status
Simulation time 303120012 ps
CPU time 8.18 seconds
Started Jul 07 05:26:42 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 216056 kb
Host smart-e18c5802-1b1f-404b-bbfe-b92e40617769
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=821600239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.spi_device
_tl_intg_err.821600239
Directory /workspace/18.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_mem_rw_with_rand_reset.4154041186
Short name T1064
Test name
Test status
Simulation time 109831106 ps
CPU time 2.96 seconds
Started Jul 07 05:26:39 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 218396 kb
Host smart-32ce97ce-ec62-4fdd-9239-7a98d743494c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154041186 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_mem_rw_with_rand_reset.4154041186
Directory /workspace/19.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_csr_rw.1449801383
Short name T1127
Test name
Test status
Simulation time 71241045 ps
CPU time 1.39 seconds
Started Jul 07 05:26:40 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 215616 kb
Host smart-e94e4143-d660-4bcb-a947-904e9c43cd7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449801383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_csr_rw.
1449801383
Directory /workspace/19.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_intr_test.4035350742
Short name T1010
Test name
Test status
Simulation time 13184512 ps
CPU time 0.79 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 203952 kb
Host smart-c3b611e8-47f2-4b45-8add-4b1f9deda9f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035350742 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_intr_test.
4035350742
Directory /workspace/19.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_same_csr_outstanding.3493310953
Short name T1113
Test name
Test status
Simulation time 297736296 ps
CPU time 2.95 seconds
Started Jul 07 05:26:40 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 215652 kb
Host smart-701128dc-6be1-4df5-8f2f-6ae09163048c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493310953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.
spi_device_same_csr_outstanding.3493310953
Directory /workspace/19.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_errors.3522805752
Short name T1059
Test name
Test status
Simulation time 95124802 ps
CPU time 2.67 seconds
Started Jul 07 05:26:47 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 215960 kb
Host smart-50691e68-dc89-4bd9-86dc-390d9ad2d698
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522805752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_device_tl_errors.
3522805752
Directory /workspace/19.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.spi_device_tl_intg_err.4119439216
Short name T107
Test name
Test status
Simulation time 866953090 ps
CPU time 23.08 seconds
Started Jul 07 05:26:47 PM PDT 24
Finished Jul 07 05:27:10 PM PDT 24
Peak memory 215724 kb
Host smart-96dcdc41-a214-4d48-bfec-64ad6544b7ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4119439216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.spi_devic
e_tl_intg_err.4119439216
Directory /workspace/19.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_aliasing.2764889401
Short name T1073
Test name
Test status
Simulation time 4325948735 ps
CPU time 15.51 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:53 PM PDT 24
Peak memory 215680 kb
Host smart-64885f07-7d9a-4da9-a782-5fde81231450
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764889401 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_aliasing.2764889401
Directory /workspace/2.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_bit_bash.965569587
Short name T1100
Test name
Test status
Simulation time 1207378247 ps
CPU time 22.51 seconds
Started Jul 07 05:26:32 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 207428 kb
Host smart-d09073fe-1f61-4c65-bb63-e4470c184783
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965569587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr
_bit_bash.965569587
Directory /workspace/2.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_hw_reset.1141631210
Short name T84
Test name
Test status
Simulation time 32018530 ps
CPU time 1.19 seconds
Started Jul 07 05:26:30 PM PDT 24
Finished Jul 07 05:26:31 PM PDT 24
Peak memory 207324 kb
Host smart-e06b08a2-5be5-41d5-9151-e87dd6ff7b9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1141631210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_cs
r_hw_reset.1141631210
Directory /workspace/2.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_mem_rw_with_rand_reset.2489943832
Short name T1105
Test name
Test status
Simulation time 420715468 ps
CPU time 2.75 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:37 PM PDT 24
Peak memory 217308 kb
Host smart-c237e88c-96e4-4363-bd90-d89fe37b6142
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489943832 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_mem_rw_with_rand_reset.2489943832
Directory /workspace/2.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_csr_rw.187667119
Short name T1023
Test name
Test status
Simulation time 39325992 ps
CPU time 1.35 seconds
Started Jul 07 05:26:49 PM PDT 24
Finished Jul 07 05:26:51 PM PDT 24
Peak memory 207504 kb
Host smart-4f1560cd-b626-4c4b-9eaf-7f4832b76715
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=187667119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_csr_rw.187667119
Directory /workspace/2.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_intr_test.1377778218
Short name T1019
Test name
Test status
Simulation time 41910037 ps
CPU time 0.77 seconds
Started Jul 07 05:26:21 PM PDT 24
Finished Jul 07 05:26:22 PM PDT 24
Peak memory 204604 kb
Host smart-6d54186a-13bd-46dd-b496-10bd9bf2804b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377778218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_intr_test.1
377778218
Directory /workspace/2.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_partial_access.4170404743
Short name T115
Test name
Test status
Simulation time 36872512 ps
CPU time 1.35 seconds
Started Jul 07 05:26:30 PM PDT 24
Finished Jul 07 05:26:32 PM PDT 24
Peak memory 215772 kb
Host smart-9ad89e90-5d01-44d5-a0cc-81e250f3b645
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4170404743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi
_device_mem_partial_access.4170404743
Directory /workspace/2.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_mem_walk.2951358630
Short name T1093
Test name
Test status
Simulation time 37748956 ps
CPU time 0.68 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 203992 kb
Host smart-60c9d36b-307d-41c6-bbe5-70f748052f9a
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2951358630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_me
m_walk.2951358630
Directory /workspace/2.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_same_csr_outstanding.1453296490
Short name T1086
Test name
Test status
Simulation time 585262168 ps
CPU time 3.71 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 215712 kb
Host smart-6a4847f4-1208-458b-b61f-16ef60406494
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453296490 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.s
pi_device_same_csr_outstanding.1453296490
Directory /workspace/2.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_errors.1178695075
Short name T1072
Test name
Test status
Simulation time 519552650 ps
CPU time 4.77 seconds
Started Jul 07 05:26:30 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 216008 kb
Host smart-8278e39c-d33f-400a-b217-380266ff93a7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178695075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device_tl_errors.1
178695075
Directory /workspace/2.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.spi_device_tl_intg_err.3179502916
Short name T1102
Test name
Test status
Simulation time 1587764524 ps
CPU time 19.97 seconds
Started Jul 07 05:26:27 PM PDT 24
Finished Jul 07 05:26:48 PM PDT 24
Peak memory 215792 kb
Host smart-ebd8c108-0e8e-48f4-b93d-7bff71df8894
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3179502916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.spi_device
_tl_intg_err.3179502916
Directory /workspace/2.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.spi_device_intr_test.3424754713
Short name T1060
Test name
Test status
Simulation time 61809615 ps
CPU time 0.78 seconds
Started Jul 07 05:26:40 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 204204 kb
Host smart-4a302aa7-f22c-4427-9745-67c9a7b89710
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424754713 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.spi_device_intr_test.
3424754713
Directory /workspace/20.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.spi_device_intr_test.3189089589
Short name T1088
Test name
Test status
Simulation time 20275973 ps
CPU time 0.8 seconds
Started Jul 07 05:26:40 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 204256 kb
Host smart-0389b51c-5a76-4543-8e47-10fa533a4800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189089589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.spi_device_intr_test.
3189089589
Directory /workspace/21.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.spi_device_intr_test.304853088
Short name T1125
Test name
Test status
Simulation time 12690689 ps
CPU time 0.79 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 204204 kb
Host smart-e18dea4b-8c70-4204-9d8a-6bdf3d1626b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304853088 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.spi_device_intr_test.304853088
Directory /workspace/22.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.spi_device_intr_test.2624759157
Short name T1099
Test name
Test status
Simulation time 11366736 ps
CPU time 0.69 seconds
Started Jul 07 05:26:52 PM PDT 24
Finished Jul 07 05:26:54 PM PDT 24
Peak memory 204268 kb
Host smart-1f4f8017-2683-4a3e-8430-edbbecf58259
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624759157 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.spi_device_intr_test.
2624759157
Directory /workspace/23.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.spi_device_intr_test.1909966309
Short name T1115
Test name
Test status
Simulation time 54187472 ps
CPU time 0.76 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 204292 kb
Host smart-6365edb7-ae61-4296-af43-9e9b2f5df7f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1909966309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.spi_device_intr_test.
1909966309
Directory /workspace/24.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.spi_device_intr_test.3371280148
Short name T1101
Test name
Test status
Simulation time 30206682 ps
CPU time 0.73 seconds
Started Jul 07 05:26:42 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 204200 kb
Host smart-7beaeaf5-0ab4-4d4e-b678-cc294d7451cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371280148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.spi_device_intr_test.
3371280148
Directory /workspace/25.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.spi_device_intr_test.3739834305
Short name T1124
Test name
Test status
Simulation time 11554434 ps
CPU time 0.8 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 204288 kb
Host smart-d05b9046-9425-4b05-b330-d2c4d1d37c62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739834305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.spi_device_intr_test.
3739834305
Directory /workspace/26.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.spi_device_intr_test.3189801422
Short name T1024
Test name
Test status
Simulation time 13760005 ps
CPU time 0.73 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:55 PM PDT 24
Peak memory 204308 kb
Host smart-1c6365ad-a0f6-4961-8060-608ad0a34c16
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3189801422 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.spi_device_intr_test.
3189801422
Directory /workspace/27.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.spi_device_intr_test.1163880329
Short name T1036
Test name
Test status
Simulation time 25497093 ps
CPU time 0.69 seconds
Started Jul 07 05:26:43 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 204272 kb
Host smart-12c1ca76-9964-49d7-b8d7-dbd67c250f93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163880329 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.spi_device_intr_test.
1163880329
Directory /workspace/28.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.spi_device_intr_test.1786608090
Short name T1028
Test name
Test status
Simulation time 13318376 ps
CPU time 0.7 seconds
Started Jul 07 05:26:46 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 204224 kb
Host smart-2a9ce1ff-ea66-4d89-8d38-ae979eda24e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786608090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.spi_device_intr_test.
1786608090
Directory /workspace/29.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_aliasing.3059982594
Short name T1032
Test name
Test status
Simulation time 216371937 ps
CPU time 7.08 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 207348 kb
Host smart-dd421f4a-69d5-4eae-9d7c-a794b85c3969
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059982594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_aliasing.3059982594
Directory /workspace/3.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_bit_bash.1910813954
Short name T149
Test name
Test status
Simulation time 7508446212 ps
CPU time 26.35 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:27:03 PM PDT 24
Peak memory 207560 kb
Host smart-e3522100-8e44-4c84-a4ae-ef293868aa7b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910813954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_cs
r_bit_bash.1910813954
Directory /workspace/3.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_mem_rw_with_rand_reset.2419284849
Short name T1109
Test name
Test status
Simulation time 103525569 ps
CPU time 2.7 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 215784 kb
Host smart-f1ce3f81-bbd3-48e2-bfbc-224a9b73888c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2419284849 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_mem_rw_with_rand_reset.2419284849
Directory /workspace/3.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_csr_rw.3940230728
Short name T1018
Test name
Test status
Simulation time 37635164 ps
CPU time 1.44 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 215624 kb
Host smart-239e7349-7d1d-4605-a99b-733af8f6b5d5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940230728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_csr_rw.3
940230728
Directory /workspace/3.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_intr_test.1012455457
Short name T1119
Test name
Test status
Simulation time 13680039 ps
CPU time 0.75 seconds
Started Jul 07 05:26:30 PM PDT 24
Finished Jul 07 05:26:31 PM PDT 24
Peak memory 204536 kb
Host smart-16b6f6a7-12da-4b6e-ac79-2a298b860054
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1012455457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_intr_test.1
012455457
Directory /workspace/3.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_partial_access.1382365554
Short name T123
Test name
Test status
Simulation time 60577298 ps
CPU time 2.7 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 215700 kb
Host smart-77dc9b13-6844-48ce-b1a7-ad57132de505
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1382365554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi
_device_mem_partial_access.1382365554
Directory /workspace/3.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_mem_walk.3720616858
Short name T1048
Test name
Test status
Simulation time 20920263 ps
CPU time 0.68 seconds
Started Jul 07 05:26:28 PM PDT 24
Finished Jul 07 05:26:29 PM PDT 24
Peak memory 204336 kb
Host smart-ef428ec3-1367-4fc1-9142-ebf9a59eecbc
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3720616858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_me
m_walk.3720616858
Directory /workspace/3.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_same_csr_outstanding.873715301
Short name T1050
Test name
Test status
Simulation time 555332778 ps
CPU time 3.94 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 215716 kb
Host smart-fcb2933f-c885-4bd0-b14e-83f24ee5f95b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873715301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sp
i_device_same_csr_outstanding.873715301
Directory /workspace/3.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_errors.2358842904
Short name T103
Test name
Test status
Simulation time 170917015 ps
CPU time 1.81 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 215856 kb
Host smart-4d656f03-00b5-4060-9d06-b32edb775d23
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2358842904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_tl_errors.2
358842904
Directory /workspace/3.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.spi_device_tl_intg_err.142212510
Short name T182
Test name
Test status
Simulation time 122736509 ps
CPU time 6.74 seconds
Started Jul 07 05:26:39 PM PDT 24
Finished Jul 07 05:26:48 PM PDT 24
Peak memory 215616 kb
Host smart-5b241fb1-82d3-454b-b729-e86b6a6240bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=142212510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.spi_device_
tl_intg_err.142212510
Directory /workspace/3.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.spi_device_intr_test.1441704831
Short name T1118
Test name
Test status
Simulation time 26404354 ps
CPU time 0.72 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:56 PM PDT 24
Peak memory 204268 kb
Host smart-e149d6bd-1d79-4bff-b62b-77dc247bd9b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1441704831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.spi_device_intr_test.
1441704831
Directory /workspace/30.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.spi_device_intr_test.3234487702
Short name T1021
Test name
Test status
Simulation time 55388861 ps
CPU time 0.71 seconds
Started Jul 07 05:26:48 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 204288 kb
Host smart-a081fdb2-b2eb-45a4-9b40-78092350edb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234487702 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.spi_device_intr_test.
3234487702
Directory /workspace/31.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.spi_device_intr_test.2964793970
Short name T1014
Test name
Test status
Simulation time 13261171 ps
CPU time 0.76 seconds
Started Jul 07 05:26:56 PM PDT 24
Finished Jul 07 05:26:57 PM PDT 24
Peak memory 204296 kb
Host smart-e4cd77d3-8dc9-4e2a-9cb3-c9443d200a60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964793970 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.spi_device_intr_test.
2964793970
Directory /workspace/32.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.spi_device_intr_test.7502072
Short name T1044
Test name
Test status
Simulation time 63079167 ps
CPU time 0.74 seconds
Started Jul 07 05:26:45 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 204612 kb
Host smart-bca65c0b-0218-4b15-aa53-90eef84fb910
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=7502072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.spi_device_intr_test.7502072
Directory /workspace/33.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.spi_device_intr_test.328494570
Short name T1078
Test name
Test status
Simulation time 10738411 ps
CPU time 0.78 seconds
Started Jul 07 05:26:55 PM PDT 24
Finished Jul 07 05:27:01 PM PDT 24
Peak memory 204260 kb
Host smart-97d706e0-b594-44e1-9bf9-ac7ebd37efc4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328494570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.spi_device_intr_test.328494570
Directory /workspace/34.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.spi_device_intr_test.1398450210
Short name T1033
Test name
Test status
Simulation time 23819774 ps
CPU time 0.73 seconds
Started Jul 07 05:26:47 PM PDT 24
Finished Jul 07 05:26:49 PM PDT 24
Peak memory 204612 kb
Host smart-16640f13-88f6-4070-b116-2b60a822797b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1398450210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.spi_device_intr_test.
1398450210
Directory /workspace/35.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.spi_device_intr_test.1932624212
Short name T1103
Test name
Test status
Simulation time 16505223 ps
CPU time 0.76 seconds
Started Jul 07 05:26:44 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 204272 kb
Host smart-b81370a2-7814-4c3c-b86d-50e5cfc4670c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1932624212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.spi_device_intr_test.
1932624212
Directory /workspace/36.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.spi_device_intr_test.4278250304
Short name T1015
Test name
Test status
Simulation time 14075846 ps
CPU time 0.79 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 204176 kb
Host smart-fc79035a-4f03-4c71-bef7-fa05c9b1f292
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278250304 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.spi_device_intr_test.
4278250304
Directory /workspace/37.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.spi_device_intr_test.750337309
Short name T1056
Test name
Test status
Simulation time 16905577 ps
CPU time 0.76 seconds
Started Jul 07 05:26:56 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 204292 kb
Host smart-1a1504d0-45db-47f7-974f-d2e1f9586f09
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750337309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.spi_device_intr_test.750337309
Directory /workspace/38.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.spi_device_intr_test.3845077895
Short name T1107
Test name
Test status
Simulation time 27152251 ps
CPU time 0.77 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 204292 kb
Host smart-58cc0412-9970-493f-b0b0-ff434019067f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845077895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.spi_device_intr_test.
3845077895
Directory /workspace/39.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_aliasing.1830504524
Short name T1082
Test name
Test status
Simulation time 432593192 ps
CPU time 7.89 seconds
Started Jul 07 05:26:31 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 207404 kb
Host smart-ae4dd937-8426-458e-8cbc-5358c2956b5f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830504524 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_aliasing.1830504524
Directory /workspace/4.spi_device_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_bit_bash.3985904436
Short name T121
Test name
Test status
Simulation time 1065328507 ps
CPU time 32.1 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:27:07 PM PDT 24
Peak memory 215636 kb
Host smart-4e056dd1-e08b-4207-8aca-8c0fe0a65345
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985904436 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_cs
r_bit_bash.3985904436
Directory /workspace/4.spi_device_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_hw_reset.117624662
Short name T87
Test name
Test status
Simulation time 24469052 ps
CPU time 0.93 seconds
Started Jul 07 05:26:38 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 207236 kb
Host smart-c68bf913-4459-43d4-a0c5-95ee8d090991
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117624662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr
_hw_reset.117624662
Directory /workspace/4.spi_device_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_mem_rw_with_rand_reset.2441363974
Short name T153
Test name
Test status
Simulation time 108626223 ps
CPU time 2.93 seconds
Started Jul 07 05:26:32 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 217520 kb
Host smart-2f8d150b-1a90-45d7-be45-4757108ddc1a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2441363974 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_mem_rw_with_rand_reset.2441363974
Directory /workspace/4.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_csr_rw.2969736825
Short name T120
Test name
Test status
Simulation time 385795336 ps
CPU time 2.81 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 215692 kb
Host smart-4e1f715a-4804-462d-8fa7-ddb54065d7ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2969736825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_csr_rw.2
969736825
Directory /workspace/4.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_intr_test.2816602491
Short name T1042
Test name
Test status
Simulation time 16650010 ps
CPU time 0.75 seconds
Started Jul 07 05:26:32 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 204264 kb
Host smart-aa226e11-0e6b-4aa0-ae01-0edeca2935ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816602491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_intr_test.2
816602491
Directory /workspace/4.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_partial_access.2454283415
Short name T119
Test name
Test status
Simulation time 128101589 ps
CPU time 1.23 seconds
Started Jul 07 05:26:32 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 215668 kb
Host smart-e333cd58-e3fb-4490-b52d-7a6132b828aa
User root
Command /workspace/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2454283415 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=s
pi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi
_device_mem_partial_access.2454283415
Directory /workspace/4.spi_device_mem_partial_access/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_mem_walk.3269993491
Short name T1057
Test name
Test status
Simulation time 41362812 ps
CPU time 0.69 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 203992 kb
Host smart-869ee5e4-3585-42aa-a402-41a1db527503
User root
Command /workspace/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269993491 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_me
m_walk.3269993491
Directory /workspace/4.spi_device_mem_walk/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_same_csr_outstanding.2661397537
Short name T1110
Test name
Test status
Simulation time 561070848 ps
CPU time 3.84 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 215664 kb
Host smart-4e2a55f4-ca10-4bac-b7c5-5ea4f9e4174c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2661397537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.s
pi_device_same_csr_outstanding.2661397537
Directory /workspace/4.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_errors.4207264954
Short name T106
Test name
Test status
Simulation time 34158611 ps
CPU time 2.36 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 215976 kb
Host smart-d413191e-9153-49d6-9127-89adf3d9d290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207264954 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device_tl_errors.4
207264954
Directory /workspace/4.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.spi_device_tl_intg_err.4066793781
Short name T1046
Test name
Test status
Simulation time 1047656607 ps
CPU time 7.29 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 216420 kb
Host smart-d556e747-9f89-4943-a97d-70dad33ddad8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066793781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devi
ce_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.spi_device
_tl_intg_err.4066793781
Directory /workspace/4.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.spi_device_intr_test.2513578128
Short name T1031
Test name
Test status
Simulation time 56764634 ps
CPU time 0.84 seconds
Started Jul 07 05:26:46 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 204224 kb
Host smart-246d2aa5-6ee7-4428-bee4-cadf42f8a12e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513578128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.spi_device_intr_test.
2513578128
Directory /workspace/40.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.spi_device_intr_test.3869950456
Short name T1017
Test name
Test status
Simulation time 18323539 ps
CPU time 0.77 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:54 PM PDT 24
Peak memory 204272 kb
Host smart-fafc0f87-ea41-4315-9d96-096bc627eed3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869950456 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.spi_device_intr_test.
3869950456
Directory /workspace/41.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.spi_device_intr_test.1548325840
Short name T1097
Test name
Test status
Simulation time 18000039 ps
CPU time 0.8 seconds
Started Jul 07 05:26:45 PM PDT 24
Finished Jul 07 05:26:47 PM PDT 24
Peak memory 204296 kb
Host smart-d3474599-d594-4563-8a0d-348fdd97b9dc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548325840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.spi_device_intr_test.
1548325840
Directory /workspace/42.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.spi_device_intr_test.1019411472
Short name T1104
Test name
Test status
Simulation time 24956958 ps
CPU time 0.74 seconds
Started Jul 07 05:26:46 PM PDT 24
Finished Jul 07 05:26:52 PM PDT 24
Peak memory 204540 kb
Host smart-847f1255-9bdf-4ec0-b0dd-a20f8134041f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019411472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.spi_device_intr_test.
1019411472
Directory /workspace/43.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.spi_device_intr_test.3582394751
Short name T1029
Test name
Test status
Simulation time 28369479 ps
CPU time 0.76 seconds
Started Jul 07 05:26:45 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 204168 kb
Host smart-3f3bf391-6b31-4078-a982-643d6965f64c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3582394751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.spi_device_intr_test.
3582394751
Directory /workspace/44.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.spi_device_intr_test.2732957986
Short name T1040
Test name
Test status
Simulation time 23218193 ps
CPU time 0.74 seconds
Started Jul 07 05:26:47 PM PDT 24
Finished Jul 07 05:26:48 PM PDT 24
Peak memory 204272 kb
Host smart-12a025e2-38af-45aa-9b37-98bbf2f3ff64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732957986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.spi_device_intr_test.
2732957986
Directory /workspace/45.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.spi_device_intr_test.2412348672
Short name T1114
Test name
Test status
Simulation time 34388120 ps
CPU time 0.73 seconds
Started Jul 07 05:26:44 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 204196 kb
Host smart-ead244cb-5f56-401d-b9e2-a582228a25b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412348672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.spi_device_intr_test.
2412348672
Directory /workspace/46.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.spi_device_intr_test.4020820137
Short name T1011
Test name
Test status
Simulation time 144064941 ps
CPU time 0.71 seconds
Started Jul 07 05:26:53 PM PDT 24
Finished Jul 07 05:26:54 PM PDT 24
Peak memory 204568 kb
Host smart-8ca96ad9-f08b-4c43-9b14-de396feb3f60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020820137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.spi_device_intr_test.
4020820137
Directory /workspace/47.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.spi_device_intr_test.801217647
Short name T1122
Test name
Test status
Simulation time 46007250 ps
CPU time 0.7 seconds
Started Jul 07 05:26:42 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 204604 kb
Host smart-7bdb4d3d-6875-43d8-b6e3-b925fdd0541b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801217647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.spi_device_intr_test.801217647
Directory /workspace/48.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.spi_device_intr_test.3933014728
Short name T1096
Test name
Test status
Simulation time 34144792 ps
CPU time 0.76 seconds
Started Jul 07 05:27:01 PM PDT 24
Finished Jul 07 05:27:02 PM PDT 24
Peak memory 204288 kb
Host smart-e1912b89-5fd8-4085-b37d-c20578660658
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933014728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.spi_device_intr_test.
3933014728
Directory /workspace/49.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_mem_rw_with_rand_reset.4123124552
Short name T1080
Test name
Test status
Simulation time 248377840 ps
CPU time 3.42 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 218460 kb
Host smart-66533591-5d19-4a2a-bc14-0e59417be469
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123124552 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_mem_rw_with_rand_reset.4123124552
Directory /workspace/5.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_csr_rw.981298740
Short name T1070
Test name
Test status
Simulation time 195580604 ps
CPU time 1.27 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 207440 kb
Host smart-ab763861-092e-4691-8410-9373dabc1a52
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981298740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_csr_rw.981298740
Directory /workspace/5.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_intr_test.670654947
Short name T1052
Test name
Test status
Simulation time 62823604 ps
CPU time 0.8 seconds
Started Jul 07 05:26:32 PM PDT 24
Finished Jul 07 05:26:34 PM PDT 24
Peak memory 204224 kb
Host smart-91e41649-3a1f-4433-b24b-a6c46b6319b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=670654947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_intr_test.670654947
Directory /workspace/5.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_same_csr_outstanding.2986607059
Short name T1075
Test name
Test status
Simulation time 576088253 ps
CPU time 3.96 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:43 PM PDT 24
Peak memory 215712 kb
Host smart-ca7bbf99-75c0-44f8-a6d2-8c567293147d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986607059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.s
pi_device_same_csr_outstanding.2986607059
Directory /workspace/5.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.spi_device_tl_errors.382930124
Short name T102
Test name
Test status
Simulation time 398331622 ps
CPU time 3.91 seconds
Started Jul 07 05:26:32 PM PDT 24
Finished Jul 07 05:26:37 PM PDT 24
Peak memory 215964 kb
Host smart-b6c1f191-e9d0-4e22-aee9-3aeb8ac612ad
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=382930124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.spi_device_tl_errors.382930124
Directory /workspace/5.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_mem_rw_with_rand_reset.150465658
Short name T1022
Test name
Test status
Simulation time 218379525 ps
CPU time 4.07 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 217984 kb
Host smart-d684a6a7-872b-4a54-ae23-99ef0cc24a5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150465658 -assert nopostproc +UVM_TESTNAME=
spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.
vdb -cm_log /dev/null -cm_name 6.spi_device_csr_mem_rw_with_rand_reset.150465658
Directory /workspace/6.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_csr_rw.4189876836
Short name T1055
Test name
Test status
Simulation time 33662982 ps
CPU time 2.06 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 215732 kb
Host smart-363e1954-fbb4-405f-a003-7f82dc24e1da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189876836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_csr_rw.4
189876836
Directory /workspace/6.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_intr_test.861253535
Short name T1038
Test name
Test status
Simulation time 16372043 ps
CPU time 0.73 seconds
Started Jul 07 05:26:36 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 204520 kb
Host smart-2623b514-178c-4a6c-b1b5-7be89ac0677c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861253535 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_intr_test.861253535
Directory /workspace/6.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_same_csr_outstanding.1413309193
Short name T1067
Test name
Test status
Simulation time 25924232 ps
CPU time 1.73 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 215764 kb
Host smart-0ae6006d-ee3e-48cb-998b-9d94d1186c4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413309193 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.s
pi_device_same_csr_outstanding.1413309193
Directory /workspace/6.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.spi_device_tl_errors.2194591839
Short name T1041
Test name
Test status
Simulation time 39826013 ps
CPU time 1.46 seconds
Started Jul 07 05:26:33 PM PDT 24
Finished Jul 07 05:26:36 PM PDT 24
Peak memory 215976 kb
Host smart-7ad22722-e0af-42a6-b9fe-ac94382606e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194591839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.spi_device_tl_errors.2
194591839
Directory /workspace/6.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_mem_rw_with_rand_reset.4036589979
Short name T1087
Test name
Test status
Simulation time 213999314 ps
CPU time 2.89 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:45 PM PDT 24
Peak memory 217160 kb
Host smart-7017b11b-7552-4193-ac7f-652a89b741da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036589979 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_mem_rw_with_rand_reset.4036589979
Directory /workspace/7.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_csr_rw.4247886262
Short name T1098
Test name
Test status
Simulation time 144688338 ps
CPU time 1.31 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 207504 kb
Host smart-c5436a53-5935-4c62-ac5a-5da236f40650
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247886262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_csr_rw.4
247886262
Directory /workspace/7.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_intr_test.4006637568
Short name T1074
Test name
Test status
Simulation time 13241027 ps
CPU time 0.84 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:40 PM PDT 24
Peak memory 204576 kb
Host smart-938ac666-695d-413d-86ba-e74cc5673570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006637568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_intr_test.4
006637568
Directory /workspace/7.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_same_csr_outstanding.1818962588
Short name T1066
Test name
Test status
Simulation time 701725667 ps
CPU time 1.88 seconds
Started Jul 07 05:26:30 PM PDT 24
Finished Jul 07 05:26:32 PM PDT 24
Peak memory 215716 kb
Host smart-96ff31ea-b06d-40b0-af54-2b3a57ebf368
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818962588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.s
pi_device_same_csr_outstanding.1818962588
Directory /workspace/7.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_errors.276337603
Short name T101
Test name
Test status
Simulation time 98915914 ps
CPU time 3.03 seconds
Started Jul 07 05:26:28 PM PDT 24
Finished Jul 07 05:26:32 PM PDT 24
Peak memory 215904 kb
Host smart-b01ef6c7-c5f3-4524-a4be-5ab4935d021c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=276337603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_tl_errors.276337603
Directory /workspace/7.spi_device_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.spi_device_tl_intg_err.216298189
Short name T110
Test name
Test status
Simulation time 434812365 ps
CPU time 6.91 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 215724 kb
Host smart-2c2d1dcd-b226-4d94-86fa-5c9e119163d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216298189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.spi_device_
tl_intg_err.216298189
Directory /workspace/7.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_mem_rw_with_rand_reset.2819550052
Short name T1043
Test name
Test status
Simulation time 170107994 ps
CPU time 2.52 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 217040 kb
Host smart-99d8ed2a-84e3-40a8-86f9-735eb6506ef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819550052 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_mem_rw_with_rand_reset.2819550052
Directory /workspace/8.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_csr_rw.3317381216
Short name T117
Test name
Test status
Simulation time 22357088 ps
CPU time 1.28 seconds
Started Jul 07 05:26:35 PM PDT 24
Finished Jul 07 05:26:39 PM PDT 24
Peak memory 207364 kb
Host smart-268005c1-7753-4f93-8fc0-537399e80879
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317381216 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_csr_rw.3
317381216
Directory /workspace/8.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_intr_test.3824994870
Short name T1112
Test name
Test status
Simulation time 32880566 ps
CPU time 0.71 seconds
Started Jul 07 05:26:38 PM PDT 24
Finished Jul 07 05:26:41 PM PDT 24
Peak memory 204260 kb
Host smart-fa49446d-1cc2-452b-b103-b51586f0c2e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824994870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_intr_test.3
824994870
Directory /workspace/8.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_same_csr_outstanding.216775669
Short name T1016
Test name
Test status
Simulation time 172930905 ps
CPU time 3.01 seconds
Started Jul 07 05:26:54 PM PDT 24
Finished Jul 07 05:26:58 PM PDT 24
Peak memory 215664 kb
Host smart-d217951d-8e61-44ad-8a8a-3282fd03672d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216775669 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=
spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sp
i_device_same_csr_outstanding.216775669
Directory /workspace/8.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.spi_device_tl_intg_err.139648312
Short name T183
Test name
Test status
Simulation time 1512184845 ps
CPU time 7.58 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:44 PM PDT 24
Peak memory 215632 kb
Host smart-4b1ee7ea-3ba7-45a9-b4ae-de36a43a62c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139648312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.spi_device_
tl_intg_err.139648312
Directory /workspace/8.spi_device_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_mem_rw_with_rand_reset.1873036038
Short name T150
Test name
Test status
Simulation time 264095971 ps
CPU time 3.12 seconds
Started Jul 07 05:26:41 PM PDT 24
Finished Jul 07 05:26:46 PM PDT 24
Peak memory 217476 kb
Host smart-6a285c41-16d7-4bab-9ab3-6c3d9745e374
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873036038 -assert nopostproc +UVM_TESTNAME
=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top
.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_mem_rw_with_rand_reset.1873036038
Directory /workspace/9.spi_device_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_csr_rw.2832356406
Short name T122
Test name
Test status
Simulation time 102846929 ps
CPU time 2.59 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:38 PM PDT 24
Peak memory 215772 kb
Host smart-52157899-83fd-4970-a963-cb314597b6db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2832356406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_csr_rw.2
832356406
Directory /workspace/9.spi_device_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_intr_test.229957182
Short name T1089
Test name
Test status
Simulation time 45239464 ps
CPU time 0.74 seconds
Started Jul 07 05:26:39 PM PDT 24
Finished Jul 07 05:26:42 PM PDT 24
Peak memory 204184 kb
Host smart-4b1903c9-bdd3-48fa-b348-f96e4a36dab0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229957182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_intr_test.229957182
Directory /workspace/9.spi_device_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_same_csr_outstanding.4181654146
Short name T1090
Test name
Test status
Simulation time 327248180 ps
CPU time 1.61 seconds
Started Jul 07 05:26:34 PM PDT 24
Finished Jul 07 05:26:37 PM PDT 24
Peak memory 216412 kb
Host smart-eec7c2bf-13c7-4d20-8f28-616fab4b088f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4181654146 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ
=spi_device_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.s
pi_device_same_csr_outstanding.4181654146
Directory /workspace/9.spi_device_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.spi_device_tl_intg_err.846652625
Short name T180
Test name
Test status
Simulation time 791080821 ps
CPU time 21.88 seconds
Started Jul 07 05:26:37 PM PDT 24
Finished Jul 07 05:27:02 PM PDT 24
Peak memory 215708 kb
Host smart-93339e73-f56d-4448-90c2-bd645cee7908
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846652625 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_devic
e_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.spi_device_
tl_intg_err.846652625
Directory /workspace/9.spi_device_tl_intg_err/latest

Test location /workspace/coverage/default/0.spi_device_alert_test.2762588686
Short name T698
Test name
Test status
Simulation time 20459425 ps
CPU time 0.74 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:28:56 PM PDT 24
Peak memory 205504 kb
Host smart-65197a54-3fe7-4a1a-85c3-6391206c23f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2762588686 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_alert_test.2
762588686
Directory /workspace/0.spi_device_alert_test/latest

Test location /workspace/coverage/default/0.spi_device_cfg_cmd.4031569515
Short name T878
Test name
Test status
Simulation time 935808916 ps
CPU time 3.75 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:45 PM PDT 24
Peak memory 224428 kb
Host smart-9077d832-1d8d-4752-aaf7-88cd447ea5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4031569515 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_cfg_cmd.4031569515
Directory /workspace/0.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/0.spi_device_csb_read.942566280
Short name T967
Test name
Test status
Simulation time 13269389 ps
CPU time 0.75 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:37 PM PDT 24
Peak memory 205572 kb
Host smart-bfe63a5b-88b4-43e8-ac9d-7871a9b928f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942566280 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_csb_read.942566280
Directory /workspace/0.spi_device_csb_read/latest

Test location /workspace/coverage/default/0.spi_device_flash_all.2872722869
Short name T670
Test name
Test status
Simulation time 1755117935 ps
CPU time 25.68 seconds
Started Jul 07 05:28:45 PM PDT 24
Finished Jul 07 05:29:11 PM PDT 24
Peak memory 224472 kb
Host smart-f628a3e7-5dba-41b2-b5f4-45981dd71b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872722869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_all.2872722869
Directory /workspace/0.spi_device_flash_all/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm.58999226
Short name T221
Test name
Test status
Simulation time 17678486018 ps
CPU time 30.58 seconds
Started Jul 07 05:28:42 PM PDT 24
Finished Jul 07 05:29:14 PM PDT 24
Peak memory 240964 kb
Host smart-1635625a-5fbd-425d-a908-c2d3ae8b33e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58999226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm.58999226
Directory /workspace/0.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/0.spi_device_flash_and_tpm_min_idle.4060527208
Short name T327
Test name
Test status
Simulation time 54323973164 ps
CPU time 262.44 seconds
Started Jul 07 05:28:42 PM PDT 24
Finished Jul 07 05:33:06 PM PDT 24
Peak memory 255788 kb
Host smart-a1367ef1-7c9b-4ddf-869b-f316749f93a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060527208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_and_tpm_min_idle
.4060527208
Directory /workspace/0.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode.3717432091
Short name T954
Test name
Test status
Simulation time 1020975361 ps
CPU time 18.26 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:29:09 PM PDT 24
Peak memory 240856 kb
Host smart-6d9f70ce-8384-4d64-a70a-4e936050bbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717432091 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode.3717432091
Directory /workspace/0.spi_device_flash_mode/latest

Test location /workspace/coverage/default/0.spi_device_flash_mode_ignore_cmds.100942425
Short name T625
Test name
Test status
Simulation time 15930605487 ps
CPU time 51.6 seconds
Started Jul 07 05:28:40 PM PDT 24
Finished Jul 07 05:29:34 PM PDT 24
Peak memory 249180 kb
Host smart-b6f69f09-d9c0-4be4-ba9f-98ea5d5ebf1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=100942425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_flash_mode_ignore_cmds.
100942425
Directory /workspace/0.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/0.spi_device_intercept.3109906052
Short name T444
Test name
Test status
Simulation time 1159649608 ps
CPU time 13.88 seconds
Started Jul 07 05:28:43 PM PDT 24
Finished Jul 07 05:28:58 PM PDT 24
Peak memory 232624 kb
Host smart-8c04fe39-ed16-401c-be64-6426c7c1058e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109906052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_intercept.3109906052
Directory /workspace/0.spi_device_intercept/latest

Test location /workspace/coverage/default/0.spi_device_mailbox.1115918040
Short name T836
Test name
Test status
Simulation time 1238999175 ps
CPU time 17.41 seconds
Started Jul 07 05:28:42 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 238580 kb
Host smart-dc78e2b8-5f98-42c2-bf05-b37e3fab2829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115918040 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_mailbox.1115918040
Directory /workspace/0.spi_device_mailbox/latest

Test location /workspace/coverage/default/0.spi_device_pass_addr_payload_swap.2189271383
Short name T274
Test name
Test status
Simulation time 68542869684 ps
CPU time 49.33 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:29:46 PM PDT 24
Peak memory 250196 kb
Host smart-db283199-8a7d-4d17-a179-894be3d540b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189271383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_addr_payload_swap
.2189271383
Directory /workspace/0.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/0.spi_device_pass_cmd_filtering.3164618433
Short name T485
Test name
Test status
Simulation time 26130406718 ps
CPU time 13.31 seconds
Started Jul 07 05:28:43 PM PDT 24
Finished Jul 07 05:28:57 PM PDT 24
Peak memory 224624 kb
Host smart-0d31c1d1-0479-44e6-907b-351cc9bc1c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164618433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_pass_cmd_filtering.3164618433
Directory /workspace/0.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/0.spi_device_read_buffer_direct.1402138367
Short name T399
Test name
Test status
Simulation time 239910793 ps
CPU time 3.37 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:45 PM PDT 24
Peak memory 221204 kb
Host smart-4cde8822-f2c8-474d-ac27-1445dfd109f5
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1402138367 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_read_buffer_dire
ct.1402138367
Directory /workspace/0.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/0.spi_device_sec_cm.4282395354
Short name T73
Test name
Test status
Simulation time 216808124 ps
CPU time 1.2 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 236016 kb
Host smart-dca7ee0e-cdf4-4cd0-910c-b01f180e857e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4282395354 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_sec_cm.4282395354
Directory /workspace/0.spi_device_sec_cm/latest

Test location /workspace/coverage/default/0.spi_device_stress_all.649917696
Short name T551
Test name
Test status
Simulation time 13842032897 ps
CPU time 47.07 seconds
Started Jul 07 05:28:42 PM PDT 24
Finished Jul 07 05:29:30 PM PDT 24
Peak memory 249224 kb
Host smart-eb81ab96-bae2-4039-b761-fc14b0bc67e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649917696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_stress
_all.649917696
Directory /workspace/0.spi_device_stress_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_all.2571008264
Short name T500
Test name
Test status
Simulation time 104165667 ps
CPU time 0.72 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:37 PM PDT 24
Peak memory 205700 kb
Host smart-0f3d63a7-6259-45ad-9f40-8893b23ea374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571008264 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_all.2571008264
Directory /workspace/0.spi_device_tpm_all/latest

Test location /workspace/coverage/default/0.spi_device_tpm_read_hw_reg.3795587431
Short name T453
Test name
Test status
Simulation time 2405632370 ps
CPU time 8.27 seconds
Started Jul 07 05:28:42 PM PDT 24
Finished Jul 07 05:28:52 PM PDT 24
Peak memory 216308 kb
Host smart-3387f1a9-1bc4-4155-adf6-5dd927065e11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795587431 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_read_hw_reg.3795587431
Directory /workspace/0.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/0.spi_device_tpm_rw.830747601
Short name T813
Test name
Test status
Simulation time 10999460 ps
CPU time 0.7 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:28:58 PM PDT 24
Peak memory 205916 kb
Host smart-12984df9-b97d-4673-9b53-e781e5d0b4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=830747601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_rw.830747601
Directory /workspace/0.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/0.spi_device_tpm_sts_read.3831671756
Short name T359
Test name
Test status
Simulation time 899020755 ps
CPU time 0.92 seconds
Started Jul 07 05:28:43 PM PDT 24
Finished Jul 07 05:28:45 PM PDT 24
Peak memory 205972 kb
Host smart-389dc4c8-1738-48dc-81d7-c8ead0f67d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831671756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_tpm_sts_read.3831671756
Directory /workspace/0.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/0.spi_device_upload.216851363
Short name T715
Test name
Test status
Simulation time 1163613091 ps
CPU time 5.45 seconds
Started Jul 07 05:28:40 PM PDT 24
Finished Jul 07 05:28:47 PM PDT 24
Peak memory 232568 kb
Host smart-35c31da3-a418-48c7-a5d3-7ac55edbea4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216851363 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.spi_device_upload.216851363
Directory /workspace/0.spi_device_upload/latest

Test location /workspace/coverage/default/1.spi_device_alert_test.1209427501
Short name T852
Test name
Test status
Simulation time 27202864 ps
CPU time 0.72 seconds
Started Jul 07 05:28:52 PM PDT 24
Finished Jul 07 05:28:53 PM PDT 24
Peak memory 205540 kb
Host smart-fa852e01-1a59-4925-9bc8-c6cd352449bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1209427501 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_alert_test.1
209427501
Directory /workspace/1.spi_device_alert_test/latest

Test location /workspace/coverage/default/1.spi_device_cfg_cmd.1483537370
Short name T262
Test name
Test status
Simulation time 754889229 ps
CPU time 5.81 seconds
Started Jul 07 05:28:48 PM PDT 24
Finished Jul 07 05:28:54 PM PDT 24
Peak memory 224488 kb
Host smart-7649b0a5-a641-4966-b674-8013403a89a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1483537370 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_cfg_cmd.1483537370
Directory /workspace/1.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/1.spi_device_csb_read.3772934980
Short name T363
Test name
Test status
Simulation time 16502596 ps
CPU time 0.78 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 205576 kb
Host smart-23c158c5-33e6-426d-8d7a-83486b085f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3772934980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_csb_read.3772934980
Directory /workspace/1.spi_device_csb_read/latest

Test location /workspace/coverage/default/1.spi_device_flash_and_tpm_min_idle.12740337
Short name T984
Test name
Test status
Simulation time 2500732712 ps
CPU time 62.68 seconds
Started Jul 07 05:28:54 PM PDT 24
Finished Jul 07 05:29:57 PM PDT 24
Peak memory 256688 kb
Host smart-0c3d16cf-5b91-42a5-b620-3919065c8a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12740337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_and_tpm_min_idle.12740337
Directory /workspace/1.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode.3850429400
Short name T77
Test name
Test status
Simulation time 4183483740 ps
CPU time 19.98 seconds
Started Jul 07 05:28:30 PM PDT 24
Finished Jul 07 05:28:50 PM PDT 24
Peak memory 224520 kb
Host smart-7b038ed7-09d0-4040-a13d-c992edc2f6d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850429400 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode.3850429400
Directory /workspace/1.spi_device_flash_mode/latest

Test location /workspace/coverage/default/1.spi_device_flash_mode_ignore_cmds.3156038810
Short name T920
Test name
Test status
Simulation time 4118972719 ps
CPU time 14.99 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:55 PM PDT 24
Peak memory 249632 kb
Host smart-b8695206-a3a8-478b-8c85-dc0a05738ce0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3156038810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_flash_mode_ignore_cmds
.3156038810
Directory /workspace/1.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/1.spi_device_intercept.205720556
Short name T280
Test name
Test status
Simulation time 2180126484 ps
CPU time 10.38 seconds
Started Jul 07 05:29:08 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 224544 kb
Host smart-e65c3118-2f45-4ec4-868c-783d4d215d5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205720556 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_intercept.205720556
Directory /workspace/1.spi_device_intercept/latest

Test location /workspace/coverage/default/1.spi_device_mailbox.3214653302
Short name T208
Test name
Test status
Simulation time 550465632 ps
CPU time 9.76 seconds
Started Jul 07 05:28:26 PM PDT 24
Finished Jul 07 05:28:37 PM PDT 24
Peak memory 224448 kb
Host smart-2728bd79-c938-48f1-8ed6-eee28c41e3b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214653302 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_mailbox.3214653302
Directory /workspace/1.spi_device_mailbox/latest

Test location /workspace/coverage/default/1.spi_device_pass_addr_payload_swap.471558223
Short name T271
Test name
Test status
Simulation time 38604831918 ps
CPU time 10.43 seconds
Started Jul 07 05:29:02 PM PDT 24
Finished Jul 07 05:29:14 PM PDT 24
Peak memory 232728 kb
Host smart-cea88f0f-17a8-44a7-87ad-5751dad72920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471558223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_addr_payload_swap.
471558223
Directory /workspace/1.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/1.spi_device_pass_cmd_filtering.4038136085
Short name T429
Test name
Test status
Simulation time 37805351 ps
CPU time 2.53 seconds
Started Jul 07 05:28:42 PM PDT 24
Finished Jul 07 05:28:45 PM PDT 24
Peak memory 232628 kb
Host smart-6be1a8dd-0c58-4ccf-b3a0-f395f5771995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038136085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_pass_cmd_filtering.4038136085
Directory /workspace/1.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/1.spi_device_read_buffer_direct.365655098
Short name T395
Test name
Test status
Simulation time 388777700 ps
CPU time 6.39 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:44 PM PDT 24
Peak memory 222972 kb
Host smart-e170facc-ce8d-40e3-86f8-0f618cafcef9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=365655098 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_read_buffer_direc
t.365655098
Directory /workspace/1.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/1.spi_device_sec_cm.2373010350
Short name T72
Test name
Test status
Simulation time 131776418 ps
CPU time 0.93 seconds
Started Jul 07 05:28:28 PM PDT 24
Finished Jul 07 05:28:29 PM PDT 24
Peak memory 236580 kb
Host smart-fc5a2b03-90b6-407b-8d0c-9d0825852d98
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2373010350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_sec_cm.2373010350
Directory /workspace/1.spi_device_sec_cm/latest

Test location /workspace/coverage/default/1.spi_device_tpm_all.3259477612
Short name T982
Test name
Test status
Simulation time 5838070367 ps
CPU time 33.49 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:29:14 PM PDT 24
Peak memory 216376 kb
Host smart-d3708b16-e9e9-47f9-b7f7-e55d8c1401a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3259477612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_all.3259477612
Directory /workspace/1.spi_device_tpm_all/latest

Test location /workspace/coverage/default/1.spi_device_tpm_read_hw_reg.2934136139
Short name T432
Test name
Test status
Simulation time 974633235 ps
CPU time 1.96 seconds
Started Jul 07 05:28:43 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 207560 kb
Host smart-1720c1da-8572-457f-be6b-cec206a59b04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2934136139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_read_hw_reg.2934136139
Directory /workspace/1.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/1.spi_device_tpm_rw.3236036810
Short name T1000
Test name
Test status
Simulation time 67309920 ps
CPU time 1.78 seconds
Started Jul 07 05:28:53 PM PDT 24
Finished Jul 07 05:28:55 PM PDT 24
Peak memory 216452 kb
Host smart-1e35c67b-6ab7-44bb-84cb-3b96598eeb1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3236036810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_rw.3236036810
Directory /workspace/1.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/1.spi_device_tpm_sts_read.2958625222
Short name T537
Test name
Test status
Simulation time 135355233 ps
CPU time 0.77 seconds
Started Jul 07 05:28:24 PM PDT 24
Finished Jul 07 05:28:26 PM PDT 24
Peak memory 205992 kb
Host smart-4d176a0f-c028-43d1-8ddf-56a4208ea5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958625222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_tpm_sts_read.2958625222
Directory /workspace/1.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/1.spi_device_upload.2554886226
Short name T507
Test name
Test status
Simulation time 123789759 ps
CPU time 2.43 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 224480 kb
Host smart-bbc2c120-eb0a-4acd-9f5f-a6f040d62055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554886226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.spi_device_upload.2554886226
Directory /workspace/1.spi_device_upload/latest

Test location /workspace/coverage/default/10.spi_device_alert_test.3910163464
Short name T771
Test name
Test status
Simulation time 161349528 ps
CPU time 0.73 seconds
Started Jul 07 05:29:12 PM PDT 24
Finished Jul 07 05:29:13 PM PDT 24
Peak memory 205736 kb
Host smart-69ebfb56-f803-41cb-8fce-a9ac8badbf39
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910163464 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_alert_test.
3910163464
Directory /workspace/10.spi_device_alert_test/latest

Test location /workspace/coverage/default/10.spi_device_cfg_cmd.3499916498
Short name T458
Test name
Test status
Simulation time 929394989 ps
CPU time 7.55 seconds
Started Jul 07 05:29:11 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 224436 kb
Host smart-da7c5cea-4df0-4a9b-94db-08fd4954c447
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499916498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_cfg_cmd.3499916498
Directory /workspace/10.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/10.spi_device_csb_read.2570371543
Short name T333
Test name
Test status
Simulation time 77603384 ps
CPU time 0.78 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:16 PM PDT 24
Peak memory 206524 kb
Host smart-070f64dd-6583-4269-964d-b31054f4f95d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570371543 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_csb_read.2570371543
Directory /workspace/10.spi_device_csb_read/latest

Test location /workspace/coverage/default/10.spi_device_flash_all.3060233282
Short name T907
Test name
Test status
Simulation time 1704885723 ps
CPU time 31.05 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:29:38 PM PDT 24
Peak memory 241068 kb
Host smart-778741f6-96da-4092-8bec-76dfdde25174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060233282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_all.3060233282
Directory /workspace/10.spi_device_flash_all/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm.2996617540
Short name T722
Test name
Test status
Simulation time 211310065 ps
CPU time 4.84 seconds
Started Jul 07 05:29:01 PM PDT 24
Finished Jul 07 05:29:06 PM PDT 24
Peak memory 235420 kb
Host smart-cbd06d74-0bfb-4c7c-852c-df9fbbce938e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996617540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm.2996617540
Directory /workspace/10.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/10.spi_device_flash_and_tpm_min_idle.3888727864
Short name T605
Test name
Test status
Simulation time 1420078022 ps
CPU time 36.22 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:29:43 PM PDT 24
Peak memory 256444 kb
Host smart-d197694e-062f-42b4-bfa8-133acd634b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3888727864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_and_tpm_min_idl
e.3888727864
Directory /workspace/10.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/10.spi_device_flash_mode.3483364207
Short name T393
Test name
Test status
Simulation time 550853685 ps
CPU time 9.18 seconds
Started Jul 07 05:29:10 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 250344 kb
Host smart-1d2979ad-1a77-4de1-a061-db3fddc99f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483364207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_flash_mode.3483364207
Directory /workspace/10.spi_device_flash_mode/latest

Test location /workspace/coverage/default/10.spi_device_intercept.847200100
Short name T909
Test name
Test status
Simulation time 1060554853 ps
CPU time 5.49 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:09 PM PDT 24
Peak memory 224452 kb
Host smart-18f416e4-26db-47b6-983f-99243cefec54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847200100 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_intercept.847200100
Directory /workspace/10.spi_device_intercept/latest

Test location /workspace/coverage/default/10.spi_device_mailbox.147883160
Short name T756
Test name
Test status
Simulation time 5660682860 ps
CPU time 50.31 seconds
Started Jul 07 05:28:58 PM PDT 24
Finished Jul 07 05:29:49 PM PDT 24
Peak memory 240428 kb
Host smart-8e9af6e8-64fa-401c-8477-b27dc0d0c8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147883160 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_mailbox.147883160
Directory /workspace/10.spi_device_mailbox/latest

Test location /workspace/coverage/default/10.spi_device_pass_addr_payload_swap.3807067892
Short name T877
Test name
Test status
Simulation time 746306232 ps
CPU time 5.88 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:29:12 PM PDT 24
Peak memory 224424 kb
Host smart-4890b401-9ca6-443f-968c-b3bd5659f8b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807067892 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_addr_payload_swa
p.3807067892
Directory /workspace/10.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/10.spi_device_pass_cmd_filtering.1554421532
Short name T78
Test name
Test status
Simulation time 3564539888 ps
CPU time 11.04 seconds
Started Jul 07 05:29:07 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 224612 kb
Host smart-cb53a627-ef64-452c-b896-3166c8c79220
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554421532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_pass_cmd_filtering.1554421532
Directory /workspace/10.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/10.spi_device_read_buffer_direct.3475357538
Short name T706
Test name
Test status
Simulation time 2071300668 ps
CPU time 8.22 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:29:22 PM PDT 24
Peak memory 218780 kb
Host smart-2dd663cb-dd62-4e48-86d1-bbbc30db2150
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3475357538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_read_buffer_dir
ect.3475357538
Directory /workspace/10.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/10.spi_device_stress_all.2873414821
Short name T321
Test name
Test status
Simulation time 15890080697 ps
CPU time 148.08 seconds
Started Jul 07 05:29:20 PM PDT 24
Finished Jul 07 05:31:50 PM PDT 24
Peak memory 249252 kb
Host smart-3455e390-dbd5-4499-bc36-df0223fd2c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2873414821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_stre
ss_all.2873414821
Directory /workspace/10.spi_device_stress_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_all.1300895368
Short name T409
Test name
Test status
Simulation time 5704520058 ps
CPU time 15.92 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:20 PM PDT 24
Peak memory 216440 kb
Host smart-26691597-a0fc-4679-8102-90767c20eec5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300895368 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_all.1300895368
Directory /workspace/10.spi_device_tpm_all/latest

Test location /workspace/coverage/default/10.spi_device_tpm_read_hw_reg.3469308036
Short name T532
Test name
Test status
Simulation time 1072181992 ps
CPU time 4.86 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:29:02 PM PDT 24
Peak memory 216180 kb
Host smart-62675882-7388-4523-bef8-2cbb75a9cc91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469308036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_read_hw_reg.3469308036
Directory /workspace/10.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/10.spi_device_tpm_rw.730496537
Short name T926
Test name
Test status
Simulation time 126847790 ps
CPU time 1.18 seconds
Started Jul 07 05:29:11 PM PDT 24
Finished Jul 07 05:29:13 PM PDT 24
Peak memory 207888 kb
Host smart-a1e22c12-ac13-48d0-9893-c8d3209b5e37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730496537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_rw.730496537
Directory /workspace/10.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/10.spi_device_tpm_sts_read.3247172453
Short name T945
Test name
Test status
Simulation time 212729889 ps
CPU time 0.9 seconds
Started Jul 07 05:29:00 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 205848 kb
Host smart-9ca225b4-7289-44bc-bf64-8fd232bb1db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247172453 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_tpm_sts_read.3247172453
Directory /workspace/10.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/10.spi_device_upload.1303315184
Short name T401
Test name
Test status
Simulation time 924266373 ps
CPU time 4.95 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:08 PM PDT 24
Peak memory 224472 kb
Host smart-4a7abd72-9d5d-4f04-9469-b948d8e7918c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303315184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.spi_device_upload.1303315184
Directory /workspace/10.spi_device_upload/latest

Test location /workspace/coverage/default/11.spi_device_alert_test.2308340876
Short name T696
Test name
Test status
Simulation time 19951799 ps
CPU time 0.71 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:16 PM PDT 24
Peak memory 205484 kb
Host smart-8bead728-682e-4566-8894-039116a7d47b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308340876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_alert_test.
2308340876
Directory /workspace/11.spi_device_alert_test/latest

Test location /workspace/coverage/default/11.spi_device_cfg_cmd.3537843493
Short name T129
Test name
Test status
Simulation time 2079478338 ps
CPU time 5.11 seconds
Started Jul 07 05:29:02 PM PDT 24
Finished Jul 07 05:29:08 PM PDT 24
Peak memory 224516 kb
Host smart-8e6e2af3-e08f-4a1d-8a4d-0eaa54abdfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537843493 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_cfg_cmd.3537843493
Directory /workspace/11.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/11.spi_device_csb_read.3234055863
Short name T524
Test name
Test status
Simulation time 18797698 ps
CPU time 0.83 seconds
Started Jul 07 05:29:02 PM PDT 24
Finished Jul 07 05:29:03 PM PDT 24
Peak memory 206568 kb
Host smart-60d88e78-57ee-4386-ad3a-bf77f0b06088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234055863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_csb_read.3234055863
Directory /workspace/11.spi_device_csb_read/latest

Test location /workspace/coverage/default/11.spi_device_flash_all.3249234992
Short name T226
Test name
Test status
Simulation time 21024948352 ps
CPU time 180.01 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:32:04 PM PDT 24
Peak memory 256860 kb
Host smart-c928d4c9-707f-497b-84ac-4cee2051db75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249234992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_all.3249234992
Directory /workspace/11.spi_device_flash_all/latest

Test location /workspace/coverage/default/11.spi_device_flash_and_tpm_min_idle.4287210859
Short name T946
Test name
Test status
Simulation time 23088165054 ps
CPU time 276.22 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:33:51 PM PDT 24
Peak memory 262916 kb
Host smart-49c594f7-684f-44df-8b12-adc777cb3000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287210859 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_and_tpm_min_idl
e.4287210859
Directory /workspace/11.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/11.spi_device_flash_mode.2242998951
Short name T312
Test name
Test status
Simulation time 2419278096 ps
CPU time 36.18 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:29:46 PM PDT 24
Peak memory 233836 kb
Host smart-0d89ec4b-4fe9-4384-b39a-d8087755975d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242998951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_flash_mode.2242998951
Directory /workspace/11.spi_device_flash_mode/latest

Test location /workspace/coverage/default/11.spi_device_intercept.826434291
Short name T194
Test name
Test status
Simulation time 231676018 ps
CPU time 4.55 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 224440 kb
Host smart-0b2bbc64-5d85-4148-ab90-7ef2813850f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826434291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_intercept.826434291
Directory /workspace/11.spi_device_intercept/latest

Test location /workspace/coverage/default/11.spi_device_mailbox.806402409
Short name T255
Test name
Test status
Simulation time 10376349287 ps
CPU time 85.83 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:30:36 PM PDT 24
Peak memory 239924 kb
Host smart-9a73c5dd-0ab3-4f65-af52-35b71e83c494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806402409 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_mailbox.806402409
Directory /workspace/11.spi_device_mailbox/latest

Test location /workspace/coverage/default/11.spi_device_pass_addr_payload_swap.1326851879
Short name T626
Test name
Test status
Simulation time 377241844 ps
CPU time 7.55 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:22 PM PDT 24
Peak memory 248692 kb
Host smart-bd9c51af-5170-448b-8cc0-ecb07080edf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1326851879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_addr_payload_swa
p.1326851879
Directory /workspace/11.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/11.spi_device_pass_cmd_filtering.3411764729
Short name T201
Test name
Test status
Simulation time 39514662445 ps
CPU time 16.76 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:29:27 PM PDT 24
Peak memory 232776 kb
Host smart-7fbc1157-ecf1-4a1a-b2a1-6630c7e062e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3411764729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_pass_cmd_filtering.3411764729
Directory /workspace/11.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/11.spi_device_read_buffer_direct.4009777714
Short name T915
Test name
Test status
Simulation time 311794213 ps
CPU time 3.94 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 223148 kb
Host smart-59b46ecb-e3a3-4518-9710-1f99fcdd0303
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4009777714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_read_buffer_dir
ect.4009777714
Directory /workspace/11.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/11.spi_device_stress_all.601719546
Short name T18
Test name
Test status
Simulation time 29749660276 ps
CPU time 124.7 seconds
Started Jul 07 05:29:11 PM PDT 24
Finished Jul 07 05:31:16 PM PDT 24
Peak memory 249316 kb
Host smart-4c030a01-3945-42e2-95c4-c1a8367e7203
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=601719546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_stres
s_all.601719546
Directory /workspace/11.spi_device_stress_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_all.1547820341
Short name T320
Test name
Test status
Simulation time 3444664825 ps
CPU time 17.73 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:29:27 PM PDT 24
Peak memory 216176 kb
Host smart-397489e6-260a-4466-a56f-0b89a7774766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1547820341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_all.1547820341
Directory /workspace/11.spi_device_tpm_all/latest

Test location /workspace/coverage/default/11.spi_device_tpm_read_hw_reg.1514063968
Short name T560
Test name
Test status
Simulation time 17517350013 ps
CPU time 5.73 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 216444 kb
Host smart-eaea9e3b-4fd3-4f37-b860-eafdb567bab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514063968 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_read_hw_reg.1514063968
Directory /workspace/11.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/11.spi_device_tpm_rw.3723226152
Short name T488
Test name
Test status
Simulation time 80534764 ps
CPU time 1.41 seconds
Started Jul 07 05:29:08 PM PDT 24
Finished Jul 07 05:29:10 PM PDT 24
Peak memory 216160 kb
Host smart-e2ad8447-934c-43b5-b258-8661d2cd0aa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723226152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_rw.3723226152
Directory /workspace/11.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/11.spi_device_tpm_sts_read.1999791655
Short name T829
Test name
Test status
Simulation time 420741285 ps
CPU time 1.01 seconds
Started Jul 07 05:29:08 PM PDT 24
Finished Jul 07 05:29:09 PM PDT 24
Peak memory 206460 kb
Host smart-d51ae9f6-dafe-4beb-b160-7d2c3ea3e1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999791655 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_tpm_sts_read.1999791655
Directory /workspace/11.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/11.spi_device_upload.894601383
Short name T516
Test name
Test status
Simulation time 39107173520 ps
CPU time 29.51 seconds
Started Jul 07 05:29:15 PM PDT 24
Finished Jul 07 05:29:45 PM PDT 24
Peak memory 232780 kb
Host smart-82cc920c-8e6c-40ec-af2e-d42bdc0814d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894601383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.spi_device_upload.894601383
Directory /workspace/11.spi_device_upload/latest

Test location /workspace/coverage/default/12.spi_device_cfg_cmd.3404587062
Short name T990
Test name
Test status
Simulation time 203895251 ps
CPU time 2.38 seconds
Started Jul 07 05:29:11 PM PDT 24
Finished Jul 07 05:29:14 PM PDT 24
Peak memory 224452 kb
Host smart-1778d2f3-547a-44fe-b454-7a6dfc986788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3404587062 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_cfg_cmd.3404587062
Directory /workspace/12.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/12.spi_device_csb_read.674002192
Short name T869
Test name
Test status
Simulation time 63654195 ps
CPU time 0.79 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:05 PM PDT 24
Peak memory 206628 kb
Host smart-8651b316-e400-4e96-8d63-e09701cd3ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674002192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_csb_read.674002192
Directory /workspace/12.spi_device_csb_read/latest

Test location /workspace/coverage/default/12.spi_device_flash_all.2276687259
Short name T41
Test name
Test status
Simulation time 4634565804 ps
CPU time 32.04 seconds
Started Jul 07 05:29:16 PM PDT 24
Finished Jul 07 05:29:49 PM PDT 24
Peak memory 249208 kb
Host smart-8b543e2e-e0ee-4920-bab6-11efdf7d7115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2276687259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_all.2276687259
Directory /workspace/12.spi_device_flash_all/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm.3384274113
Short name T816
Test name
Test status
Simulation time 45934806038 ps
CPU time 194.53 seconds
Started Jul 07 05:29:12 PM PDT 24
Finished Jul 07 05:32:28 PM PDT 24
Peak memory 252260 kb
Host smart-ce789602-0c81-4446-b08b-952fe318898c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384274113 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm.3384274113
Directory /workspace/12.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/12.spi_device_flash_and_tpm_min_idle.1884829446
Short name T889
Test name
Test status
Simulation time 67781677374 ps
CPU time 172.98 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:32:06 PM PDT 24
Peak memory 256744 kb
Host smart-cbb97209-4634-43b0-aa4f-ca1f6d7634c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884829446 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_and_tpm_min_idl
e.1884829446
Directory /workspace/12.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode.4055771818
Short name T841
Test name
Test status
Simulation time 2276399588 ps
CPU time 6.38 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:26 PM PDT 24
Peak memory 232756 kb
Host smart-2485a183-8b44-49db-bce3-2b344899d7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055771818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode.4055771818
Directory /workspace/12.spi_device_flash_mode/latest

Test location /workspace/coverage/default/12.spi_device_flash_mode_ignore_cmds.2864009830
Short name T971
Test name
Test status
Simulation time 37417663 ps
CPU time 0.72 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 215792 kb
Host smart-20d98261-ef53-4e7a-818d-16fd92faef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864009830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_flash_mode_ignore_cmd
s.2864009830
Directory /workspace/12.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/12.spi_device_intercept.779485073
Short name T213
Test name
Test status
Simulation time 7178580769 ps
CPU time 12.44 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:30 PM PDT 24
Peak memory 232772 kb
Host smart-29861e57-4ca5-4ca2-8c1a-1168941851e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779485073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_intercept.779485073
Directory /workspace/12.spi_device_intercept/latest

Test location /workspace/coverage/default/12.spi_device_mailbox.779272444
Short name T591
Test name
Test status
Simulation time 548295531 ps
CPU time 14.23 seconds
Started Jul 07 05:29:20 PM PDT 24
Finished Jul 07 05:29:36 PM PDT 24
Peak memory 249612 kb
Host smart-24980ceb-7f6b-42b4-95f0-c2bacadd7415
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779272444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_mailbox.779272444
Directory /workspace/12.spi_device_mailbox/latest

Test location /workspace/coverage/default/12.spi_device_pass_addr_payload_swap.2509651950
Short name T125
Test name
Test status
Simulation time 12446879734 ps
CPU time 19.83 seconds
Started Jul 07 05:29:10 PM PDT 24
Finished Jul 07 05:29:30 PM PDT 24
Peak memory 232764 kb
Host smart-9d22c1c1-76bd-498f-ba0c-74128eaae536
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509651950 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_addr_payload_swa
p.2509651950
Directory /workspace/12.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/12.spi_device_pass_cmd_filtering.1044481072
Short name T582
Test name
Test status
Simulation time 4210622712 ps
CPU time 8.64 seconds
Started Jul 07 05:29:12 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 232728 kb
Host smart-0aecaa37-3cec-4b96-9792-663aeab5c56a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1044481072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_pass_cmd_filtering.1044481072
Directory /workspace/12.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/12.spi_device_read_buffer_direct.2386871714
Short name T793
Test name
Test status
Simulation time 845262148 ps
CPU time 4.36 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:27 PM PDT 24
Peak memory 222832 kb
Host smart-c4cc2d0e-c127-4120-9d7f-9afc6d153774
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2386871714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_read_buffer_dir
ect.2386871714
Directory /workspace/12.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/12.spi_device_stress_all.3245268608
Short name T163
Test name
Test status
Simulation time 46087536 ps
CPU time 0.92 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 207584 kb
Host smart-a04d638b-24fb-4f85-8e83-a69d09461d36
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245268608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_stre
ss_all.3245268608
Directory /workspace/12.spi_device_stress_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_all.2363375152
Short name T638
Test name
Test status
Simulation time 1724746848 ps
CPU time 4.14 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:29:14 PM PDT 24
Peak memory 216192 kb
Host smart-a5b2e8dc-a0bb-49d5-aec3-063c8a0f0e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363375152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_all.2363375152
Directory /workspace/12.spi_device_tpm_all/latest

Test location /workspace/coverage/default/12.spi_device_tpm_read_hw_reg.3528412570
Short name T610
Test name
Test status
Simulation time 17875708786 ps
CPU time 16.9 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:29:24 PM PDT 24
Peak memory 216356 kb
Host smart-38d82e68-eae1-4230-ada4-6f0ff92d9906
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3528412570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_read_hw_reg.3528412570
Directory /workspace/12.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/12.spi_device_tpm_rw.1331511214
Short name T22
Test name
Test status
Simulation time 326935534 ps
CPU time 1.68 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 216252 kb
Host smart-2f9b6f3c-311c-48bd-8402-322cbf2e5ecc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331511214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_rw.1331511214
Directory /workspace/12.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/12.spi_device_tpm_sts_read.2080499306
Short name T623
Test name
Test status
Simulation time 81425458 ps
CPU time 0.83 seconds
Started Jul 07 05:29:02 PM PDT 24
Finished Jul 07 05:29:04 PM PDT 24
Peak memory 205988 kb
Host smart-36b6e81e-df06-4a70-8286-f78698c953f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2080499306 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_tpm_sts_read.2080499306
Directory /workspace/12.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/12.spi_device_upload.3795464020
Short name T379
Test name
Test status
Simulation time 8504804155 ps
CPU time 25.36 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:45 PM PDT 24
Peak memory 232764 kb
Host smart-e1aa5038-d1e9-496b-b45a-549601c79bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795464020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.spi_device_upload.3795464020
Directory /workspace/12.spi_device_upload/latest

Test location /workspace/coverage/default/13.spi_device_alert_test.3272545554
Short name T567
Test name
Test status
Simulation time 46357267 ps
CPU time 0.73 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:29:10 PM PDT 24
Peak memory 205536 kb
Host smart-39d62069-df63-4985-8189-d2fd5e816548
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3272545554 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_alert_test.
3272545554
Directory /workspace/13.spi_device_alert_test/latest

Test location /workspace/coverage/default/13.spi_device_cfg_cmd.1692292983
Short name T792
Test name
Test status
Simulation time 377126681 ps
CPU time 5.78 seconds
Started Jul 07 05:29:16 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 224448 kb
Host smart-aca7d4e2-718f-4e8f-9a85-f0f9a5cc7e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692292983 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_cfg_cmd.1692292983
Directory /workspace/13.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/13.spi_device_csb_read.561366465
Short name T672
Test name
Test status
Simulation time 18248208 ps
CPU time 0.82 seconds
Started Jul 07 05:29:00 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 205860 kb
Host smart-ea8607f6-797d-4729-801d-d57dbb40251e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561366465 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_csb_read.561366465
Directory /workspace/13.spi_device_csb_read/latest

Test location /workspace/coverage/default/13.spi_device_flash_all.312428889
Short name T345
Test name
Test status
Simulation time 18175364 ps
CPU time 0.79 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 215768 kb
Host smart-5ee93e9f-251c-4569-a2df-c8f7445f2e7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312428889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_all.312428889
Directory /workspace/13.spi_device_flash_all/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm.3092387551
Short name T447
Test name
Test status
Simulation time 4156584414 ps
CPU time 58.15 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:30:07 PM PDT 24
Peak memory 254284 kb
Host smart-a755b831-da05-4aae-8d77-73528effc308
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092387551 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm.3092387551
Directory /workspace/13.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/13.spi_device_flash_and_tpm_min_idle.3031340182
Short name T780
Test name
Test status
Simulation time 1386618345 ps
CPU time 26.34 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:44 PM PDT 24
Peak memory 239400 kb
Host smart-87d88673-1530-41b8-aae1-774467567a8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031340182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_and_tpm_min_idl
e.3031340182
Directory /workspace/13.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode.893551499
Short name T960
Test name
Test status
Simulation time 932067002 ps
CPU time 11.97 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:27 PM PDT 24
Peak memory 240816 kb
Host smart-201c5b26-f537-4ca3-ba1a-51cfb13a45fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893551499 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode.893551499
Directory /workspace/13.spi_device_flash_mode/latest

Test location /workspace/coverage/default/13.spi_device_flash_mode_ignore_cmds.3568892913
Short name T11
Test name
Test status
Simulation time 1537895675 ps
CPU time 11.2 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:32 PM PDT 24
Peak memory 224452 kb
Host smart-5d29b1d8-f641-43e5-a4d0-4cd7f5403da5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568892913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_flash_mode_ignore_cmd
s.3568892913
Directory /workspace/13.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/13.spi_device_intercept.3601534452
Short name T244
Test name
Test status
Simulation time 1876605407 ps
CPU time 7.76 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 224388 kb
Host smart-c7c32ae8-3893-442f-a0dd-cfdb39d3c35e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601534452 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_intercept.3601534452
Directory /workspace/13.spi_device_intercept/latest

Test location /workspace/coverage/default/13.spi_device_mailbox.2483637037
Short name T779
Test name
Test status
Simulation time 36450691590 ps
CPU time 116.84 seconds
Started Jul 07 05:29:15 PM PDT 24
Finished Jul 07 05:31:12 PM PDT 24
Peak memory 224544 kb
Host smart-7fe573ae-1f32-43d0-ab08-2ae5b70b6c39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483637037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_mailbox.2483637037
Directory /workspace/13.spi_device_mailbox/latest

Test location /workspace/coverage/default/13.spi_device_pass_addr_payload_swap.1229878715
Short name T604
Test name
Test status
Simulation time 1328653279 ps
CPU time 3.89 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 224480 kb
Host smart-7ffa3bcd-28a0-49e2-9ab7-cf3baabbb09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229878715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_addr_payload_swa
p.1229878715
Directory /workspace/13.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/13.spi_device_pass_cmd_filtering.3557860659
Short name T711
Test name
Test status
Simulation time 4086637630 ps
CPU time 8.38 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:26 PM PDT 24
Peak memory 232688 kb
Host smart-1ed2d8a4-7d76-4ab4-ba6a-9632ce6b920a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557860659 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_pass_cmd_filtering.3557860659
Directory /workspace/13.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/13.spi_device_read_buffer_direct.3802795174
Short name T403
Test name
Test status
Simulation time 160113241 ps
CPU time 3.55 seconds
Started Jul 07 05:29:12 PM PDT 24
Finished Jul 07 05:29:16 PM PDT 24
Peak memory 222624 kb
Host smart-519de479-790f-4214-bcf1-76c8bdcefd70
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3802795174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_read_buffer_dir
ect.3802795174
Directory /workspace/13.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/13.spi_device_stress_all.4003641823
Short name T468
Test name
Test status
Simulation time 59503019 ps
CPU time 1.06 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:18 PM PDT 24
Peak memory 206968 kb
Host smart-da6680ca-c578-4b10-a6d4-17bf03408627
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003641823 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_stre
ss_all.4003641823
Directory /workspace/13.spi_device_stress_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_all.3648515887
Short name T521
Test name
Test status
Simulation time 24252972177 ps
CPU time 33.88 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 216328 kb
Host smart-6d13ea31-e7a0-4c78-817b-dc7ff507f52d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648515887 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_all.3648515887
Directory /workspace/13.spi_device_tpm_all/latest

Test location /workspace/coverage/default/13.spi_device_tpm_read_hw_reg.1638235164
Short name T661
Test name
Test status
Simulation time 13304824 ps
CPU time 0.69 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 205696 kb
Host smart-960ac72f-8429-4005-be9a-5e4e8e963206
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638235164 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_read_hw_reg.1638235164
Directory /workspace/13.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/13.spi_device_tpm_rw.2563369807
Short name T916
Test name
Test status
Simulation time 92698311 ps
CPU time 1.24 seconds
Started Jul 07 05:29:10 PM PDT 24
Finished Jul 07 05:29:11 PM PDT 24
Peak memory 207508 kb
Host smart-cda9a16a-b896-486d-aa9c-a5e50ac928c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2563369807 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_rw.2563369807
Directory /workspace/13.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/13.spi_device_tpm_sts_read.1642832090
Short name T391
Test name
Test status
Simulation time 326605358 ps
CPU time 0.92 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 205976 kb
Host smart-4d73b705-16ed-4acf-8bc6-91613a2c2540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642832090 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_tpm_sts_read.1642832090
Directory /workspace/13.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/13.spi_device_upload.1158573820
Short name T880
Test name
Test status
Simulation time 4111926184 ps
CPU time 7.58 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 232824 kb
Host smart-dbe960a3-2100-42b3-a849-4ae51e085ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158573820 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.spi_device_upload.1158573820
Directory /workspace/13.spi_device_upload/latest

Test location /workspace/coverage/default/14.spi_device_alert_test.2164458578
Short name T886
Test name
Test status
Simulation time 32616745 ps
CPU time 0.69 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 204980 kb
Host smart-ca4d8452-3579-419f-84f8-e1c3f935c02b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164458578 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_alert_test.
2164458578
Directory /workspace/14.spi_device_alert_test/latest

Test location /workspace/coverage/default/14.spi_device_cfg_cmd.145079941
Short name T91
Test name
Test status
Simulation time 3173114536 ps
CPU time 22.95 seconds
Started Jul 07 05:29:16 PM PDT 24
Finished Jul 07 05:29:39 PM PDT 24
Peak memory 224580 kb
Host smart-78ba99fc-6ffb-4ada-89e1-cb8b1a74a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145079941 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_cfg_cmd.145079941
Directory /workspace/14.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/14.spi_device_csb_read.931694385
Short name T462
Test name
Test status
Simulation time 58185222 ps
CPU time 0.81 seconds
Started Jul 07 05:29:07 PM PDT 24
Finished Jul 07 05:29:08 PM PDT 24
Peak memory 206932 kb
Host smart-5192caac-cda5-43a5-a23a-35f83d3b0859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931694385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_csb_read.931694385
Directory /workspace/14.spi_device_csb_read/latest

Test location /workspace/coverage/default/14.spi_device_flash_all.2532618364
Short name T565
Test name
Test status
Simulation time 62878179089 ps
CPU time 96.72 seconds
Started Jul 07 05:29:33 PM PDT 24
Finished Jul 07 05:31:10 PM PDT 24
Peak memory 250788 kb
Host smart-8a88df04-e206-4a4f-bf82-4029a946c9b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532618364 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_all.2532618364
Directory /workspace/14.spi_device_flash_all/latest

Test location /workspace/coverage/default/14.spi_device_flash_and_tpm_min_idle.1071584982
Short name T808
Test name
Test status
Simulation time 405732844445 ps
CPU time 356.4 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 251060 kb
Host smart-c9f60fb5-4c58-4936-971f-c2e8b9192e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071584982 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_and_tpm_min_idl
e.1071584982
Directory /workspace/14.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/14.spi_device_flash_mode_ignore_cmds.319986576
Short name T854
Test name
Test status
Simulation time 20389837196 ps
CPU time 164.47 seconds
Started Jul 07 05:29:10 PM PDT 24
Finished Jul 07 05:31:55 PM PDT 24
Peak memory 249188 kb
Host smart-33266d68-a00e-4d57-adf4-7e52c756085c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=319986576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_flash_mode_ignore_cmds
.319986576
Directory /workspace/14.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/14.spi_device_intercept.706087159
Short name T899
Test name
Test status
Simulation time 6632294093 ps
CPU time 18.02 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:39 PM PDT 24
Peak memory 224560 kb
Host smart-2d080aa3-7ece-44b1-99bf-fecbc2f89381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706087159 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_intercept.706087159
Directory /workspace/14.spi_device_intercept/latest

Test location /workspace/coverage/default/14.spi_device_mailbox.2569233353
Short name T240
Test name
Test status
Simulation time 2474045740 ps
CPU time 5.2 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:20 PM PDT 24
Peak memory 232812 kb
Host smart-6867c04a-0839-4faf-89e0-f56de4cc15fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569233353 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_mailbox.2569233353
Directory /workspace/14.spi_device_mailbox/latest

Test location /workspace/coverage/default/14.spi_device_pass_addr_payload_swap.3001236559
Short name T309
Test name
Test status
Simulation time 4122510593 ps
CPU time 19.15 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:29:34 PM PDT 24
Peak memory 232704 kb
Host smart-fca9e34a-0c78-4d0f-afa2-7deb9e40b587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3001236559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_addr_payload_swa
p.3001236559
Directory /workspace/14.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/14.spi_device_pass_cmd_filtering.90951133
Short name T472
Test name
Test status
Simulation time 273209702 ps
CPU time 4.76 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 232668 kb
Host smart-276bf1f2-341d-45f8-8a43-ac167164cbbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90951133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_pass_cmd_filtering.90951133
Directory /workspace/14.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/14.spi_device_read_buffer_direct.718950728
Short name T82
Test name
Test status
Simulation time 783565847 ps
CPU time 8.46 seconds
Started Jul 07 05:29:15 PM PDT 24
Finished Jul 07 05:29:24 PM PDT 24
Peak memory 222072 kb
Host smart-3cc5a0e8-0795-41ff-ae89-1d54de855b95
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=718950728 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_read_buffer_dire
ct.718950728
Directory /workspace/14.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/14.spi_device_stress_all.1316637443
Short name T512
Test name
Test status
Simulation time 271366647 ps
CPU time 1.05 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 206900 kb
Host smart-c62183bf-715e-44fc-a477-34d52dc84228
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316637443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_stre
ss_all.1316637443
Directory /workspace/14.spi_device_stress_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_all.2759894013
Short name T362
Test name
Test status
Simulation time 738029723 ps
CPU time 4.64 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:22 PM PDT 24
Peak memory 216348 kb
Host smart-1e7a1834-4e99-44af-be6b-524db304a88f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2759894013 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_all.2759894013
Directory /workspace/14.spi_device_tpm_all/latest

Test location /workspace/coverage/default/14.spi_device_tpm_read_hw_reg.384114391
Short name T962
Test name
Test status
Simulation time 12101258553 ps
CPU time 5.23 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:33 PM PDT 24
Peak memory 216344 kb
Host smart-4e68c545-22ef-438c-8492-7f97808bcc73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=384114391 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_read_hw_reg.384114391
Directory /workspace/14.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/14.spi_device_tpm_rw.2900593751
Short name T791
Test name
Test status
Simulation time 86925106 ps
CPU time 1.43 seconds
Started Jul 07 05:29:23 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 216284 kb
Host smart-709e17ca-a36c-4edf-b593-c8938561b8e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900593751 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_rw.2900593751
Directory /workspace/14.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/14.spi_device_tpm_sts_read.4020567949
Short name T822
Test name
Test status
Simulation time 16855144 ps
CPU time 0.75 seconds
Started Jul 07 05:29:15 PM PDT 24
Finished Jul 07 05:29:16 PM PDT 24
Peak memory 205856 kb
Host smart-40d24aec-1119-41e5-9644-33cfc50a8648
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020567949 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_tpm_sts_read.4020567949
Directory /workspace/14.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/14.spi_device_upload.2889147526
Short name T578
Test name
Test status
Simulation time 143104629 ps
CPU time 4.69 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:19 PM PDT 24
Peak memory 235352 kb
Host smart-39b31967-bebc-4fa3-8715-c10242026b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889147526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.spi_device_upload.2889147526
Directory /workspace/14.spi_device_upload/latest

Test location /workspace/coverage/default/15.spi_device_alert_test.3907740057
Short name T901
Test name
Test status
Simulation time 39776335 ps
CPU time 0.73 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:32 PM PDT 24
Peak memory 204948 kb
Host smart-2030490b-c363-4d84-b1e9-eb45f53eb804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907740057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_alert_test.
3907740057
Directory /workspace/15.spi_device_alert_test/latest

Test location /workspace/coverage/default/15.spi_device_cfg_cmd.221245148
Short name T3
Test name
Test status
Simulation time 135808998 ps
CPU time 4.21 seconds
Started Jul 07 05:29:31 PM PDT 24
Finished Jul 07 05:29:36 PM PDT 24
Peak memory 232676 kb
Host smart-05c25753-d843-4b73-8b5e-db90b43bae56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221245148 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_cfg_cmd.221245148
Directory /workspace/15.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/15.spi_device_csb_read.2733750652
Short name T349
Test name
Test status
Simulation time 36904789 ps
CPU time 0.8 seconds
Started Jul 07 05:29:12 PM PDT 24
Finished Jul 07 05:29:13 PM PDT 24
Peak memory 206624 kb
Host smart-3e8ff785-61df-4631-8cca-bcde81f42c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733750652 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_csb_read.2733750652
Directory /workspace/15.spi_device_csb_read/latest

Test location /workspace/coverage/default/15.spi_device_flash_all.2531259392
Short name T247
Test name
Test status
Simulation time 34242885082 ps
CPU time 64.2 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:30:19 PM PDT 24
Peak memory 249200 kb
Host smart-13eb7857-6dba-4e0c-8be4-c4ad238925e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531259392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_all.2531259392
Directory /workspace/15.spi_device_flash_all/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm.1990087648
Short name T298
Test name
Test status
Simulation time 108892995400 ps
CPU time 197.53 seconds
Started Jul 07 05:29:45 PM PDT 24
Finished Jul 07 05:33:03 PM PDT 24
Peak memory 273008 kb
Host smart-cc116011-b2ff-413c-905d-ab104140a50f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1990087648 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm.1990087648
Directory /workspace/15.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/15.spi_device_flash_and_tpm_min_idle.1486210466
Short name T131
Test name
Test status
Simulation time 202495535420 ps
CPU time 356.3 seconds
Started Jul 07 05:29:37 PM PDT 24
Finished Jul 07 05:35:33 PM PDT 24
Peak memory 270496 kb
Host smart-08d2dfc1-73ba-40f3-a428-e0f1e99244b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486210466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_and_tpm_min_idl
e.1486210466
Directory /workspace/15.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode.3067334343
Short name T146
Test name
Test status
Simulation time 151460287 ps
CPU time 4.4 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:22 PM PDT 24
Peak memory 224424 kb
Host smart-6f7df60b-d4a5-466f-9633-03d04a4e1a7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067334343 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode.3067334343
Directory /workspace/15.spi_device_flash_mode/latest

Test location /workspace/coverage/default/15.spi_device_flash_mode_ignore_cmds.4269980099
Short name T12
Test name
Test status
Simulation time 16813974155 ps
CPU time 143.22 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:31:38 PM PDT 24
Peak memory 252368 kb
Host smart-0005fa1a-96e8-40b1-a0a3-5ad07ed15aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4269980099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_flash_mode_ignore_cmd
s.4269980099
Directory /workspace/15.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/15.spi_device_intercept.480941079
Short name T486
Test name
Test status
Simulation time 783479884 ps
CPU time 4.73 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 232660 kb
Host smart-d005aa77-3511-48bd-9585-a63465f3dc0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480941079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_intercept.480941079
Directory /workspace/15.spi_device_intercept/latest

Test location /workspace/coverage/default/15.spi_device_mailbox.926652555
Short name T702
Test name
Test status
Simulation time 8295540428 ps
CPU time 28.28 seconds
Started Jul 07 05:29:20 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 248760 kb
Host smart-2468923c-2419-4622-88c8-898874f699a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926652555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_mailbox.926652555
Directory /workspace/15.spi_device_mailbox/latest

Test location /workspace/coverage/default/15.spi_device_pass_cmd_filtering.3085969218
Short name T895
Test name
Test status
Simulation time 389584943 ps
CPU time 6.53 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 240012 kb
Host smart-d5748732-ee91-4741-8b29-5b87056fcadf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085969218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_pass_cmd_filtering.3085969218
Directory /workspace/15.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/15.spi_device_read_buffer_direct.3443496445
Short name T744
Test name
Test status
Simulation time 1893592656 ps
CPU time 6.88 seconds
Started Jul 07 05:29:24 PM PDT 24
Finished Jul 07 05:29:32 PM PDT 24
Peak memory 218932 kb
Host smart-b13a15a0-ce9a-4e08-b3bc-d40c4813ee63
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3443496445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_read_buffer_dir
ect.3443496445
Directory /workspace/15.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/15.spi_device_stress_all.2428243845
Short name T159
Test name
Test status
Simulation time 43130291841 ps
CPU time 339.55 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:35:10 PM PDT 24
Peak memory 272532 kb
Host smart-228d98be-ed40-450b-82fc-dafbb2024fc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2428243845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_stre
ss_all.2428243845
Directory /workspace/15.spi_device_stress_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_all.774161962
Short name T934
Test name
Test status
Simulation time 2077536337 ps
CPU time 10.79 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:28 PM PDT 24
Peak memory 216244 kb
Host smart-904e5310-7e58-49d9-9521-305e4f8f50e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774161962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_all.774161962
Directory /workspace/15.spi_device_tpm_all/latest

Test location /workspace/coverage/default/15.spi_device_tpm_read_hw_reg.812114023
Short name T10
Test name
Test status
Simulation time 19263946132 ps
CPU time 10.6 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:30 PM PDT 24
Peak memory 216376 kb
Host smart-da914ff2-b68e-4609-b9a7-9682f34ba5f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812114023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_read_hw_reg.812114023
Directory /workspace/15.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/15.spi_device_tpm_rw.2799594715
Short name T339
Test name
Test status
Simulation time 95099573 ps
CPU time 1.45 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 216176 kb
Host smart-2ddca542-f54a-4c22-a0cd-eb962c578b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799594715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_rw.2799594715
Directory /workspace/15.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/15.spi_device_tpm_sts_read.71477641
Short name T414
Test name
Test status
Simulation time 361593646 ps
CPU time 0.99 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:18 PM PDT 24
Peak memory 206972 kb
Host smart-dd0847e1-c194-43bc-a21b-ee662bf7f1a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=71477641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_tpm_sts_read.71477641
Directory /workspace/15.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/15.spi_device_upload.774990008
Short name T449
Test name
Test status
Simulation time 19569025517 ps
CPU time 22.64 seconds
Started Jul 07 05:29:43 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 232576 kb
Host smart-ef0a197e-155e-4cf7-9506-f6293281ec8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774990008 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.spi_device_upload.774990008
Directory /workspace/15.spi_device_upload/latest

Test location /workspace/coverage/default/16.spi_device_alert_test.1027496906
Short name T385
Test name
Test status
Simulation time 14973407 ps
CPU time 0.78 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:31 PM PDT 24
Peak memory 205744 kb
Host smart-c2c54d2f-ebca-4b7c-8501-1cec5dab7c2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027496906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_alert_test.
1027496906
Directory /workspace/16.spi_device_alert_test/latest

Test location /workspace/coverage/default/16.spi_device_cfg_cmd.1082549171
Short name T665
Test name
Test status
Simulation time 235527810 ps
CPU time 5.69 seconds
Started Jul 07 05:29:45 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 224336 kb
Host smart-084592a1-a090-4ca2-84d9-46fda0beaa74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1082549171 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_cfg_cmd.1082549171
Directory /workspace/16.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/16.spi_device_csb_read.1073072155
Short name T165
Test name
Test status
Simulation time 18245986 ps
CPU time 0.78 seconds
Started Jul 07 05:29:45 PM PDT 24
Finished Jul 07 05:29:52 PM PDT 24
Peak memory 205796 kb
Host smart-b684ca94-a5b0-437a-8687-8b90b3186354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073072155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_csb_read.1073072155
Directory /workspace/16.spi_device_csb_read/latest

Test location /workspace/coverage/default/16.spi_device_flash_all.4278538772
Short name T526
Test name
Test status
Simulation time 1548371293 ps
CPU time 25.66 seconds
Started Jul 07 05:29:40 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 250508 kb
Host smart-662b148b-1c92-43a5-8a94-fde8ec31b0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278538772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_all.4278538772
Directory /workspace/16.spi_device_flash_all/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm.4062058169
Short name T308
Test name
Test status
Simulation time 2078293689 ps
CPU time 46.5 seconds
Started Jul 07 05:29:32 PM PDT 24
Finished Jul 07 05:30:19 PM PDT 24
Peak memory 249304 kb
Host smart-460d4630-b44e-4fc3-83ae-3465fc63b0d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062058169 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm.4062058169
Directory /workspace/16.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/16.spi_device_flash_and_tpm_min_idle.2762326063
Short name T220
Test name
Test status
Simulation time 345294182372 ps
CPU time 499.25 seconds
Started Jul 07 05:29:34 PM PDT 24
Finished Jul 07 05:37:53 PM PDT 24
Peak memory 265540 kb
Host smart-56689972-c323-45b6-9cc8-23574e0bf555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762326063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_and_tpm_min_idl
e.2762326063
Directory /workspace/16.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode.3512206511
Short name T76
Test name
Test status
Simulation time 21193483691 ps
CPU time 49.14 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:30:20 PM PDT 24
Peak memory 240824 kb
Host smart-ebaf727f-81bd-40a1-9739-f7ecb21f175a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512206511 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode.3512206511
Directory /workspace/16.spi_device_flash_mode/latest

Test location /workspace/coverage/default/16.spi_device_flash_mode_ignore_cmds.4227397663
Short name T795
Test name
Test status
Simulation time 556330867 ps
CPU time 12.25 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:43 PM PDT 24
Peak memory 234316 kb
Host smart-a2fbc936-60b1-4617-91fe-0af5156756ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227397663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_flash_mode_ignore_cmd
s.4227397663
Directory /workspace/16.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/16.spi_device_intercept.3766423477
Short name T214
Test name
Test status
Simulation time 1072062731 ps
CPU time 5.46 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:26 PM PDT 24
Peak memory 224304 kb
Host smart-e68a8c02-35aa-46b0-a2f2-6d0f481f5fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3766423477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_intercept.3766423477
Directory /workspace/16.spi_device_intercept/latest

Test location /workspace/coverage/default/16.spi_device_mailbox.3603382031
Short name T523
Test name
Test status
Simulation time 10798337854 ps
CPU time 36.87 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:56 PM PDT 24
Peak memory 232800 kb
Host smart-7da4b6cb-1a7c-4983-afd3-17418409cf05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603382031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_mailbox.3603382031
Directory /workspace/16.spi_device_mailbox/latest

Test location /workspace/coverage/default/16.spi_device_pass_addr_payload_swap.3985834347
Short name T914
Test name
Test status
Simulation time 289623213 ps
CPU time 2.29 seconds
Started Jul 07 05:29:33 PM PDT 24
Finished Jul 07 05:29:36 PM PDT 24
Peak memory 223632 kb
Host smart-e07d4063-32c2-44dd-8f28-94893d588a63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985834347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_addr_payload_swa
p.3985834347
Directory /workspace/16.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/16.spi_device_pass_cmd_filtering.2621891591
Short name T466
Test name
Test status
Simulation time 1009559804 ps
CPU time 5.26 seconds
Started Jul 07 05:29:17 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 232588 kb
Host smart-8218d06d-5959-4272-9d8c-33a6f0b6ce8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2621891591 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_pass_cmd_filtering.2621891591
Directory /workspace/16.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/16.spi_device_read_buffer_direct.3027693312
Short name T809
Test name
Test status
Simulation time 2011700374 ps
CPU time 9.32 seconds
Started Jul 07 05:29:28 PM PDT 24
Finished Jul 07 05:29:38 PM PDT 24
Peak memory 222060 kb
Host smart-85820d7c-6243-40da-9dd4-4167ead2e53f
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3027693312 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_read_buffer_dir
ect.3027693312
Directory /workspace/16.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/16.spi_device_stress_all.3621764725
Short name T297
Test name
Test status
Simulation time 58617699600 ps
CPU time 591.55 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:39:10 PM PDT 24
Peak memory 273148 kb
Host smart-a835d100-2a96-478a-88f6-b44cd0875de7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621764725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_stre
ss_all.3621764725
Directory /workspace/16.spi_device_stress_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_all.2951574371
Short name T553
Test name
Test status
Simulation time 886085883 ps
CPU time 5.05 seconds
Started Jul 07 05:29:28 PM PDT 24
Finished Jul 07 05:29:33 PM PDT 24
Peak memory 216084 kb
Host smart-506fb17d-816b-47e5-b300-907de2e16f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951574371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_all.2951574371
Directory /workspace/16.spi_device_tpm_all/latest

Test location /workspace/coverage/default/16.spi_device_tpm_read_hw_reg.2631597774
Short name T944
Test name
Test status
Simulation time 12982032626 ps
CPU time 16.27 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:35 PM PDT 24
Peak memory 216324 kb
Host smart-e9c117ad-7806-48f3-b671-7b1228ec8635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631597774 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_read_hw_reg.2631597774
Directory /workspace/16.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/16.spi_device_tpm_rw.171161050
Short name T55
Test name
Test status
Simulation time 43145584 ps
CPU time 2.49 seconds
Started Jul 07 05:29:45 PM PDT 24
Finished Jul 07 05:29:48 PM PDT 24
Peak memory 215496 kb
Host smart-b493835b-afd6-4f70-9ad5-530fbf58f5b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171161050 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_rw.171161050
Directory /workspace/16.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/16.spi_device_tpm_sts_read.445003996
Short name T364
Test name
Test status
Simulation time 191067654 ps
CPU time 0.92 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:32 PM PDT 24
Peak memory 205856 kb
Host smart-051cd5c7-1e2d-41a4-bdf2-513c5170ddf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445003996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_tpm_sts_read.445003996
Directory /workspace/16.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/16.spi_device_upload.1322416257
Short name T475
Test name
Test status
Simulation time 939781380 ps
CPU time 2.74 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 224292 kb
Host smart-1681f63e-95f5-49ac-8ecb-73f1d5231bd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1322416257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.spi_device_upload.1322416257
Directory /workspace/16.spi_device_upload/latest

Test location /workspace/coverage/default/17.spi_device_alert_test.79803581
Short name T509
Test name
Test status
Simulation time 13783460 ps
CPU time 0.72 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:32 PM PDT 24
Peak memory 204940 kb
Host smart-f8adf56e-a73b-43ca-a4e0-929af029cdb9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79803581 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_alert_test.79803581
Directory /workspace/17.spi_device_alert_test/latest

Test location /workspace/coverage/default/17.spi_device_cfg_cmd.2486406477
Short name T927
Test name
Test status
Simulation time 693886052 ps
CPU time 3.7 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 224516 kb
Host smart-33e9f92d-e9c7-42c5-930e-d4d2be284c01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486406477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_cfg_cmd.2486406477
Directory /workspace/17.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/17.spi_device_csb_read.692349460
Short name T612
Test name
Test status
Simulation time 16485623 ps
CPU time 0.79 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:29:24 PM PDT 24
Peak memory 206572 kb
Host smart-0120c60c-1710-4769-9f53-d30f53ecec83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=692349460 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_csb_read.692349460
Directory /workspace/17.spi_device_csb_read/latest

Test location /workspace/coverage/default/17.spi_device_flash_all.3572697048
Short name T659
Test name
Test status
Simulation time 4084403054 ps
CPU time 28.09 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:29:52 PM PDT 24
Peak memory 234452 kb
Host smart-a66231de-00eb-4625-bb2f-9405d5d26ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572697048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_all.3572697048
Directory /workspace/17.spi_device_flash_all/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode.1360469909
Short name T412
Test name
Test status
Simulation time 891232257 ps
CPU time 6.41 seconds
Started Jul 07 05:29:47 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 232636 kb
Host smart-73cbb65f-802a-4999-8b90-4f71e876f793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360469909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode.1360469909
Directory /workspace/17.spi_device_flash_mode/latest

Test location /workspace/coverage/default/17.spi_device_flash_mode_ignore_cmds.378987505
Short name T430
Test name
Test status
Simulation time 3622647522 ps
CPU time 62.1 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:30:54 PM PDT 24
Peak memory 249144 kb
Host smart-73695895-19a1-4d3b-b30b-b616bfc0b6f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=378987505 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_flash_mode_ignore_cmds
.378987505
Directory /workspace/17.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/17.spi_device_intercept.1119838723
Short name T170
Test name
Test status
Simulation time 1828118833 ps
CPU time 18.32 seconds
Started Jul 07 05:29:33 PM PDT 24
Finished Jul 07 05:29:52 PM PDT 24
Peak memory 224264 kb
Host smart-c964f733-282f-477d-b665-ffc06fdc328a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119838723 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_intercept.1119838723
Directory /workspace/17.spi_device_intercept/latest

Test location /workspace/coverage/default/17.spi_device_mailbox.1933204534
Short name T745
Test name
Test status
Simulation time 16741020989 ps
CPU time 37.42 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:58 PM PDT 24
Peak memory 232804 kb
Host smart-14ca7709-aef4-46c9-9516-3aacbde02c90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933204534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_mailbox.1933204534
Directory /workspace/17.spi_device_mailbox/latest

Test location /workspace/coverage/default/17.spi_device_pass_addr_payload_swap.1344828108
Short name T755
Test name
Test status
Simulation time 31388572 ps
CPU time 2.41 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:33 PM PDT 24
Peak memory 232196 kb
Host smart-85a9759c-93a5-482b-9865-c79a46d33b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344828108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_addr_payload_swa
p.1344828108
Directory /workspace/17.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/17.spi_device_pass_cmd_filtering.2541376020
Short name T248
Test name
Test status
Simulation time 10733117171 ps
CPU time 8.67 seconds
Started Jul 07 05:29:16 PM PDT 24
Finished Jul 07 05:29:26 PM PDT 24
Peak memory 224624 kb
Host smart-05a68519-7d6e-40eb-a46c-4f8b7f8af8c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541376020 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_pass_cmd_filtering.2541376020
Directory /workspace/17.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/17.spi_device_read_buffer_direct.1187822201
Short name T781
Test name
Test status
Simulation time 190642008 ps
CPU time 3.94 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:29:17 PM PDT 24
Peak memory 223064 kb
Host smart-a77ccdda-a3ba-4d17-b99d-1867e8f99eed
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=1187822201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_read_buffer_dir
ect.1187822201
Directory /workspace/17.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/17.spi_device_stress_all.1448654423
Short name T647
Test name
Test status
Simulation time 50765215 ps
CPU time 1.08 seconds
Started Jul 07 05:29:46 PM PDT 24
Finished Jul 07 05:29:48 PM PDT 24
Peak memory 206860 kb
Host smart-f42e0d19-6c98-43c4-8469-81c684702f67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448654423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_stre
ss_all.1448654423
Directory /workspace/17.spi_device_stress_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_all.941610626
Short name T540
Test name
Test status
Simulation time 1625076033 ps
CPU time 18.98 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:42 PM PDT 24
Peak memory 216204 kb
Host smart-2390cc3a-0168-47cb-864d-1b1e89e5acd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=941610626 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_all.941610626
Directory /workspace/17.spi_device_tpm_all/latest

Test location /workspace/coverage/default/17.spi_device_tpm_read_hw_reg.2461823211
Short name T408
Test name
Test status
Simulation time 1845791936 ps
CPU time 5.19 seconds
Started Jul 07 05:29:12 PM PDT 24
Finished Jul 07 05:29:18 PM PDT 24
Peak memory 216220 kb
Host smart-84ca569b-169f-462f-a2c9-8b2bbe98451b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461823211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_read_hw_reg.2461823211
Directory /workspace/17.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/17.spi_device_tpm_rw.2237419463
Short name T476
Test name
Test status
Simulation time 335313308 ps
CPU time 1.92 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:29:12 PM PDT 24
Peak memory 216196 kb
Host smart-23af9145-1637-4d58-a830-4adda4cea4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2237419463 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_rw.2237419463
Directory /workspace/17.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/17.spi_device_tpm_sts_read.1039443061
Short name T88
Test name
Test status
Simulation time 404269034 ps
CPU time 0.99 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:24 PM PDT 24
Peak memory 206968 kb
Host smart-5e4a1e07-cab8-4e73-9cdb-46b9e8c96659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1039443061 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_tpm_sts_read.1039443061
Directory /workspace/17.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/17.spi_device_upload.2999306527
Short name T819
Test name
Test status
Simulation time 767819468 ps
CPU time 7.11 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:38 PM PDT 24
Peak memory 232572 kb
Host smart-bc416db7-0ca3-4a0b-b6b7-c0fb629e3e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2999306527 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.spi_device_upload.2999306527
Directory /workspace/17.spi_device_upload/latest

Test location /workspace/coverage/default/18.spi_device_alert_test.3587284537
Short name T767
Test name
Test status
Simulation time 17405987 ps
CPU time 0.71 seconds
Started Jul 07 05:29:43 PM PDT 24
Finished Jul 07 05:29:44 PM PDT 24
Peak memory 205452 kb
Host smart-7fa152db-70e7-401f-a394-90ebe40b228d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587284537 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_alert_test.
3587284537
Directory /workspace/18.spi_device_alert_test/latest

Test location /workspace/coverage/default/18.spi_device_cfg_cmd.3753807399
Short name T853
Test name
Test status
Simulation time 596323592 ps
CPU time 4.5 seconds
Started Jul 07 05:29:45 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 232572 kb
Host smart-9c5e16b0-a666-4472-9629-cb90198e3ce9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753807399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_cfg_cmd.3753807399
Directory /workspace/18.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/18.spi_device_csb_read.3798093265
Short name T968
Test name
Test status
Simulation time 23423394 ps
CPU time 0.83 seconds
Started Jul 07 05:29:31 PM PDT 24
Finished Jul 07 05:29:33 PM PDT 24
Peak memory 206548 kb
Host smart-d2c0dbc5-0777-474c-aff2-85cd57ab7cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798093265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_csb_read.3798093265
Directory /workspace/18.spi_device_csb_read/latest

Test location /workspace/coverage/default/18.spi_device_flash_all.2713854882
Short name T727
Test name
Test status
Simulation time 40779757822 ps
CPU time 285.57 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:34:17 PM PDT 24
Peak memory 251768 kb
Host smart-40c2967a-0995-47ee-a27c-a6f93b418d27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2713854882 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_all.2713854882
Directory /workspace/18.spi_device_flash_all/latest

Test location /workspace/coverage/default/18.spi_device_flash_and_tpm.3843073544
Short name T742
Test name
Test status
Simulation time 2530664841 ps
CPU time 15.19 seconds
Started Jul 07 05:29:42 PM PDT 24
Finished Jul 07 05:29:57 PM PDT 24
Peak memory 249148 kb
Host smart-3255c2c0-ed33-42d4-9635-1c27954d5cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843073544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_and_tpm.3843073544
Directory /workspace/18.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode.932492226
Short name T997
Test name
Test status
Simulation time 135902421 ps
CPU time 2.81 seconds
Started Jul 07 05:29:24 PM PDT 24
Finished Jul 07 05:29:28 PM PDT 24
Peak memory 232692 kb
Host smart-deaf9a7c-71ea-45e3-addb-71ffa6a35dea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932492226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode.932492226
Directory /workspace/18.spi_device_flash_mode/latest

Test location /workspace/coverage/default/18.spi_device_flash_mode_ignore_cmds.3922104036
Short name T460
Test name
Test status
Simulation time 26089862572 ps
CPU time 109.18 seconds
Started Jul 07 05:29:25 PM PDT 24
Finished Jul 07 05:31:16 PM PDT 24
Peak memory 256536 kb
Host smart-8e10ed97-0e61-4a6e-9f45-942f88546744
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922104036 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_flash_mode_ignore_cmd
s.3922104036
Directory /workspace/18.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/18.spi_device_intercept.1233922288
Short name T223
Test name
Test status
Simulation time 470150650 ps
CPU time 6.89 seconds
Started Jul 07 05:29:45 PM PDT 24
Finished Jul 07 05:29:52 PM PDT 24
Peak memory 232640 kb
Host smart-3c456c35-f0a7-4d4f-b5e3-2c5aca81e3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233922288 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_intercept.1233922288
Directory /workspace/18.spi_device_intercept/latest

Test location /workspace/coverage/default/18.spi_device_mailbox.2880821561
Short name T340
Test name
Test status
Simulation time 42370439 ps
CPU time 2.82 seconds
Started Jul 07 05:29:45 PM PDT 24
Finished Jul 07 05:29:49 PM PDT 24
Peak memory 232584 kb
Host smart-242701b8-4f3d-41b4-8ef3-287894a34ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2880821561 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_mailbox.2880821561
Directory /workspace/18.spi_device_mailbox/latest

Test location /workspace/coverage/default/18.spi_device_pass_addr_payload_swap.2760848154
Short name T266
Test name
Test status
Simulation time 6302377861 ps
CPU time 5.37 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:33 PM PDT 24
Peak memory 224600 kb
Host smart-71e23fbb-7103-4c0b-8c90-a428e5a63d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2760848154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_addr_payload_swa
p.2760848154
Directory /workspace/18.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/18.spi_device_pass_cmd_filtering.1928588384
Short name T860
Test name
Test status
Simulation time 15774924579 ps
CPU time 14.27 seconds
Started Jul 07 05:29:25 PM PDT 24
Finished Jul 07 05:29:40 PM PDT 24
Peak memory 240528 kb
Host smart-3a0a65d7-c3f1-46d2-8fca-c09fd7df5813
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928588384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_pass_cmd_filtering.1928588384
Directory /workspace/18.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/18.spi_device_stress_all.1766395147
Short name T955
Test name
Test status
Simulation time 983716696 ps
CPU time 21.78 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:29:45 PM PDT 24
Peak memory 239728 kb
Host smart-2134cafa-cd0e-4e4b-b915-5fc65e3ee8b3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1766395147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_stre
ss_all.1766395147
Directory /workspace/18.spi_device_stress_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_all.3973191839
Short name T498
Test name
Test status
Simulation time 6876413491 ps
CPU time 31.44 seconds
Started Jul 07 05:29:24 PM PDT 24
Finished Jul 07 05:29:56 PM PDT 24
Peak memory 220340 kb
Host smart-9c585e66-4afc-4a30-9f7d-032d27b8fbb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973191839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_all.3973191839
Directory /workspace/18.spi_device_tpm_all/latest

Test location /workspace/coverage/default/18.spi_device_tpm_read_hw_reg.2056872246
Short name T826
Test name
Test status
Simulation time 8343836425 ps
CPU time 7.33 seconds
Started Jul 07 05:29:15 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 216372 kb
Host smart-e3905d03-cbc9-4ba1-8e09-3c0e0ab01b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056872246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_read_hw_reg.2056872246
Directory /workspace/18.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/18.spi_device_tpm_rw.3069027885
Short name T648
Test name
Test status
Simulation time 332611051 ps
CPU time 2.13 seconds
Started Jul 07 05:29:34 PM PDT 24
Finished Jul 07 05:29:37 PM PDT 24
Peak memory 216140 kb
Host smart-b5fb05db-0f2a-4a0e-a9b6-49502ea5ae6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069027885 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_rw.3069027885
Directory /workspace/18.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/18.spi_device_tpm_sts_read.4120397947
Short name T519
Test name
Test status
Simulation time 57908103 ps
CPU time 0.88 seconds
Started Jul 07 05:29:47 PM PDT 24
Finished Jul 07 05:29:48 PM PDT 24
Peak memory 205916 kb
Host smart-a6bac0f4-7f59-4152-9a8d-014c4905369b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120397947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_tpm_sts_read.4120397947
Directory /workspace/18.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/18.spi_device_upload.2920167979
Short name T941
Test name
Test status
Simulation time 89941720 ps
CPU time 2.11 seconds
Started Jul 07 05:29:25 PM PDT 24
Finished Jul 07 05:29:29 PM PDT 24
Peak memory 224112 kb
Host smart-8f74dffa-411b-4232-a8cd-84226c0f9621
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920167979 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.spi_device_upload.2920167979
Directory /workspace/18.spi_device_upload/latest

Test location /workspace/coverage/default/19.spi_device_alert_test.2758864705
Short name T574
Test name
Test status
Simulation time 25340925 ps
CPU time 0.74 seconds
Started Jul 07 05:29:20 PM PDT 24
Finished Jul 07 05:29:22 PM PDT 24
Peak memory 205524 kb
Host smart-a3ae0892-b84f-4ecb-88c7-2c62c0497e34
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2758864705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_alert_test.
2758864705
Directory /workspace/19.spi_device_alert_test/latest

Test location /workspace/coverage/default/19.spi_device_cfg_cmd.2534951476
Short name T840
Test name
Test status
Simulation time 31031662 ps
CPU time 2.2 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:17 PM PDT 24
Peak memory 224472 kb
Host smart-261451cc-3969-41f6-94a3-a326b5923def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534951476 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_cfg_cmd.2534951476
Directory /workspace/19.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/19.spi_device_csb_read.1620607695
Short name T653
Test name
Test status
Simulation time 15662863 ps
CPU time 0.72 seconds
Started Jul 07 05:29:42 PM PDT 24
Finished Jul 07 05:29:48 PM PDT 24
Peak memory 205500 kb
Host smart-f282cc89-ca9d-47b4-acac-316c46cb1725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620607695 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_csb_read.1620607695
Directory /workspace/19.spi_device_csb_read/latest

Test location /workspace/coverage/default/19.spi_device_flash_all.3322562048
Short name T176
Test name
Test status
Simulation time 6076038232 ps
CPU time 43.82 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 248340 kb
Host smart-86f40a41-060e-4707-a9d2-b0830e927ccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322562048 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_all.3322562048
Directory /workspace/19.spi_device_flash_all/latest

Test location /workspace/coverage/default/19.spi_device_flash_and_tpm_min_idle.1250983243
Short name T790
Test name
Test status
Simulation time 2190499365 ps
CPU time 38.13 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 237236 kb
Host smart-7f482b12-da66-4504-95d3-ddc89dd8017a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250983243 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_and_tpm_min_idl
e.1250983243
Directory /workspace/19.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode.1549458494
Short name T169
Test name
Test status
Simulation time 333588305 ps
CPU time 5.55 seconds
Started Jul 07 05:29:34 PM PDT 24
Finished Jul 07 05:29:40 PM PDT 24
Peak memory 224292 kb
Host smart-ce2a2aa2-bc15-4897-a5ed-3da3deb3288d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549458494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode.1549458494
Directory /workspace/19.spi_device_flash_mode/latest

Test location /workspace/coverage/default/19.spi_device_flash_mode_ignore_cmds.1686887158
Short name T269
Test name
Test status
Simulation time 17242930654 ps
CPU time 85.11 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:30:47 PM PDT 24
Peak memory 249868 kb
Host smart-0683101d-27ce-47c1-a41d-793308e6de52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1686887158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_flash_mode_ignore_cmd
s.1686887158
Directory /workspace/19.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/19.spi_device_intercept.2507968172
Short name T510
Test name
Test status
Simulation time 83093124 ps
CPU time 2.32 seconds
Started Jul 07 05:29:43 PM PDT 24
Finished Jul 07 05:29:46 PM PDT 24
Peak memory 224412 kb
Host smart-883b9adb-9b7d-463e-9ec1-14c2171b6dd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507968172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_intercept.2507968172
Directory /workspace/19.spi_device_intercept/latest

Test location /workspace/coverage/default/19.spi_device_mailbox.4019215719
Short name T839
Test name
Test status
Simulation time 14318687211 ps
CPU time 40.77 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:30:00 PM PDT 24
Peak memory 232740 kb
Host smart-cfd9cd5d-113a-40d5-9fec-de8b217c6210
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019215719 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_mailbox.4019215719
Directory /workspace/19.spi_device_mailbox/latest

Test location /workspace/coverage/default/19.spi_device_pass_addr_payload_swap.1454582424
Short name T707
Test name
Test status
Simulation time 10512909027 ps
CPU time 12.34 seconds
Started Jul 07 05:29:42 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 249028 kb
Host smart-2a5d760a-1ae6-4fcb-abd9-8678397ed6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454582424 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_addr_payload_swa
p.1454582424
Directory /workspace/19.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/19.spi_device_pass_cmd_filtering.1332035775
Short name T26
Test name
Test status
Simulation time 596158440 ps
CPU time 7.71 seconds
Started Jul 07 05:29:33 PM PDT 24
Finished Jul 07 05:29:41 PM PDT 24
Peak memory 232648 kb
Host smart-5a3002ff-7710-4140-93f3-db1dac83fa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1332035775 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_pass_cmd_filtering.1332035775
Directory /workspace/19.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/19.spi_device_read_buffer_direct.3350920955
Short name T147
Test name
Test status
Simulation time 275219967 ps
CPU time 3.72 seconds
Started Jul 07 05:29:31 PM PDT 24
Finished Jul 07 05:29:35 PM PDT 24
Peak memory 223084 kb
Host smart-a9140c8c-c6b6-4455-9295-126e05552375
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3350920955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_read_buffer_dir
ect.3350920955
Directory /workspace/19.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/19.spi_device_tpm_all.1193684375
Short name T942
Test name
Test status
Simulation time 8286577360 ps
CPU time 11.85 seconds
Started Jul 07 05:29:41 PM PDT 24
Finished Jul 07 05:29:53 PM PDT 24
Peak memory 216300 kb
Host smart-e1fc4c71-7482-421f-9eca-54920c6097d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193684375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_all.1193684375
Directory /workspace/19.spi_device_tpm_all/latest

Test location /workspace/coverage/default/19.spi_device_tpm_read_hw_reg.1919066420
Short name T415
Test name
Test status
Simulation time 610557212 ps
CPU time 4.35 seconds
Started Jul 07 05:29:39 PM PDT 24
Finished Jul 07 05:29:44 PM PDT 24
Peak memory 216152 kb
Host smart-0640ce47-7ce1-46ba-9f21-ffa6485c71d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919066420 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_read_hw_reg.1919066420
Directory /workspace/19.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/19.spi_device_tpm_rw.3527599261
Short name T777
Test name
Test status
Simulation time 158649490 ps
CPU time 1.6 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:22 PM PDT 24
Peak memory 216192 kb
Host smart-e79e12eb-b6bb-4570-b4ab-e763178d70cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527599261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_rw.3527599261
Directory /workspace/19.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/19.spi_device_tpm_sts_read.1351844085
Short name T883
Test name
Test status
Simulation time 75232884 ps
CPU time 0.74 seconds
Started Jul 07 05:29:43 PM PDT 24
Finished Jul 07 05:29:44 PM PDT 24
Peak memory 205916 kb
Host smart-a191f9fe-434e-420f-aeed-840421ca3436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351844085 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_tpm_sts_read.1351844085
Directory /workspace/19.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/19.spi_device_upload.4033389587
Short name T386
Test name
Test status
Simulation time 876910618 ps
CPU time 5.82 seconds
Started Jul 07 05:29:23 PM PDT 24
Finished Jul 07 05:29:30 PM PDT 24
Peak memory 232656 kb
Host smart-e99c3c0e-b6eb-44ec-ae3f-7f0c75216d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033389587 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.spi_device_upload.4033389587
Directory /workspace/19.spi_device_upload/latest

Test location /workspace/coverage/default/2.spi_device_alert_test.1578749599
Short name T63
Test name
Test status
Simulation time 24688748 ps
CPU time 0.72 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:28:56 PM PDT 24
Peak memory 205372 kb
Host smart-bf75fd6c-17cc-474a-b452-4c360bf0a441
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578749599 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_alert_test.1
578749599
Directory /workspace/2.spi_device_alert_test/latest

Test location /workspace/coverage/default/2.spi_device_cfg_cmd.637974147
Short name T344
Test name
Test status
Simulation time 73899370 ps
CPU time 2.94 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:44 PM PDT 24
Peak memory 232676 kb
Host smart-7a8f527a-14b0-49c0-a982-158b6ba70f13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637974147 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_cfg_cmd.637974147
Directory /workspace/2.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/2.spi_device_csb_read.2474511481
Short name T454
Test name
Test status
Simulation time 37296781 ps
CPU time 0.79 seconds
Started Jul 07 05:28:40 PM PDT 24
Finished Jul 07 05:28:42 PM PDT 24
Peak memory 206616 kb
Host smart-338b8eb3-1483-4874-a4e8-4896ec0ff15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474511481 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_csb_read.2474511481
Directory /workspace/2.spi_device_csb_read/latest

Test location /workspace/coverage/default/2.spi_device_flash_all.630954779
Short name T823
Test name
Test status
Simulation time 76103818971 ps
CPU time 186.39 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:31:44 PM PDT 24
Peak memory 254156 kb
Host smart-43bfdd22-97cd-499f-ba0e-1d31777f6d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630954779 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_all.630954779
Directory /workspace/2.spi_device_flash_all/latest

Test location /workspace/coverage/default/2.spi_device_flash_and_tpm_min_idle.2337395423
Short name T606
Test name
Test status
Simulation time 13138837545 ps
CPU time 23.9 seconds
Started Jul 07 05:29:00 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 224484 kb
Host smart-0a611eaa-63e4-4866-90b6-7e842f13ad0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337395423 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_and_tpm_min_idle
.2337395423
Directory /workspace/2.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode.914622672
Short name T234
Test name
Test status
Simulation time 411659219 ps
CPU time 5.55 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 232712 kb
Host smart-dddd3e0b-b622-4b87-a7d2-b49e1df0ab53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=914622672 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode.914622672
Directory /workspace/2.spi_device_flash_mode/latest

Test location /workspace/coverage/default/2.spi_device_flash_mode_ignore_cmds.1493001663
Short name T871
Test name
Test status
Simulation time 19261808740 ps
CPU time 145.84 seconds
Started Jul 07 05:28:38 PM PDT 24
Finished Jul 07 05:31:06 PM PDT 24
Peak memory 249216 kb
Host smart-c02198c2-3a4f-4db3-a0bb-d06e8c1514a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493001663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_flash_mode_ignore_cmds
.1493001663
Directory /workspace/2.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/2.spi_device_intercept.3394722430
Short name T1009
Test name
Test status
Simulation time 240847351 ps
CPU time 4.36 seconds
Started Jul 07 05:28:52 PM PDT 24
Finished Jul 07 05:28:57 PM PDT 24
Peak memory 232644 kb
Host smart-7044df6f-9307-4301-ae0c-e04c0dc06ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3394722430 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_intercept.3394722430
Directory /workspace/2.spi_device_intercept/latest

Test location /workspace/coverage/default/2.spi_device_mailbox.1917461121
Short name T478
Test name
Test status
Simulation time 494313672 ps
CPU time 7.8 seconds
Started Jul 07 05:28:53 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 232704 kb
Host smart-71d58095-312d-46e0-97e9-d8290ab881f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1917461121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_mailbox.1917461121
Directory /workspace/2.spi_device_mailbox/latest

Test location /workspace/coverage/default/2.spi_device_pass_addr_payload_swap.68597831
Short name T876
Test name
Test status
Simulation time 204820306 ps
CPU time 2.08 seconds
Started Jul 07 05:28:33 PM PDT 24
Finished Jul 07 05:28:36 PM PDT 24
Peak memory 223400 kb
Host smart-7e87f389-e3c4-4505-861c-37f263e36600
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68597831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_addr_payload_swap.68597831
Directory /workspace/2.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/2.spi_device_pass_cmd_filtering.2397243317
Short name T282
Test name
Test status
Simulation time 2137190049 ps
CPU time 8.03 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 232588 kb
Host smart-a2506e63-ec34-4034-9b53-f1c6475882dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397243317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_pass_cmd_filtering.2397243317
Directory /workspace/2.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/2.spi_device_read_buffer_direct.2466391903
Short name T817
Test name
Test status
Simulation time 1274661772 ps
CPU time 10.07 seconds
Started Jul 07 05:28:47 PM PDT 24
Finished Jul 07 05:28:58 PM PDT 24
Peak memory 223092 kb
Host smart-579db39a-c116-48b8-8a10-21a3c57f491a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2466391903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_read_buffer_dire
ct.2466391903
Directory /workspace/2.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/2.spi_device_stress_all.1646763117
Short name T19
Test name
Test status
Simulation time 43163184 ps
CPU time 1.02 seconds
Started Jul 07 05:28:59 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 207592 kb
Host smart-d4a65124-b303-49d7-9966-c89f0e430571
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646763117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_stres
s_all.1646763117
Directory /workspace/2.spi_device_stress_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_all.3633513864
Short name T703
Test name
Test status
Simulation time 1627784965 ps
CPU time 20.14 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 216192 kb
Host smart-b9b55424-6481-4050-a2af-1f7e1c82e402
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633513864 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_all.3633513864
Directory /workspace/2.spi_device_tpm_all/latest

Test location /workspace/coverage/default/2.spi_device_tpm_read_hw_reg.2819666743
Short name T685
Test name
Test status
Simulation time 426985184 ps
CPU time 3.32 seconds
Started Jul 07 05:28:56 PM PDT 24
Finished Jul 07 05:29:00 PM PDT 24
Peak memory 216196 kb
Host smart-ad88ba36-8bef-4c91-98f5-440e7c8a9260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819666743 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_read_hw_reg.2819666743
Directory /workspace/2.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/2.spi_device_tpm_rw.1947808119
Short name T761
Test name
Test status
Simulation time 106987141 ps
CPU time 1.88 seconds
Started Jul 07 05:28:59 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 216264 kb
Host smart-eadb173d-6b1f-41f1-9b0f-5f6b859afe28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947808119 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_rw.1947808119
Directory /workspace/2.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/2.spi_device_tpm_sts_read.1042455218
Short name T499
Test name
Test status
Simulation time 159827882 ps
CPU time 0.79 seconds
Started Jul 07 05:28:43 PM PDT 24
Finished Jul 07 05:28:45 PM PDT 24
Peak memory 205992 kb
Host smart-4a7f01b4-a8b7-4b68-878c-a47e75be8392
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042455218 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_tpm_sts_read.1042455218
Directory /workspace/2.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/2.spi_device_upload.2720387433
Short name T586
Test name
Test status
Simulation time 716840910 ps
CPU time 2.37 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:28:52 PM PDT 24
Peak memory 224152 kb
Host smart-0838b523-d6ec-43b3-837e-d30ac0eecfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720387433 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.spi_device_upload.2720387433
Directory /workspace/2.spi_device_upload/latest

Test location /workspace/coverage/default/20.spi_device_alert_test.2379280130
Short name T351
Test name
Test status
Simulation time 48687558 ps
CPU time 0.71 seconds
Started Jul 07 05:29:43 PM PDT 24
Finished Jul 07 05:29:44 PM PDT 24
Peak memory 205420 kb
Host smart-6cfe1404-4791-4bed-a87d-f3ce50f26c15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379280130 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_alert_test.
2379280130
Directory /workspace/20.spi_device_alert_test/latest

Test location /workspace/coverage/default/20.spi_device_cfg_cmd.4226575757
Short name T986
Test name
Test status
Simulation time 327298679 ps
CPU time 2.94 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:34 PM PDT 24
Peak memory 232636 kb
Host smart-db889e92-af90-482b-86e7-a874844c8b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226575757 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_cfg_cmd.4226575757
Directory /workspace/20.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/20.spi_device_csb_read.2842442122
Short name T657
Test name
Test status
Simulation time 96615841 ps
CPU time 0.76 seconds
Started Jul 07 05:29:28 PM PDT 24
Finished Jul 07 05:29:29 PM PDT 24
Peak memory 206932 kb
Host smart-2ffb9fa3-9965-485d-916a-c014da49118b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842442122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_csb_read.2842442122
Directory /workspace/20.spi_device_csb_read/latest

Test location /workspace/coverage/default/20.spi_device_flash_all.533560376
Short name T708
Test name
Test status
Simulation time 3490291001 ps
CPU time 43.71 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 249188 kb
Host smart-c83a7106-9099-42d9-b787-5839eb7319c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533560376 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_all.533560376
Directory /workspace/20.spi_device_flash_all/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm.799717810
Short name T1001
Test name
Test status
Simulation time 6128856431 ps
CPU time 28.36 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:29:52 PM PDT 24
Peak memory 255804 kb
Host smart-35aef6ac-973a-4665-8f68-c194b1aa8849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799717810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm.799717810
Directory /workspace/20.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/20.spi_device_flash_and_tpm_min_idle.3193869810
Short name T624
Test name
Test status
Simulation time 5460679028 ps
CPU time 12.92 seconds
Started Jul 07 05:29:23 PM PDT 24
Finished Jul 07 05:29:37 PM PDT 24
Peak memory 224560 kb
Host smart-b6eb8bb3-e21d-4cd0-b0f6-466d4987c971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193869810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_and_tpm_min_idl
e.3193869810
Directory /workspace/20.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/20.spi_device_flash_mode_ignore_cmds.2151871194
Short name T855
Test name
Test status
Simulation time 417771603 ps
CPU time 10.03 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:32 PM PDT 24
Peak memory 238088 kb
Host smart-43656de5-6f2b-4dc0-8ab7-b7883a264d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151871194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_flash_mode_ignore_cmd
s.2151871194
Directory /workspace/20.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/20.spi_device_intercept.3970622998
Short name T277
Test name
Test status
Simulation time 3892579539 ps
CPU time 5.89 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:27 PM PDT 24
Peak memory 224564 kb
Host smart-cdaa6640-0e6d-4487-8de0-70b645b6c75e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970622998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_intercept.3970622998
Directory /workspace/20.spi_device_intercept/latest

Test location /workspace/coverage/default/20.spi_device_mailbox.3035242314
Short name T464
Test name
Test status
Simulation time 3593048384 ps
CPU time 42.93 seconds
Started Jul 07 05:29:25 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 240372 kb
Host smart-ee34bb2d-207d-43b2-b9b4-771ecdcec933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035242314 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_mailbox.3035242314
Directory /workspace/20.spi_device_mailbox/latest

Test location /workspace/coverage/default/20.spi_device_pass_addr_payload_swap.2666843523
Short name T508
Test name
Test status
Simulation time 112658898 ps
CPU time 2.54 seconds
Started Jul 07 05:29:27 PM PDT 24
Finished Jul 07 05:29:30 PM PDT 24
Peak memory 232276 kb
Host smart-7a1f412b-818a-4d1e-85b0-2a14837f7657
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666843523 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_addr_payload_swa
p.2666843523
Directory /workspace/20.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/20.spi_device_pass_cmd_filtering.2514358646
Short name T242
Test name
Test status
Simulation time 1115574888 ps
CPU time 8.35 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:29:41 PM PDT 24
Peak memory 224516 kb
Host smart-04c44a76-0698-49ec-bbc0-4baee73b5b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514358646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_pass_cmd_filtering.2514358646
Directory /workspace/20.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/20.spi_device_read_buffer_direct.698175602
Short name T382
Test name
Test status
Simulation time 481493950 ps
CPU time 3.71 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:31 PM PDT 24
Peak memory 219180 kb
Host smart-6721cba8-986c-4a0e-8d46-9ccf75e2e025
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=698175602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_read_buffer_dire
ct.698175602
Directory /workspace/20.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/20.spi_device_tpm_all.3127932906
Short name T372
Test name
Test status
Simulation time 38146238 ps
CPU time 0.71 seconds
Started Jul 07 05:29:20 PM PDT 24
Finished Jul 07 05:29:22 PM PDT 24
Peak memory 205708 kb
Host smart-043b5249-7af9-45fc-987f-49f80169bc6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127932906 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_all.3127932906
Directory /workspace/20.spi_device_tpm_all/latest

Test location /workspace/coverage/default/20.spi_device_tpm_read_hw_reg.3433911017
Short name T443
Test name
Test status
Simulation time 750824823 ps
CPU time 4.47 seconds
Started Jul 07 05:29:24 PM PDT 24
Finished Jul 07 05:29:29 PM PDT 24
Peak memory 216172 kb
Host smart-b9b44900-ab77-473a-8c96-0f16901f7ecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433911017 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_read_hw_reg.3433911017
Directory /workspace/20.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/20.spi_device_tpm_rw.1779218521
Short name T635
Test name
Test status
Simulation time 14016671 ps
CPU time 0.67 seconds
Started Jul 07 05:29:35 PM PDT 24
Finished Jul 07 05:29:36 PM PDT 24
Peak memory 205456 kb
Host smart-14615df1-c484-4cff-88df-2e9a392bc45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779218521 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_rw.1779218521
Directory /workspace/20.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/20.spi_device_tpm_sts_read.245545056
Short name T369
Test name
Test status
Simulation time 178367911 ps
CPU time 0.9 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 207020 kb
Host smart-08c81c9c-2773-4b22-995b-3acc27fd8453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245545056 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_tpm_sts_read.245545056
Directory /workspace/20.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/20.spi_device_upload.707019909
Short name T445
Test name
Test status
Simulation time 38714516839 ps
CPU time 15.3 seconds
Started Jul 07 05:29:52 PM PDT 24
Finished Jul 07 05:30:08 PM PDT 24
Peak memory 232740 kb
Host smart-5206ee21-d965-46bb-9666-fce6786cbfce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707019909 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.spi_device_upload.707019909
Directory /workspace/20.spi_device_upload/latest

Test location /workspace/coverage/default/21.spi_device_alert_test.152194347
Short name T491
Test name
Test status
Simulation time 18438765 ps
CPU time 0.71 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 205516 kb
Host smart-aaaa13ad-da04-4645-b026-4dbbbcb62cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152194347 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_alert_test.152194347
Directory /workspace/21.spi_device_alert_test/latest

Test location /workspace/coverage/default/21.spi_device_cfg_cmd.2159539502
Short name T888
Test name
Test status
Simulation time 637834075 ps
CPU time 3.8 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:29:27 PM PDT 24
Peak memory 232644 kb
Host smart-c7204e8d-0eca-49af-b8b4-7c91ac82458d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159539502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_cfg_cmd.2159539502
Directory /workspace/21.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/21.spi_device_csb_read.59748583
Short name T520
Test name
Test status
Simulation time 13559659 ps
CPU time 0.73 seconds
Started Jul 07 05:29:34 PM PDT 24
Finished Jul 07 05:29:35 PM PDT 24
Peak memory 206388 kb
Host smart-67ba8a94-3b24-4af9-98ef-fdd25363dff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59748583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_csb_read.59748583
Directory /workspace/21.spi_device_csb_read/latest

Test location /workspace/coverage/default/21.spi_device_flash_all.2735951836
Short name T961
Test name
Test status
Simulation time 25472714785 ps
CPU time 97.82 seconds
Started Jul 07 05:29:29 PM PDT 24
Finished Jul 07 05:31:08 PM PDT 24
Peak memory 251904 kb
Host smart-f1a50136-1084-4b9b-9532-b3b8901dbe7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735951836 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_all.2735951836
Directory /workspace/21.spi_device_flash_all/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm.3329878842
Short name T206
Test name
Test status
Simulation time 1656966238 ps
CPU time 43.16 seconds
Started Jul 07 05:29:23 PM PDT 24
Finished Jul 07 05:30:07 PM PDT 24
Peak memory 241108 kb
Host smart-e8eb7157-7eac-4140-8219-3947bc4f2176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3329878842 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm.3329878842
Directory /workspace/21.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/21.spi_device_flash_and_tpm_min_idle.2446513316
Short name T668
Test name
Test status
Simulation time 44589856322 ps
CPU time 159.31 seconds
Started Jul 07 05:29:23 PM PDT 24
Finished Jul 07 05:32:03 PM PDT 24
Peak memory 249268 kb
Host smart-5a81daa2-cfd1-4bc9-97ad-2b079005af1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446513316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_and_tpm_min_idl
e.2446513316
Directory /workspace/21.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode.626892710
Short name T313
Test name
Test status
Simulation time 446219868 ps
CPU time 9.56 seconds
Started Jul 07 05:29:18 PM PDT 24
Finished Jul 07 05:29:28 PM PDT 24
Peak memory 224496 kb
Host smart-a7bd0332-3369-4100-9258-90128288f697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626892710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode.626892710
Directory /workspace/21.spi_device_flash_mode/latest

Test location /workspace/coverage/default/21.spi_device_flash_mode_ignore_cmds.2372091467
Short name T956
Test name
Test status
Simulation time 49449308584 ps
CPU time 74.73 seconds
Started Jul 07 05:29:25 PM PDT 24
Finished Jul 07 05:30:41 PM PDT 24
Peak memory 249176 kb
Host smart-6d200384-3835-4ed5-8bd1-9af39329bd04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372091467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_flash_mode_ignore_cmd
s.2372091467
Directory /workspace/21.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/21.spi_device_intercept.983128330
Short name T928
Test name
Test status
Simulation time 3029134192 ps
CPU time 8.65 seconds
Started Jul 07 05:29:42 PM PDT 24
Finished Jul 07 05:29:51 PM PDT 24
Peak memory 232740 kb
Host smart-176079cd-7d41-4a5c-b36a-35a6eab96af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983128330 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_intercept.983128330
Directory /workspace/21.spi_device_intercept/latest

Test location /workspace/coverage/default/21.spi_device_mailbox.2285873840
Short name T564
Test name
Test status
Simulation time 2904573798 ps
CPU time 26.75 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:47 PM PDT 24
Peak memory 224572 kb
Host smart-ebca5252-dfc9-4cab-b054-d4d4e6586968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2285873840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_mailbox.2285873840
Directory /workspace/21.spi_device_mailbox/latest

Test location /workspace/coverage/default/21.spi_device_pass_addr_payload_swap.2342917392
Short name T896
Test name
Test status
Simulation time 251918235 ps
CPU time 3.13 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 224440 kb
Host smart-51162a61-4c79-465b-a646-c3c4a9433d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2342917392 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_addr_payload_swa
p.2342917392
Directory /workspace/21.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/21.spi_device_pass_cmd_filtering.843075923
Short name T96
Test name
Test status
Simulation time 379892346 ps
CPU time 2.35 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:29 PM PDT 24
Peak memory 224308 kb
Host smart-f27fa224-43ec-4e99-892c-df4b3398e625
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843075923 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_pass_cmd_filtering.843075923
Directory /workspace/21.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/21.spi_device_read_buffer_direct.687064614
Short name T448
Test name
Test status
Simulation time 253049300 ps
CPU time 4.63 seconds
Started Jul 07 05:29:32 PM PDT 24
Finished Jul 07 05:29:37 PM PDT 24
Peak memory 218884 kb
Host smart-0ebfcba8-5b1c-4f35-9d6d-78ffbd245099
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=687064614 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_read_buffer_dire
ct.687064614
Directory /workspace/21.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/21.spi_device_stress_all.133360869
Short name T972
Test name
Test status
Simulation time 10588359600 ps
CPU time 87.37 seconds
Started Jul 07 05:29:34 PM PDT 24
Finished Jul 07 05:31:02 PM PDT 24
Peak memory 249284 kb
Host smart-7fb66cdb-658f-4e1f-8195-30db176c9953
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=133360869 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_stres
s_all.133360869
Directory /workspace/21.spi_device_stress_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_all.2085753261
Short name T2
Test name
Test status
Simulation time 3108944831 ps
CPU time 25.28 seconds
Started Jul 07 05:29:29 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 216384 kb
Host smart-41337e4d-e0bf-4792-b83a-458ebac0812e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085753261 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_all.2085753261
Directory /workspace/21.spi_device_tpm_all/latest

Test location /workspace/coverage/default/21.spi_device_tpm_read_hw_reg.2564926529
Short name T335
Test name
Test status
Simulation time 71089717133 ps
CPU time 18.36 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:45 PM PDT 24
Peak memory 216480 kb
Host smart-80d53b68-f6d5-4051-b546-9f9dbdad8c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564926529 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_read_hw_reg.2564926529
Directory /workspace/21.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/21.spi_device_tpm_rw.3044993140
Short name T985
Test name
Test status
Simulation time 60194704 ps
CPU time 1.28 seconds
Started Jul 07 05:29:37 PM PDT 24
Finished Jul 07 05:29:38 PM PDT 24
Peak memory 216124 kb
Host smart-349f8b2d-d5b8-441a-92d1-6e92e4cc0116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3044993140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_rw.3044993140
Directory /workspace/21.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/21.spi_device_tpm_sts_read.3854009904
Short name T493
Test name
Test status
Simulation time 36551603 ps
CPU time 0.77 seconds
Started Jul 07 05:29:28 PM PDT 24
Finished Jul 07 05:29:29 PM PDT 24
Peak memory 205904 kb
Host smart-feef4e9a-dd25-42ac-835d-2abe2bd25f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854009904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_tpm_sts_read.3854009904
Directory /workspace/21.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/21.spi_device_upload.1616280558
Short name T969
Test name
Test status
Simulation time 286763940 ps
CPU time 2.34 seconds
Started Jul 07 05:29:27 PM PDT 24
Finished Jul 07 05:29:30 PM PDT 24
Peak memory 224500 kb
Host smart-7d24a0b4-90a2-464b-9d7d-ea28c152d9dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616280558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.spi_device_upload.1616280558
Directory /workspace/21.spi_device_upload/latest

Test location /workspace/coverage/default/22.spi_device_alert_test.4283233618
Short name T402
Test name
Test status
Simulation time 23892637 ps
CPU time 0.69 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 204956 kb
Host smart-918ae253-4dce-41e3-9ae1-9e6f9c41c2ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283233618 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_alert_test.
4283233618
Directory /workspace/22.spi_device_alert_test/latest

Test location /workspace/coverage/default/22.spi_device_cfg_cmd.3225857996
Short name T720
Test name
Test status
Simulation time 378872747 ps
CPU time 3.54 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:29:27 PM PDT 24
Peak memory 232644 kb
Host smart-c903d544-bc95-45a4-b42e-aee4aa099a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225857996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_cfg_cmd.3225857996
Directory /workspace/22.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/22.spi_device_csb_read.3387077221
Short name T346
Test name
Test status
Simulation time 62159639 ps
CPU time 0.77 seconds
Started Jul 07 05:29:23 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 205568 kb
Host smart-4f3a3dd4-b891-4414-af08-5d46e3636c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387077221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_csb_read.3387077221
Directory /workspace/22.spi_device_csb_read/latest

Test location /workspace/coverage/default/22.spi_device_flash_all.1953936006
Short name T426
Test name
Test status
Simulation time 25400036147 ps
CPU time 113.38 seconds
Started Jul 07 05:29:33 PM PDT 24
Finished Jul 07 05:31:27 PM PDT 24
Peak memory 257368 kb
Host smart-2ea2fc34-de5d-4636-aa37-46c1caa9ba1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953936006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_all.1953936006
Directory /workspace/22.spi_device_flash_all/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm.2194538699
Short name T921
Test name
Test status
Simulation time 97351800118 ps
CPU time 489.08 seconds
Started Jul 07 05:29:34 PM PDT 24
Finished Jul 07 05:37:43 PM PDT 24
Peak memory 255536 kb
Host smart-cb8a1d36-e73d-4765-877b-29e448c46799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2194538699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm.2194538699
Directory /workspace/22.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/22.spi_device_flash_and_tpm_min_idle.1995634819
Short name T940
Test name
Test status
Simulation time 153095093634 ps
CPU time 144.11 seconds
Started Jul 07 05:29:28 PM PDT 24
Finished Jul 07 05:31:52 PM PDT 24
Peak memory 241072 kb
Host smart-97f16b28-72ad-460b-90f9-2e1812a2523e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995634819 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_and_tpm_min_idl
e.1995634819
Directory /workspace/22.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/22.spi_device_flash_mode.1330459475
Short name T776
Test name
Test status
Simulation time 2350567869 ps
CPU time 8.55 seconds
Started Jul 07 05:29:27 PM PDT 24
Finished Jul 07 05:29:36 PM PDT 24
Peak memory 232780 kb
Host smart-b4646eb6-c582-41bf-9fee-ccb9f2931f02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330459475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_flash_mode.1330459475
Directory /workspace/22.spi_device_flash_mode/latest

Test location /workspace/coverage/default/22.spi_device_intercept.2818581791
Short name T947
Test name
Test status
Simulation time 345513914 ps
CPU time 3.52 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:34 PM PDT 24
Peak memory 224492 kb
Host smart-25717592-ad98-4c1c-84e0-e309b7cce64b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818581791 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_intercept.2818581791
Directory /workspace/22.spi_device_intercept/latest

Test location /workspace/coverage/default/22.spi_device_mailbox.255961385
Short name T797
Test name
Test status
Simulation time 13360394339 ps
CPU time 35.84 seconds
Started Jul 07 05:29:25 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 240756 kb
Host smart-66dd60c2-a263-4fdb-88f8-e37de14d7506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255961385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_mailbox.255961385
Directory /workspace/22.spi_device_mailbox/latest

Test location /workspace/coverage/default/22.spi_device_pass_addr_payload_swap.1427784829
Short name T592
Test name
Test status
Simulation time 798075491 ps
CPU time 6.61 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:34 PM PDT 24
Peak memory 224436 kb
Host smart-aef5fa5e-038a-40d4-85cb-96827287e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427784829 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_addr_payload_swa
p.1427784829
Directory /workspace/22.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/22.spi_device_pass_cmd_filtering.2652458928
Short name T995
Test name
Test status
Simulation time 9990123893 ps
CPU time 9.5 seconds
Started Jul 07 05:29:28 PM PDT 24
Finished Jul 07 05:29:38 PM PDT 24
Peak memory 232840 kb
Host smart-6429f842-d572-4b49-9e5b-3ec6eb9de623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652458928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_pass_cmd_filtering.2652458928
Directory /workspace/22.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/22.spi_device_read_buffer_direct.138626682
Short name T427
Test name
Test status
Simulation time 5761988555 ps
CPU time 16.39 seconds
Started Jul 07 05:29:49 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 219036 kb
Host smart-37e95687-1fc8-4881-90f9-de2d2d0ebb50
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=138626682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_read_buffer_dire
ct.138626682
Directory /workspace/22.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/22.spi_device_stress_all.1971362662
Short name T904
Test name
Test status
Simulation time 49088754 ps
CPU time 1.01 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 207636 kb
Host smart-5cfdd8bb-6f6f-4b28-ab4b-132a04155107
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971362662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_stre
ss_all.1971362662
Directory /workspace/22.spi_device_stress_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_all.261188018
Short name T897
Test name
Test status
Simulation time 6713954699 ps
CPU time 27.29 seconds
Started Jul 07 05:29:46 PM PDT 24
Finished Jul 07 05:30:13 PM PDT 24
Peak memory 216328 kb
Host smart-5132934f-432b-41a4-9fd4-33301493a366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261188018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_all.261188018
Directory /workspace/22.spi_device_tpm_all/latest

Test location /workspace/coverage/default/22.spi_device_tpm_read_hw_reg.649515043
Short name T407
Test name
Test status
Simulation time 7656131981 ps
CPU time 13.73 seconds
Started Jul 07 05:29:22 PM PDT 24
Finished Jul 07 05:29:37 PM PDT 24
Peak memory 216300 kb
Host smart-90e118c6-c91d-4ada-a6c0-25b7ac61abc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649515043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_read_hw_reg.649515043
Directory /workspace/22.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/22.spi_device_tpm_rw.2745446274
Short name T784
Test name
Test status
Simulation time 231900291 ps
CPU time 1.32 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:28 PM PDT 24
Peak memory 216216 kb
Host smart-db41551e-fa7a-416a-9ba7-0fe964e92d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745446274 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_rw.2745446274
Directory /workspace/22.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/22.spi_device_tpm_sts_read.3248211185
Short name T368
Test name
Test status
Simulation time 63483806 ps
CPU time 0.89 seconds
Started Jul 07 05:29:49 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 205972 kb
Host smart-60efc74e-cb18-403b-af36-b2557cf745ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3248211185 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_tpm_sts_read.3248211185
Directory /workspace/22.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/22.spi_device_upload.829030658
Short name T388
Test name
Test status
Simulation time 780079409 ps
CPU time 2.61 seconds
Started Jul 07 05:29:20 PM PDT 24
Finished Jul 07 05:29:24 PM PDT 24
Peak memory 224504 kb
Host smart-0da8292f-f7b4-401b-b9f9-df861e5055b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829030658 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.spi_device_upload.829030658
Directory /workspace/22.spi_device_upload/latest

Test location /workspace/coverage/default/23.spi_device_alert_test.2111510662
Short name T347
Test name
Test status
Simulation time 42999399 ps
CPU time 0.74 seconds
Started Jul 07 05:29:32 PM PDT 24
Finished Jul 07 05:29:33 PM PDT 24
Peak memory 205920 kb
Host smart-63cf7091-80c2-457b-ad7e-89228cde4757
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111510662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_alert_test.
2111510662
Directory /workspace/23.spi_device_alert_test/latest

Test location /workspace/coverage/default/23.spi_device_cfg_cmd.1827472281
Short name T815
Test name
Test status
Simulation time 560204936 ps
CPU time 8.07 seconds
Started Jul 07 05:29:21 PM PDT 24
Finished Jul 07 05:29:31 PM PDT 24
Peak memory 232680 kb
Host smart-857d6cd0-5135-4bad-87b0-b2e6846b6edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827472281 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_cfg_cmd.1827472281
Directory /workspace/23.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/23.spi_device_csb_read.2801850611
Short name T410
Test name
Test status
Simulation time 212626724 ps
CPU time 0.73 seconds
Started Jul 07 05:29:28 PM PDT 24
Finished Jul 07 05:29:29 PM PDT 24
Peak memory 205516 kb
Host smart-44b8c07d-ca7d-4126-8d5a-770f79c9c341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801850611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_csb_read.2801850611
Directory /workspace/23.spi_device_csb_read/latest

Test location /workspace/coverage/default/23.spi_device_flash_all.1400006044
Short name T433
Test name
Test status
Simulation time 2407630913 ps
CPU time 53.2 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:30:23 PM PDT 24
Peak memory 249160 kb
Host smart-86f22ece-b308-40e5-a798-33b20fc52af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1400006044 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_all.1400006044
Directory /workspace/23.spi_device_flash_all/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm.2954765318
Short name T974
Test name
Test status
Simulation time 76806028283 ps
CPU time 196.18 seconds
Started Jul 07 05:29:37 PM PDT 24
Finished Jul 07 05:32:53 PM PDT 24
Peak memory 252240 kb
Host smart-a2016e95-1eb1-4781-a780-e31c9d2bd0a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954765318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm.2954765318
Directory /workspace/23.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/23.spi_device_flash_and_tpm_min_idle.363749752
Short name T589
Test name
Test status
Simulation time 47853405005 ps
CPU time 42.54 seconds
Started Jul 07 05:29:42 PM PDT 24
Finished Jul 07 05:30:25 PM PDT 24
Peak memory 217604 kb
Host smart-f7189d41-f1b3-43ae-b625-5c53fad1d44b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=363749752 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_and_tpm_min_idle
.363749752
Directory /workspace/23.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/23.spi_device_flash_mode.2315715612
Short name T8
Test name
Test status
Simulation time 320867298 ps
CPU time 3.05 seconds
Started Jul 07 05:29:24 PM PDT 24
Finished Jul 07 05:29:28 PM PDT 24
Peak memory 224440 kb
Host smart-5cd1e29e-aee1-40ed-a014-74ce57b8a37c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315715612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_flash_mode.2315715612
Directory /workspace/23.spi_device_flash_mode/latest

Test location /workspace/coverage/default/23.spi_device_intercept.1231787199
Short name T450
Test name
Test status
Simulation time 2766641016 ps
CPU time 9.48 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:37 PM PDT 24
Peak memory 224508 kb
Host smart-d90a45a8-9e11-4cdb-acba-074bc8a25054
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231787199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_intercept.1231787199
Directory /workspace/23.spi_device_intercept/latest

Test location /workspace/coverage/default/23.spi_device_mailbox.2673778369
Short name T736
Test name
Test status
Simulation time 3409273916 ps
CPU time 14.85 seconds
Started Jul 07 05:29:33 PM PDT 24
Finished Jul 07 05:29:53 PM PDT 24
Peak memory 232848 kb
Host smart-71b6a688-95fc-46b5-9a1b-7e81e1a4b134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673778369 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_mailbox.2673778369
Directory /workspace/23.spi_device_mailbox/latest

Test location /workspace/coverage/default/23.spi_device_pass_addr_payload_swap.2422147832
Short name T232
Test name
Test status
Simulation time 46092846485 ps
CPU time 27.37 seconds
Started Jul 07 05:29:19 PM PDT 24
Finished Jul 07 05:29:48 PM PDT 24
Peak memory 224572 kb
Host smart-d7ccad08-f324-4663-9c26-76edb3021856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2422147832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_addr_payload_swa
p.2422147832
Directory /workspace/23.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/23.spi_device_pass_cmd_filtering.1885406029
Short name T502
Test name
Test status
Simulation time 25879916965 ps
CPU time 8.34 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:35 PM PDT 24
Peak memory 224580 kb
Host smart-6afc70bd-768a-442f-9792-69bea6efa00d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1885406029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_pass_cmd_filtering.1885406029
Directory /workspace/23.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/23.spi_device_read_buffer_direct.2106431286
Short name T873
Test name
Test status
Simulation time 1795176206 ps
CPU time 24.63 seconds
Started Jul 07 05:29:29 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 218864 kb
Host smart-cd5d2821-b586-4b74-82a4-17955b707cde
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2106431286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_read_buffer_dir
ect.2106431286
Directory /workspace/23.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/23.spi_device_stress_all.2153467203
Short name T35
Test name
Test status
Simulation time 21982871123 ps
CPU time 160.32 seconds
Started Jul 07 05:29:25 PM PDT 24
Finished Jul 07 05:32:06 PM PDT 24
Peak memory 249164 kb
Host smart-8fe4b3f4-b1b1-4a9e-8a3e-5603f18ed11e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153467203 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_stre
ss_all.2153467203
Directory /workspace/23.spi_device_stress_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_all.2351546457
Short name T74
Test name
Test status
Simulation time 2081256421 ps
CPU time 12.31 seconds
Started Jul 07 05:29:38 PM PDT 24
Finished Jul 07 05:29:51 PM PDT 24
Peak memory 216344 kb
Host smart-d7ae3779-a187-49b8-a1f6-ccd870292057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2351546457 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_all.2351546457
Directory /workspace/23.spi_device_tpm_all/latest

Test location /workspace/coverage/default/23.spi_device_tpm_read_hw_reg.1346014105
Short name T965
Test name
Test status
Simulation time 2693106920 ps
CPU time 7.2 seconds
Started Jul 07 05:29:27 PM PDT 24
Finished Jul 07 05:29:35 PM PDT 24
Peak memory 216348 kb
Host smart-a8f2ca1c-d25d-483a-8de0-1c052aee811a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1346014105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_read_hw_reg.1346014105
Directory /workspace/23.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/23.spi_device_tpm_rw.586476472
Short name T30
Test name
Test status
Simulation time 36368684 ps
CPU time 1.79 seconds
Started Jul 07 05:29:26 PM PDT 24
Finished Jul 07 05:29:29 PM PDT 24
Peak memory 216240 kb
Host smart-ec2bb1b6-7acf-47ec-a67a-e9070c609264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586476472 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_rw.586476472
Directory /workspace/23.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/23.spi_device_tpm_sts_read.2894670663
Short name T390
Test name
Test status
Simulation time 92230004 ps
CPU time 0.75 seconds
Started Jul 07 05:29:25 PM PDT 24
Finished Jul 07 05:29:27 PM PDT 24
Peak memory 205996 kb
Host smart-fec3d150-86c6-4210-b833-264d7de2bec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894670663 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_tpm_sts_read.2894670663
Directory /workspace/23.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/23.spi_device_upload.3862822319
Short name T442
Test name
Test status
Simulation time 10136194532 ps
CPU time 31.31 seconds
Started Jul 07 05:29:38 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 224552 kb
Host smart-38f61d8b-690b-4704-9847-d8b889d0a33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862822319 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.spi_device_upload.3862822319
Directory /workspace/23.spi_device_upload/latest

Test location /workspace/coverage/default/24.spi_device_alert_test.278079221
Short name T683
Test name
Test status
Simulation time 32125517 ps
CPU time 0.69 seconds
Started Jul 07 05:29:39 PM PDT 24
Finished Jul 07 05:29:40 PM PDT 24
Peak memory 205800 kb
Host smart-c2b71016-bd4f-42bf-a9a1-ddef035f48e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278079221 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_alert_test.278079221
Directory /workspace/24.spi_device_alert_test/latest

Test location /workspace/coverage/default/24.spi_device_cfg_cmd.2848493548
Short name T548
Test name
Test status
Simulation time 115175789 ps
CPU time 2.51 seconds
Started Jul 07 05:29:43 PM PDT 24
Finished Jul 07 05:29:45 PM PDT 24
Peak memory 232340 kb
Host smart-9cc75932-a47e-46c2-81a7-00305d1c361e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848493548 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_cfg_cmd.2848493548
Directory /workspace/24.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/24.spi_device_csb_read.4219080647
Short name T737
Test name
Test status
Simulation time 79431017 ps
CPU time 0.78 seconds
Started Jul 07 05:29:24 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 206592 kb
Host smart-d384797a-63dd-4b09-98c0-6fdaa9664458
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219080647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_csb_read.4219080647
Directory /workspace/24.spi_device_csb_read/latest

Test location /workspace/coverage/default/24.spi_device_flash_all.2189565126
Short name T693
Test name
Test status
Simulation time 4350449470 ps
CPU time 19.29 seconds
Started Jul 07 05:29:28 PM PDT 24
Finished Jul 07 05:29:48 PM PDT 24
Peak memory 224604 kb
Host smart-506105bd-1c03-45f8-a305-df1865beb7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189565126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_all.2189565126
Directory /workspace/24.spi_device_flash_all/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm.3232808248
Short name T276
Test name
Test status
Simulation time 79204684419 ps
CPU time 192.69 seconds
Started Jul 07 05:29:33 PM PDT 24
Finished Jul 07 05:32:46 PM PDT 24
Peak memory 255296 kb
Host smart-d188baf6-60b9-4b2d-bafa-9d2c044b132a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232808248 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm.3232808248
Directory /workspace/24.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/24.spi_device_flash_and_tpm_min_idle.778766030
Short name T618
Test name
Test status
Simulation time 3457669950 ps
CPU time 43.09 seconds
Started Jul 07 05:29:42 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 257464 kb
Host smart-eac5b475-e853-4e7c-9b81-74b546869778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778766030 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_and_tpm_min_idle
.778766030
Directory /workspace/24.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode.2520343585
Short name T239
Test name
Test status
Simulation time 100001691 ps
CPU time 4.18 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:29:55 PM PDT 24
Peak memory 240888 kb
Host smart-79103c8d-ab80-4586-96a5-27558233fd76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520343585 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode.2520343585
Directory /workspace/24.spi_device_flash_mode/latest

Test location /workspace/coverage/default/24.spi_device_flash_mode_ignore_cmds.1504966239
Short name T842
Test name
Test status
Simulation time 23869086087 ps
CPU time 109.29 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:31:39 PM PDT 24
Peak memory 255352 kb
Host smart-f2dbe861-658f-4db0-93bb-b6be3f0277af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504966239 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_flash_mode_ignore_cmd
s.1504966239
Directory /workspace/24.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/24.spi_device_intercept.2833048231
Short name T263
Test name
Test status
Simulation time 9741244788 ps
CPU time 21.75 seconds
Started Jul 07 05:29:38 PM PDT 24
Finished Jul 07 05:30:00 PM PDT 24
Peak memory 224504 kb
Host smart-bc019146-a5d5-4e43-a921-ab5855cfcaf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833048231 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_intercept.2833048231
Directory /workspace/24.spi_device_intercept/latest

Test location /workspace/coverage/default/24.spi_device_mailbox.2727688041
Short name T663
Test name
Test status
Simulation time 1149309641 ps
CPU time 9.47 seconds
Started Jul 07 05:29:41 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 224396 kb
Host smart-624fccc4-d992-49ef-b4a3-16c74db28253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2727688041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_mailbox.2727688041
Directory /workspace/24.spi_device_mailbox/latest

Test location /workspace/coverage/default/24.spi_device_pass_addr_payload_swap.1621156458
Short name T925
Test name
Test status
Simulation time 3097257109 ps
CPU time 12.68 seconds
Started Jul 07 05:29:51 PM PDT 24
Finished Jul 07 05:30:05 PM PDT 24
Peak memory 232744 kb
Host smart-c266346b-fb44-4664-a491-a80daef5d5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1621156458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_addr_payload_swa
p.1621156458
Directory /workspace/24.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/24.spi_device_pass_cmd_filtering.3167258498
Short name T650
Test name
Test status
Simulation time 273361615 ps
CPU time 3.47 seconds
Started Jul 07 05:29:44 PM PDT 24
Finished Jul 07 05:29:48 PM PDT 24
Peak memory 232608 kb
Host smart-7483bc82-56be-4e1f-8012-c8f5a0822ed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167258498 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_pass_cmd_filtering.3167258498
Directory /workspace/24.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/24.spi_device_read_buffer_direct.3670365247
Short name T723
Test name
Test status
Simulation time 24375432331 ps
CPU time 12.86 seconds
Started Jul 07 05:29:55 PM PDT 24
Finished Jul 07 05:30:08 PM PDT 24
Peak memory 220292 kb
Host smart-54f050b5-a7a6-4caf-9694-f2c24dd092e8
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3670365247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_read_buffer_dir
ect.3670365247
Directory /workspace/24.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/24.spi_device_stress_all.1058393099
Short name T607
Test name
Test status
Simulation time 132636078 ps
CPU time 0.93 seconds
Started Jul 07 05:29:45 PM PDT 24
Finished Jul 07 05:29:46 PM PDT 24
Peak memory 207012 kb
Host smart-16f3c6b6-0738-4a95-8760-2e3c3f7f8a98
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058393099 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_stre
ss_all.1058393099
Directory /workspace/24.spi_device_stress_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_all.2341026127
Short name T380
Test name
Test status
Simulation time 808818271 ps
CPU time 4.17 seconds
Started Jul 07 05:29:25 PM PDT 24
Finished Jul 07 05:29:30 PM PDT 24
Peak memory 216208 kb
Host smart-d94cfbc3-b582-4a65-9ea7-d00bb31c38ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341026127 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_all.2341026127
Directory /workspace/24.spi_device_tpm_all/latest

Test location /workspace/coverage/default/24.spi_device_tpm_read_hw_reg.237275219
Short name T89
Test name
Test status
Simulation time 1459175069 ps
CPU time 6.7 seconds
Started Jul 07 05:29:23 PM PDT 24
Finished Jul 07 05:29:31 PM PDT 24
Peak memory 216448 kb
Host smart-45d37051-5233-414b-ba8f-9579c0fbdb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237275219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_read_hw_reg.237275219
Directory /workspace/24.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/24.spi_device_tpm_rw.2481483908
Short name T1003
Test name
Test status
Simulation time 1095243862 ps
CPU time 3.65 seconds
Started Jul 07 05:29:20 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 216472 kb
Host smart-ec6e1933-2e84-42f6-ac04-e5d0d54a4124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481483908 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_rw.2481483908
Directory /workspace/24.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/24.spi_device_tpm_sts_read.3754944154
Short name T376
Test name
Test status
Simulation time 90875151 ps
CPU time 0.85 seconds
Started Jul 07 05:29:24 PM PDT 24
Finished Jul 07 05:29:26 PM PDT 24
Peak memory 206944 kb
Host smart-2045c508-e8a7-4d29-8120-e95e05976c71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754944154 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_tpm_sts_read.3754944154
Directory /workspace/24.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/24.spi_device_upload.2364360904
Short name T569
Test name
Test status
Simulation time 123757384 ps
CPU time 2.58 seconds
Started Jul 07 05:29:40 PM PDT 24
Finished Jul 07 05:29:43 PM PDT 24
Peak memory 224436 kb
Host smart-cfe56ade-95a8-4f1c-a544-87f387051134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364360904 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.spi_device_upload.2364360904
Directory /workspace/24.spi_device_upload/latest

Test location /workspace/coverage/default/25.spi_device_alert_test.3030725124
Short name T700
Test name
Test status
Simulation time 25359754 ps
CPU time 0.74 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:01 PM PDT 24
Peak memory 205576 kb
Host smart-cacb1b9f-b77a-40b0-a67f-734b0dc7dade
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030725124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_alert_test.
3030725124
Directory /workspace/25.spi_device_alert_test/latest

Test location /workspace/coverage/default/25.spi_device_cfg_cmd.1604262126
Short name T251
Test name
Test status
Simulation time 543548357 ps
CPU time 4.23 seconds
Started Jul 07 05:29:41 PM PDT 24
Finished Jul 07 05:29:45 PM PDT 24
Peak memory 224436 kb
Host smart-30947e4c-0e5a-4f42-8dd0-d2a78c5f3382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604262126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_cfg_cmd.1604262126
Directory /workspace/25.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/25.spi_device_csb_read.3710457060
Short name T561
Test name
Test status
Simulation time 36560613 ps
CPU time 0.8 seconds
Started Jul 07 05:29:32 PM PDT 24
Finished Jul 07 05:29:33 PM PDT 24
Peak memory 206580 kb
Host smart-cdda8db0-54ea-46e3-86b4-44d4985f81de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3710457060 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_csb_read.3710457060
Directory /workspace/25.spi_device_csb_read/latest

Test location /workspace/coverage/default/25.spi_device_flash_all.2061009532
Short name T428
Test name
Test status
Simulation time 3523126317 ps
CPU time 25.18 seconds
Started Jul 07 05:29:52 PM PDT 24
Finished Jul 07 05:30:18 PM PDT 24
Peak memory 257296 kb
Host smart-68873c2f-be6e-4278-85ee-572de9f22e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061009532 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_all.2061009532
Directory /workspace/25.spi_device_flash_all/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm.1277575935
Short name T473
Test name
Test status
Simulation time 3301437812 ps
CPU time 75.95 seconds
Started Jul 07 05:29:43 PM PDT 24
Finished Jul 07 05:30:59 PM PDT 24
Peak memory 249212 kb
Host smart-f1f567d6-4729-4111-9738-5746a96c22ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277575935 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm.1277575935
Directory /workspace/25.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/25.spi_device_flash_and_tpm_min_idle.361618538
Short name T397
Test name
Test status
Simulation time 9535234184 ps
CPU time 88.09 seconds
Started Jul 07 05:29:55 PM PDT 24
Finished Jul 07 05:31:23 PM PDT 24
Peak memory 241068 kb
Host smart-69d91f0f-d8a0-4139-94f2-439ddcd46b28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361618538 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_and_tpm_min_idle
.361618538
Directory /workspace/25.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode.977156852
Short name T656
Test name
Test status
Simulation time 88832084 ps
CPU time 2.78 seconds
Started Jul 07 05:29:41 PM PDT 24
Finished Jul 07 05:29:44 PM PDT 24
Peak memory 224448 kb
Host smart-5babedaf-bc1d-4452-b3ca-839365d31bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977156852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode.977156852
Directory /workspace/25.spi_device_flash_mode/latest

Test location /workspace/coverage/default/25.spi_device_flash_mode_ignore_cmds.2030040571
Short name T764
Test name
Test status
Simulation time 15156926136 ps
CPU time 100.21 seconds
Started Jul 07 05:29:46 PM PDT 24
Finished Jul 07 05:31:26 PM PDT 24
Peak memory 249364 kb
Host smart-5c9de313-5d31-4987-b0b4-16c1dc8da467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030040571 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_flash_mode_ignore_cmd
s.2030040571
Directory /workspace/25.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/25.spi_device_intercept.1077130877
Short name T459
Test name
Test status
Simulation time 695112625 ps
CPU time 4.31 seconds
Started Jul 07 05:29:49 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 232712 kb
Host smart-0f96b562-d662-48a0-a5c7-0d0744381d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077130877 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_intercept.1077130877
Directory /workspace/25.spi_device_intercept/latest

Test location /workspace/coverage/default/25.spi_device_mailbox.717164831
Short name T913
Test name
Test status
Simulation time 3845547968 ps
CPU time 7.71 seconds
Started Jul 07 05:29:40 PM PDT 24
Finished Jul 07 05:29:48 PM PDT 24
Peak memory 224500 kb
Host smart-44b5f3ce-5edd-4442-b996-8318737bc836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=717164831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_mailbox.717164831
Directory /workspace/25.spi_device_mailbox/latest

Test location /workspace/coverage/default/25.spi_device_pass_addr_payload_swap.388551500
Short name T267
Test name
Test status
Simulation time 4497239031 ps
CPU time 8.03 seconds
Started Jul 07 05:29:29 PM PDT 24
Finished Jul 07 05:29:37 PM PDT 24
Peak memory 232780 kb
Host smart-1afd65d1-a4e1-42a2-868f-367b57efaaad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388551500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_addr_payload_swap
.388551500
Directory /workspace/25.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/25.spi_device_pass_cmd_filtering.575338969
Short name T7
Test name
Test status
Simulation time 625462878 ps
CPU time 2.19 seconds
Started Jul 07 05:30:03 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 224464 kb
Host smart-f8612f18-e71f-4c38-b96f-62fd52d340a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=575338969 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_pass_cmd_filtering.575338969
Directory /workspace/25.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/25.spi_device_read_buffer_direct.3606432682
Short name T501
Test name
Test status
Simulation time 2609800936 ps
CPU time 8.53 seconds
Started Jul 07 05:29:49 PM PDT 24
Finished Jul 07 05:29:58 PM PDT 24
Peak memory 219088 kb
Host smart-9f41d498-9a2e-4b0f-a4ab-45bc434a89e6
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3606432682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_read_buffer_dir
ect.3606432682
Directory /workspace/25.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/25.spi_device_stress_all.2009695425
Short name T377
Test name
Test status
Simulation time 116473023 ps
CPU time 0.84 seconds
Started Jul 07 05:29:51 PM PDT 24
Finished Jul 07 05:29:53 PM PDT 24
Peak memory 205668 kb
Host smart-178954a2-10f7-4d47-80e3-edb62177d523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009695425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_stre
ss_all.2009695425
Directory /workspace/25.spi_device_stress_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_all.2606715925
Short name T75
Test name
Test status
Simulation time 4072660718 ps
CPU time 27.6 seconds
Started Jul 07 05:29:31 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 216324 kb
Host smart-4ae059e1-4c81-4703-92bf-9eaf19586e2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606715925 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_all.2606715925
Directory /workspace/25.spi_device_tpm_all/latest

Test location /workspace/coverage/default/25.spi_device_tpm_read_hw_reg.760393111
Short name T422
Test name
Test status
Simulation time 4062818958 ps
CPU time 5.41 seconds
Started Jul 07 05:29:31 PM PDT 24
Finished Jul 07 05:29:37 PM PDT 24
Peak memory 216376 kb
Host smart-409ace35-e222-455a-82c9-81d27fc525b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760393111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_read_hw_reg.760393111
Directory /workspace/25.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/25.spi_device_tpm_rw.1341669784
Short name T531
Test name
Test status
Simulation time 168930582 ps
CPU time 1.7 seconds
Started Jul 07 05:29:42 PM PDT 24
Finished Jul 07 05:29:44 PM PDT 24
Peak memory 216260 kb
Host smart-75ee0d2a-ab52-4791-b457-f6de3c2be809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341669784 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_rw.1341669784
Directory /workspace/25.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/25.spi_device_tpm_sts_read.605671009
Short name T128
Test name
Test status
Simulation time 37070585 ps
CPU time 0.85 seconds
Started Jul 07 05:29:30 PM PDT 24
Finished Jul 07 05:29:32 PM PDT 24
Peak memory 205948 kb
Host smart-8d7d54e3-4112-47d4-980f-e1498c78f78c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=605671009 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_tpm_sts_read.605671009
Directory /workspace/25.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/25.spi_device_upload.3135710773
Short name T957
Test name
Test status
Simulation time 1865483257 ps
CPU time 9.72 seconds
Started Jul 07 05:29:46 PM PDT 24
Finished Jul 07 05:29:56 PM PDT 24
Peak memory 232612 kb
Host smart-04cc1ea4-3a9c-4c84-b4f6-c6355664393f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135710773 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.spi_device_upload.3135710773
Directory /workspace/25.spi_device_upload/latest

Test location /workspace/coverage/default/26.spi_device_alert_test.4189869488
Short name T843
Test name
Test status
Simulation time 15091978 ps
CPU time 0.75 seconds
Started Jul 07 05:30:01 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 205560 kb
Host smart-d15d578e-9756-49fa-9474-bd1930d65d50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189869488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_alert_test.
4189869488
Directory /workspace/26.spi_device_alert_test/latest

Test location /workspace/coverage/default/26.spi_device_cfg_cmd.3080487317
Short name T253
Test name
Test status
Simulation time 45769843 ps
CPU time 2.95 seconds
Started Jul 07 05:29:47 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 232936 kb
Host smart-1bc28864-41fe-4026-9e93-6ebdc0575e20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080487317 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_cfg_cmd.3080487317
Directory /workspace/26.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/26.spi_device_csb_read.2949985679
Short name T545
Test name
Test status
Simulation time 52426266 ps
CPU time 0.78 seconds
Started Jul 07 05:29:52 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 206596 kb
Host smart-b6fcfa5e-1143-4937-93d2-033e1878ec3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2949985679 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_csb_read.2949985679
Directory /workspace/26.spi_device_csb_read/latest

Test location /workspace/coverage/default/26.spi_device_flash_all.2386119794
Short name T812
Test name
Test status
Simulation time 55001054181 ps
CPU time 87.89 seconds
Started Jul 07 05:29:33 PM PDT 24
Finished Jul 07 05:31:02 PM PDT 24
Peak memory 240948 kb
Host smart-af72a476-bf45-4cfc-85dd-b1666615b9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2386119794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_all.2386119794
Directory /workspace/26.spi_device_flash_all/latest

Test location /workspace/coverage/default/26.spi_device_flash_and_tpm_min_idle.3976131577
Short name T803
Test name
Test status
Simulation time 4846921609 ps
CPU time 55.44 seconds
Started Jul 07 05:29:51 PM PDT 24
Finished Jul 07 05:30:48 PM PDT 24
Peak memory 252436 kb
Host smart-1645b0f5-f80b-41b9-bde1-61909d58f2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976131577 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_and_tpm_min_idl
e.3976131577
Directory /workspace/26.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode.653204251
Short name T770
Test name
Test status
Simulation time 5059935438 ps
CPU time 12.81 seconds
Started Jul 07 05:29:44 PM PDT 24
Finished Jul 07 05:29:57 PM PDT 24
Peak memory 223820 kb
Host smart-7d54e1b8-d129-4647-86b2-e01e99f206f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653204251 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode.653204251
Directory /workspace/26.spi_device_flash_mode/latest

Test location /workspace/coverage/default/26.spi_device_flash_mode_ignore_cmds.3496532674
Short name T295
Test name
Test status
Simulation time 10903929841 ps
CPU time 140.35 seconds
Started Jul 07 05:29:43 PM PDT 24
Finished Jul 07 05:32:04 PM PDT 24
Peak memory 268340 kb
Host smart-249a3e04-85ff-41ea-8e36-ad50d1e3e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496532674 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_flash_mode_ignore_cmd
s.3496532674
Directory /workspace/26.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/26.spi_device_intercept.537121647
Short name T474
Test name
Test status
Simulation time 2245389822 ps
CPU time 19.71 seconds
Started Jul 07 05:29:44 PM PDT 24
Finished Jul 07 05:30:04 PM PDT 24
Peak memory 232736 kb
Host smart-a1b0a3bb-6ac2-47f8-92f4-688948a673a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537121647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_intercept.537121647
Directory /workspace/26.spi_device_intercept/latest

Test location /workspace/coverage/default/26.spi_device_mailbox.3866531226
Short name T210
Test name
Test status
Simulation time 4733036863 ps
CPU time 16.28 seconds
Started Jul 07 05:29:46 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 239736 kb
Host smart-acd6da8f-f93a-4fb1-b92c-0f52eeb8f60e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3866531226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_mailbox.3866531226
Directory /workspace/26.spi_device_mailbox/latest

Test location /workspace/coverage/default/26.spi_device_pass_addr_payload_swap.923913558
Short name T949
Test name
Test status
Simulation time 2733249793 ps
CPU time 10.03 seconds
Started Jul 07 05:29:48 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 232772 kb
Host smart-ba9289c4-b3fd-4fcf-a5a0-025960a3cba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923913558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_addr_payload_swap
.923913558
Directory /workspace/26.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/26.spi_device_pass_cmd_filtering.3746401004
Short name T563
Test name
Test status
Simulation time 303801231 ps
CPU time 2.94 seconds
Started Jul 07 05:29:40 PM PDT 24
Finished Jul 07 05:29:43 PM PDT 24
Peak memory 232668 kb
Host smart-bc8a47a0-6931-4406-8463-eed1c29a63cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746401004 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_pass_cmd_filtering.3746401004
Directory /workspace/26.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/26.spi_device_read_buffer_direct.3770304372
Short name T406
Test name
Test status
Simulation time 132984941 ps
CPU time 3.43 seconds
Started Jul 07 05:29:34 PM PDT 24
Finished Jul 07 05:29:42 PM PDT 24
Peak memory 222556 kb
Host smart-c0dec480-acb6-4f9b-b359-ca1c3979d76d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3770304372 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_read_buffer_dir
ect.3770304372
Directory /workspace/26.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/26.spi_device_stress_all.3866856697
Short name T673
Test name
Test status
Simulation time 55585460 ps
CPU time 1.1 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:29:55 PM PDT 24
Peak memory 207696 kb
Host smart-c3d357e3-eb27-4a7a-86e4-42ac86052493
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866856697 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_stre
ss_all.3866856697
Directory /workspace/26.spi_device_stress_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_all.2649757250
Short name T785
Test name
Test status
Simulation time 2720253311 ps
CPU time 10.09 seconds
Started Jul 07 05:29:48 PM PDT 24
Finished Jul 07 05:29:58 PM PDT 24
Peak memory 216728 kb
Host smart-b9cf2083-30e1-4b92-8b3e-b75d5ecba3aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649757250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_all.2649757250
Directory /workspace/26.spi_device_tpm_all/latest

Test location /workspace/coverage/default/26.spi_device_tpm_read_hw_reg.631679502
Short name T435
Test name
Test status
Simulation time 1245455493 ps
CPU time 6.3 seconds
Started Jul 07 05:29:51 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 216152 kb
Host smart-6ea2e0ca-a43c-4230-bd07-aabf221d1ca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631679502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_read_hw_reg.631679502
Directory /workspace/26.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/26.spi_device_tpm_rw.2827847326
Short name T762
Test name
Test status
Simulation time 51264187 ps
CPU time 1.71 seconds
Started Jul 07 05:29:44 PM PDT 24
Finished Jul 07 05:29:46 PM PDT 24
Peak memory 216304 kb
Host smart-25d183c2-82a4-4bea-89cc-66cabe7ea78a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2827847326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_rw.2827847326
Directory /workspace/26.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/26.spi_device_tpm_sts_read.2436093574
Short name T629
Test name
Test status
Simulation time 115401040 ps
CPU time 0.84 seconds
Started Jul 07 05:29:48 PM PDT 24
Finished Jul 07 05:29:49 PM PDT 24
Peak memory 205976 kb
Host smart-9f1f0017-0492-49b9-8d20-084601cc59ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436093574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_tpm_sts_read.2436093574
Directory /workspace/26.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/26.spi_device_upload.3597800260
Short name T265
Test name
Test status
Simulation time 10784397318 ps
CPU time 11.69 seconds
Started Jul 07 05:29:51 PM PDT 24
Finished Jul 07 05:30:04 PM PDT 24
Peak memory 232792 kb
Host smart-41a92b99-ddd1-4833-b22d-58fb5b14f751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3597800260 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.spi_device_upload.3597800260
Directory /workspace/26.spi_device_upload/latest

Test location /workspace/coverage/default/27.spi_device_alert_test.464197873
Short name T400
Test name
Test status
Simulation time 41507584 ps
CPU time 0.71 seconds
Started Jul 07 05:29:43 PM PDT 24
Finished Jul 07 05:29:44 PM PDT 24
Peak memory 204984 kb
Host smart-c2eeb6a1-9e9d-4826-b5b4-ff12228d83c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=464197873 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_alert_test.464197873
Directory /workspace/27.spi_device_alert_test/latest

Test location /workspace/coverage/default/27.spi_device_cfg_cmd.2121993777
Short name T684
Test name
Test status
Simulation time 69566422 ps
CPU time 2.62 seconds
Started Jul 07 05:29:45 PM PDT 24
Finished Jul 07 05:29:48 PM PDT 24
Peak memory 232340 kb
Host smart-ffc7efdb-d42c-4aff-bbd3-0cbc044de620
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121993777 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_cfg_cmd.2121993777
Directory /workspace/27.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/27.spi_device_csb_read.286258863
Short name T354
Test name
Test status
Simulation time 19983561 ps
CPU time 0.8 seconds
Started Jul 07 05:29:46 PM PDT 24
Finished Jul 07 05:29:47 PM PDT 24
Peak memory 205588 kb
Host smart-6f7cf580-c608-40fe-a46b-b406d6605b2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=286258863 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_csb_read.286258863
Directory /workspace/27.spi_device_csb_read/latest

Test location /workspace/coverage/default/27.spi_device_flash_all.2474210931
Short name T292
Test name
Test status
Simulation time 7071257245 ps
CPU time 91.86 seconds
Started Jul 07 05:29:52 PM PDT 24
Finished Jul 07 05:31:25 PM PDT 24
Peak memory 256028 kb
Host smart-4a28733d-62fb-44a8-8c46-b3e8c7d704ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474210931 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_all.2474210931
Directory /workspace/27.spi_device_flash_all/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm.3452213844
Short name T552
Test name
Test status
Simulation time 3269682953 ps
CPU time 68.92 seconds
Started Jul 07 05:29:48 PM PDT 24
Finished Jul 07 05:30:57 PM PDT 24
Peak memory 249288 kb
Host smart-7730d7b5-f60a-41d0-b4c5-0ac69083dfad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452213844 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm.3452213844
Directory /workspace/27.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/27.spi_device_flash_and_tpm_min_idle.1525088818
Short name T124
Test name
Test status
Simulation time 29359899672 ps
CPU time 130.34 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:32:01 PM PDT 24
Peak memory 256524 kb
Host smart-000a14f0-f4ef-4648-b43d-791567ae8728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525088818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_and_tpm_min_idl
e.1525088818
Directory /workspace/27.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode.2692349579
Short name T789
Test name
Test status
Simulation time 332595840 ps
CPU time 7.65 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:30:02 PM PDT 24
Peak memory 232500 kb
Host smart-2e42a820-b0b6-48f4-b73f-ace9530b5284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2692349579 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode.2692349579
Directory /workspace/27.spi_device_flash_mode/latest

Test location /workspace/coverage/default/27.spi_device_flash_mode_ignore_cmds.3531797602
Short name T187
Test name
Test status
Simulation time 17393249094 ps
CPU time 104.55 seconds
Started Jul 07 05:29:56 PM PDT 24
Finished Jul 07 05:31:41 PM PDT 24
Peak memory 232804 kb
Host smart-5032408e-b33e-4c86-bb04-df820c5e28c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531797602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_flash_mode_ignore_cmd
s.3531797602
Directory /workspace/27.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/27.spi_device_intercept.430847918
Short name T455
Test name
Test status
Simulation time 3183124574 ps
CPU time 5.71 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:29:56 PM PDT 24
Peak memory 224548 kb
Host smart-e8368a56-0804-4a9e-ad0f-8dd156f942e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430847918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_intercept.430847918
Directory /workspace/27.spi_device_intercept/latest

Test location /workspace/coverage/default/27.spi_device_mailbox.902292055
Short name T740
Test name
Test status
Simulation time 218176000 ps
CPU time 3.67 seconds
Started Jul 07 05:29:57 PM PDT 24
Finished Jul 07 05:30:01 PM PDT 24
Peak memory 224432 kb
Host smart-d2545f68-c17c-4012-9d82-7893bb675cab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=902292055 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_mailbox.902292055
Directory /workspace/27.spi_device_mailbox/latest

Test location /workspace/coverage/default/27.spi_device_pass_addr_payload_swap.2460718510
Short name T757
Test name
Test status
Simulation time 10860865718 ps
CPU time 32.75 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:30:27 PM PDT 24
Peak memory 248276 kb
Host smart-553ea92e-34c2-495d-958e-4b4112eb7e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460718510 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_addr_payload_swa
p.2460718510
Directory /workspace/27.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/27.spi_device_pass_cmd_filtering.3152845351
Short name T675
Test name
Test status
Simulation time 75468964 ps
CPU time 2.14 seconds
Started Jul 07 05:29:48 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 224108 kb
Host smart-3ce39e83-a217-4a14-98af-fa3701e792fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152845351 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_pass_cmd_filtering.3152845351
Directory /workspace/27.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/27.spi_device_read_buffer_direct.138530418
Short name T833
Test name
Test status
Simulation time 287697967 ps
CPU time 5.92 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:29:57 PM PDT 24
Peak memory 222816 kb
Host smart-17aed640-255d-4aef-8d7f-cc960ddad82a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=138530418 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_read_buffer_dire
ct.138530418
Directory /workspace/27.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/27.spi_device_stress_all.104591740
Short name T487
Test name
Test status
Simulation time 6767974783 ps
CPU time 24.93 seconds
Started Jul 07 05:29:49 PM PDT 24
Finished Jul 07 05:30:14 PM PDT 24
Peak memory 232812 kb
Host smart-f48670ec-fb10-4691-9ea2-8a9fe9395906
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104591740 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_stres
s_all.104591740
Directory /workspace/27.spi_device_stress_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_all.321795542
Short name T477
Test name
Test status
Simulation time 9776820872 ps
CPU time 17.67 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 216308 kb
Host smart-5acc4579-6a1e-42a6-b182-a947b2049bbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321795542 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_all.321795542
Directory /workspace/27.spi_device_tpm_all/latest

Test location /workspace/coverage/default/27.spi_device_tpm_read_hw_reg.3325654698
Short name T530
Test name
Test status
Simulation time 2004781560 ps
CPU time 2.19 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:29:56 PM PDT 24
Peak memory 207872 kb
Host smart-abdefea4-e53e-4856-9e03-c5b7ed3add6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3325654698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_read_hw_reg.3325654698
Directory /workspace/27.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/27.spi_device_tpm_rw.109772305
Short name T857
Test name
Test status
Simulation time 45137325 ps
CPU time 0.71 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:29:52 PM PDT 24
Peak memory 205988 kb
Host smart-bc592af1-5855-40f9-8cef-7f5fe3a7858e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109772305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_rw.109772305
Directory /workspace/27.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/27.spi_device_tpm_sts_read.440116764
Short name T411
Test name
Test status
Simulation time 18239920 ps
CPU time 0.72 seconds
Started Jul 07 05:29:49 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 205664 kb
Host smart-78193365-6550-46c7-a01e-550ec47e9a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=440116764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_tpm_sts_read.440116764
Directory /workspace/27.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/27.spi_device_upload.2238898687
Short name T132
Test name
Test status
Simulation time 917619226 ps
CPU time 2.78 seconds
Started Jul 07 05:29:51 PM PDT 24
Finished Jul 07 05:29:55 PM PDT 24
Peak memory 232660 kb
Host smart-dcc9836c-85ac-42d1-b573-8d343fc77873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2238898687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.spi_device_upload.2238898687
Directory /workspace/27.spi_device_upload/latest

Test location /workspace/coverage/default/28.spi_device_alert_test.720108007
Short name T56
Test name
Test status
Simulation time 43261965 ps
CPU time 0.75 seconds
Started Jul 07 05:29:49 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 204960 kb
Host smart-97351bed-b31b-4020-a805-2a71d8f25516
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720108007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_alert_test.720108007
Directory /workspace/28.spi_device_alert_test/latest

Test location /workspace/coverage/default/28.spi_device_cfg_cmd.1490667123
Short name T257
Test name
Test status
Simulation time 126146845 ps
CPU time 3.2 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:30:02 PM PDT 24
Peak memory 232644 kb
Host smart-8cf2f008-94f8-4269-a02c-70a3626eca1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1490667123 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_cfg_cmd.1490667123
Directory /workspace/28.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/28.spi_device_csb_read.3487769971
Short name T691
Test name
Test status
Simulation time 43754252 ps
CPU time 0.84 seconds
Started Jul 07 05:29:40 PM PDT 24
Finished Jul 07 05:29:41 PM PDT 24
Peak memory 206612 kb
Host smart-dc4af2a7-2b2b-4ba9-898c-e041a5ce21e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487769971 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_csb_read.3487769971
Directory /workspace/28.spi_device_csb_read/latest

Test location /workspace/coverage/default/28.spi_device_flash_all.2656538441
Short name T238
Test name
Test status
Simulation time 22627697033 ps
CPU time 181 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:32:56 PM PDT 24
Peak memory 250500 kb
Host smart-ec9b5559-de2a-401a-95cf-7e0eea67a5ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656538441 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_all.2656538441
Directory /workspace/28.spi_device_flash_all/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm.180598651
Short name T296
Test name
Test status
Simulation time 282461034361 ps
CPU time 711.88 seconds
Started Jul 07 05:29:52 PM PDT 24
Finished Jul 07 05:41:45 PM PDT 24
Peak memory 272748 kb
Host smart-3c7a64ba-11de-47d0-83a2-5f5075c2822c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180598651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm.180598651
Directory /workspace/28.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/28.spi_device_flash_and_tpm_min_idle.3511229143
Short name T778
Test name
Test status
Simulation time 4921562927 ps
CPU time 34.13 seconds
Started Jul 07 05:29:41 PM PDT 24
Finished Jul 07 05:30:15 PM PDT 24
Peak memory 224672 kb
Host smart-b370e96c-91a4-436c-95c2-3b583845d363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511229143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_and_tpm_min_idl
e.3511229143
Directory /workspace/28.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode.1513480916
Short name T538
Test name
Test status
Simulation time 2990240707 ps
CPU time 15.8 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:30:10 PM PDT 24
Peak memory 232816 kb
Host smart-3505ad18-30d7-4419-bb3d-86669fb8c7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1513480916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode.1513480916
Directory /workspace/28.spi_device_flash_mode/latest

Test location /workspace/coverage/default/28.spi_device_flash_mode_ignore_cmds.4164906432
Short name T174
Test name
Test status
Simulation time 11686846751 ps
CPU time 15.17 seconds
Started Jul 07 05:30:06 PM PDT 24
Finished Jul 07 05:30:22 PM PDT 24
Peak memory 251836 kb
Host smart-fd06c228-de77-4c0f-9c78-7cdb611069f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164906432 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_flash_mode_ignore_cmd
s.4164906432
Directory /workspace/28.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/28.spi_device_intercept.1481035732
Short name T81
Test name
Test status
Simulation time 4107142036 ps
CPU time 13.07 seconds
Started Jul 07 05:30:02 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 224492 kb
Host smart-5c052eb2-96bc-4fc8-8b76-91bd41c6ebca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481035732 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_intercept.1481035732
Directory /workspace/28.spi_device_intercept/latest

Test location /workspace/coverage/default/28.spi_device_mailbox.2133109604
Short name T463
Test name
Test status
Simulation time 5005213492 ps
CPU time 16.55 seconds
Started Jul 07 05:29:57 PM PDT 24
Finished Jul 07 05:30:14 PM PDT 24
Peak memory 249160 kb
Host smart-9d2ecb55-7c9e-4e78-86ab-9acb8380a1db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2133109604 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_mailbox.2133109604
Directory /workspace/28.spi_device_mailbox/latest

Test location /workspace/coverage/default/28.spi_device_pass_addr_payload_swap.295214109
Short name T831
Test name
Test status
Simulation time 152586157 ps
CPU time 3.01 seconds
Started Jul 07 05:29:52 PM PDT 24
Finished Jul 07 05:29:56 PM PDT 24
Peak memory 232608 kb
Host smart-2eb8a506-2074-4e71-89f4-942483e47b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295214109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_addr_payload_swap
.295214109
Directory /workspace/28.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/28.spi_device_pass_cmd_filtering.735115416
Short name T482
Test name
Test status
Simulation time 1002687495 ps
CPU time 8.09 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 232716 kb
Host smart-51739bc6-6ded-4306-afb0-50d3fc63be90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735115416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_pass_cmd_filtering.735115416
Directory /workspace/28.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/28.spi_device_read_buffer_direct.2273061384
Short name T127
Test name
Test status
Simulation time 688133093 ps
CPU time 7.13 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 220620 kb
Host smart-36937ba0-5d77-4884-9ae5-4c30056e6073
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2273061384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_read_buffer_dir
ect.2273061384
Directory /workspace/28.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/28.spi_device_stress_all.2959958522
Short name T161
Test name
Test status
Simulation time 3839266165 ps
CPU time 34.67 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:35 PM PDT 24
Peak memory 253720 kb
Host smart-84903bf4-4176-4445-ae69-3f9bbf5827ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959958522 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_stre
ss_all.2959958522
Directory /workspace/28.spi_device_stress_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_all.2983241437
Short name T31
Test name
Test status
Simulation time 8964580503 ps
CPU time 17.5 seconds
Started Jul 07 05:29:46 PM PDT 24
Finished Jul 07 05:30:04 PM PDT 24
Peak memory 216728 kb
Host smart-721f148e-bf40-474b-8f9f-fd8ec4146bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983241437 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_all.2983241437
Directory /workspace/28.spi_device_tpm_all/latest

Test location /workspace/coverage/default/28.spi_device_tpm_read_hw_reg.3722743910
Short name T374
Test name
Test status
Simulation time 15253167860 ps
CPU time 15.02 seconds
Started Jul 07 05:29:56 PM PDT 24
Finished Jul 07 05:30:11 PM PDT 24
Peak memory 216308 kb
Host smart-f9d50e9c-8290-4645-9c89-79e8ae013ca5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722743910 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_read_hw_reg.3722743910
Directory /workspace/28.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/28.spi_device_tpm_rw.2450647114
Short name T358
Test name
Test status
Simulation time 42543103 ps
CPU time 0.76 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 205980 kb
Host smart-60f522ef-3797-41ce-985e-572f91481f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2450647114 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_rw.2450647114
Directory /workspace/28.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/28.spi_device_tpm_sts_read.3039204903
Short name T690
Test name
Test status
Simulation time 178626696 ps
CPU time 0.81 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:29:52 PM PDT 24
Peak memory 205992 kb
Host smart-385c390f-791d-4fe4-bb2b-1527fd8c3578
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039204903 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_tpm_sts_read.3039204903
Directory /workspace/28.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/28.spi_device_upload.2938927194
Short name T935
Test name
Test status
Simulation time 4269275718 ps
CPU time 10.1 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 224540 kb
Host smart-f3105df5-2310-4775-8ee5-511a2f2ad6bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2938927194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.spi_device_upload.2938927194
Directory /workspace/28.spi_device_upload/latest

Test location /workspace/coverage/default/29.spi_device_alert_test.2585598714
Short name T1005
Test name
Test status
Simulation time 34990156 ps
CPU time 0.73 seconds
Started Jul 07 05:29:52 PM PDT 24
Finished Jul 07 05:29:53 PM PDT 24
Peak memory 205836 kb
Host smart-b994f5a5-8187-4ab5-a207-93d238cfa4c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585598714 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_alert_test.
2585598714
Directory /workspace/29.spi_device_alert_test/latest

Test location /workspace/coverage/default/29.spi_device_cfg_cmd.178255964
Short name T261
Test name
Test status
Simulation time 158008310 ps
CPU time 3.03 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 224452 kb
Host smart-33464a55-cdb8-4921-b2b6-9bb4562ec11e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=178255964 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_cfg_cmd.178255964
Directory /workspace/29.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/29.spi_device_csb_read.3491596750
Short name T568
Test name
Test status
Simulation time 17645407 ps
CPU time 0.76 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:30:00 PM PDT 24
Peak memory 205596 kb
Host smart-214792b4-f88c-4d1c-9a77-7dd04669b6ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491596750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_csb_read.3491596750
Directory /workspace/29.spi_device_csb_read/latest

Test location /workspace/coverage/default/29.spi_device_flash_all.1827703818
Short name T747
Test name
Test status
Simulation time 35804878073 ps
CPU time 268.86 seconds
Started Jul 07 05:30:02 PM PDT 24
Finished Jul 07 05:34:32 PM PDT 24
Peak memory 250968 kb
Host smart-7a0941ad-d6ad-41e6-9892-647663eda04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827703818 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_all.1827703818
Directory /workspace/29.spi_device_flash_all/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm.4199925335
Short name T701
Test name
Test status
Simulation time 86842564510 ps
CPU time 226.16 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:33:47 PM PDT 24
Peak memory 250792 kb
Host smart-5dda510f-9d57-4877-9181-d9b36f8c1276
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199925335 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm.4199925335
Directory /workspace/29.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/29.spi_device_flash_and_tpm_min_idle.3042291830
Short name T138
Test name
Test status
Simulation time 3594971476 ps
CPU time 61.26 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:30:52 PM PDT 24
Peak memory 249236 kb
Host smart-fdf55f11-bf88-4f71-a1f5-24c3265c8d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042291830 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_and_tpm_min_idl
e.3042291830
Directory /workspace/29.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode.2270828135
Short name T1002
Test name
Test status
Simulation time 9540107928 ps
CPU time 35.35 seconds
Started Jul 07 05:29:49 PM PDT 24
Finished Jul 07 05:30:25 PM PDT 24
Peak memory 232828 kb
Host smart-feb817b9-fe60-408f-b8b4-8bf76d696566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270828135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode.2270828135
Directory /workspace/29.spi_device_flash_mode/latest

Test location /workspace/coverage/default/29.spi_device_flash_mode_ignore_cmds.3725935745
Short name T42
Test name
Test status
Simulation time 226702786298 ps
CPU time 380.4 seconds
Started Jul 07 05:29:48 PM PDT 24
Finished Jul 07 05:36:09 PM PDT 24
Peak memory 254316 kb
Host smart-eab99c9e-6613-4d7f-ab2b-3ce8de3cfa54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725935745 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_flash_mode_ignore_cmd
s.3725935745
Directory /workspace/29.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/29.spi_device_intercept.471747273
Short name T750
Test name
Test status
Simulation time 2575343382 ps
CPU time 16.05 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 232796 kb
Host smart-bcddfc37-2cb5-4ce0-8277-3cbd7725eade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471747273 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_intercept.471747273
Directory /workspace/29.spi_device_intercept/latest

Test location /workspace/coverage/default/29.spi_device_mailbox.2195284348
Short name T686
Test name
Test status
Simulation time 349075816 ps
CPU time 5.54 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 232168 kb
Host smart-3836bbbb-a7a4-4460-a860-9d9b443dd019
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195284348 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_mailbox.2195284348
Directory /workspace/29.spi_device_mailbox/latest

Test location /workspace/coverage/default/29.spi_device_pass_addr_payload_swap.3700443782
Short name T5
Test name
Test status
Simulation time 16751280079 ps
CPU time 5.76 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 232800 kb
Host smart-86a6058b-ed99-4396-9a13-fb830b92d85e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3700443782 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_addr_payload_swa
p.3700443782
Directory /workspace/29.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/29.spi_device_pass_cmd_filtering.2457033240
Short name T260
Test name
Test status
Simulation time 11851671802 ps
CPU time 17.18 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 232752 kb
Host smart-52373235-bebb-4f85-a8bd-5fb69c6e7132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457033240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_pass_cmd_filtering.2457033240
Directory /workspace/29.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/29.spi_device_read_buffer_direct.3252339015
Short name T794
Test name
Test status
Simulation time 1178488646 ps
CPU time 6.31 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:07 PM PDT 24
Peak memory 221776 kb
Host smart-4d41cec3-7108-4f66-8ee0-a9b64a279920
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3252339015 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_read_buffer_dir
ect.3252339015
Directory /workspace/29.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/29.spi_device_tpm_all.992853371
Short name T929
Test name
Test status
Simulation time 3571710901 ps
CPU time 13.2 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:30:07 PM PDT 24
Peak memory 216348 kb
Host smart-dbb9c6b8-c110-4f61-b74c-dd2048ef4af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=992853371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_all.992853371
Directory /workspace/29.spi_device_tpm_all/latest

Test location /workspace/coverage/default/29.spi_device_tpm_read_hw_reg.156682269
Short name T712
Test name
Test status
Simulation time 13639507866 ps
CPU time 10.66 seconds
Started Jul 07 05:29:39 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 216336 kb
Host smart-4bebf8ce-baed-4535-90d3-5d0603bb5f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156682269 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_read_hw_reg.156682269
Directory /workspace/29.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/29.spi_device_tpm_rw.2179751340
Short name T572
Test name
Test status
Simulation time 75285376 ps
CPU time 1.02 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 206660 kb
Host smart-7742a763-5480-47a3-b58d-4fb22189beec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179751340 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_rw.2179751340
Directory /workspace/29.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/29.spi_device_tpm_sts_read.2284528190
Short name T832
Test name
Test status
Simulation time 161541131 ps
CPU time 0.76 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:01 PM PDT 24
Peak memory 205976 kb
Host smart-40e14ed9-8789-4660-8351-0e42811242fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284528190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_tpm_sts_read.2284528190
Directory /workspace/29.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/29.spi_device_upload.959535073
Short name T821
Test name
Test status
Simulation time 9968037392 ps
CPU time 5.14 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:29:57 PM PDT 24
Peak memory 232788 kb
Host smart-120f4e32-07f8-430b-9d12-0d3a4b910083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959535073 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.spi_device_upload.959535073
Directory /workspace/29.spi_device_upload/latest

Test location /workspace/coverage/default/3.spi_device_alert_test.3608561809
Short name T887
Test name
Test status
Simulation time 15123336 ps
CPU time 0.84 seconds
Started Jul 07 05:28:53 PM PDT 24
Finished Jul 07 05:28:55 PM PDT 24
Peak memory 205484 kb
Host smart-c1c0e0a4-7bf7-48ea-ae2c-58d235bf3b41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608561809 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_alert_test.3
608561809
Directory /workspace/3.spi_device_alert_test/latest

Test location /workspace/coverage/default/3.spi_device_cfg_cmd.218944052
Short name T973
Test name
Test status
Simulation time 593189731 ps
CPU time 6.74 seconds
Started Jul 07 05:28:56 PM PDT 24
Finished Jul 07 05:29:03 PM PDT 24
Peak memory 232644 kb
Host smart-cf551101-3df2-41a8-924c-948cd28235ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218944052 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_cfg_cmd.218944052
Directory /workspace/3.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/3.spi_device_csb_read.2785081640
Short name T457
Test name
Test status
Simulation time 92027050 ps
CPU time 0.84 seconds
Started Jul 07 05:28:58 PM PDT 24
Finished Jul 07 05:28:59 PM PDT 24
Peak memory 206912 kb
Host smart-26b63c82-76f1-47fd-bce6-185ba837abf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2785081640 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_csb_read.2785081640
Directory /workspace/3.spi_device_csb_read/latest

Test location /workspace/coverage/default/3.spi_device_flash_all.1464146111
Short name T481
Test name
Test status
Simulation time 40353557944 ps
CPU time 69.86 seconds
Started Jul 07 05:28:48 PM PDT 24
Finished Jul 07 05:29:58 PM PDT 24
Peak memory 249188 kb
Host smart-77dd5011-06de-4296-8bfa-686904f377f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464146111 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_all.1464146111
Directory /workspace/3.spi_device_flash_all/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm.3039315838
Short name T281
Test name
Test status
Simulation time 118944354044 ps
CPU time 320.6 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:34:18 PM PDT 24
Peak memory 254180 kb
Host smart-cc366111-6750-4814-b450-5f065455a495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039315838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm.3039315838
Directory /workspace/3.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/3.spi_device_flash_and_tpm_min_idle.641487447
Short name T751
Test name
Test status
Simulation time 3718761418 ps
CPU time 86.87 seconds
Started Jul 07 05:28:58 PM PDT 24
Finished Jul 07 05:30:25 PM PDT 24
Peak memory 272840 kb
Host smart-1955eeef-6b10-4418-88b5-a5b3b995968c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641487447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_and_tpm_min_idle.
641487447
Directory /workspace/3.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode.3146208208
Short name T416
Test name
Test status
Simulation time 257848596 ps
CPU time 4.63 seconds
Started Jul 07 05:29:02 PM PDT 24
Finished Jul 07 05:29:07 PM PDT 24
Peak memory 224480 kb
Host smart-0762a350-ff71-4071-8ff1-999c1e5b0581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3146208208 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode.3146208208
Directory /workspace/3.spi_device_flash_mode/latest

Test location /workspace/coverage/default/3.spi_device_flash_mode_ignore_cmds.142169627
Short name T465
Test name
Test status
Simulation time 13197395741 ps
CPU time 93.89 seconds
Started Jul 07 05:28:52 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 253188 kb
Host smart-e923ae84-afcf-4aa3-8d5c-35275a98c143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142169627 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_flash_mode_ignore_cmds.
142169627
Directory /workspace/3.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/3.spi_device_intercept.290391421
Short name T837
Test name
Test status
Simulation time 1768337613 ps
CPU time 8.08 seconds
Started Jul 07 05:29:04 PM PDT 24
Finished Jul 07 05:29:13 PM PDT 24
Peak memory 232512 kb
Host smart-1ffb95a2-8319-4010-be5f-315fa2c4f2f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290391421 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_intercept.290391421
Directory /workspace/3.spi_device_intercept/latest

Test location /workspace/coverage/default/3.spi_device_mailbox.1447810905
Short name T215
Test name
Test status
Simulation time 544287150 ps
CPU time 12.34 seconds
Started Jul 07 05:28:59 PM PDT 24
Finished Jul 07 05:29:12 PM PDT 24
Peak memory 232644 kb
Host smart-5da79b33-b7f2-4b04-819e-d5fd9609de42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447810905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_mailbox.1447810905
Directory /workspace/3.spi_device_mailbox/latest

Test location /workspace/coverage/default/3.spi_device_pass_addr_payload_swap.4225594612
Short name T729
Test name
Test status
Simulation time 715370555 ps
CPU time 6.23 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:39 PM PDT 24
Peak memory 224520 kb
Host smart-e90a29a0-b7e3-40cb-bea8-94833c5cf6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225594612 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_addr_payload_swap
.4225594612
Directory /workspace/3.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/3.spi_device_pass_cmd_filtering.3134407759
Short name T906
Test name
Test status
Simulation time 1574302686 ps
CPU time 7.72 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:29:14 PM PDT 24
Peak memory 227864 kb
Host smart-bfefb0ce-10c3-4c22-86d5-e9e35fad515d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134407759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_pass_cmd_filtering.3134407759
Directory /workspace/3.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/3.spi_device_read_buffer_direct.2456596181
Short name T964
Test name
Test status
Simulation time 967181159 ps
CPU time 7.22 seconds
Started Jul 07 05:28:56 PM PDT 24
Finished Jul 07 05:29:04 PM PDT 24
Peak memory 218968 kb
Host smart-881126c0-4f75-47d6-a00e-6320bd95a69e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2456596181 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_read_buffer_dire
ct.2456596181
Directory /workspace/3.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/3.spi_device_sec_cm.1948089905
Short name T70
Test name
Test status
Simulation time 198951323 ps
CPU time 1.29 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:28:52 PM PDT 24
Peak memory 237528 kb
Host smart-6c386d85-78e7-4655-b8b5-53f860537891
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948089905 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_sec_cm.1948089905
Directory /workspace/3.spi_device_sec_cm/latest

Test location /workspace/coverage/default/3.spi_device_stress_all.2169468987
Short name T160
Test name
Test status
Simulation time 70439089294 ps
CPU time 233.29 seconds
Started Jul 07 05:29:11 PM PDT 24
Finished Jul 07 05:33:05 PM PDT 24
Peak memory 262352 kb
Host smart-43e0c015-9b86-496b-95bb-a93e59c9aae2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2169468987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_stres
s_all.2169468987
Directory /workspace/3.spi_device_stress_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_all.80463029
Short name T859
Test name
Test status
Simulation time 6578959165 ps
CPU time 36.41 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:29:47 PM PDT 24
Peak memory 216424 kb
Host smart-1e76ed39-227f-4084-a00a-b027394bb024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80463029 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_all.80463029
Directory /workspace/3.spi_device_tpm_all/latest

Test location /workspace/coverage/default/3.spi_device_tpm_read_hw_reg.3118836219
Short name T615
Test name
Test status
Simulation time 20507697 ps
CPU time 0.69 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 205716 kb
Host smart-d8bf29d8-f3a0-4c58-82e0-3135ed5c82b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118836219 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_read_hw_reg.3118836219
Directory /workspace/3.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/3.spi_device_tpm_rw.1110828930
Short name T166
Test name
Test status
Simulation time 199902308 ps
CPU time 2.53 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:28:38 PM PDT 24
Peak memory 216256 kb
Host smart-f5ea9d80-16e1-44b0-bd88-42bcd51a36be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110828930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_rw.1110828930
Directory /workspace/3.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/3.spi_device_tpm_sts_read.900957399
Short name T484
Test name
Test status
Simulation time 28068747 ps
CPU time 0.78 seconds
Started Jul 07 05:28:32 PM PDT 24
Finished Jul 07 05:28:33 PM PDT 24
Peak memory 205996 kb
Host smart-7497f31a-d963-426b-8cc3-b43023105f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=900957399 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_tpm_sts_read.900957399
Directory /workspace/3.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/3.spi_device_upload.1209550318
Short name T765
Test name
Test status
Simulation time 22430447398 ps
CPU time 8.26 seconds
Started Jul 07 05:28:40 PM PDT 24
Finished Jul 07 05:28:50 PM PDT 24
Peak memory 228360 kb
Host smart-948652dc-1e37-4735-95db-02da4331effc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209550318 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.spi_device_upload.1209550318
Directory /workspace/3.spi_device_upload/latest

Test location /workspace/coverage/default/30.spi_device_alert_test.2308557137
Short name T680
Test name
Test status
Simulation time 12883916 ps
CPU time 0.71 seconds
Started Jul 07 05:29:56 PM PDT 24
Finished Jul 07 05:30:04 PM PDT 24
Peak memory 205564 kb
Host smart-ef87be86-e7a3-4274-9374-c0e6e5b7b14f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308557137 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_alert_test.
2308557137
Directory /workspace/30.spi_device_alert_test/latest

Test location /workspace/coverage/default/30.spi_device_cfg_cmd.2168901282
Short name T190
Test name
Test status
Simulation time 78964359 ps
CPU time 2.37 seconds
Started Jul 07 05:29:49 PM PDT 24
Finished Jul 07 05:29:51 PM PDT 24
Peak memory 224408 kb
Host smart-cb161af6-7060-4b04-915f-ae571116b93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168901282 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_cfg_cmd.2168901282
Directory /workspace/30.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/30.spi_device_csb_read.3978389606
Short name T937
Test name
Test status
Simulation time 42783721 ps
CPU time 0.77 seconds
Started Jul 07 05:29:52 PM PDT 24
Finished Jul 07 05:29:53 PM PDT 24
Peak memory 205864 kb
Host smart-428eb154-585b-420d-a57e-b3f82957c669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3978389606 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_csb_read.3978389606
Directory /workspace/30.spi_device_csb_read/latest

Test location /workspace/coverage/default/30.spi_device_flash_all.2802150474
Short name T52
Test name
Test status
Simulation time 3229400514 ps
CPU time 24.15 seconds
Started Jul 07 05:30:03 PM PDT 24
Finished Jul 07 05:30:29 PM PDT 24
Peak memory 224600 kb
Host smart-d7641155-e266-4fe5-a51b-888b9939c7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802150474 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_all.2802150474
Directory /workspace/30.spi_device_flash_all/latest

Test location /workspace/coverage/default/30.spi_device_flash_and_tpm_min_idle.2749785832
Short name T599
Test name
Test status
Simulation time 84003326537 ps
CPU time 199.43 seconds
Started Jul 07 05:30:02 PM PDT 24
Finished Jul 07 05:33:23 PM PDT 24
Peak memory 252864 kb
Host smart-e3f6c4bc-cd9f-4487-851f-c6f0cbd10255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2749785832 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_and_tpm_min_idl
e.2749785832
Directory /workspace/30.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode.2723435032
Short name T528
Test name
Test status
Simulation time 704085796 ps
CPU time 7.22 seconds
Started Jul 07 05:30:04 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 240808 kb
Host smart-fa16961f-0f47-4ae1-bb08-5ddca8f18ff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723435032 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode.2723435032
Directory /workspace/30.spi_device_flash_mode/latest

Test location /workspace/coverage/default/30.spi_device_flash_mode_ignore_cmds.1321847555
Short name T584
Test name
Test status
Simulation time 17429625436 ps
CPU time 126.21 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:32:21 PM PDT 24
Peak memory 252988 kb
Host smart-7026d56f-3180-4a8f-ac9a-e7ae16862fb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1321847555 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_flash_mode_ignore_cmd
s.1321847555
Directory /workspace/30.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/30.spi_device_intercept.2335827608
Short name T90
Test name
Test status
Simulation time 569981784 ps
CPU time 7.36 seconds
Started Jul 07 05:29:55 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 232636 kb
Host smart-fb586222-2e71-4e54-86ab-24e29d4e8a3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335827608 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_intercept.2335827608
Directory /workspace/30.spi_device_intercept/latest

Test location /workspace/coverage/default/30.spi_device_mailbox.3352957172
Short name T222
Test name
Test status
Simulation time 4700852079 ps
CPU time 33.26 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:34 PM PDT 24
Peak memory 236016 kb
Host smart-fe9d6531-2a61-4b08-97bf-10790909df56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352957172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_mailbox.3352957172
Directory /workspace/30.spi_device_mailbox/latest

Test location /workspace/coverage/default/30.spi_device_pass_addr_payload_swap.2770742131
Short name T302
Test name
Test status
Simulation time 465135377 ps
CPU time 6.65 seconds
Started Jul 07 05:29:50 PM PDT 24
Finished Jul 07 05:29:57 PM PDT 24
Peak memory 239848 kb
Host smart-4407f30a-0600-42a0-b117-0008623c464c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770742131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_addr_payload_swa
p.2770742131
Directory /workspace/30.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/30.spi_device_pass_cmd_filtering.1109894101
Short name T23
Test name
Test status
Simulation time 22673375009 ps
CPU time 13.17 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:30:13 PM PDT 24
Peak memory 232804 kb
Host smart-aed0ea89-d7c4-4b58-9b95-7346b4eab73f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109894101 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_pass_cmd_filtering.1109894101
Directory /workspace/30.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/30.spi_device_read_buffer_direct.669818624
Short name T881
Test name
Test status
Simulation time 916570542 ps
CPU time 10.81 seconds
Started Jul 07 05:29:56 PM PDT 24
Finished Jul 07 05:30:08 PM PDT 24
Peak memory 218796 kb
Host smart-f26dc1e0-9d4b-4969-b33a-65351c33c38b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=669818624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_read_buffer_dire
ct.669818624
Directory /workspace/30.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/30.spi_device_stress_all.489967559
Short name T1006
Test name
Test status
Simulation time 70261681 ps
CPU time 0.91 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 205672 kb
Host smart-aae4106a-d285-4cb9-b3f0-a1e04c2de2d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489967559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_stres
s_all.489967559
Directory /workspace/30.spi_device_stress_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_all.1570387443
Short name T360
Test name
Test status
Simulation time 1347265309 ps
CPU time 7.73 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:30:01 PM PDT 24
Peak memory 219940 kb
Host smart-29b3024d-9590-41b7-802b-847d2f45ebd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570387443 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_all.1570387443
Directory /workspace/30.spi_device_tpm_all/latest

Test location /workspace/coverage/default/30.spi_device_tpm_read_hw_reg.1194890028
Short name T126
Test name
Test status
Simulation time 1261580123 ps
CPU time 3.58 seconds
Started Jul 07 05:29:52 PM PDT 24
Finished Jul 07 05:29:57 PM PDT 24
Peak memory 216192 kb
Host smart-a42b2d08-8978-4966-9431-a6404e86d618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194890028 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_read_hw_reg.1194890028
Directory /workspace/30.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/30.spi_device_tpm_rw.2044076898
Short name T355
Test name
Test status
Simulation time 44361704 ps
CPU time 1.03 seconds
Started Jul 07 05:30:06 PM PDT 24
Finished Jul 07 05:30:08 PM PDT 24
Peak memory 207676 kb
Host smart-dc0ef6f0-0473-4dc9-a87a-596b512a5df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044076898 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_rw.2044076898
Directory /workspace/30.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/30.spi_device_tpm_sts_read.4229734214
Short name T980
Test name
Test status
Simulation time 69579773 ps
CPU time 0.76 seconds
Started Jul 07 05:30:01 PM PDT 24
Finished Jul 07 05:30:04 PM PDT 24
Peak memory 205928 kb
Host smart-7671a425-4999-40bb-9b1f-2bd381c46879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4229734214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_tpm_sts_read.4229734214
Directory /workspace/30.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/30.spi_device_upload.2315457361
Short name T763
Test name
Test status
Simulation time 503252856 ps
CPU time 2.41 seconds
Started Jul 07 05:29:51 PM PDT 24
Finished Jul 07 05:29:54 PM PDT 24
Peak memory 224392 kb
Host smart-14a8a89c-93e1-46e8-a519-cca7d5b1fdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2315457361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.spi_device_upload.2315457361
Directory /workspace/30.spi_device_upload/latest

Test location /workspace/coverage/default/31.spi_device_alert_test.2930356184
Short name T850
Test name
Test status
Simulation time 122181591 ps
CPU time 0.77 seconds
Started Jul 07 05:30:02 PM PDT 24
Finished Jul 07 05:30:04 PM PDT 24
Peak memory 204988 kb
Host smart-4049024d-a883-4f15-ae5f-9e4756c9c56c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930356184 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_alert_test.
2930356184
Directory /workspace/31.spi_device_alert_test/latest

Test location /workspace/coverage/default/31.spi_device_cfg_cmd.3810931096
Short name T828
Test name
Test status
Simulation time 412278346 ps
CPU time 3.56 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:29:58 PM PDT 24
Peak memory 232688 kb
Host smart-103afe94-c90c-42bc-b589-867e85059957
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810931096 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_cfg_cmd.3810931096
Directory /workspace/31.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/31.spi_device_csb_read.3196060200
Short name T348
Test name
Test status
Simulation time 13036725 ps
CPU time 0.75 seconds
Started Jul 07 05:29:48 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 206924 kb
Host smart-9d2e2c6e-abea-424c-a24c-c84542ccd721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196060200 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_csb_read.3196060200
Directory /workspace/31.spi_device_csb_read/latest

Test location /workspace/coverage/default/31.spi_device_flash_all.2860331845
Short name T936
Test name
Test status
Simulation time 11389555544 ps
CPU time 56.07 seconds
Started Jul 07 05:30:03 PM PDT 24
Finished Jul 07 05:31:00 PM PDT 24
Peak memory 236216 kb
Host smart-9667189f-b145-4008-a8a3-8caeececa413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860331845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_all.2860331845
Directory /workspace/31.spi_device_flash_all/latest

Test location /workspace/coverage/default/31.spi_device_flash_and_tpm_min_idle.580147246
Short name T930
Test name
Test status
Simulation time 38794057058 ps
CPU time 284.12 seconds
Started Jul 07 05:29:56 PM PDT 24
Finished Jul 07 05:34:40 PM PDT 24
Peak memory 257464 kb
Host smart-ddf95629-5e27-4913-8ab0-ffca242b009b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580147246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_and_tpm_min_idle
.580147246
Directory /workspace/31.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode.3157818065
Short name T662
Test name
Test status
Simulation time 3265734267 ps
CPU time 13.13 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:27 PM PDT 24
Peak memory 224492 kb
Host smart-3ea13da3-1243-4c03-9321-bfcc33e06613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157818065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode.3157818065
Directory /workspace/31.spi_device_flash_mode/latest

Test location /workspace/coverage/default/31.spi_device_flash_mode_ignore_cmds.2464966297
Short name T517
Test name
Test status
Simulation time 91155789316 ps
CPU time 166.66 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:32:48 PM PDT 24
Peak memory 254592 kb
Host smart-b71fdfae-e7e9-4105-9305-fa20c7988de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464966297 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_flash_mode_ignore_cmd
s.2464966297
Directory /workspace/31.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/31.spi_device_intercept.3082989117
Short name T802
Test name
Test status
Simulation time 5372925242 ps
CPU time 23.74 seconds
Started Jul 07 05:29:48 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 230272 kb
Host smart-03cae19a-93e8-4dfe-a983-5a28ced0dd1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082989117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_intercept.3082989117
Directory /workspace/31.spi_device_intercept/latest

Test location /workspace/coverage/default/31.spi_device_mailbox.2722262767
Short name T229
Test name
Test status
Simulation time 6156338048 ps
CPU time 11.01 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 232772 kb
Host smart-8b1e8065-860e-478f-99f0-598b4b5336bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722262767 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_mailbox.2722262767
Directory /workspace/31.spi_device_mailbox/latest

Test location /workspace/coverage/default/31.spi_device_pass_addr_payload_swap.1015346429
Short name T970
Test name
Test status
Simulation time 3241125667 ps
CPU time 4.59 seconds
Started Jul 07 05:30:01 PM PDT 24
Finished Jul 07 05:30:07 PM PDT 24
Peak memory 224556 kb
Host smart-7713850b-386a-4742-b244-405fb8c6d192
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015346429 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_addr_payload_swa
p.1015346429
Directory /workspace/31.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/31.spi_device_pass_cmd_filtering.2045692710
Short name T547
Test name
Test status
Simulation time 8474353064 ps
CPU time 8.68 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:30:08 PM PDT 24
Peak memory 224552 kb
Host smart-39493a8c-76b8-4822-b6b9-c807fba03057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045692710 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_pass_cmd_filtering.2045692710
Directory /workspace/31.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/31.spi_device_read_buffer_direct.3941506630
Short name T858
Test name
Test status
Simulation time 2020516317 ps
CPU time 12.37 seconds
Started Jul 07 05:30:05 PM PDT 24
Finished Jul 07 05:30:18 PM PDT 24
Peak memory 222056 kb
Host smart-8255602b-76e7-4a2b-9413-13857713523d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3941506630 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_read_buffer_dir
ect.3941506630
Directory /workspace/31.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/31.spi_device_stress_all.1723147980
Short name T546
Test name
Test status
Simulation time 54865084 ps
CPU time 1.02 seconds
Started Jul 07 05:29:55 PM PDT 24
Finished Jul 07 05:29:56 PM PDT 24
Peak memory 206788 kb
Host smart-891ff9a7-e50e-4e79-ae92-4559913a2769
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1723147980 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_stre
ss_all.1723147980
Directory /workspace/31.spi_device_stress_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_all.2729306315
Short name T326
Test name
Test status
Simulation time 448223637 ps
CPU time 3.44 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:29:57 PM PDT 24
Peak memory 216512 kb
Host smart-4b2727f1-5fc1-473e-a344-0401bb56e12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729306315 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_all.2729306315
Directory /workspace/31.spi_device_tpm_all/latest

Test location /workspace/coverage/default/31.spi_device_tpm_read_hw_reg.3775550994
Short name T838
Test name
Test status
Simulation time 6206887566 ps
CPU time 6.93 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:21 PM PDT 24
Peak memory 216300 kb
Host smart-83f8b16a-d371-4055-896d-e0b5e39bf6e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3775550994 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_read_hw_reg.3775550994
Directory /workspace/31.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/31.spi_device_tpm_rw.2537414155
Short name T699
Test name
Test status
Simulation time 721666154 ps
CPU time 4.34 seconds
Started Jul 07 05:30:05 PM PDT 24
Finished Jul 07 05:30:10 PM PDT 24
Peak memory 216204 kb
Host smart-0787c5c2-4a6c-4a64-a7cd-710c22cd8793
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537414155 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_rw.2537414155
Directory /workspace/31.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/31.spi_device_tpm_sts_read.598202559
Short name T646
Test name
Test status
Simulation time 56575535 ps
CPU time 0.98 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:30:02 PM PDT 24
Peak memory 206536 kb
Host smart-732990ec-d1ab-4254-b7e7-4f3e6c8eca01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=598202559 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_tpm_sts_read.598202559
Directory /workspace/31.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/31.spi_device_upload.3421874602
Short name T189
Test name
Test status
Simulation time 296349321 ps
CPU time 3.83 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 224456 kb
Host smart-f87a52d4-a525-4b2b-b735-6aaa6f5480e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421874602 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.spi_device_upload.3421874602
Directory /workspace/31.spi_device_upload/latest

Test location /workspace/coverage/default/32.spi_device_alert_test.1043938191
Short name T943
Test name
Test status
Simulation time 15669664 ps
CPU time 0.74 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:29:55 PM PDT 24
Peak memory 205880 kb
Host smart-6594254d-58ce-4c18-b516-e3844dca59f9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043938191 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_alert_test.
1043938191
Directory /workspace/32.spi_device_alert_test/latest

Test location /workspace/coverage/default/32.spi_device_cfg_cmd.3684211152
Short name T571
Test name
Test status
Simulation time 428226860 ps
CPU time 3.56 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 232632 kb
Host smart-d7bbbc1a-21ea-4098-a27a-04b279780a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684211152 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_cfg_cmd.3684211152
Directory /workspace/32.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/32.spi_device_csb_read.1251984093
Short name T894
Test name
Test status
Simulation time 74511844 ps
CPU time 0.82 seconds
Started Jul 07 05:30:01 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 206588 kb
Host smart-5de95d35-c1cc-4a4f-a9c8-c21721986bda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251984093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_csb_read.1251984093
Directory /workspace/32.spi_device_csb_read/latest

Test location /workspace/coverage/default/32.spi_device_flash_all.2925916705
Short name T783
Test name
Test status
Simulation time 159562555154 ps
CPU time 296.11 seconds
Started Jul 07 05:30:02 PM PDT 24
Finished Jul 07 05:34:59 PM PDT 24
Peak memory 249208 kb
Host smart-23f98af5-dbf6-47b9-9901-d024a16a2ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925916705 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_all.2925916705
Directory /workspace/32.spi_device_flash_all/latest

Test location /workspace/coverage/default/32.spi_device_flash_and_tpm.3444054756
Short name T734
Test name
Test status
Simulation time 105439668839 ps
CPU time 255.05 seconds
Started Jul 07 05:29:53 PM PDT 24
Finished Jul 07 05:34:09 PM PDT 24
Peak memory 255216 kb
Host smart-e59e975f-dae4-4519-9eaf-464c7cc53ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444054756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_and_tpm.3444054756
Directory /workspace/32.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode.2874975558
Short name T952
Test name
Test status
Simulation time 2914833317 ps
CPU time 52.31 seconds
Started Jul 07 05:29:56 PM PDT 24
Finished Jul 07 05:30:49 PM PDT 24
Peak memory 249204 kb
Host smart-295de926-fd25-4a67-a0fc-75c15d5dd3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874975558 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode.2874975558
Directory /workspace/32.spi_device_flash_mode/latest

Test location /workspace/coverage/default/32.spi_device_flash_mode_ignore_cmds.4134159341
Short name T305
Test name
Test status
Simulation time 63575517312 ps
CPU time 156.14 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:32:49 PM PDT 24
Peak memory 255896 kb
Host smart-8b182f65-45a2-45ea-925a-0c39fd2606ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134159341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_flash_mode_ignore_cmd
s.4134159341
Directory /workspace/32.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/32.spi_device_intercept.263401406
Short name T835
Test name
Test status
Simulation time 4990448693 ps
CPU time 23.41 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:30:18 PM PDT 24
Peak memory 232784 kb
Host smart-da1e9904-7ae9-4b2a-a4fd-405a3783b1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263401406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_intercept.263401406
Directory /workspace/32.spi_device_intercept/latest

Test location /workspace/coverage/default/32.spi_device_mailbox.3941036024
Short name T898
Test name
Test status
Simulation time 3938436965 ps
CPU time 7.76 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 235312 kb
Host smart-fa2589a8-234c-49e7-955f-6b25e5ac7a08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941036024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_mailbox.3941036024
Directory /workspace/32.spi_device_mailbox/latest

Test location /workspace/coverage/default/32.spi_device_pass_addr_payload_swap.3837788641
Short name T908
Test name
Test status
Simulation time 1564034715 ps
CPU time 4.59 seconds
Started Jul 07 05:30:04 PM PDT 24
Finished Jul 07 05:30:10 PM PDT 24
Peak memory 232628 kb
Host smart-dd0f061e-5797-4767-96d4-e3ec0392fa36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3837788641 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_addr_payload_swa
p.3837788641
Directory /workspace/32.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/32.spi_device_pass_cmd_filtering.2556734512
Short name T891
Test name
Test status
Simulation time 25974635466 ps
CPU time 7.63 seconds
Started Jul 07 05:29:55 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 232836 kb
Host smart-cb29206c-a60d-4a3d-8aac-7c9c664aaec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556734512 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_pass_cmd_filtering.2556734512
Directory /workspace/32.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/32.spi_device_read_buffer_direct.307771262
Short name T640
Test name
Test status
Simulation time 167073886 ps
CPU time 4.33 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 222528 kb
Host smart-3bce16cf-8ab6-4f13-a588-3fdb8bc39f71
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=307771262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_read_buffer_dire
ct.307771262
Directory /workspace/32.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/32.spi_device_stress_all.3632244638
Short name T158
Test name
Test status
Simulation time 23031423475 ps
CPU time 203.42 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:33:18 PM PDT 24
Peak memory 252856 kb
Host smart-17969ff4-30bb-41ab-b1f9-6d6ce12cc3c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632244638 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_stre
ss_all.3632244638
Directory /workspace/32.spi_device_stress_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_all.1382698143
Short name T993
Test name
Test status
Simulation time 1195703838 ps
CPU time 10.87 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:30:06 PM PDT 24
Peak memory 216280 kb
Host smart-95fb5c17-9bc3-4322-adb7-5d15ab026c29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382698143 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_all.1382698143
Directory /workspace/32.spi_device_tpm_all/latest

Test location /workspace/coverage/default/32.spi_device_tpm_read_hw_reg.3986610682
Short name T800
Test name
Test status
Simulation time 21401370759 ps
CPU time 8.54 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:24 PM PDT 24
Peak memory 216324 kb
Host smart-470f2fc4-422b-4b6c-905d-e45033851c21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986610682 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_read_hw_reg.3986610682
Directory /workspace/32.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/32.spi_device_tpm_rw.4070722688
Short name T614
Test name
Test status
Simulation time 211492955 ps
CPU time 1.77 seconds
Started Jul 07 05:30:05 PM PDT 24
Finished Jul 07 05:30:07 PM PDT 24
Peak memory 216244 kb
Host smart-7a91ea5b-d788-4ae4-9ea4-b40e6b2265b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070722688 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_rw.4070722688
Directory /workspace/32.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/32.spi_device_tpm_sts_read.868212174
Short name T541
Test name
Test status
Simulation time 93932263 ps
CPU time 0.98 seconds
Started Jul 07 05:29:54 PM PDT 24
Finished Jul 07 05:29:56 PM PDT 24
Peak memory 205992 kb
Host smart-9391f036-e97f-4507-a4a3-c4c5ade443b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868212174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_tpm_sts_read.868212174
Directory /workspace/32.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/32.spi_device_upload.3014231628
Short name T998
Test name
Test status
Simulation time 3284352803 ps
CPU time 7.28 seconds
Started Jul 07 05:29:51 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 232716 kb
Host smart-8d3476f4-bee5-4895-87cf-e5b1f50f8ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014231628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.spi_device_upload.3014231628
Directory /workspace/32.spi_device_upload/latest

Test location /workspace/coverage/default/33.spi_device_alert_test.2970317311
Short name T658
Test name
Test status
Simulation time 33458910 ps
CPU time 0.71 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:00 PM PDT 24
Peak memory 204976 kb
Host smart-6ae8b13b-60ae-4a8d-b5ac-6293eebf8763
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2970317311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_alert_test.
2970317311
Directory /workspace/33.spi_device_alert_test/latest

Test location /workspace/coverage/default/33.spi_device_cfg_cmd.1865900108
Short name T645
Test name
Test status
Simulation time 1554846440 ps
CPU time 3.54 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:14 PM PDT 24
Peak memory 224496 kb
Host smart-f591cbf3-53e2-452c-a3dd-b7176a2644cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865900108 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_cfg_cmd.1865900108
Directory /workspace/33.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/33.spi_device_csb_read.704322540
Short name T365
Test name
Test status
Simulation time 45061415 ps
CPU time 0.83 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 206568 kb
Host smart-64611c03-53cd-4a18-bf94-e9d0472e15f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704322540 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_csb_read.704322540
Directory /workspace/33.spi_device_csb_read/latest

Test location /workspace/coverage/default/33.spi_device_flash_all.349289361
Short name T807
Test name
Test status
Simulation time 1795333811 ps
CPU time 40.53 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:30:38 PM PDT 24
Peak memory 252304 kb
Host smart-466bd226-b96a-4099-bcde-d3a4452b11ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349289361 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_all.349289361
Directory /workspace/33.spi_device_flash_all/latest

Test location /workspace/coverage/default/33.spi_device_flash_and_tpm_min_idle.434640417
Short name T197
Test name
Test status
Simulation time 305651505052 ps
CPU time 496.31 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:38:35 PM PDT 24
Peak memory 270872 kb
Host smart-42936142-c1f3-4c04-87c4-afaa1b51faa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=434640417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_and_tpm_min_idle
.434640417
Directory /workspace/33.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode.1205820122
Short name T617
Test name
Test status
Simulation time 174518612 ps
CPU time 5.76 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:30:05 PM PDT 24
Peak memory 234572 kb
Host smart-556f9694-33d8-4316-8321-17598cba6d6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205820122 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode.1205820122
Directory /workspace/33.spi_device_flash_mode/latest

Test location /workspace/coverage/default/33.spi_device_flash_mode_ignore_cmds.1127659701
Short name T168
Test name
Test status
Simulation time 57627711632 ps
CPU time 109.63 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:31:50 PM PDT 24
Peak memory 249200 kb
Host smart-0716b5e8-5803-4f13-8654-aba179d60e2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127659701 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_flash_mode_ignore_cmd
s.1127659701
Directory /workspace/33.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/33.spi_device_intercept.1727692545
Short name T966
Test name
Test status
Simulation time 536482785 ps
CPU time 7.88 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:19 PM PDT 24
Peak memory 227012 kb
Host smart-1961207e-6dbd-43a8-91f1-104c84f37cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727692545 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_intercept.1727692545
Directory /workspace/33.spi_device_intercept/latest

Test location /workspace/coverage/default/33.spi_device_mailbox.3873968386
Short name T44
Test name
Test status
Simulation time 1120611248 ps
CPU time 11.94 seconds
Started Jul 07 05:30:01 PM PDT 24
Finished Jul 07 05:30:14 PM PDT 24
Peak memory 240580 kb
Host smart-8217d30b-1c17-408d-8097-83a9dc4c2f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873968386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_mailbox.3873968386
Directory /workspace/33.spi_device_mailbox/latest

Test location /workspace/coverage/default/33.spi_device_pass_addr_payload_swap.3672008911
Short name T948
Test name
Test status
Simulation time 287734917 ps
CPU time 3.14 seconds
Started Jul 07 05:29:56 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 232604 kb
Host smart-60576be4-1561-4978-8c31-add356ca528e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672008911 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_addr_payload_swa
p.3672008911
Directory /workspace/33.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/33.spi_device_pass_cmd_filtering.3745495077
Short name T489
Test name
Test status
Simulation time 114013026 ps
CPU time 2.69 seconds
Started Jul 07 05:30:03 PM PDT 24
Finished Jul 07 05:30:07 PM PDT 24
Peak memory 232324 kb
Host smart-854bc774-b03f-4dfd-8302-9524403417cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745495077 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_pass_cmd_filtering.3745495077
Directory /workspace/33.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/33.spi_device_read_buffer_direct.2198003337
Short name T573
Test name
Test status
Simulation time 445415666 ps
CPU time 4.16 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:19 PM PDT 24
Peak memory 222612 kb
Host smart-91b15ff8-3eb6-43d3-90e2-eea53735cfb9
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2198003337 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_read_buffer_dir
ect.2198003337
Directory /workspace/33.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/33.spi_device_stress_all.3215593811
Short name T20
Test name
Test status
Simulation time 1227173124 ps
CPU time 15.89 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:30:29 PM PDT 24
Peak memory 232784 kb
Host smart-a63fc604-29e1-4f21-ad61-8fb07290004a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3215593811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_stre
ss_all.3215593811
Directory /workspace/33.spi_device_stress_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_all.3100864749
Short name T687
Test name
Test status
Simulation time 23063985711 ps
CPU time 17.82 seconds
Started Jul 07 05:30:02 PM PDT 24
Finished Jul 07 05:30:21 PM PDT 24
Peak memory 216428 kb
Host smart-7d3785eb-5b7d-4620-8db3-7933bd06f32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100864749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_all.3100864749
Directory /workspace/33.spi_device_tpm_all/latest

Test location /workspace/coverage/default/33.spi_device_tpm_read_hw_reg.2832715613
Short name T330
Test name
Test status
Simulation time 799740553 ps
CPU time 5.75 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:30:19 PM PDT 24
Peak memory 216220 kb
Host smart-6d7e6e5d-2024-464e-8f4a-82b89a3378ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832715613 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_read_hw_reg.2832715613
Directory /workspace/33.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/33.spi_device_tpm_rw.1849520565
Short name T884
Test name
Test status
Simulation time 482578169 ps
CPU time 4.23 seconds
Started Jul 07 05:30:06 PM PDT 24
Finished Jul 07 05:30:11 PM PDT 24
Peak memory 216172 kb
Host smart-3ce1e250-18ca-4550-9b6c-9f3ae07390a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849520565 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_rw.1849520565
Directory /workspace/33.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/33.spi_device_tpm_sts_read.3294703375
Short name T958
Test name
Test status
Simulation time 28460657 ps
CPU time 0.78 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:15 PM PDT 24
Peak memory 205908 kb
Host smart-5923fbc8-7128-4d56-a24d-55bd991a6845
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3294703375 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_tpm_sts_read.3294703375
Directory /workspace/33.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/33.spi_device_upload.3656559860
Short name T436
Test name
Test status
Simulation time 1455111735 ps
CPU time 8.73 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:30:10 PM PDT 24
Peak memory 224504 kb
Host smart-886af3d5-8f3b-48ae-976e-31b31028c16f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656559860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.spi_device_upload.3656559860
Directory /workspace/33.spi_device_upload/latest

Test location /workspace/coverage/default/34.spi_device_alert_test.2109425856
Short name T342
Test name
Test status
Simulation time 52025111 ps
CPU time 0.74 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:15 PM PDT 24
Peak memory 205896 kb
Host smart-901732a7-298f-4a5e-bb92-e1944d55dcd5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109425856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_alert_test.
2109425856
Directory /workspace/34.spi_device_alert_test/latest

Test location /workspace/coverage/default/34.spi_device_cfg_cmd.202123373
Short name T533
Test name
Test status
Simulation time 578419936 ps
CPU time 5.65 seconds
Started Jul 07 05:30:20 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 232660 kb
Host smart-acde555f-422b-40d7-9eae-c5a2714c9ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202123373 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_cfg_cmd.202123373
Directory /workspace/34.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/34.spi_device_csb_read.179111687
Short name T80
Test name
Test status
Simulation time 35671053 ps
CPU time 0.81 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:30:20 PM PDT 24
Peak memory 206572 kb
Host smart-a7c838f7-5871-45b9-965a-0cd4badad66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=179111687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_csb_read.179111687
Directory /workspace/34.spi_device_csb_read/latest

Test location /workspace/coverage/default/34.spi_device_flash_all.2113576840
Short name T559
Test name
Test status
Simulation time 1953732386 ps
CPU time 16.54 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:30:34 PM PDT 24
Peak memory 224472 kb
Host smart-e529f6cb-8cdf-4bd0-bf5f-5f26c6173d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113576840 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_all.2113576840
Directory /workspace/34.spi_device_flash_all/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode.3881539495
Short name T759
Test name
Test status
Simulation time 977623286 ps
CPU time 15.02 seconds
Started Jul 07 05:30:20 PM PDT 24
Finished Jul 07 05:30:35 PM PDT 24
Peak memory 232616 kb
Host smart-4c7588ba-9724-42fa-9b23-f455c54ba9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881539495 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode.3881539495
Directory /workspace/34.spi_device_flash_mode/latest

Test location /workspace/coverage/default/34.spi_device_flash_mode_ignore_cmds.3537405893
Short name T735
Test name
Test status
Simulation time 695396467 ps
CPU time 17.19 seconds
Started Jul 07 05:30:04 PM PDT 24
Finished Jul 07 05:30:22 PM PDT 24
Peak memory 238332 kb
Host smart-4f2aec84-e22b-4479-aa93-71fbf7b8524a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3537405893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_flash_mode_ignore_cmd
s.3537405893
Directory /workspace/34.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/34.spi_device_intercept.3515368089
Short name T912
Test name
Test status
Simulation time 1456950308 ps
CPU time 14.97 seconds
Started Jul 07 05:29:58 PM PDT 24
Finished Jul 07 05:30:13 PM PDT 24
Peak memory 228192 kb
Host smart-c48e4efa-52ad-4964-a5a2-f2a61d3e4cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515368089 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_intercept.3515368089
Directory /workspace/34.spi_device_intercept/latest

Test location /workspace/coverage/default/34.spi_device_mailbox.2636296092
Short name T421
Test name
Test status
Simulation time 1158784050 ps
CPU time 21.97 seconds
Started Jul 07 05:30:08 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 232616 kb
Host smart-148ddce6-a59b-4b85-8af8-7d1df986b9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636296092 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_mailbox.2636296092
Directory /workspace/34.spi_device_mailbox/latest

Test location /workspace/coverage/default/34.spi_device_pass_addr_payload_swap.2375559943
Short name T919
Test name
Test status
Simulation time 19073746950 ps
CPU time 12.76 seconds
Started Jul 07 05:30:17 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 232788 kb
Host smart-0d2f44d3-8261-4c0d-8c45-c5f11debc539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375559943 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_addr_payload_swa
p.2375559943
Directory /workspace/34.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/34.spi_device_pass_cmd_filtering.3829444670
Short name T59
Test name
Test status
Simulation time 5107421018 ps
CPU time 15.3 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:29 PM PDT 24
Peak memory 232764 kb
Host smart-7391f258-1b71-496c-bedb-f2d68410eda8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3829444670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_pass_cmd_filtering.3829444670
Directory /workspace/34.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/34.spi_device_read_buffer_direct.726938787
Short name T471
Test name
Test status
Simulation time 1163726476 ps
CPU time 13.3 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:21 PM PDT 24
Peak memory 219504 kb
Host smart-7bc4a54d-1db1-4337-b3cc-9b26862b0ac4
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=726938787 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_read_buffer_dire
ct.726938787
Directory /workspace/34.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/34.spi_device_stress_all.1482179285
Short name T621
Test name
Test status
Simulation time 17035015997 ps
CPU time 85.98 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:31:42 PM PDT 24
Peak memory 253756 kb
Host smart-6b5749eb-0d41-4f3d-af3c-4318375b2f00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482179285 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_stre
ss_all.1482179285
Directory /workspace/34.spi_device_stress_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_all.3419327916
Short name T317
Test name
Test status
Simulation time 9640425154 ps
CPU time 18.6 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:29 PM PDT 24
Peak memory 216296 kb
Host smart-bd3189f6-2069-4ec6-8d00-56adc94d24a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419327916 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_all.3419327916
Directory /workspace/34.spi_device_tpm_all/latest

Test location /workspace/coverage/default/34.spi_device_tpm_read_hw_reg.2197486852
Short name T705
Test name
Test status
Simulation time 7387041160 ps
CPU time 16 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 216356 kb
Host smart-1bd26385-06fe-4a1d-ba4f-296b49e4eeb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197486852 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_read_hw_reg.2197486852
Directory /workspace/34.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/34.spi_device_tpm_rw.3030913310
Short name T655
Test name
Test status
Simulation time 37400200 ps
CPU time 0.92 seconds
Started Jul 07 05:29:51 PM PDT 24
Finished Jul 07 05:29:53 PM PDT 24
Peak memory 207860 kb
Host smart-3f1cbe84-8f0e-481e-bef0-37fe3f15fea4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030913310 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_rw.3030913310
Directory /workspace/34.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/34.spi_device_tpm_sts_read.2109115211
Short name T356
Test name
Test status
Simulation time 554176042 ps
CPU time 0.85 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:30:20 PM PDT 24
Peak memory 205956 kb
Host smart-583ede6d-e0e4-4fae-a4c8-ea18a1158484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109115211 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_tpm_sts_read.2109115211
Directory /workspace/34.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/34.spi_device_upload.1109030237
Short name T818
Test name
Test status
Simulation time 4201478839 ps
CPU time 9.8 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:20 PM PDT 24
Peak memory 224632 kb
Host smart-b374c298-8898-4b8b-8553-3209fa3586b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109030237 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.spi_device_upload.1109030237
Directory /workspace/34.spi_device_upload/latest

Test location /workspace/coverage/default/35.spi_device_alert_test.4213276619
Short name T861
Test name
Test status
Simulation time 16209169 ps
CPU time 0.79 seconds
Started Jul 07 05:30:03 PM PDT 24
Finished Jul 07 05:30:05 PM PDT 24
Peak memory 205492 kb
Host smart-a51917cf-323e-4672-a968-688a8b190b0d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213276619 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_alert_test.
4213276619
Directory /workspace/35.spi_device_alert_test/latest

Test location /workspace/coverage/default/35.spi_device_cfg_cmd.3695584082
Short name T959
Test name
Test status
Simulation time 1444500876 ps
CPU time 8.65 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:30:08 PM PDT 24
Peak memory 232672 kb
Host smart-933479ea-5f73-4a07-816f-9b3edf026269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695584082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_cfg_cmd.3695584082
Directory /workspace/35.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/35.spi_device_csb_read.458633868
Short name T61
Test name
Test status
Simulation time 87284898 ps
CPU time 0.74 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:16 PM PDT 24
Peak memory 205552 kb
Host smart-27e5bfdd-5343-4efb-b597-3d01365ff4a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458633868 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_csb_read.458633868
Directory /workspace/35.spi_device_csb_read/latest

Test location /workspace/coverage/default/35.spi_device_flash_all.4007143079
Short name T175
Test name
Test status
Simulation time 19886162314 ps
CPU time 47.17 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:31:02 PM PDT 24
Peak memory 257368 kb
Host smart-1f4e6497-02bd-4b0a-8d11-522072a45a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007143079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_all.4007143079
Directory /workspace/35.spi_device_flash_all/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm.275343188
Short name T241
Test name
Test status
Simulation time 801992699734 ps
CPU time 699.81 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:41:58 PM PDT 24
Peak memory 273692 kb
Host smart-4caa8c9f-5dae-4080-8721-c493d2752702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275343188 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm.275343188
Directory /workspace/35.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/35.spi_device_flash_and_tpm_min_idle.1424414789
Short name T219
Test name
Test status
Simulation time 122376592602 ps
CPU time 303.08 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:35:04 PM PDT 24
Peak memory 254720 kb
Host smart-5b78aedd-6f2d-442e-b56f-77e514178c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424414789 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_and_tpm_min_idl
e.1424414789
Directory /workspace/35.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode.2617982518
Short name T6
Test name
Test status
Simulation time 23264875750 ps
CPU time 72 seconds
Started Jul 07 05:29:59 PM PDT 24
Finished Jul 07 05:31:12 PM PDT 24
Peak memory 249232 kb
Host smart-3703d5cb-a174-4438-8315-6b515451fb80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617982518 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode.2617982518
Directory /workspace/35.spi_device_flash_mode/latest

Test location /workspace/coverage/default/35.spi_device_flash_mode_ignore_cmds.1174509576
Short name T367
Test name
Test status
Simulation time 1043865884 ps
CPU time 7.88 seconds
Started Jul 07 05:30:08 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 232684 kb
Host smart-87453143-a68c-44d9-9699-dfb69bf220d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1174509576 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_flash_mode_ignore_cmd
s.1174509576
Directory /workspace/35.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/35.spi_device_intercept.2029286087
Short name T924
Test name
Test status
Simulation time 1666755693 ps
CPU time 5.85 seconds
Started Jul 07 05:30:02 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 232636 kb
Host smart-82b2ebd9-c2d3-403b-b1bb-df631bec9fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029286087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_intercept.2029286087
Directory /workspace/35.spi_device_intercept/latest

Test location /workspace/coverage/default/35.spi_device_mailbox.2993611301
Short name T79
Test name
Test status
Simulation time 534161606 ps
CPU time 2.72 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 232728 kb
Host smart-685f25cc-f45c-4bbe-82c0-4bc22bf16200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993611301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_mailbox.2993611301
Directory /workspace/35.spi_device_mailbox/latest

Test location /workspace/coverage/default/35.spi_device_pass_addr_payload_swap.181488037
Short name T494
Test name
Test status
Simulation time 2323266120 ps
CPU time 6.07 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:21 PM PDT 24
Peak memory 224644 kb
Host smart-fb46d7be-29bc-4f08-a871-5900dfba8d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181488037 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_addr_payload_swap
.181488037
Directory /workspace/35.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/35.spi_device_pass_cmd_filtering.1470791246
Short name T725
Test name
Test status
Simulation time 472034709 ps
CPU time 8.33 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:30:27 PM PDT 24
Peak memory 240508 kb
Host smart-11e0ae03-5276-4849-93ea-354ba933a647
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470791246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_pass_cmd_filtering.1470791246
Directory /workspace/35.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/35.spi_device_read_buffer_direct.3779664693
Short name T543
Test name
Test status
Simulation time 2276152821 ps
CPU time 18.62 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:32 PM PDT 24
Peak memory 222088 kb
Host smart-49e3ceb4-cb7e-45a7-a7b6-d9717e07a510
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3779664693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_read_buffer_dir
ect.3779664693
Directory /workspace/35.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/35.spi_device_stress_all.2200935956
Short name T293
Test name
Test status
Simulation time 8057597202 ps
CPU time 100.3 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:31:59 PM PDT 24
Peak memory 256584 kb
Host smart-eb8aa143-952c-46ac-84a2-d991f0846231
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200935956 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_stre
ss_all.2200935956
Directory /workspace/35.spi_device_stress_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_all.3400265359
Short name T325
Test name
Test status
Simulation time 7172482777 ps
CPU time 26.4 seconds
Started Jul 07 05:30:00 PM PDT 24
Finished Jul 07 05:30:27 PM PDT 24
Peak memory 221052 kb
Host smart-68da73a1-f412-4671-9e3b-e9c8b725e9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400265359 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_all.3400265359
Directory /workspace/35.spi_device_tpm_all/latest

Test location /workspace/coverage/default/35.spi_device_tpm_read_hw_reg.2987596141
Short name T480
Test name
Test status
Simulation time 7403057071 ps
CPU time 12.09 seconds
Started Jul 07 05:30:17 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 216232 kb
Host smart-3d1e85d7-ed4a-49e7-9162-251d658bcf6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987596141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_read_hw_reg.2987596141
Directory /workspace/35.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/35.spi_device_tpm_rw.3426378928
Short name T27
Test name
Test status
Simulation time 136214975 ps
CPU time 1.74 seconds
Started Jul 07 05:30:01 PM PDT 24
Finished Jul 07 05:30:04 PM PDT 24
Peak memory 216108 kb
Host smart-38025202-df38-48e6-a86d-f8328763ea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426378928 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_rw.3426378928
Directory /workspace/35.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/35.spi_device_tpm_sts_read.3954389592
Short name T865
Test name
Test status
Simulation time 30875692 ps
CPU time 0.76 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 205944 kb
Host smart-f58d547e-72fd-46a8-b2de-6d62755f382c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954389592 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_tpm_sts_read.3954389592
Directory /workspace/35.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/35.spi_device_upload.3834131174
Short name T209
Test name
Test status
Simulation time 6738889227 ps
CPU time 6.88 seconds
Started Jul 07 05:30:06 PM PDT 24
Finished Jul 07 05:30:13 PM PDT 24
Peak memory 237120 kb
Host smart-248ea5ff-c95b-4e2a-bf39-08292290833e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3834131174 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.spi_device_upload.3834131174
Directory /workspace/35.spi_device_upload/latest

Test location /workspace/coverage/default/36.spi_device_alert_test.2815143046
Short name T164
Test name
Test status
Simulation time 64186831 ps
CPU time 0.71 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:30:13 PM PDT 24
Peak memory 205824 kb
Host smart-ac3dfbda-586c-4acf-b2e9-c3188feec7f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815143046 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_alert_test.
2815143046
Directory /workspace/36.spi_device_alert_test/latest

Test location /workspace/coverage/default/36.spi_device_cfg_cmd.2274475021
Short name T396
Test name
Test status
Simulation time 104833169 ps
CPU time 2.09 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:16 PM PDT 24
Peak memory 224500 kb
Host smart-c788a5e6-fd54-4ffd-89be-10b64d6d66bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274475021 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_cfg_cmd.2274475021
Directory /workspace/36.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/36.spi_device_csb_read.2319253093
Short name T375
Test name
Test status
Simulation time 54586623 ps
CPU time 0.79 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:30:19 PM PDT 24
Peak memory 206564 kb
Host smart-7c47eae3-06e5-49ee-a139-c3b3c6d4a3c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319253093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_csb_read.2319253093
Directory /workspace/36.spi_device_csb_read/latest

Test location /workspace/coverage/default/36.spi_device_flash_all.3370055549
Short name T306
Test name
Test status
Simulation time 64586201629 ps
CPU time 397.35 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:36:45 PM PDT 24
Peak memory 256544 kb
Host smart-50c9930d-ba81-4912-9fb8-30e388c36b11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370055549 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_all.3370055549
Directory /workspace/36.spi_device_flash_all/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm.3873843235
Short name T212
Test name
Test status
Simulation time 149921318153 ps
CPU time 601.45 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:40:18 PM PDT 24
Peak memory 268064 kb
Host smart-114a4f0f-2a2f-485f-96b0-b37084a8eef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3873843235 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm.3873843235
Directory /workspace/36.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/36.spi_device_flash_and_tpm_min_idle.4224446889
Short name T136
Test name
Test status
Simulation time 37907797465 ps
CPU time 360.53 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:36:10 PM PDT 24
Peak memory 252368 kb
Host smart-0aa99535-3fc3-4e16-bb68-87db18e83253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224446889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_and_tpm_min_idl
e.4224446889
Directory /workspace/36.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode.1031351403
Short name T518
Test name
Test status
Simulation time 321331974 ps
CPU time 8.77 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 224452 kb
Host smart-86adc21b-8010-4203-927f-ce91ec128b19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031351403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode.1031351403
Directory /workspace/36.spi_device_flash_mode/latest

Test location /workspace/coverage/default/36.spi_device_flash_mode_ignore_cmds.1842964895
Short name T660
Test name
Test status
Simulation time 48673805 ps
CPU time 0.9 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:15 PM PDT 24
Peak memory 215932 kb
Host smart-6c0cfbfa-2c10-4f62-a7aa-42df3d338f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842964895 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_flash_mode_ignore_cmd
s.1842964895
Directory /workspace/36.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/36.spi_device_intercept.1234414265
Short name T597
Test name
Test status
Simulation time 6265944875 ps
CPU time 14.74 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 224564 kb
Host smart-34331cc0-0156-40dd-b8ce-e0e6ac3c85bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234414265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_intercept.1234414265
Directory /workspace/36.spi_device_intercept/latest

Test location /workspace/coverage/default/36.spi_device_mailbox.2211203190
Short name T844
Test name
Test status
Simulation time 2748050204 ps
CPU time 6.27 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:23 PM PDT 24
Peak memory 224608 kb
Host smart-f3c91966-d726-4a29-978c-96abbb6d4a27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211203190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_mailbox.2211203190
Directory /workspace/36.spi_device_mailbox/latest

Test location /workspace/coverage/default/36.spi_device_pass_addr_payload_swap.836236331
Short name T1007
Test name
Test status
Simulation time 4401765713 ps
CPU time 14.84 seconds
Started Jul 07 05:30:04 PM PDT 24
Finished Jul 07 05:30:20 PM PDT 24
Peak memory 232836 kb
Host smart-f75794f0-ebd2-4de9-9d13-1be3d8b01184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836236331 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_addr_payload_swap
.836236331
Directory /workspace/36.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/36.spi_device_pass_cmd_filtering.1463816133
Short name T724
Test name
Test status
Simulation time 1440005826 ps
CPU time 5.33 seconds
Started Jul 07 05:29:57 PM PDT 24
Finished Jul 07 05:30:03 PM PDT 24
Peak memory 224432 kb
Host smart-6a7c081c-dee3-4e07-9653-1d981a8d6aca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463816133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_pass_cmd_filtering.1463816133
Directory /workspace/36.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/36.spi_device_read_buffer_direct.3923662496
Short name T786
Test name
Test status
Simulation time 2049354513 ps
CPU time 8.52 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 222256 kb
Host smart-3b853539-fc69-44c1-b5bc-cff3939ebeca
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3923662496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_read_buffer_dir
ect.3923662496
Directory /workspace/36.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/36.spi_device_stress_all.118214268
Short name T157
Test name
Test status
Simulation time 32589364527 ps
CPU time 310.83 seconds
Started Jul 07 05:30:08 PM PDT 24
Finished Jul 07 05:35:19 PM PDT 24
Peak memory 265112 kb
Host smart-b9ead2eb-f2cf-4304-810f-450f6dafc33e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=118214268 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_stres
s_all.118214268
Directory /workspace/36.spi_device_stress_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_all.1724653647
Short name T1008
Test name
Test status
Simulation time 8902264151 ps
CPU time 48.62 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:31:06 PM PDT 24
Peak memory 220536 kb
Host smart-d8ca7aae-f182-4377-a4aa-d811cc1cd107
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724653647 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_all.1724653647
Directory /workspace/36.spi_device_tpm_all/latest

Test location /workspace/coverage/default/36.spi_device_tpm_read_hw_reg.973765676
Short name T731
Test name
Test status
Simulation time 24348030705 ps
CPU time 8.21 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:25 PM PDT 24
Peak memory 216260 kb
Host smart-82aaf766-75a9-45ca-be8e-131fd962a94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=973765676 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_read_hw_reg.973765676
Directory /workspace/36.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/36.spi_device_tpm_rw.3189983145
Short name T911
Test name
Test status
Simulation time 50485100 ps
CPU time 1.63 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 216164 kb
Host smart-d4a8ecae-3647-494f-b811-3a94d933216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189983145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_rw.3189983145
Directory /workspace/36.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/36.spi_device_tpm_sts_read.2556635781
Short name T870
Test name
Test status
Simulation time 94411074 ps
CPU time 0.81 seconds
Started Jul 07 05:30:08 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 205916 kb
Host smart-deb55faf-50bc-4b2b-8055-6d25ee295bf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2556635781 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_tpm_sts_read.2556635781
Directory /workspace/36.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/36.spi_device_upload.3383732182
Short name T851
Test name
Test status
Simulation time 3106537106 ps
CPU time 7.75 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:30:27 PM PDT 24
Peak memory 232752 kb
Host smart-78f6e0ef-0188-4dd8-8ae9-0e8c2950cbea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3383732182 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.spi_device_upload.3383732182
Directory /workspace/36.spi_device_upload/latest

Test location /workspace/coverage/default/37.spi_device_alert_test.3342855135
Short name T801
Test name
Test status
Simulation time 16879030 ps
CPU time 0.73 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:13 PM PDT 24
Peak memory 205876 kb
Host smart-8e828798-5f6f-452c-af15-b061db74e9ec
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342855135 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_alert_test.
3342855135
Directory /workspace/37.spi_device_alert_test/latest

Test location /workspace/coverage/default/37.spi_device_cfg_cmd.2548443284
Short name T467
Test name
Test status
Simulation time 73962255 ps
CPU time 2.13 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 223040 kb
Host smart-7df6a75e-8064-45c5-8370-a476e2f1deb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548443284 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_cfg_cmd.2548443284
Directory /workspace/37.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/37.spi_device_csb_read.4071302584
Short name T378
Test name
Test status
Simulation time 52051338 ps
CPU time 0.78 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:30:14 PM PDT 24
Peak memory 206884 kb
Host smart-cf5c765e-ca55-4227-a9ce-33b52e8992c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071302584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_csb_read.4071302584
Directory /workspace/37.spi_device_csb_read/latest

Test location /workspace/coverage/default/37.spi_device_flash_all.1011103894
Short name T54
Test name
Test status
Simulation time 91689244913 ps
CPU time 274.97 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:34:52 PM PDT 24
Peak memory 261896 kb
Host smart-2a10dbf5-7e52-4cc6-b585-9d71ab4811bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011103894 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_all.1011103894
Directory /workspace/37.spi_device_flash_all/latest

Test location /workspace/coverage/default/37.spi_device_flash_and_tpm.3492215778
Short name T237
Test name
Test status
Simulation time 3861108153 ps
CPU time 96.63 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:31:53 PM PDT 24
Peak memory 256684 kb
Host smart-c2f7b1d3-2248-4284-b917-aa6ca6b6766b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3492215778 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_and_tpm.3492215778
Directory /workspace/37.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode.2024442161
Short name T603
Test name
Test status
Simulation time 4195722415 ps
CPU time 7.17 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:24 PM PDT 24
Peak memory 224536 kb
Host smart-1427e371-d0a9-4a4d-9683-e11a5a96830c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2024442161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode.2024442161
Directory /workspace/37.spi_device_flash_mode/latest

Test location /workspace/coverage/default/37.spi_device_flash_mode_ignore_cmds.3846670528
Short name T627
Test name
Test status
Simulation time 5251617514 ps
CPU time 71.86 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:31:29 PM PDT 24
Peak memory 249184 kb
Host smart-00755080-95d4-420f-9a73-e2d85917ff69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846670528 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_flash_mode_ignore_cmd
s.3846670528
Directory /workspace/37.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/37.spi_device_intercept.4203273696
Short name T544
Test name
Test status
Simulation time 542901849 ps
CPU time 6.98 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 224448 kb
Host smart-84257826-d18a-4b01-828d-55b0a11ebb35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203273696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_intercept.4203273696
Directory /workspace/37.spi_device_intercept/latest

Test location /workspace/coverage/default/37.spi_device_mailbox.141033500
Short name T845
Test name
Test status
Simulation time 2906835619 ps
CPU time 4.92 seconds
Started Jul 07 05:30:06 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 224476 kb
Host smart-182af1a6-102e-4637-8638-9fde2dbeee83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141033500 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_mailbox.141033500
Directory /workspace/37.spi_device_mailbox/latest

Test location /workspace/coverage/default/37.spi_device_pass_addr_payload_swap.1338642953
Short name T796
Test name
Test status
Simulation time 2665728208 ps
CPU time 6.54 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:22 PM PDT 24
Peak memory 237400 kb
Host smart-9be549cd-5e82-4aca-a75e-836eb7024b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338642953 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_addr_payload_swa
p.1338642953
Directory /workspace/37.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/37.spi_device_pass_cmd_filtering.59428388
Short name T704
Test name
Test status
Simulation time 25329932541 ps
CPU time 9.66 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:25 PM PDT 24
Peak memory 240648 kb
Host smart-0873ebc5-0cca-4cc5-af3b-362c396186f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59428388 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_pass_cmd_filtering.59428388
Directory /workspace/37.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/37.spi_device_read_buffer_direct.122965134
Short name T452
Test name
Test status
Simulation time 1999932684 ps
CPU time 12.03 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:30:25 PM PDT 24
Peak memory 222144 kb
Host smart-8d23816f-d217-43ad-8005-1a69371af687
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=122965134 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_read_buffer_dire
ct.122965134
Directory /workspace/37.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/37.spi_device_stress_all.3793506932
Short name T616
Test name
Test status
Simulation time 180484951 ps
CPU time 1.09 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:15 PM PDT 24
Peak memory 215172 kb
Host smart-83c06950-c754-45ed-ab26-5cb5c8c44a69
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793506932 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_stre
ss_all.3793506932
Directory /workspace/37.spi_device_stress_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_all.3479054128
Short name T322
Test name
Test status
Simulation time 21112032139 ps
CPU time 33.76 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:49 PM PDT 24
Peak memory 216224 kb
Host smart-b21b46a0-2dfc-4865-908c-0f3c5978fd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479054128 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_all.3479054128
Directory /workspace/37.spi_device_tpm_all/latest

Test location /workspace/coverage/default/37.spi_device_tpm_read_hw_reg.3945801502
Short name T752
Test name
Test status
Simulation time 1497395384 ps
CPU time 2.94 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:30:21 PM PDT 24
Peak memory 216188 kb
Host smart-7b69a197-b6fe-48e4-b2a5-9d570051cc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945801502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_read_hw_reg.3945801502
Directory /workspace/37.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/37.spi_device_tpm_rw.2134595059
Short name T357
Test name
Test status
Simulation time 184623010 ps
CPU time 2.31 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 216204 kb
Host smart-1eb4339b-45f9-467c-ad3e-c11ac3372437
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134595059 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_rw.2134595059
Directory /workspace/37.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/37.spi_device_tpm_sts_read.979919486
Short name T343
Test name
Test status
Simulation time 24089286 ps
CPU time 0.8 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 205980 kb
Host smart-4b703504-9dca-412c-ac4d-ef1117463979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=979919486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_tpm_sts_read.979919486
Directory /workspace/37.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/37.spi_device_upload.380682645
Short name T192
Test name
Test status
Simulation time 184149683 ps
CPU time 2.32 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:30:20 PM PDT 24
Peak memory 224332 kb
Host smart-cb0a5cd4-c38d-44b1-ae8d-bd44258c7bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380682645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.spi_device_upload.380682645
Directory /workspace/37.spi_device_upload/latest

Test location /workspace/coverage/default/38.spi_device_alert_test.876536876
Short name T849
Test name
Test status
Simulation time 36753388 ps
CPU time 0.73 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:30:18 PM PDT 24
Peak memory 205856 kb
Host smart-1e350a6a-cae0-4652-8e18-eaae05e376f4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=876536876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_alert_test.876536876
Directory /workspace/38.spi_device_alert_test/latest

Test location /workspace/coverage/default/38.spi_device_cfg_cmd.1659244257
Short name T938
Test name
Test status
Simulation time 81895177 ps
CPU time 2.5 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:18 PM PDT 24
Peak memory 232612 kb
Host smart-1442b18c-7750-4a2d-9372-dcea17e0f1ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1659244257 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_cfg_cmd.1659244257
Directory /workspace/38.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/38.spi_device_csb_read.743500295
Short name T863
Test name
Test status
Simulation time 38402707 ps
CPU time 0.82 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:30:11 PM PDT 24
Peak memory 206556 kb
Host smart-f2752fdd-1b53-4b9c-82bd-388b64f30d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743500295 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_csb_read.743500295
Directory /workspace/38.spi_device_csb_read/latest

Test location /workspace/coverage/default/38.spi_device_flash_all.2649539473
Short name T746
Test name
Test status
Simulation time 2187621737 ps
CPU time 15 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:29 PM PDT 24
Peak memory 233784 kb
Host smart-cbfe2d3e-ba36-4694-ac98-b2fde9cd3299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649539473 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_all.2649539473
Directory /workspace/38.spi_device_flash_all/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm.2123841226
Short name T319
Test name
Test status
Simulation time 22284272947 ps
CPU time 96.04 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:31:52 PM PDT 24
Peak memory 256688 kb
Host smart-bc58a04d-7a6d-4a57-a0e0-2529a1f3e388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123841226 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm.2123841226
Directory /workspace/38.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/38.spi_device_flash_and_tpm_min_idle.3796334309
Short name T469
Test name
Test status
Simulation time 7065055204 ps
CPU time 44.06 seconds
Started Jul 07 05:30:04 PM PDT 24
Finished Jul 07 05:30:49 PM PDT 24
Peak memory 224608 kb
Host smart-1a1a5ed5-c604-4e50-818d-c264f9a0068d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796334309 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_and_tpm_min_idl
e.3796334309
Directory /workspace/38.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode.2072561262
Short name T1
Test name
Test status
Simulation time 17486079613 ps
CPU time 59.34 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:31:17 PM PDT 24
Peak memory 241044 kb
Host smart-81e4ae12-cd41-4737-92f3-6c5acb29670a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072561262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode.2072561262
Directory /workspace/38.spi_device_flash_mode/latest

Test location /workspace/coverage/default/38.spi_device_flash_mode_ignore_cmds.2052173398
Short name T890
Test name
Test status
Simulation time 3248426597 ps
CPU time 27.26 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:43 PM PDT 24
Peak memory 249064 kb
Host smart-b0d80bac-9b9f-4f18-954d-86149de52f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052173398 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_flash_mode_ignore_cmd
s.2052173398
Directory /workspace/38.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/38.spi_device_intercept.3051367881
Short name T504
Test name
Test status
Simulation time 46503218506 ps
CPU time 18.19 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:34 PM PDT 24
Peak memory 232696 kb
Host smart-e3a3f0f1-6c21-4f72-8e47-74bd5083233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051367881 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_intercept.3051367881
Directory /workspace/38.spi_device_intercept/latest

Test location /workspace/coverage/default/38.spi_device_mailbox.2515210356
Short name T111
Test name
Test status
Simulation time 2019140652 ps
CPU time 14.17 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:22 PM PDT 24
Peak memory 249092 kb
Host smart-d977d4dd-c5ae-49c4-86ee-98cff9bd7e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2515210356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_mailbox.2515210356
Directory /workspace/38.spi_device_mailbox/latest

Test location /workspace/coverage/default/38.spi_device_pass_addr_payload_swap.2502669880
Short name T820
Test name
Test status
Simulation time 612650550 ps
CPU time 4.08 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 224452 kb
Host smart-1b3c4a33-080d-4d23-b6c3-6607632416a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2502669880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_addr_payload_swa
p.2502669880
Directory /workspace/38.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/38.spi_device_pass_cmd_filtering.3298728397
Short name T713
Test name
Test status
Simulation time 43748042063 ps
CPU time 17.74 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 233840 kb
Host smart-7d1aa6d0-1b85-45e0-90d8-b96e1277f4e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298728397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_pass_cmd_filtering.3298728397
Directory /workspace/38.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/38.spi_device_read_buffer_direct.19267756
Short name T730
Test name
Test status
Simulation time 2752948641 ps
CPU time 9.47 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:24 PM PDT 24
Peak memory 220380 kb
Host smart-ac4543f6-457e-433a-8023-6debd9e63166
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=19267756 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_read_buffer_direc
t.19267756
Directory /workspace/38.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/38.spi_device_stress_all.3007601242
Short name T134
Test name
Test status
Simulation time 83511541332 ps
CPU time 429.44 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:37:24 PM PDT 24
Peak memory 262676 kb
Host smart-af20cf9d-d9c9-48db-abce-ff498c675ed7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007601242 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_stre
ss_all.3007601242
Directory /workspace/38.spi_device_stress_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_all.2296295962
Short name T987
Test name
Test status
Simulation time 450071503 ps
CPU time 4.19 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:30:23 PM PDT 24
Peak memory 216116 kb
Host smart-554102b2-5351-4af4-b4cf-003fc28fa1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296295962 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_all.2296295962
Directory /workspace/38.spi_device_tpm_all/latest

Test location /workspace/coverage/default/38.spi_device_tpm_read_hw_reg.933324484
Short name T441
Test name
Test status
Simulation time 182257705 ps
CPU time 1.71 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 207840 kb
Host smart-f3cfe44a-7829-4f8d-9515-b9185218df51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933324484 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_read_hw_reg.933324484
Directory /workspace/38.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/38.spi_device_tpm_rw.810125651
Short name T754
Test name
Test status
Simulation time 27877733 ps
CPU time 1.1 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 207248 kb
Host smart-c966e599-73e3-4e27-a311-4996e8c6a052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810125651 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_rw.810125651
Directory /workspace/38.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/38.spi_device_tpm_sts_read.584932987
Short name T717
Test name
Test status
Simulation time 30737234 ps
CPU time 0.77 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:30:10 PM PDT 24
Peak memory 205988 kb
Host smart-0547a2c4-72e7-41ef-8b42-e9bd7f1b24f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584932987 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_tpm_sts_read.584932987
Directory /workspace/38.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/38.spi_device_upload.2940769066
Short name T275
Test name
Test status
Simulation time 3534413678 ps
CPU time 9.14 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:30:22 PM PDT 24
Peak memory 232736 kb
Host smart-c0b927c0-fc90-435c-a4fa-ccd39bd01a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940769066 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.spi_device_upload.2940769066
Directory /workspace/38.spi_device_upload/latest

Test location /workspace/coverage/default/39.spi_device_alert_test.2658509811
Short name T456
Test name
Test status
Simulation time 13482229 ps
CPU time 0.79 seconds
Started Jul 07 05:30:08 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 205544 kb
Host smart-33bb1c7f-dffb-4bce-ae32-6bb94f152700
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658509811 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_alert_test.
2658509811
Directory /workspace/39.spi_device_alert_test/latest

Test location /workspace/coverage/default/39.spi_device_cfg_cmd.170967145
Short name T334
Test name
Test status
Simulation time 3443470479 ps
CPU time 8.47 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 224432 kb
Host smart-2d934ddc-1caf-4acf-8180-fd1acdb8bcc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170967145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_cfg_cmd.170967145
Directory /workspace/39.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/39.spi_device_csb_read.1385602798
Short name T36
Test name
Test status
Simulation time 36381340 ps
CPU time 0.78 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:30:20 PM PDT 24
Peak memory 205432 kb
Host smart-62f5c1f2-da1f-41c3-bfdf-7508b80a91d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385602798 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_csb_read.1385602798
Directory /workspace/39.spi_device_csb_read/latest

Test location /workspace/coverage/default/39.spi_device_flash_all.1435370256
Short name T270
Test name
Test status
Simulation time 4995355762 ps
CPU time 71.39 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:31:28 PM PDT 24
Peak memory 256872 kb
Host smart-960ecac4-e85e-4fb8-b2fe-91fdfc2cd96e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435370256 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_all.1435370256
Directory /workspace/39.spi_device_flash_all/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm.3631142687
Short name T216
Test name
Test status
Simulation time 18173887885 ps
CPU time 122.44 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:32:13 PM PDT 24
Peak memory 254972 kb
Host smart-a3205b7c-1681-4b3f-a3e1-b3047b93234e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631142687 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm.3631142687
Directory /workspace/39.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/39.spi_device_flash_and_tpm_min_idle.820399006
Short name T328
Test name
Test status
Simulation time 24603414757 ps
CPU time 90.1 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:31:49 PM PDT 24
Peak memory 255240 kb
Host smart-3c44f181-42db-4e56-9c8e-42c91238faf1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=820399006 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_and_tpm_min_idle
.820399006
Directory /workspace/39.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/39.spi_device_flash_mode.353986247
Short name T353
Test name
Test status
Simulation time 161662663 ps
CPU time 3.85 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:30:22 PM PDT 24
Peak memory 224776 kb
Host smart-03915cc6-7af9-4f5e-9722-886a59c4120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353986247 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_flash_mode.353986247
Directory /workspace/39.spi_device_flash_mode/latest

Test location /workspace/coverage/default/39.spi_device_intercept.3800386596
Short name T774
Test name
Test status
Simulation time 301302362 ps
CPU time 4.28 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:30:23 PM PDT 24
Peak memory 224428 kb
Host smart-064d30c9-74a2-4f31-bf18-fc72a41a6703
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3800386596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_intercept.3800386596
Directory /workspace/39.spi_device_intercept/latest

Test location /workspace/coverage/default/39.spi_device_mailbox.1367036475
Short name T503
Test name
Test status
Simulation time 5770844128 ps
CPU time 12.02 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 224564 kb
Host smart-ce6aada4-7819-4f8d-bdd9-5d1e61feffef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367036475 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_mailbox.1367036475
Directory /workspace/39.spi_device_mailbox/latest

Test location /workspace/coverage/default/39.spi_device_pass_addr_payload_swap.3681676293
Short name T288
Test name
Test status
Simulation time 975618233 ps
CPU time 7.21 seconds
Started Jul 07 05:30:17 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 232664 kb
Host smart-e349f32c-f2e4-44c1-af9a-f435c29b21d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3681676293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_addr_payload_swa
p.3681676293
Directory /workspace/39.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/39.spi_device_pass_cmd_filtering.965392531
Short name T575
Test name
Test status
Simulation time 232401497 ps
CPU time 4.35 seconds
Started Jul 07 05:30:17 PM PDT 24
Finished Jul 07 05:30:23 PM PDT 24
Peak memory 232584 kb
Host smart-efb58d15-3d42-4234-ab53-8ddb0ff8520b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965392531 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_pass_cmd_filtering.965392531
Directory /workspace/39.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/39.spi_device_read_buffer_direct.3991076990
Short name T133
Test name
Test status
Simulation time 1897521724 ps
CPU time 14.92 seconds
Started Jul 07 05:30:06 PM PDT 24
Finished Jul 07 05:30:22 PM PDT 24
Peak memory 222036 kb
Host smart-f1f8ca5a-1784-4f17-8a57-919fcc6f64e1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3991076990 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_read_buffer_dir
ect.3991076990
Directory /workspace/39.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/39.spi_device_stress_all.552189488
Short name T16
Test name
Test status
Simulation time 159138383 ps
CPU time 0.97 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:08 PM PDT 24
Peak memory 207584 kb
Host smart-794f67c7-0d58-43d9-a7c2-0c5bf30479c2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=552189488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_stres
s_all.552189488
Directory /workspace/39.spi_device_stress_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_all.732008629
Short name T666
Test name
Test status
Simulation time 14610604751 ps
CPU time 44.69 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:31:01 PM PDT 24
Peak memory 216264 kb
Host smart-29650825-6de8-4d0e-9f70-4970e96a0f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732008629 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_all.732008629
Directory /workspace/39.spi_device_tpm_all/latest

Test location /workspace/coverage/default/39.spi_device_tpm_read_hw_reg.3803306371
Short name T419
Test name
Test status
Simulation time 15220922 ps
CPU time 0.71 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:08 PM PDT 24
Peak memory 205696 kb
Host smart-2f242c51-39b2-43b7-8d3d-692828bad704
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803306371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_read_hw_reg.3803306371
Directory /workspace/39.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/39.spi_device_tpm_rw.607212156
Short name T739
Test name
Test status
Simulation time 238577081 ps
CPU time 3.15 seconds
Started Jul 07 05:30:08 PM PDT 24
Finished Jul 07 05:30:11 PM PDT 24
Peak memory 216256 kb
Host smart-47f06c1f-b6a8-4c7a-85af-46fe0e5c8c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607212156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_rw.607212156
Directory /workspace/39.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/39.spi_device_tpm_sts_read.1245803735
Short name T341
Test name
Test status
Simulation time 22087656 ps
CPU time 0.73 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 205916 kb
Host smart-cd354ffd-3cac-4f78-9ab7-bdb29578ef32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245803735 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_tpm_sts_read.1245803735
Directory /workspace/39.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/39.spi_device_upload.3116318918
Short name T417
Test name
Test status
Simulation time 15308098147 ps
CPU time 13.01 seconds
Started Jul 07 05:30:07 PM PDT 24
Finished Jul 07 05:30:21 PM PDT 24
Peak memory 224560 kb
Host smart-c223bfd2-99f9-4aaa-8a5a-fdec0760ece6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116318918 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.spi_device_upload.3116318918
Directory /workspace/39.spi_device_upload/latest

Test location /workspace/coverage/default/4.spi_device_alert_test.2327304207
Short name T979
Test name
Test status
Simulation time 41132777 ps
CPU time 0.72 seconds
Started Jul 07 05:28:45 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 204968 kb
Host smart-0d3610a2-34d4-40aa-a410-c68944522980
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327304207 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_alert_test.2
327304207
Directory /workspace/4.spi_device_alert_test/latest

Test location /workspace/coverage/default/4.spi_device_cfg_cmd.945549408
Short name T404
Test name
Test status
Simulation time 456547253 ps
CPU time 3.5 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:07 PM PDT 24
Peak memory 224440 kb
Host smart-54571889-57f9-474f-a25c-f1559565dd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945549408 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_cfg_cmd.945549408
Directory /workspace/4.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/4.spi_device_csb_read.1649871214
Short name T32
Test name
Test status
Simulation time 12412420 ps
CPU time 0.75 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:29:11 PM PDT 24
Peak memory 206588 kb
Host smart-3d7995a4-11f0-44b2-8729-7b1ab9db0457
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649871214 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_csb_read.1649871214
Directory /workspace/4.spi_device_csb_read/latest

Test location /workspace/coverage/default/4.spi_device_flash_all.2406617790
Short name T83
Test name
Test status
Simulation time 38094436263 ps
CPU time 308.84 seconds
Started Jul 07 05:29:04 PM PDT 24
Finished Jul 07 05:34:14 PM PDT 24
Peak memory 255528 kb
Host smart-0f8aa72b-eb86-4a21-b6e9-2b7df904078b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406617790 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_all.2406617790
Directory /workspace/4.spi_device_flash_all/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm.723261079
Short name T249
Test name
Test status
Simulation time 15936166065 ps
CPU time 38.75 seconds
Started Jul 07 05:29:01 PM PDT 24
Finished Jul 07 05:29:41 PM PDT 24
Peak memory 240904 kb
Host smart-276a8e54-9df6-4e60-8576-0c6946ca1a22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=723261079 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm.723261079
Directory /workspace/4.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/4.spi_device_flash_and_tpm_min_idle.2267435425
Short name T495
Test name
Test status
Simulation time 110148334071 ps
CPU time 216.37 seconds
Started Jul 07 05:28:33 PM PDT 24
Finished Jul 07 05:32:09 PM PDT 24
Peak memory 253016 kb
Host smart-9da72656-c33f-4fae-94ca-f08173ccad36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267435425 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_and_tpm_min_idle
.2267435425
Directory /workspace/4.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode.310439693
Short name T874
Test name
Test status
Simulation time 4221346466 ps
CPU time 41.79 seconds
Started Jul 07 05:28:38 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 249040 kb
Host smart-bfa9c507-226e-4b73-8036-d751e1b15618
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310439693 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode.310439693
Directory /workspace/4.spi_device_flash_mode/latest

Test location /workspace/coverage/default/4.spi_device_flash_mode_ignore_cmds.181824311
Short name T92
Test name
Test status
Simulation time 3485969659 ps
CPU time 19.19 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:24 PM PDT 24
Peak memory 238456 kb
Host smart-5219ccd0-7769-43a4-8e32-a33f33ca278b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=181824311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_flash_mode_ignore_cmds.
181824311
Directory /workspace/4.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/4.spi_device_intercept.1729433139
Short name T522
Test name
Test status
Simulation time 470348569 ps
CPU time 3.83 seconds
Started Jul 07 05:28:51 PM PDT 24
Finished Jul 07 05:28:55 PM PDT 24
Peak memory 224452 kb
Host smart-880fb7ef-6cbb-43dc-8fa7-3555b963ccc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729433139 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_intercept.1729433139
Directory /workspace/4.spi_device_intercept/latest

Test location /workspace/coverage/default/4.spi_device_mailbox.4282671879
Short name T875
Test name
Test status
Simulation time 3765049252 ps
CPU time 38.75 seconds
Started Jul 07 05:28:48 PM PDT 24
Finished Jul 07 05:29:28 PM PDT 24
Peak memory 240724 kb
Host smart-483887e5-0ef2-43da-b990-a4ba131b524f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4282671879 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_mailbox.4282671879
Directory /workspace/4.spi_device_mailbox/latest

Test location /workspace/coverage/default/4.spi_device_pass_addr_payload_swap.112969064
Short name T225
Test name
Test status
Simulation time 17794465771 ps
CPU time 29.64 seconds
Started Jul 07 05:28:59 PM PDT 24
Finished Jul 07 05:29:29 PM PDT 24
Peak memory 232852 kb
Host smart-f256cfb3-1f66-4bec-8f07-4bf25fed18de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112969064 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_addr_payload_swap.
112969064
Directory /workspace/4.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/4.spi_device_pass_cmd_filtering.1635024677
Short name T431
Test name
Test status
Simulation time 31133668 ps
CPU time 2.19 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:29:17 PM PDT 24
Peak memory 223088 kb
Host smart-af496695-fc65-42be-814e-aec2d1de0b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635024677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_pass_cmd_filtering.1635024677
Directory /workspace/4.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/4.spi_device_read_buffer_direct.2738200708
Short name T511
Test name
Test status
Simulation time 1528105551 ps
CPU time 15.37 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:29:22 PM PDT 24
Peak memory 219880 kb
Host smart-5c0ebede-c072-4dbe-86b9-79a13c75c8a0
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2738200708 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_read_buffer_dire
ct.2738200708
Directory /workspace/4.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/4.spi_device_sec_cm.2971474386
Short name T71
Test name
Test status
Simulation time 33339568 ps
CPU time 0.98 seconds
Started Jul 07 05:28:53 PM PDT 24
Finished Jul 07 05:28:54 PM PDT 24
Peak memory 235896 kb
Host smart-b50456ee-845d-48e3-a10f-00df9611b595
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971474386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_sec_cm.2971474386
Directory /workspace/4.spi_device_sec_cm/latest

Test location /workspace/coverage/default/4.spi_device_stress_all.612495025
Short name T294
Test name
Test status
Simulation time 396101317620 ps
CPU time 859.51 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:43:28 PM PDT 24
Peak memory 284736 kb
Host smart-f65952ba-cb2c-4f0d-8a2d-8d7f35cf42c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612495025 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_stress
_all.612495025
Directory /workspace/4.spi_device_stress_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_all.3718663427
Short name T636
Test name
Test status
Simulation time 4546368082 ps
CPU time 27.53 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:29:41 PM PDT 24
Peak memory 219648 kb
Host smart-0d3d91ed-400a-415c-8631-57fb6be5b2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718663427 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_all.3718663427
Directory /workspace/4.spi_device_tpm_all/latest

Test location /workspace/coverage/default/4.spi_device_tpm_read_hw_reg.1942315371
Short name T373
Test name
Test status
Simulation time 4828121938 ps
CPU time 9.12 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:29:07 PM PDT 24
Peak memory 216296 kb
Host smart-b6a479f9-b53a-4daf-a0c0-82238915009d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1942315371 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_read_hw_reg.1942315371
Directory /workspace/4.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/4.spi_device_tpm_rw.1685224467
Short name T425
Test name
Test status
Simulation time 1075231393 ps
CPU time 4.91 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:29:18 PM PDT 24
Peak memory 216124 kb
Host smart-b432b25d-d3c5-4703-bf6d-1a5df89da722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685224467 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_rw.1685224467
Directory /workspace/4.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/4.spi_device_tpm_sts_read.1018860078
Short name T760
Test name
Test status
Simulation time 92957721 ps
CPU time 0.79 seconds
Started Jul 07 05:28:45 PM PDT 24
Finished Jul 07 05:28:46 PM PDT 24
Peak memory 205980 kb
Host smart-21051996-c090-4c34-a747-8c8c3964c3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018860078 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_tpm_sts_read.1018860078
Directory /workspace/4.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/4.spi_device_upload.2575428417
Short name T235
Test name
Test status
Simulation time 1647415017 ps
CPU time 4.33 seconds
Started Jul 07 05:28:37 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 232652 kb
Host smart-1d08e04d-633e-4935-ab91-2a46c3f3b51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575428417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.spi_device_upload.2575428417
Directory /workspace/4.spi_device_upload/latest

Test location /workspace/coverage/default/40.spi_device_alert_test.4128704262
Short name T525
Test name
Test status
Simulation time 14348690 ps
CPU time 0.71 seconds
Started Jul 07 05:30:08 PM PDT 24
Finished Jul 07 05:30:09 PM PDT 24
Peak memory 205856 kb
Host smart-2ff7e2ff-5c2c-45ea-8859-07c645dd7515
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128704262 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_alert_test.
4128704262
Directory /workspace/40.spi_device_alert_test/latest

Test location /workspace/coverage/default/40.spi_device_cfg_cmd.1850740567
Short name T950
Test name
Test status
Simulation time 2825322311 ps
CPU time 14.46 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:30:32 PM PDT 24
Peak memory 232796 kb
Host smart-dbd695db-bc87-4a79-af50-1ede49b05f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1850740567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_cfg_cmd.1850740567
Directory /workspace/40.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/40.spi_device_csb_read.2263272102
Short name T743
Test name
Test status
Simulation time 19995629 ps
CPU time 0.78 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 205528 kb
Host smart-4e3751c5-5427-4e1f-8f85-abb79ca7500a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2263272102 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_csb_read.2263272102
Directory /workspace/40.spi_device_csb_read/latest

Test location /workspace/coverage/default/40.spi_device_flash_all.697478985
Short name T951
Test name
Test status
Simulation time 35902351455 ps
CPU time 255.95 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:34:28 PM PDT 24
Peak memory 251484 kb
Host smart-8adb15bc-848d-4333-b0ef-52e626003ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=697478985 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_all.697478985
Directory /workspace/40.spi_device_flash_all/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm.2622379291
Short name T318
Test name
Test status
Simulation time 7260476917 ps
CPU time 116.31 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:32:14 PM PDT 24
Peak memory 255580 kb
Host smart-914b95ba-eb62-4b6e-a1ba-b0d5fdfcdca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622379291 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm.2622379291
Directory /workspace/40.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/40.spi_device_flash_and_tpm_min_idle.1523082594
Short name T978
Test name
Test status
Simulation time 34121879276 ps
CPU time 332.72 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:35:46 PM PDT 24
Peak memory 249264 kb
Host smart-e2c5e757-2e1c-427a-a0d9-37c216a2ca80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523082594 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_and_tpm_min_idl
e.1523082594
Directory /workspace/40.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode.544756149
Short name T496
Test name
Test status
Simulation time 422265350 ps
CPU time 6.92 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:24 PM PDT 24
Peak memory 224448 kb
Host smart-ea5e216d-0835-4133-b58c-79aea42b7bc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544756149 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode.544756149
Directory /workspace/40.spi_device_flash_mode/latest

Test location /workspace/coverage/default/40.spi_device_flash_mode_ignore_cmds.54938831
Short name T303
Test name
Test status
Simulation time 13289766738 ps
CPU time 68.38 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:31:27 PM PDT 24
Peak memory 255648 kb
Host smart-26f47e55-fa07-47f7-91e6-bb4a19a406f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54938831 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_flash_mode_ignore_cmds.54938831
Directory /workspace/40.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/40.spi_device_intercept.246431378
Short name T556
Test name
Test status
Simulation time 613526068 ps
CPU time 4.55 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:16 PM PDT 24
Peak memory 224416 kb
Host smart-bdef56fa-b11a-4ac8-b846-bf129515c983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246431378 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_intercept.246431378
Directory /workspace/40.spi_device_intercept/latest

Test location /workspace/coverage/default/40.spi_device_mailbox.4262441254
Short name T246
Test name
Test status
Simulation time 6386570944 ps
CPU time 7.39 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:30:16 PM PDT 24
Peak memory 232764 kb
Host smart-f4c3738e-cf66-475b-9653-ebfc8433c422
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262441254 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_mailbox.4262441254
Directory /workspace/40.spi_device_mailbox/latest

Test location /workspace/coverage/default/40.spi_device_pass_addr_payload_swap.895619574
Short name T810
Test name
Test status
Simulation time 10017514406 ps
CPU time 6.14 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:21 PM PDT 24
Peak memory 224636 kb
Host smart-31a1eff4-d1f8-41a8-bd3d-057cbe97a19b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895619574 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_addr_payload_swap
.895619574
Directory /workspace/40.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/40.spi_device_pass_cmd_filtering.107901516
Short name T678
Test name
Test status
Simulation time 4583739026 ps
CPU time 5.88 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:30:16 PM PDT 24
Peak memory 224620 kb
Host smart-7b91e3a1-cbf2-4341-a82e-bcde9879f9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107901516 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_pass_cmd_filtering.107901516
Directory /workspace/40.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/40.spi_device_read_buffer_direct.311847236
Short name T144
Test name
Test status
Simulation time 240024341 ps
CPU time 3.78 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 221004 kb
Host smart-e9550e2f-b491-437d-9a68-4effa3a7934d
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=311847236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_read_buffer_dire
ct.311847236
Directory /workspace/40.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/40.spi_device_stress_all.1639081972
Short name T939
Test name
Test status
Simulation time 158055752524 ps
CPU time 397.14 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:36:55 PM PDT 24
Peak memory 273608 kb
Host smart-c85b4e54-bc1a-4589-8d50-efdaaad3aaf6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639081972 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_stre
ss_all.1639081972
Directory /workspace/40.spi_device_stress_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_all.3963820880
Short name T741
Test name
Test status
Simulation time 6427168692 ps
CPU time 15.28 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:32 PM PDT 24
Peak memory 216400 kb
Host smart-e32daeeb-2d05-4726-8572-1a11f0f1a332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963820880 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_all.3963820880
Directory /workspace/40.spi_device_tpm_all/latest

Test location /workspace/coverage/default/40.spi_device_tpm_read_hw_reg.3359612093
Short name T585
Test name
Test status
Simulation time 4687801370 ps
CPU time 7.74 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:30:25 PM PDT 24
Peak memory 216588 kb
Host smart-fc27f59f-949f-4763-9dc1-a9d0608afb50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359612093 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_read_hw_reg.3359612093
Directory /workspace/40.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/40.spi_device_tpm_rw.423272977
Short name T389
Test name
Test status
Simulation time 16892811 ps
CPU time 0.83 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 206764 kb
Host smart-d6a2d465-956d-4eee-848c-64a8e1a68e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=423272977 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_rw.423272977
Directory /workspace/40.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/40.spi_device_tpm_sts_read.2523458661
Short name T872
Test name
Test status
Simulation time 24731839 ps
CPU time 0.75 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 205940 kb
Host smart-03f0d29c-64dc-4e31-99ee-91764cb544d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523458661 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_tpm_sts_read.2523458661
Directory /workspace/40.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/40.spi_device_upload.160424212
Short name T39
Test name
Test status
Simulation time 1844409082 ps
CPU time 3.82 seconds
Started Jul 07 05:30:15 PM PDT 24
Finished Jul 07 05:30:22 PM PDT 24
Peak memory 229004 kb
Host smart-ec6ad027-fb8a-41b6-90e2-d97104e19f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=160424212 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.spi_device_upload.160424212
Directory /workspace/40.spi_device_upload/latest

Test location /workspace/coverage/default/41.spi_device_alert_test.2027005445
Short name T595
Test name
Test status
Simulation time 38305713 ps
CPU time 0.72 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:16 PM PDT 24
Peak memory 205860 kb
Host smart-3e797f5a-4fe4-4803-8b04-e1304da0c933
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027005445 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_alert_test.
2027005445
Directory /workspace/41.spi_device_alert_test/latest

Test location /workspace/coverage/default/41.spi_device_cfg_cmd.1281993417
Short name T188
Test name
Test status
Simulation time 75730852 ps
CPU time 2.6 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:14 PM PDT 24
Peak memory 232672 kb
Host smart-58392de3-239f-4e3d-a813-50e00aab81b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281993417 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_cfg_cmd.1281993417
Directory /workspace/41.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/41.spi_device_csb_read.1444446838
Short name T405
Test name
Test status
Simulation time 65333134 ps
CPU time 0.75 seconds
Started Jul 07 05:30:11 PM PDT 24
Finished Jul 07 05:30:13 PM PDT 24
Peak memory 205556 kb
Host smart-5f128a2c-8f23-41a4-9def-82b1f1e9052d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1444446838 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_csb_read.1444446838
Directory /workspace/41.spi_device_csb_read/latest

Test location /workspace/coverage/default/41.spi_device_flash_all.4188795645
Short name T649
Test name
Test status
Simulation time 23838152431 ps
CPU time 51.18 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:31:02 PM PDT 24
Peak memory 238832 kb
Host smart-4bc65d24-4f2f-451a-83b3-b7fc5b4c6a03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188795645 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_all.4188795645
Directory /workspace/41.spi_device_flash_all/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode.1521880250
Short name T310
Test name
Test status
Simulation time 2311318530 ps
CPU time 12.82 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:28 PM PDT 24
Peak memory 232836 kb
Host smart-64cbe7cd-a98a-42c2-b32f-4bf020787b44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1521880250 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode.1521880250
Directory /workspace/41.spi_device_flash_mode/latest

Test location /workspace/coverage/default/41.spi_device_flash_mode_ignore_cmds.3038478138
Short name T689
Test name
Test status
Simulation time 23110805785 ps
CPU time 77.36 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:31:48 PM PDT 24
Peak memory 249244 kb
Host smart-43dfab64-37e6-4799-aa69-316ac94a496f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038478138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_flash_mode_ignore_cmd
s.3038478138
Directory /workspace/41.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/41.spi_device_intercept.80715
Short name T252
Test name
Test status
Simulation time 372706768 ps
CPU time 5.74 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:30:25 PM PDT 24
Peak memory 232668 kb
Host smart-87e605c4-6172-4a8d-a71a-c119938018a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=80715 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_intercept.80715
Directory /workspace/41.spi_device_intercept/latest

Test location /workspace/coverage/default/41.spi_device_mailbox.4072712387
Short name T677
Test name
Test status
Simulation time 8317808936 ps
CPU time 30.71 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:30:50 PM PDT 24
Peak memory 232820 kb
Host smart-2affe678-9026-49c9-9d07-4f3d831e3cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072712387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_mailbox.4072712387
Directory /workspace/41.spi_device_mailbox/latest

Test location /workspace/coverage/default/41.spi_device_pass_addr_payload_swap.1034128670
Short name T542
Test name
Test status
Simulation time 1771843354 ps
CPU time 7.81 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:22 PM PDT 24
Peak memory 232476 kb
Host smart-c67d1083-c8b8-4073-90fe-7d29873dbd97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034128670 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_addr_payload_swa
p.1034128670
Directory /workspace/41.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/41.spi_device_pass_cmd_filtering.537599919
Short name T228
Test name
Test status
Simulation time 7595437144 ps
CPU time 7.72 seconds
Started Jul 07 05:30:21 PM PDT 24
Finished Jul 07 05:30:29 PM PDT 24
Peak memory 232844 kb
Host smart-d0615909-4089-4bf6-865c-7c6f7adb541d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537599919 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_pass_cmd_filtering.537599919
Directory /workspace/41.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/41.spi_device_read_buffer_direct.459617856
Short name T371
Test name
Test status
Simulation time 1036406788 ps
CPU time 9.39 seconds
Started Jul 07 05:30:12 PM PDT 24
Finished Jul 07 05:30:24 PM PDT 24
Peak memory 222488 kb
Host smart-962f470b-6b03-43a0-bb48-ab8c1c13865b
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=459617856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_read_buffer_dire
ct.459617856
Directory /workspace/41.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/41.spi_device_stress_all.3723387075
Short name T497
Test name
Test status
Simulation time 85176979 ps
CPU time 0.93 seconds
Started Jul 07 05:30:22 PM PDT 24
Finished Jul 07 05:30:24 PM PDT 24
Peak memory 206600 kb
Host smart-16563e32-c756-44ec-a996-99f13233797e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723387075 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_stre
ss_all.3723387075
Directory /workspace/41.spi_device_stress_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_all.2645413986
Short name T350
Test name
Test status
Simulation time 35672182 ps
CPU time 0.73 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:30:18 PM PDT 24
Peak memory 205992 kb
Host smart-daa46f6b-8361-4dcb-87c7-e063da88a12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645413986 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_all.2645413986
Directory /workspace/41.spi_device_tpm_all/latest

Test location /workspace/coverage/default/41.spi_device_tpm_read_hw_reg.3243255766
Short name T634
Test name
Test status
Simulation time 14841213815 ps
CPU time 10.84 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:30:29 PM PDT 24
Peak memory 216376 kb
Host smart-6ca72520-0d0b-458a-abf9-ddde5d5091d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243255766 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_read_hw_reg.3243255766
Directory /workspace/41.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/41.spi_device_tpm_rw.1355034287
Short name T667
Test name
Test status
Simulation time 86592077 ps
CPU time 1.07 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:12 PM PDT 24
Peak memory 207868 kb
Host smart-d8a924f4-e9b2-43da-ba7a-ceff56ba7654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1355034287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_rw.1355034287
Directory /workspace/41.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/41.spi_device_tpm_sts_read.3516853628
Short name T681
Test name
Test status
Simulation time 92190974 ps
CPU time 0.88 seconds
Started Jul 07 05:30:09 PM PDT 24
Finished Jul 07 05:30:11 PM PDT 24
Peak memory 205984 kb
Host smart-d644950b-74f1-4822-baee-76f48cf4c91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516853628 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_tpm_sts_read.3516853628
Directory /workspace/41.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/41.spi_device_upload.4014373486
Short name T259
Test name
Test status
Simulation time 11184792473 ps
CPU time 4.85 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:30:24 PM PDT 24
Peak memory 232796 kb
Host smart-1b4c33af-d216-4453-95d7-c73af14a8921
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014373486 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.spi_device_upload.4014373486
Directory /workspace/41.spi_device_upload/latest

Test location /workspace/coverage/default/42.spi_device_alert_test.1494462210
Short name T461
Test name
Test status
Simulation time 13096969 ps
CPU time 0.75 seconds
Started Jul 07 05:30:36 PM PDT 24
Finished Jul 07 05:30:37 PM PDT 24
Peak memory 205796 kb
Host smart-4b43057b-2b2e-4deb-91e5-9d77bfe8d60a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494462210 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_alert_test.
1494462210
Directory /workspace/42.spi_device_alert_test/latest

Test location /workspace/coverage/default/42.spi_device_cfg_cmd.109821065
Short name T811
Test name
Test status
Simulation time 459001729 ps
CPU time 4.45 seconds
Started Jul 07 05:30:21 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 232632 kb
Host smart-2f7e4a6c-2e24-4c24-8d58-c034cf341dbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109821065 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_cfg_cmd.109821065
Directory /workspace/42.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/42.spi_device_csb_read.1676174206
Short name T769
Test name
Test status
Simulation time 15693127 ps
CPU time 0.74 seconds
Started Jul 07 05:30:20 PM PDT 24
Finished Jul 07 05:30:21 PM PDT 24
Peak memory 206540 kb
Host smart-dbdbdb6a-d343-46d1-a1e9-0b57c96a5830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676174206 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_csb_read.1676174206
Directory /workspace/42.spi_device_csb_read/latest

Test location /workspace/coverage/default/42.spi_device_flash_all.1142543043
Short name T695
Test name
Test status
Simulation time 48664933291 ps
CPU time 43.69 seconds
Started Jul 07 05:30:32 PM PDT 24
Finished Jul 07 05:31:16 PM PDT 24
Peak memory 238564 kb
Host smart-51c687c0-8d68-478a-91c0-c975bb52dced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1142543043 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_all.1142543043
Directory /workspace/42.spi_device_flash_all/latest

Test location /workspace/coverage/default/42.spi_device_flash_and_tpm.3508339047
Short name T301
Test name
Test status
Simulation time 77463938739 ps
CPU time 258.3 seconds
Started Jul 07 05:30:17 PM PDT 24
Finished Jul 07 05:34:37 PM PDT 24
Peak memory 257456 kb
Host smart-65a2b950-11c7-4d83-9853-582a71f6240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508339047 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_and_tpm.3508339047
Directory /workspace/42.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode.3422492544
Short name T905
Test name
Test status
Simulation time 957482958 ps
CPU time 5.79 seconds
Started Jul 07 05:30:20 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 224476 kb
Host smart-1b714e05-8a3b-446d-a1b6-7c85608d4b51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422492544 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode.3422492544
Directory /workspace/42.spi_device_flash_mode/latest

Test location /workspace/coverage/default/42.spi_device_flash_mode_ignore_cmds.3954810992
Short name T256
Test name
Test status
Simulation time 162815875027 ps
CPU time 166.11 seconds
Started Jul 07 05:30:27 PM PDT 24
Finished Jul 07 05:33:18 PM PDT 24
Peak memory 239460 kb
Host smart-9d44669c-91cf-4f4e-81a8-c54121a1e464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954810992 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_flash_mode_ignore_cmd
s.3954810992
Directory /workspace/42.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/42.spi_device_intercept.427855104
Short name T534
Test name
Test status
Simulation time 2202505988 ps
CPU time 28.07 seconds
Started Jul 07 05:30:20 PM PDT 24
Finished Jul 07 05:30:49 PM PDT 24
Peak memory 224536 kb
Host smart-6faa9faf-c77b-4458-8b2e-101cce524bf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=427855104 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_intercept.427855104
Directory /workspace/42.spi_device_intercept/latest

Test location /workspace/coverage/default/42.spi_device_mailbox.2486937870
Short name T514
Test name
Test status
Simulation time 8387083671 ps
CPU time 41.13 seconds
Started Jul 07 05:30:10 PM PDT 24
Finished Jul 07 05:30:53 PM PDT 24
Peak memory 240796 kb
Host smart-f2c01125-129d-4583-ba10-95170aa0c34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2486937870 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_mailbox.2486937870
Directory /workspace/42.spi_device_mailbox/latest

Test location /workspace/coverage/default/42.spi_device_pass_addr_payload_swap.3440596271
Short name T332
Test name
Test status
Simulation time 58308046 ps
CPU time 2.55 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:18 PM PDT 24
Peak memory 232280 kb
Host smart-08dd60ac-55b4-4a36-ad74-54817203d97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440596271 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_addr_payload_swa
p.3440596271
Directory /workspace/42.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/42.spi_device_pass_cmd_filtering.1966382952
Short name T975
Test name
Test status
Simulation time 3340031108 ps
CPU time 9.43 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:30:29 PM PDT 24
Peak memory 233028 kb
Host smart-d11a8ea5-0b45-488a-9207-b57fec48a2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966382952 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_pass_cmd_filtering.1966382952
Directory /workspace/42.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/42.spi_device_read_buffer_direct.3052664590
Short name T991
Test name
Test status
Simulation time 694397871 ps
CPU time 11.52 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:42 PM PDT 24
Peak memory 220464 kb
Host smart-2033618a-3a42-4f92-8ad3-66b224aff2c1
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3052664590 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_read_buffer_dir
ect.3052664590
Directory /workspace/42.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/42.spi_device_stress_all.3171655034
Short name T824
Test name
Test status
Simulation time 47337673 ps
CPU time 1.01 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 207440 kb
Host smart-dfffa7e1-18a3-4d1d-b7ff-906392f8de30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171655034 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_stre
ss_all.3171655034
Directory /workspace/42.spi_device_stress_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_all.3098667996
Short name T24
Test name
Test status
Simulation time 2165763081 ps
CPU time 27.99 seconds
Started Jul 07 05:30:19 PM PDT 24
Finished Jul 07 05:30:47 PM PDT 24
Peak memory 219800 kb
Host smart-c7aa77b0-6f1e-4811-8df0-c6b0717574a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098667996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_all.3098667996
Directory /workspace/42.spi_device_tpm_all/latest

Test location /workspace/coverage/default/42.spi_device_tpm_read_hw_reg.1389004568
Short name T622
Test name
Test status
Simulation time 4102268937 ps
CPU time 5.13 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:21 PM PDT 24
Peak memory 216268 kb
Host smart-378ea9b6-fd76-4c4f-a012-b25e1f7cb45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389004568 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_read_hw_reg.1389004568
Directory /workspace/42.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/42.spi_device_tpm_rw.3727720082
Short name T171
Test name
Test status
Simulation time 12118431 ps
CPU time 0.68 seconds
Started Jul 07 05:30:13 PM PDT 24
Finished Jul 07 05:30:16 PM PDT 24
Peak memory 205664 kb
Host smart-8204ff16-b48c-4323-8331-5d3b129fe349
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727720082 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_rw.3727720082
Directory /workspace/42.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/42.spi_device_tpm_sts_read.15916070
Short name T420
Test name
Test status
Simulation time 225792599 ps
CPU time 0.89 seconds
Started Jul 07 05:30:14 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 207000 kb
Host smart-023b4485-a676-42fd-80b6-fee0f0239f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15916070 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_tpm_sts_read.15916070
Directory /workspace/42.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/42.spi_device_upload.565506246
Short name T60
Test name
Test status
Simulation time 411798131 ps
CPU time 5.56 seconds
Started Jul 07 05:30:18 PM PDT 24
Finished Jul 07 05:30:25 PM PDT 24
Peak memory 224428 kb
Host smart-5f894af9-76e6-4f3c-b78c-a995f0d5dbc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=565506246 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.spi_device_upload.565506246
Directory /workspace/42.spi_device_upload/latest

Test location /workspace/coverage/default/43.spi_device_alert_test.3728607458
Short name T749
Test name
Test status
Simulation time 42230992 ps
CPU time 0.78 seconds
Started Jul 07 05:30:28 PM PDT 24
Finished Jul 07 05:30:30 PM PDT 24
Peak memory 204968 kb
Host smart-93e7eb18-d506-4b74-9e96-8a5076a6734a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728607458 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_alert_test.
3728607458
Directory /workspace/43.spi_device_alert_test/latest

Test location /workspace/coverage/default/43.spi_device_cfg_cmd.2748790444
Short name T451
Test name
Test status
Simulation time 95942479 ps
CPU time 3.13 seconds
Started Jul 07 05:30:27 PM PDT 24
Finished Jul 07 05:30:30 PM PDT 24
Peak memory 232632 kb
Host smart-4eba89c1-30c4-49e9-b2c7-cfaa79418bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748790444 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_cfg_cmd.2748790444
Directory /workspace/43.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/43.spi_device_csb_read.4265125292
Short name T671
Test name
Test status
Simulation time 26038682 ps
CPU time 0.77 seconds
Started Jul 07 05:30:22 PM PDT 24
Finished Jul 07 05:30:23 PM PDT 24
Peak memory 206600 kb
Host smart-e36e4014-efe7-485e-ab98-bcd9b2a0e912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265125292 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_csb_read.4265125292
Directory /workspace/43.spi_device_csb_read/latest

Test location /workspace/coverage/default/43.spi_device_flash_all.3440576761
Short name T286
Test name
Test status
Simulation time 2438268386 ps
CPU time 51.71 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:31:39 PM PDT 24
Peak memory 265504 kb
Host smart-1a90db2f-87de-4c3a-a559-fe17627f226d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440576761 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_all.3440576761
Directory /workspace/43.spi_device_flash_all/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm.3655229583
Short name T923
Test name
Test status
Simulation time 7872899568 ps
CPU time 76.97 seconds
Started Jul 07 05:30:27 PM PDT 24
Finished Jul 07 05:31:44 PM PDT 24
Peak memory 240616 kb
Host smart-71fe9e49-04c6-4886-8d64-4c15dd824fad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655229583 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm.3655229583
Directory /workspace/43.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/43.spi_device_flash_and_tpm_min_idle.1943951240
Short name T637
Test name
Test status
Simulation time 40459304323 ps
CPU time 368.39 seconds
Started Jul 07 05:30:28 PM PDT 24
Finished Jul 07 05:36:37 PM PDT 24
Peak memory 237024 kb
Host smart-501cb1c3-1fb0-4b9f-8de8-97bfa3f47c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943951240 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_and_tpm_min_idl
e.1943951240
Directory /workspace/43.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode.2730085293
Short name T440
Test name
Test status
Simulation time 38212813 ps
CPU time 2.63 seconds
Started Jul 07 05:30:24 PM PDT 24
Finished Jul 07 05:30:27 PM PDT 24
Peak memory 232688 kb
Host smart-27fc1c58-a251-4fb6-a874-85dbab6d326b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730085293 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode.2730085293
Directory /workspace/43.spi_device_flash_mode/latest

Test location /workspace/coverage/default/43.spi_device_flash_mode_ignore_cmds.1231661158
Short name T203
Test name
Test status
Simulation time 82018166142 ps
CPU time 71.34 seconds
Started Jul 07 05:30:32 PM PDT 24
Finished Jul 07 05:31:43 PM PDT 24
Peak memory 234588 kb
Host smart-988d8edc-5ec7-4f57-b068-aef620e84907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231661158 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_flash_mode_ignore_cmd
s.1231661158
Directory /workspace/43.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/43.spi_device_intercept.2927230384
Short name T598
Test name
Test status
Simulation time 10471237696 ps
CPU time 10.76 seconds
Started Jul 07 05:30:23 PM PDT 24
Finished Jul 07 05:30:34 PM PDT 24
Peak memory 224572 kb
Host smart-903d96e2-6f99-4d62-9abe-afadad6598d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927230384 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_intercept.2927230384
Directory /workspace/43.spi_device_intercept/latest

Test location /workspace/coverage/default/43.spi_device_mailbox.2896753934
Short name T580
Test name
Test status
Simulation time 5302064989 ps
CPU time 43.38 seconds
Started Jul 07 05:30:27 PM PDT 24
Finished Jul 07 05:31:16 PM PDT 24
Peak memory 224512 kb
Host smart-4cc43bf6-de2b-4992-a59a-3d75ea6276fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2896753934 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_mailbox.2896753934
Directory /workspace/43.spi_device_mailbox/latest

Test location /workspace/coverage/default/43.spi_device_pass_addr_payload_swap.2121148699
Short name T562
Test name
Test status
Simulation time 630935057 ps
CPU time 2.69 seconds
Started Jul 07 05:30:29 PM PDT 24
Finished Jul 07 05:30:32 PM PDT 24
Peak memory 232660 kb
Host smart-19cff37a-645f-4dd8-9155-0ea87f06f47f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121148699 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_addr_payload_swa
p.2121148699
Directory /workspace/43.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/43.spi_device_pass_cmd_filtering.2028640624
Short name T867
Test name
Test status
Simulation time 26912633535 ps
CPU time 16.11 seconds
Started Jul 07 05:30:16 PM PDT 24
Finished Jul 07 05:30:34 PM PDT 24
Peak memory 224532 kb
Host smart-161d5e83-7412-443e-90c0-faacb616894f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028640624 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_pass_cmd_filtering.2028640624
Directory /workspace/43.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/43.spi_device_read_buffer_direct.4075477109
Short name T536
Test name
Test status
Simulation time 231890117 ps
CPU time 4.27 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:35 PM PDT 24
Peak memory 223248 kb
Host smart-9dc52871-dbaf-4ebe-b662-f52b6e64e3a2
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=4075477109 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_read_buffer_dir
ect.4075477109
Directory /workspace/43.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/43.spi_device_stress_all.666584947
Short name T17
Test name
Test status
Simulation time 23694562423 ps
CPU time 230.78 seconds
Started Jul 07 05:30:31 PM PDT 24
Finished Jul 07 05:34:23 PM PDT 24
Peak memory 249236 kb
Host smart-011d367f-daad-471e-a199-827e2ae99eb0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666584947 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_stres
s_all.666584947
Directory /workspace/43.spi_device_stress_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_all.3721711010
Short name T931
Test name
Test status
Simulation time 8948850552 ps
CPU time 42.34 seconds
Started Jul 07 05:30:29 PM PDT 24
Finished Jul 07 05:31:12 PM PDT 24
Peak memory 216312 kb
Host smart-2f571a54-3b54-4704-9185-1a4c2a25ff55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721711010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_all.3721711010
Directory /workspace/43.spi_device_tpm_all/latest

Test location /workspace/coverage/default/43.spi_device_tpm_read_hw_reg.2718811662
Short name T529
Test name
Test status
Simulation time 4443813705 ps
CPU time 10.96 seconds
Started Jul 07 05:30:46 PM PDT 24
Finished Jul 07 05:30:58 PM PDT 24
Peak memory 216304 kb
Host smart-f957e0a2-2754-419e-9d6f-b8d5f439b5c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2718811662 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_read_hw_reg.2718811662
Directory /workspace/43.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/43.spi_device_tpm_rw.2302051502
Short name T652
Test name
Test status
Simulation time 56182980 ps
CPU time 0.93 seconds
Started Jul 07 05:30:22 PM PDT 24
Finished Jul 07 05:30:28 PM PDT 24
Peak memory 207164 kb
Host smart-5ef04834-c0dd-45f7-bdd2-d19a2557f0ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302051502 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_rw.2302051502
Directory /workspace/43.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/43.spi_device_tpm_sts_read.2472354385
Short name T804
Test name
Test status
Simulation time 130848420 ps
CPU time 1.06 seconds
Started Jul 07 05:30:26 PM PDT 24
Finished Jul 07 05:30:28 PM PDT 24
Peak memory 207016 kb
Host smart-1e0e1815-43f9-418b-825f-27f2541767a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2472354385 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_tpm_sts_read.2472354385
Directory /workspace/43.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/43.spi_device_upload.3712559141
Short name T423
Test name
Test status
Simulation time 2955558122 ps
CPU time 11.87 seconds
Started Jul 07 05:30:19 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 232760 kb
Host smart-2d2d0a60-bd64-4a5c-9a9b-87e43ff3ebe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712559141 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.spi_device_upload.3712559141
Directory /workspace/43.spi_device_upload/latest

Test location /workspace/coverage/default/44.spi_device_alert_test.4142171856
Short name T594
Test name
Test status
Simulation time 12589519 ps
CPU time 0.72 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 204988 kb
Host smart-4a36a416-f869-4d48-9d6e-7ee4619afd63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4142171856 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_alert_test.
4142171856
Directory /workspace/44.spi_device_alert_test/latest

Test location /workspace/coverage/default/44.spi_device_cfg_cmd.645214236
Short name T825
Test name
Test status
Simulation time 437242574 ps
CPU time 4.68 seconds
Started Jul 07 05:30:26 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 224456 kb
Host smart-da43236e-7cac-4d89-9c04-58728e56f3ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645214236 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_cfg_cmd.645214236
Directory /workspace/44.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/44.spi_device_csb_read.2055543589
Short name T902
Test name
Test status
Simulation time 31937722 ps
CPU time 0.8 seconds
Started Jul 07 05:30:31 PM PDT 24
Finished Jul 07 05:30:32 PM PDT 24
Peak memory 206616 kb
Host smart-c5d0b7d8-9b9b-4672-8aad-d5e35174d912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055543589 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_csb_read.2055543589
Directory /workspace/44.spi_device_csb_read/latest

Test location /workspace/coverage/default/44.spi_device_flash_all.2697451189
Short name T588
Test name
Test status
Simulation time 10496594141 ps
CPU time 55.65 seconds
Started Jul 07 05:30:35 PM PDT 24
Finished Jul 07 05:31:31 PM PDT 24
Peak memory 249196 kb
Host smart-8261658d-e473-48f9-9bde-0a4b26f8e273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697451189 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_all.2697451189
Directory /workspace/44.spi_device_flash_all/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm.3199938843
Short name T989
Test name
Test status
Simulation time 37836898442 ps
CPU time 95.4 seconds
Started Jul 07 05:31:35 PM PDT 24
Finished Jul 07 05:33:11 PM PDT 24
Peak memory 249248 kb
Host smart-c87eb9bc-d7ea-4c64-9441-1ad8ca22189b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199938843 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm.3199938843
Directory /workspace/44.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/44.spi_device_flash_and_tpm_min_idle.1049371138
Short name T51
Test name
Test status
Simulation time 8207530900 ps
CPU time 51.59 seconds
Started Jul 07 05:30:27 PM PDT 24
Finished Jul 07 05:31:19 PM PDT 24
Peak memory 249204 kb
Host smart-d0e5577a-d442-48f3-aff1-62af356262b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049371138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_and_tpm_min_idl
e.1049371138
Directory /workspace/44.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode.4210221386
Short name T527
Test name
Test status
Simulation time 340110539 ps
CPU time 3.52 seconds
Started Jul 07 05:30:34 PM PDT 24
Finished Jul 07 05:30:38 PM PDT 24
Peak memory 232692 kb
Host smart-4b9153db-5522-4e84-b62d-12e17db198d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210221386 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode.4210221386
Directory /workspace/44.spi_device_flash_mode/latest

Test location /workspace/coverage/default/44.spi_device_flash_mode_ignore_cmds.3983469552
Short name T988
Test name
Test status
Simulation time 31064535626 ps
CPU time 239.08 seconds
Started Jul 07 05:30:22 PM PDT 24
Finished Jul 07 05:34:22 PM PDT 24
Peak memory 257372 kb
Host smart-8ce8390a-da6e-4465-9866-eed8b7ac205a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3983469552 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_flash_mode_ignore_cmd
s.3983469552
Directory /workspace/44.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/44.spi_device_intercept.1283721394
Short name T278
Test name
Test status
Simulation time 160590186 ps
CPU time 3.28 seconds
Started Jul 07 05:30:29 PM PDT 24
Finished Jul 07 05:30:33 PM PDT 24
Peak memory 224484 kb
Host smart-f80977fb-4b82-4521-89b7-115a3d1aad0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283721394 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_intercept.1283721394
Directory /workspace/44.spi_device_intercept/latest

Test location /workspace/coverage/default/44.spi_device_mailbox.3857285996
Short name T862
Test name
Test status
Simulation time 3488451499 ps
CPU time 14.97 seconds
Started Jul 07 05:30:38 PM PDT 24
Finished Jul 07 05:30:53 PM PDT 24
Peak memory 232768 kb
Host smart-0b6a581f-da9d-4e71-b1b4-61534368e50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857285996 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_mailbox.3857285996
Directory /workspace/44.spi_device_mailbox/latest

Test location /workspace/coverage/default/44.spi_device_pass_addr_payload_swap.2910275227
Short name T424
Test name
Test status
Simulation time 600205169 ps
CPU time 11.51 seconds
Started Jul 07 05:30:35 PM PDT 24
Finished Jul 07 05:30:47 PM PDT 24
Peak memory 224520 kb
Host smart-a1511a85-8c70-44c9-bba3-d477ad32ffdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910275227 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_addr_payload_swa
p.2910275227
Directory /workspace/44.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/44.spi_device_pass_cmd_filtering.4243082569
Short name T697
Test name
Test status
Simulation time 6971960972 ps
CPU time 22.09 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:52 PM PDT 24
Peak memory 248684 kb
Host smart-55033475-ba6c-4eff-8e16-f2dabed7d81e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243082569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_pass_cmd_filtering.4243082569
Directory /workspace/44.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/44.spi_device_read_buffer_direct.292348390
Short name T619
Test name
Test status
Simulation time 306630995 ps
CPU time 3.7 seconds
Started Jul 07 05:30:22 PM PDT 24
Finished Jul 07 05:30:26 PM PDT 24
Peak memory 223076 kb
Host smart-8467eb1f-7187-483e-8bf9-d4f4d333a17c
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=292348390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_read_buffer_dire
ct.292348390
Directory /workspace/44.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/44.spi_device_stress_all.3867391584
Short name T631
Test name
Test status
Simulation time 81289486 ps
CPU time 0.95 seconds
Started Jul 07 05:30:23 PM PDT 24
Finished Jul 07 05:30:24 PM PDT 24
Peak memory 206788 kb
Host smart-cd9abe98-ad72-4125-8699-a1ac705edbed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3867391584 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_stre
ss_all.3867391584
Directory /workspace/44.spi_device_stress_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_all.4035946133
Short name T323
Test name
Test status
Simulation time 12742468840 ps
CPU time 27.66 seconds
Started Jul 07 05:30:34 PM PDT 24
Finished Jul 07 05:31:02 PM PDT 24
Peak memory 216360 kb
Host smart-181d5da6-203f-438b-88c5-e188aad8e2d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035946133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_all.4035946133
Directory /workspace/44.spi_device_tpm_all/latest

Test location /workspace/coverage/default/44.spi_device_tpm_read_hw_reg.4251535466
Short name T910
Test name
Test status
Simulation time 1421922892 ps
CPU time 8.98 seconds
Started Jul 07 05:30:51 PM PDT 24
Finished Jul 07 05:31:01 PM PDT 24
Peak memory 216240 kb
Host smart-02f92f9c-45f1-4d9a-89e4-7bc63a01f861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251535466 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_read_hw_reg.4251535466
Directory /workspace/44.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/44.spi_device_tpm_rw.1895169107
Short name T418
Test name
Test status
Simulation time 76309668 ps
CPU time 0.98 seconds
Started Jul 07 05:30:33 PM PDT 24
Finished Jul 07 05:30:34 PM PDT 24
Peak memory 206996 kb
Host smart-b0568a76-7612-4d37-9394-41875a3d131a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1895169107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_rw.1895169107
Directory /workspace/44.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/44.spi_device_tpm_sts_read.1260283930
Short name T728
Test name
Test status
Simulation time 361816323 ps
CPU time 0.88 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:30:44 PM PDT 24
Peak memory 207012 kb
Host smart-32d7d732-bf94-4464-bead-9f2039430c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260283930 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_tpm_sts_read.1260283930
Directory /workspace/44.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/44.spi_device_upload.1620107758
Short name T40
Test name
Test status
Simulation time 2611300387 ps
CPU time 8.67 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:39 PM PDT 24
Peak memory 232816 kb
Host smart-3e498831-ce94-4b52-83f4-71b840244427
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620107758 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.spi_device_upload.1620107758
Directory /workspace/44.spi_device_upload/latest

Test location /workspace/coverage/default/45.spi_device_alert_test.3192787569
Short name T62
Test name
Test status
Simulation time 14903746 ps
CPU time 0.76 seconds
Started Jul 07 05:30:35 PM PDT 24
Finished Jul 07 05:30:36 PM PDT 24
Peak memory 205880 kb
Host smart-3ae7a389-a31c-4ef9-9b69-1a6fdf54429b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192787569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_alert_test.
3192787569
Directory /workspace/45.spi_device_alert_test/latest

Test location /workspace/coverage/default/45.spi_device_cfg_cmd.1382029998
Short name T643
Test name
Test status
Simulation time 65307081 ps
CPU time 2.59 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:30:44 PM PDT 24
Peak memory 232680 kb
Host smart-e88a2e23-d6ad-4516-a1b9-062a080221e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382029998 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_cfg_cmd.1382029998
Directory /workspace/45.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/45.spi_device_csb_read.2307988698
Short name T917
Test name
Test status
Simulation time 19740110 ps
CPU time 0.78 seconds
Started Jul 07 05:30:33 PM PDT 24
Finished Jul 07 05:30:34 PM PDT 24
Peak memory 206864 kb
Host smart-5ddd339c-4b2a-462a-968d-026cbc271cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307988698 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_csb_read.2307988698
Directory /workspace/45.spi_device_csb_read/latest

Test location /workspace/coverage/default/45.spi_device_flash_all.3797231063
Short name T217
Test name
Test status
Simulation time 30844452407 ps
CPU time 49.64 seconds
Started Jul 07 05:30:28 PM PDT 24
Finished Jul 07 05:31:18 PM PDT 24
Peak memory 237872 kb
Host smart-ff97305e-aefe-4737-9f45-9ad7b6979747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797231063 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_all.3797231063
Directory /workspace/45.spi_device_flash_all/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm.2484021810
Short name T413
Test name
Test status
Simulation time 3629722535 ps
CPU time 44.83 seconds
Started Jul 07 05:30:31 PM PDT 24
Finished Jul 07 05:31:16 PM PDT 24
Peak memory 239864 kb
Host smart-8556038a-8d52-4900-b9f4-d1d9f0a51ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2484021810 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm.2484021810
Directory /workspace/45.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/45.spi_device_flash_and_tpm_min_idle.971755596
Short name T383
Test name
Test status
Simulation time 2155209773 ps
CPU time 49.66 seconds
Started Jul 07 05:30:29 PM PDT 24
Finished Jul 07 05:31:19 PM PDT 24
Peak memory 254340 kb
Host smart-affadcf0-2e74-4643-960a-d00fb79b489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971755596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_and_tpm_min_idle
.971755596
Directory /workspace/45.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode.641545477
Short name T143
Test name
Test status
Simulation time 2045134069 ps
CPU time 6.48 seconds
Started Jul 07 05:30:39 PM PDT 24
Finished Jul 07 05:30:46 PM PDT 24
Peak memory 224476 kb
Host smart-0f8a43eb-2769-497f-a61e-6c1fba20bf75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641545477 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode.641545477
Directory /workspace/45.spi_device_flash_mode/latest

Test location /workspace/coverage/default/45.spi_device_flash_mode_ignore_cmds.2065603374
Short name T918
Test name
Test status
Simulation time 5318578086 ps
CPU time 27.53 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:31:11 PM PDT 24
Peak memory 239156 kb
Host smart-c66ad635-ef5e-4b68-ade5-726732620e1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065603374 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_flash_mode_ignore_cmd
s.2065603374
Directory /workspace/45.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/45.spi_device_intercept.1100924858
Short name T788
Test name
Test status
Simulation time 83678623 ps
CPU time 3.73 seconds
Started Jul 07 05:30:34 PM PDT 24
Finished Jul 07 05:30:38 PM PDT 24
Peak memory 232712 kb
Host smart-ea997dca-06cc-4334-8148-5421371f916f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100924858 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_intercept.1100924858
Directory /workspace/45.spi_device_intercept/latest

Test location /workspace/coverage/default/45.spi_device_mailbox.3137981440
Short name T799
Test name
Test status
Simulation time 1023916826 ps
CPU time 5.41 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:36 PM PDT 24
Peak memory 224420 kb
Host smart-01094185-f475-42ae-905f-8f053bffcbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137981440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_mailbox.3137981440
Directory /workspace/45.spi_device_mailbox/latest

Test location /workspace/coverage/default/45.spi_device_pass_addr_payload_swap.745822677
Short name T130
Test name
Test status
Simulation time 8611160210 ps
CPU time 15.35 seconds
Started Jul 07 05:30:34 PM PDT 24
Finished Jul 07 05:30:50 PM PDT 24
Peak memory 232780 kb
Host smart-11ea5725-38af-4aaa-b63d-7dbd3fc364bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=745822677 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_addr_payload_swap
.745822677
Directory /workspace/45.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/45.spi_device_pass_cmd_filtering.803642601
Short name T806
Test name
Test status
Simulation time 1395219141 ps
CPU time 11.14 seconds
Started Jul 07 05:30:36 PM PDT 24
Finished Jul 07 05:30:48 PM PDT 24
Peak memory 240776 kb
Host smart-156077e7-ed58-41db-86ad-31f442443eb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803642601 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_pass_cmd_filtering.803642601
Directory /workspace/45.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/45.spi_device_read_buffer_direct.3795339526
Short name T384
Test name
Test status
Simulation time 749532063 ps
CPU time 4.19 seconds
Started Jul 07 05:30:40 PM PDT 24
Finished Jul 07 05:30:44 PM PDT 24
Peak memory 223228 kb
Host smart-ac20eccb-6909-4f88-bf6e-6ade1b358f78
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3795339526 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_read_buffer_dir
ect.3795339526
Directory /workspace/45.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/45.spi_device_stress_all.2511583755
Short name T515
Test name
Test status
Simulation time 181830198 ps
CPU time 0.91 seconds
Started Jul 07 05:30:28 PM PDT 24
Finished Jul 07 05:30:30 PM PDT 24
Peak memory 207560 kb
Host smart-7707cebf-759c-4b7c-86aa-8f00ac531c39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511583755 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_stre
ss_all.2511583755
Directory /workspace/45.spi_device_stress_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_all.4039328131
Short name T483
Test name
Test status
Simulation time 1983092115 ps
CPU time 5.4 seconds
Started Jul 07 05:30:44 PM PDT 24
Finished Jul 07 05:30:50 PM PDT 24
Peak memory 216508 kb
Host smart-81508629-429d-4a3d-87fd-1ec44d83b888
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039328131 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_all.4039328131
Directory /workspace/45.spi_device_tpm_all/latest

Test location /workspace/coverage/default/45.spi_device_tpm_read_hw_reg.1408324145
Short name T338
Test name
Test status
Simulation time 2351723858 ps
CPU time 6.13 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:36 PM PDT 24
Peak memory 216316 kb
Host smart-8f55f786-2cc6-48f4-b206-328510e61455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1408324145 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_read_hw_reg.1408324145
Directory /workspace/45.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/45.spi_device_tpm_rw.208903117
Short name T651
Test name
Test status
Simulation time 104721679 ps
CPU time 0.85 seconds
Started Jul 07 05:30:23 PM PDT 24
Finished Jul 07 05:30:24 PM PDT 24
Peak memory 207036 kb
Host smart-532b75ae-c2ef-4e9c-9f72-32be737444f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208903117 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_rw.208903117
Directory /workspace/45.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/45.spi_device_tpm_sts_read.695258822
Short name T688
Test name
Test status
Simulation time 60413361 ps
CPU time 0.92 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:30:51 PM PDT 24
Peak memory 206952 kb
Host smart-1efb85c0-1140-4a70-8cb8-84a4dbbea01a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695258822 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_tpm_sts_read.695258822
Directory /workspace/45.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/45.spi_device_upload.3416651323
Short name T846
Test name
Test status
Simulation time 286295718 ps
CPU time 2.82 seconds
Started Jul 07 05:30:35 PM PDT 24
Finished Jul 07 05:30:38 PM PDT 24
Peak memory 232724 kb
Host smart-1c85c462-515e-4bdb-8a31-90ccc9fa305f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416651323 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.spi_device_upload.3416651323
Directory /workspace/45.spi_device_upload/latest

Test location /workspace/coverage/default/46.spi_device_alert_test.2403190286
Short name T726
Test name
Test status
Simulation time 34475141 ps
CPU time 0.71 seconds
Started Jul 07 05:30:45 PM PDT 24
Finished Jul 07 05:30:47 PM PDT 24
Peak memory 204980 kb
Host smart-dc1fc66c-1b7c-46e5-99c1-e1915cc92346
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403190286 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_alert_test.
2403190286
Directory /workspace/46.spi_device_alert_test/latest

Test location /workspace/coverage/default/46.spi_device_cfg_cmd.1264728471
Short name T254
Test name
Test status
Simulation time 7566720186 ps
CPU time 20.78 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:31:05 PM PDT 24
Peak memory 224568 kb
Host smart-5df8a179-c9f5-4611-b785-676111a9bcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1264728471 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_cfg_cmd.1264728471
Directory /workspace/46.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/46.spi_device_csb_read.3550780509
Short name T513
Test name
Test status
Simulation time 52349512 ps
CPU time 0.76 seconds
Started Jul 07 05:30:32 PM PDT 24
Finished Jul 07 05:30:33 PM PDT 24
Peak memory 205576 kb
Host smart-34409917-74cb-4cff-8299-c0cc035d90dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3550780509 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_csb_read.3550780509
Directory /workspace/46.spi_device_csb_read/latest

Test location /workspace/coverage/default/46.spi_device_flash_all.972683567
Short name T53
Test name
Test status
Simulation time 4361712948 ps
CPU time 68.95 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:31:58 PM PDT 24
Peak memory 257316 kb
Host smart-4f240d9a-b6f3-4511-b89d-d5f3ca37e275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972683567 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_all.972683567
Directory /workspace/46.spi_device_flash_all/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm.3302957720
Short name T48
Test name
Test status
Simulation time 8816914674 ps
CPU time 59.64 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:31:48 PM PDT 24
Peak memory 260412 kb
Host smart-c52bb996-7f5b-4ce6-82d8-980ec11787c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302957720 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm.3302957720
Directory /workspace/46.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/46.spi_device_flash_and_tpm_min_idle.3341365703
Short name T602
Test name
Test status
Simulation time 19919368355 ps
CPU time 84.06 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:32:08 PM PDT 24
Peak memory 249252 kb
Host smart-eb583b52-7d7a-4dd7-88bc-39dedfc273f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341365703 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_and_tpm_min_idl
e.3341365703
Directory /workspace/46.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode.3830845051
Short name T674
Test name
Test status
Simulation time 440241594 ps
CPU time 5.69 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:30:49 PM PDT 24
Peak memory 232708 kb
Host smart-89605534-f883-4289-b47f-acf2a257b65f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830845051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode.3830845051
Directory /workspace/46.spi_device_flash_mode/latest

Test location /workspace/coverage/default/46.spi_device_flash_mode_ignore_cmds.2207306081
Short name T1004
Test name
Test status
Simulation time 78957736543 ps
CPU time 57.56 seconds
Started Jul 07 05:30:51 PM PDT 24
Finished Jul 07 05:31:49 PM PDT 24
Peak memory 249212 kb
Host smart-564da7b6-d287-4a49-924b-d59878a8b66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2207306081 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_flash_mode_ignore_cmd
s.2207306081
Directory /workspace/46.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/46.spi_device_intercept.3151272014
Short name T758
Test name
Test status
Simulation time 83211483 ps
CPU time 2.64 seconds
Started Jul 07 05:30:35 PM PDT 24
Finished Jul 07 05:30:38 PM PDT 24
Peak memory 224444 kb
Host smart-4c8f39d8-ad18-477d-820b-03e4fcc1d73d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151272014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_intercept.3151272014
Directory /workspace/46.spi_device_intercept/latest

Test location /workspace/coverage/default/46.spi_device_mailbox.2794112786
Short name T600
Test name
Test status
Simulation time 24820126873 ps
CPU time 17.41 seconds
Started Jul 07 05:30:38 PM PDT 24
Finished Jul 07 05:30:56 PM PDT 24
Peak memory 236648 kb
Host smart-3eb5730a-96ab-40f2-832c-11ea7be884d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794112786 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_mailbox.2794112786
Directory /workspace/46.spi_device_mailbox/latest

Test location /workspace/coverage/default/46.spi_device_pass_addr_payload_swap.3307453889
Short name T782
Test name
Test status
Simulation time 322221365 ps
CPU time 3.07 seconds
Started Jul 07 05:30:39 PM PDT 24
Finished Jul 07 05:30:42 PM PDT 24
Peak memory 232708 kb
Host smart-1f4fc062-46ca-41b0-9bf6-ebb0a5a1e6dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3307453889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_addr_payload_swa
p.3307453889
Directory /workspace/46.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/46.spi_device_pass_cmd_filtering.3175528447
Short name T167
Test name
Test status
Simulation time 1103149251 ps
CPU time 6.64 seconds
Started Jul 07 05:30:36 PM PDT 24
Finished Jul 07 05:30:43 PM PDT 24
Peak memory 224500 kb
Host smart-872fe3ac-b066-4f80-a47a-a505acf2776d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175528447 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_pass_cmd_filtering.3175528447
Directory /workspace/46.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/46.spi_device_read_buffer_direct.3372471539
Short name T694
Test name
Test status
Simulation time 2383758152 ps
CPU time 7.29 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:30:50 PM PDT 24
Peak memory 222184 kb
Host smart-cd1b7269-29f5-4a87-a36d-06e0ad854c1a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3372471539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_read_buffer_dir
ect.3372471539
Directory /workspace/46.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/46.spi_device_stress_all.708919397
Short name T719
Test name
Test status
Simulation time 14406568765 ps
CPU time 133.4 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:32:57 PM PDT 24
Peak memory 241096 kb
Host smart-f02bc0e9-9600-4892-a4e5-e03278c83aeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708919397 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_stres
s_all.708919397
Directory /workspace/46.spi_device_stress_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_all.2213242194
Short name T590
Test name
Test status
Simulation time 43654216215 ps
CPU time 25.08 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:56 PM PDT 24
Peak memory 216428 kb
Host smart-fa222c09-6e41-4198-bf51-3438231d1169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213242194 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_all.2213242194
Directory /workspace/46.spi_device_tpm_all/latest

Test location /workspace/coverage/default/46.spi_device_tpm_read_hw_reg.461535876
Short name T977
Test name
Test status
Simulation time 6611134904 ps
CPU time 13.15 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:30:57 PM PDT 24
Peak memory 216348 kb
Host smart-1ad04445-cdb9-44ea-a365-ed760e09cfdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461535876 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_read_hw_reg.461535876
Directory /workspace/46.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/46.spi_device_tpm_rw.2102509121
Short name T733
Test name
Test status
Simulation time 250482358 ps
CPU time 1.5 seconds
Started Jul 07 05:30:31 PM PDT 24
Finished Jul 07 05:30:33 PM PDT 24
Peak memory 216252 kb
Host smart-1e4892a1-4764-4598-9144-4ab64f2f0564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102509121 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_rw.2102509121
Directory /workspace/46.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/46.spi_device_tpm_sts_read.2960509973
Short name T581
Test name
Test status
Simulation time 161373134 ps
CPU time 0.83 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 206272 kb
Host smart-1324b91a-3c78-4d74-982f-8b556dfb3d85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2960509973 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_tpm_sts_read.2960509973
Directory /workspace/46.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/46.spi_device_upload.3485137140
Short name T710
Test name
Test status
Simulation time 1149896347 ps
CPU time 6.38 seconds
Started Jul 07 05:30:39 PM PDT 24
Finished Jul 07 05:30:45 PM PDT 24
Peak memory 224484 kb
Host smart-129c4a75-6633-4083-b965-bae9a64cd7af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485137140 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.spi_device_upload.3485137140
Directory /workspace/46.spi_device_upload/latest

Test location /workspace/coverage/default/47.spi_device_alert_test.2052374053
Short name T996
Test name
Test status
Simulation time 26439089 ps
CPU time 0.69 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 05:30:50 PM PDT 24
Peak memory 205540 kb
Host smart-8555b6bf-cd80-4bdb-81d7-dd52d45fb566
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052374053 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_alert_test.
2052374053
Directory /workspace/47.spi_device_alert_test/latest

Test location /workspace/coverage/default/47.spi_device_cfg_cmd.1560381582
Short name T981
Test name
Test status
Simulation time 618276380 ps
CPU time 3.13 seconds
Started Jul 07 05:30:38 PM PDT 24
Finished Jul 07 05:30:41 PM PDT 24
Peak memory 224500 kb
Host smart-0ee4b0d9-576e-4156-8cbd-1acfe480c7c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560381582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_cfg_cmd.1560381582
Directory /workspace/47.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/47.spi_device_csb_read.2152128007
Short name T787
Test name
Test status
Simulation time 25751633 ps
CPU time 0.74 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:31 PM PDT 24
Peak memory 205904 kb
Host smart-b306f678-c9f7-4b9e-8503-79e4dd709224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152128007 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_csb_read.2152128007
Directory /workspace/47.spi_device_csb_read/latest

Test location /workspace/coverage/default/47.spi_device_flash_all.1783327300
Short name T630
Test name
Test status
Simulation time 8487324534 ps
CPU time 65.86 seconds
Started Jul 07 05:30:33 PM PDT 24
Finished Jul 07 05:31:39 PM PDT 24
Peak memory 249188 kb
Host smart-e0bfa0dd-3cd9-4527-bbd3-413dfe447fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783327300 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_all.1783327300
Directory /workspace/47.spi_device_flash_all/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm.3220572860
Short name T676
Test name
Test status
Simulation time 54972757489 ps
CPU time 237 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:34:47 PM PDT 24
Peak memory 253308 kb
Host smart-3128c77e-7b28-46cc-af83-067f0f88d1b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220572860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm.3220572860
Directory /workspace/47.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/47.spi_device_flash_and_tpm_min_idle.1730281215
Short name T882
Test name
Test status
Simulation time 91848341093 ps
CPU time 213.65 seconds
Started Jul 07 05:30:28 PM PDT 24
Finished Jul 07 05:34:03 PM PDT 24
Peak memory 255196 kb
Host smart-cdcb0d02-8723-4776-a2b1-666a119411d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1730281215 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_and_tpm_min_idl
e.1730281215
Directory /workspace/47.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode.1522538403
Short name T644
Test name
Test status
Simulation time 1996459953 ps
CPU time 23.73 seconds
Started Jul 07 05:30:32 PM PDT 24
Finished Jul 07 05:30:56 PM PDT 24
Peak memory 251064 kb
Host smart-b48289eb-2e27-4a90-baea-610a2c67ad21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522538403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode.1522538403
Directory /workspace/47.spi_device_flash_mode/latest

Test location /workspace/coverage/default/47.spi_device_flash_mode_ignore_cmds.2852616305
Short name T224
Test name
Test status
Simulation time 169906444638 ps
CPU time 54.91 seconds
Started Jul 07 05:30:39 PM PDT 24
Finished Jul 07 05:31:34 PM PDT 24
Peak memory 232740 kb
Host smart-4c228bd3-7188-4316-97cc-5897e0a53db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2852616305 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_flash_mode_ignore_cmd
s.2852616305
Directory /workspace/47.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/47.spi_device_intercept.2497920603
Short name T394
Test name
Test status
Simulation time 387125443 ps
CPU time 3.41 seconds
Started Jul 07 05:30:40 PM PDT 24
Finished Jul 07 05:30:44 PM PDT 24
Peak memory 232624 kb
Host smart-0ca39c5a-c9e3-4c74-8861-daa8d6c918e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497920603 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_intercept.2497920603
Directory /workspace/47.spi_device_intercept/latest

Test location /workspace/coverage/default/47.spi_device_mailbox.983306488
Short name T439
Test name
Test status
Simulation time 182953741 ps
CPU time 2.16 seconds
Started Jul 07 05:30:30 PM PDT 24
Finished Jul 07 05:30:32 PM PDT 24
Peak memory 224096 kb
Host smart-dd5271a0-68f5-44f7-aba4-b18496d5f947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983306488 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_mailbox.983306488
Directory /workspace/47.spi_device_mailbox/latest

Test location /workspace/coverage/default/47.spi_device_pass_addr_payload_swap.357646112
Short name T601
Test name
Test status
Simulation time 2552033661 ps
CPU time 5.1 seconds
Started Jul 07 05:30:53 PM PDT 24
Finished Jul 07 05:30:58 PM PDT 24
Peak memory 224556 kb
Host smart-aef5388b-5fff-4dcc-a394-507a95de3fee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357646112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_addr_payload_swap
.357646112
Directory /workspace/47.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/47.spi_device_pass_cmd_filtering.2240237729
Short name T642
Test name
Test status
Simulation time 10757734474 ps
CPU time 4.98 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:30:48 PM PDT 24
Peak memory 224660 kb
Host smart-bcca61e8-122a-43ea-a986-1047df1f0076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2240237729 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_pass_cmd_filtering.2240237729
Directory /workspace/47.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/47.spi_device_read_buffer_direct.2188829138
Short name T714
Test name
Test status
Simulation time 1445936522 ps
CPU time 12.91 seconds
Started Jul 07 05:30:40 PM PDT 24
Finished Jul 07 05:30:53 PM PDT 24
Peak memory 220428 kb
Host smart-caf6fc89-716b-4ccd-92b9-f950cfabdf62
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2188829138 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_read_buffer_dir
ect.2188829138
Directory /workspace/47.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/47.spi_device_tpm_all.2853038042
Short name T718
Test name
Test status
Simulation time 93591140 ps
CPU time 0.78 seconds
Started Jul 07 05:30:44 PM PDT 24
Finished Jul 07 05:30:46 PM PDT 24
Peak memory 205708 kb
Host smart-7cc520ac-227c-4775-8f52-ad8a0cb7bd59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2853038042 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_all.2853038042
Directory /workspace/47.spi_device_tpm_all/latest

Test location /workspace/coverage/default/47.spi_device_tpm_read_hw_reg.1777250749
Short name T566
Test name
Test status
Simulation time 2782811156 ps
CPU time 5.57 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:30:49 PM PDT 24
Peak memory 216300 kb
Host smart-259ba991-c30c-459d-9a73-ce4f29fa99fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777250749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_read_hw_reg.1777250749
Directory /workspace/47.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/47.spi_device_tpm_rw.3955361172
Short name T550
Test name
Test status
Simulation time 469906968 ps
CPU time 1.85 seconds
Started Jul 07 05:30:33 PM PDT 24
Finished Jul 07 05:30:35 PM PDT 24
Peak memory 216200 kb
Host smart-8f4535a4-4c2e-4eef-abbf-c9a525f60c51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955361172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_rw.3955361172
Directory /workspace/47.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/47.spi_device_tpm_sts_read.475676311
Short name T470
Test name
Test status
Simulation time 14544460 ps
CPU time 0.7 seconds
Started Jul 07 05:30:46 PM PDT 24
Finished Jul 07 05:30:47 PM PDT 24
Peak memory 205656 kb
Host smart-5a4f389d-24fc-4336-9b53-4dc547e8744d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475676311 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_tpm_sts_read.475676311
Directory /workspace/47.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/47.spi_device_upload.4182994086
Short name T506
Test name
Test status
Simulation time 8975025425 ps
CPU time 10.34 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 05:30:59 PM PDT 24
Peak memory 224620 kb
Host smart-1da7b725-a2f1-4e12-97e3-dc43ff7cdc41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182994086 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.spi_device_upload.4182994086
Directory /workspace/47.spi_device_upload/latest

Test location /workspace/coverage/default/48.spi_device_alert_test.3045695190
Short name T479
Test name
Test status
Simulation time 26916760 ps
CPU time 0.78 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:30:45 PM PDT 24
Peak memory 205496 kb
Host smart-e738b0ca-337a-4fd9-a075-5071bd6828b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045695190 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_alert_test.
3045695190
Directory /workspace/48.spi_device_alert_test/latest

Test location /workspace/coverage/default/48.spi_device_cfg_cmd.3640454671
Short name T868
Test name
Test status
Simulation time 375416729 ps
CPU time 6.26 seconds
Started Jul 07 05:30:46 PM PDT 24
Finished Jul 07 05:30:53 PM PDT 24
Peak memory 224448 kb
Host smart-4d4958cb-f7cb-4170-a522-298243b68f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640454671 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_cfg_cmd.3640454671
Directory /workspace/48.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/48.spi_device_csb_read.1643204301
Short name T753
Test name
Test status
Simulation time 27225138 ps
CPU time 0.88 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:30:43 PM PDT 24
Peak memory 206620 kb
Host smart-07b5f310-6289-4b2b-9a71-fc0c343012e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643204301 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_csb_read.1643204301
Directory /workspace/48.spi_device_csb_read/latest

Test location /workspace/coverage/default/48.spi_device_flash_all.289355071
Short name T287
Test name
Test status
Simulation time 1364427804 ps
CPU time 24.83 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:31:07 PM PDT 24
Peak memory 249088 kb
Host smart-4e0f7eb6-5c3e-4e17-84ba-23a17a71bf3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289355071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_all.289355071
Directory /workspace/48.spi_device_flash_all/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm.3217186172
Short name T236
Test name
Test status
Simulation time 66123834229 ps
CPU time 163.73 seconds
Started Jul 07 05:30:45 PM PDT 24
Finished Jul 07 05:33:29 PM PDT 24
Peak memory 268128 kb
Host smart-75d4ccb7-5413-468d-ae05-fcb376aae5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217186172 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm.3217186172
Directory /workspace/48.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/48.spi_device_flash_and_tpm_min_idle.1711553051
Short name T200
Test name
Test status
Simulation time 4948547291 ps
CPU time 64.1 seconds
Started Jul 07 05:30:52 PM PDT 24
Finished Jul 07 05:31:57 PM PDT 24
Peak memory 250276 kb
Host smart-0b8c250a-4a03-4aab-ad44-0b71cfae7965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711553051 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_and_tpm_min_idl
e.1711553051
Directory /workspace/48.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode.1210419287
Short name T315
Test name
Test status
Simulation time 1335079580 ps
CPU time 15.5 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 05:31:05 PM PDT 24
Peak memory 249020 kb
Host smart-c1b0f1d8-57ab-4d15-9383-563fb4dde149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210419287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode.1210419287
Directory /workspace/48.spi_device_flash_mode/latest

Test location /workspace/coverage/default/48.spi_device_flash_mode_ignore_cmds.1221697454
Short name T57
Test name
Test status
Simulation time 19587960566 ps
CPU time 74.72 seconds
Started Jul 07 05:30:54 PM PDT 24
Finished Jul 07 05:32:09 PM PDT 24
Peak memory 269632 kb
Host smart-94064bb0-9aec-4467-a628-c4c8cad07bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1221697454 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_flash_mode_ignore_cmd
s.1221697454
Directory /workspace/48.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/48.spi_device_intercept.3496452187
Short name T611
Test name
Test status
Simulation time 236081510 ps
CPU time 4.06 seconds
Started Jul 07 05:30:34 PM PDT 24
Finished Jul 07 05:30:38 PM PDT 24
Peak memory 224456 kb
Host smart-4533461f-f46a-4db9-9b87-36fb08d09f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496452187 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_intercept.3496452187
Directory /workspace/48.spi_device_intercept/latest

Test location /workspace/coverage/default/48.spi_device_mailbox.1529977112
Short name T202
Test name
Test status
Simulation time 1156128719 ps
CPU time 18.67 seconds
Started Jul 07 05:30:34 PM PDT 24
Finished Jul 07 05:30:53 PM PDT 24
Peak memory 240736 kb
Host smart-8827a10c-17b3-459f-92a9-97309777ccf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529977112 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_mailbox.1529977112
Directory /workspace/48.spi_device_mailbox/latest

Test location /workspace/coverage/default/48.spi_device_pass_addr_payload_swap.481199201
Short name T903
Test name
Test status
Simulation time 2724520686 ps
CPU time 9.87 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:30:57 PM PDT 24
Peak memory 224568 kb
Host smart-bf21b994-013a-477d-bc90-f8db1017810d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481199201 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_addr_payload_swap
.481199201
Directory /workspace/48.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/48.spi_device_pass_cmd_filtering.448470041
Short name T258
Test name
Test status
Simulation time 124657286161 ps
CPU time 22.31 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:31:13 PM PDT 24
Peak memory 232708 kb
Host smart-d578780b-d0b7-4117-9cc6-92fa0f420d6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448470041 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_pass_cmd_filtering.448470041
Directory /workspace/48.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/48.spi_device_read_buffer_direct.2836723572
Short name T148
Test name
Test status
Simulation time 339040043 ps
CPU time 4.59 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:30:52 PM PDT 24
Peak memory 222736 kb
Host smart-1e590adf-acde-4fdc-a145-50e0d1278669
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2836723572 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_read_buffer_dir
ect.2836723572
Directory /workspace/48.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/48.spi_device_tpm_all.2137469024
Short name T398
Test name
Test status
Simulation time 21057968748 ps
CPU time 7.43 seconds
Started Jul 07 05:30:44 PM PDT 24
Finished Jul 07 05:30:53 PM PDT 24
Peak memory 216264 kb
Host smart-b07e49db-eed7-4237-87a2-28209cbc5031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137469024 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_all.2137469024
Directory /workspace/48.spi_device_tpm_all/latest

Test location /workspace/coverage/default/48.spi_device_tpm_read_hw_reg.1794181018
Short name T549
Test name
Test status
Simulation time 1581254967 ps
CPU time 9.29 seconds
Started Jul 07 05:30:50 PM PDT 24
Finished Jul 07 05:31:00 PM PDT 24
Peak memory 216140 kb
Host smart-92d3422e-fab2-43fe-89d6-3e86aa761c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794181018 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_read_hw_reg.1794181018
Directory /workspace/48.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/48.spi_device_tpm_rw.1567351541
Short name T892
Test name
Test status
Simulation time 211474954 ps
CPU time 2.83 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:30:45 PM PDT 24
Peak memory 216184 kb
Host smart-e75fdf92-3f7a-4e21-965a-ed3296c2ab45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567351541 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_rw.1567351541
Directory /workspace/48.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/48.spi_device_tpm_sts_read.1832959192
Short name T366
Test name
Test status
Simulation time 36574492 ps
CPU time 0.86 seconds
Started Jul 07 05:30:43 PM PDT 24
Finished Jul 07 05:30:45 PM PDT 24
Peak memory 206252 kb
Host smart-295a2985-1ccc-4721-89fa-e0508a4e8ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832959192 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_tpm_sts_read.1832959192
Directory /workspace/48.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/48.spi_device_upload.491869951
Short name T437
Test name
Test status
Simulation time 10797885050 ps
CPU time 16.8 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:31:04 PM PDT 24
Peak memory 224556 kb
Host smart-c065e25c-43c0-4d4c-b98c-ebac19e8a8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491869951 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.spi_device_upload.491869951
Directory /workspace/48.spi_device_upload/latest

Test location /workspace/coverage/default/49.spi_device_alert_test.550621270
Short name T856
Test name
Test status
Simulation time 20853328 ps
CPU time 0.81 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:30:49 PM PDT 24
Peak memory 205860 kb
Host smart-292f16e3-72bf-4362-870f-f7e6b47840e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550621270 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_alert_test.550621270
Directory /workspace/49.spi_device_alert_test/latest

Test location /workspace/coverage/default/49.spi_device_cfg_cmd.231350031
Short name T963
Test name
Test status
Simulation time 475457066 ps
CPU time 5.63 seconds
Started Jul 07 05:30:42 PM PDT 24
Finished Jul 07 05:30:49 PM PDT 24
Peak memory 232644 kb
Host smart-b52b2bfa-3139-4d17-9a3e-1988d527dbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231350031 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_cfg_cmd.231350031
Directory /workspace/49.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/49.spi_device_csb_read.2614440759
Short name T361
Test name
Test status
Simulation time 48764117 ps
CPU time 0.78 seconds
Started Jul 07 05:30:45 PM PDT 24
Finished Jul 07 05:30:46 PM PDT 24
Peak memory 205888 kb
Host smart-1ed3b7bf-eab4-415d-b331-8622db879b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614440759 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_csb_read.2614440759
Directory /workspace/49.spi_device_csb_read/latest

Test location /workspace/coverage/default/49.spi_device_flash_all.1170099156
Short name T679
Test name
Test status
Simulation time 13925688532 ps
CPU time 28.26 seconds
Started Jul 07 05:30:53 PM PDT 24
Finished Jul 07 05:31:22 PM PDT 24
Peak memory 249212 kb
Host smart-c2b381f2-88aa-461d-90be-0363398e7571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170099156 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_all.1170099156
Directory /workspace/49.spi_device_flash_all/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm.312281707
Short name T299
Test name
Test status
Simulation time 600921183880 ps
CPU time 642.22 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 05:41:39 PM PDT 24
Peak memory 273800 kb
Host smart-beb61472-043f-4fe2-9dc4-a2495117bfbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=312281707 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm.312281707
Directory /workspace/49.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/49.spi_device_flash_and_tpm_min_idle.403440222
Short name T173
Test name
Test status
Simulation time 30510190717 ps
CPU time 55.19 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:31:44 PM PDT 24
Peak memory 249268 kb
Host smart-d89dcd74-1a1b-4f25-913d-e5c27ebf88f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403440222 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_and_tpm_min_idle
.403440222
Directory /workspace/49.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode.2443153955
Short name T576
Test name
Test status
Simulation time 322305801 ps
CPU time 5.36 seconds
Started Jul 07 05:30:45 PM PDT 24
Finished Jul 07 05:30:51 PM PDT 24
Peak memory 232704 kb
Host smart-54475c52-3325-4b66-a2ad-9e3b1f307357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443153955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode.2443153955
Directory /workspace/49.spi_device_flash_mode/latest

Test location /workspace/coverage/default/49.spi_device_flash_mode_ignore_cmds.355111087
Short name T283
Test name
Test status
Simulation time 68653272558 ps
CPU time 282.04 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 05:35:31 PM PDT 24
Peak memory 268116 kb
Host smart-03e55e6a-d2b3-4712-a2b2-b390f6a61300
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355111087 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_flash_mode_ignore_cmds
.355111087
Directory /workspace/49.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/49.spi_device_intercept.1822553126
Short name T608
Test name
Test status
Simulation time 354632104 ps
CPU time 5.02 seconds
Started Jul 07 05:30:38 PM PDT 24
Finished Jul 07 05:30:44 PM PDT 24
Peak memory 224432 kb
Host smart-4a2b4293-fbaa-4731-a51a-66dae7a5f714
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822553126 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_intercept.1822553126
Directory /workspace/49.spi_device_intercept/latest

Test location /workspace/coverage/default/49.spi_device_mailbox.3147488724
Short name T620
Test name
Test status
Simulation time 163449330 ps
CPU time 2.29 seconds
Started Jul 07 05:30:44 PM PDT 24
Finished Jul 07 05:30:47 PM PDT 24
Peak memory 224436 kb
Host smart-ace50a78-aec4-49ed-bea3-aa9aa5e7067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147488724 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_mailbox.3147488724
Directory /workspace/49.spi_device_mailbox/latest

Test location /workspace/coverage/default/49.spi_device_pass_addr_payload_swap.2948514199
Short name T211
Test name
Test status
Simulation time 7741679374 ps
CPU time 14.28 seconds
Started Jul 07 05:30:50 PM PDT 24
Finished Jul 07 05:31:05 PM PDT 24
Peak memory 232852 kb
Host smart-bc5621ac-332e-43f0-b086-0e0cda267cf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948514199 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_addr_payload_swa
p.2948514199
Directory /workspace/49.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/49.spi_device_pass_cmd_filtering.2728448380
Short name T45
Test name
Test status
Simulation time 1582705710 ps
CPU time 7.91 seconds
Started Jul 07 05:30:46 PM PDT 24
Finished Jul 07 05:30:54 PM PDT 24
Peak memory 224496 kb
Host smart-1abc6636-1f30-4956-ad59-d2c961b54f34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728448380 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_pass_cmd_filtering.2728448380
Directory /workspace/49.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/49.spi_device_read_buffer_direct.2945418326
Short name T145
Test name
Test status
Simulation time 791650400 ps
CPU time 10.35 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:31:01 PM PDT 24
Peak memory 220120 kb
Host smart-771e0873-e1cf-4bd5-8a96-52246b923f22
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=2945418326 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_read_buffer_dir
ect.2945418326
Directory /workspace/49.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/49.spi_device_stress_all.480605390
Short name T21
Test name
Test status
Simulation time 198383508 ps
CPU time 1.07 seconds
Started Jul 07 05:30:56 PM PDT 24
Finished Jul 07 05:30:57 PM PDT 24
Peak memory 215884 kb
Host smart-c47dbbc0-6359-488f-8c33-369df8171d68
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480605390 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_st
ress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_stres
s_all.480605390
Directory /workspace/49.spi_device_stress_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_all.1265174926
Short name T387
Test name
Test status
Simulation time 3617577246 ps
CPU time 10.17 seconds
Started Jul 07 05:30:44 PM PDT 24
Finished Jul 07 05:30:55 PM PDT 24
Peak memory 216384 kb
Host smart-3e4ed5d7-1774-4bc9-8820-713e61c3f201
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265174926 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_all.1265174926
Directory /workspace/49.spi_device_tpm_all/latest

Test location /workspace/coverage/default/49.spi_device_tpm_read_hw_reg.4178022765
Short name T490
Test name
Test status
Simulation time 495736879 ps
CPU time 2.59 seconds
Started Jul 07 05:30:48 PM PDT 24
Finished Jul 07 05:30:52 PM PDT 24
Peak memory 216192 kb
Host smart-e7a3de67-d7ae-45db-b5a8-19d40e2233ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178022765 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_read_hw_reg.4178022765
Directory /workspace/49.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/49.spi_device_tpm_rw.1768830889
Short name T329
Test name
Test status
Simulation time 684133570 ps
CPU time 4.44 seconds
Started Jul 07 05:30:49 PM PDT 24
Finished Jul 07 05:30:54 PM PDT 24
Peak memory 216152 kb
Host smart-a8d4c606-4f1c-49f1-a2e3-751658393e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1768830889 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_rw.1768830889
Directory /workspace/49.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/49.spi_device_tpm_sts_read.3376569569
Short name T492
Test name
Test status
Simulation time 21090979 ps
CPU time 0.79 seconds
Started Jul 07 05:30:47 PM PDT 24
Finished Jul 07 05:30:48 PM PDT 24
Peak memory 205992 kb
Host smart-066935aa-7e77-4f9b-9b46-99d09bbf13c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376569569 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_tpm_sts_read.3376569569
Directory /workspace/49.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/49.spi_device_upload.1388200383
Short name T112
Test name
Test status
Simulation time 2396007068 ps
CPU time 11.52 seconds
Started Jul 07 05:31:10 PM PDT 24
Finished Jul 07 05:31:22 PM PDT 24
Peak memory 232716 kb
Host smart-848fd672-6fb7-4839-9826-0d3455d3fe50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388200383 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.spi_device_upload.1388200383
Directory /workspace/49.spi_device_upload/latest

Test location /workspace/coverage/default/5.spi_device_alert_test.3702962153
Short name T814
Test name
Test status
Simulation time 29084032 ps
CPU time 0.73 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:29:08 PM PDT 24
Peak memory 205460 kb
Host smart-df06d61c-f402-4b58-ad13-0689612567b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702962153 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_alert_test.3
702962153
Directory /workspace/5.spi_device_alert_test/latest

Test location /workspace/coverage/default/5.spi_device_cfg_cmd.2942679845
Short name T593
Test name
Test status
Simulation time 2488627455 ps
CPU time 3.54 seconds
Started Jul 07 05:28:47 PM PDT 24
Finished Jul 07 05:28:51 PM PDT 24
Peak memory 232832 kb
Host smart-a9d23d37-1722-4f4e-879e-59181f892589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2942679845 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_cfg_cmd.2942679845
Directory /workspace/5.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/5.spi_device_csb_read.4111544175
Short name T434
Test name
Test status
Simulation time 19953574 ps
CPU time 0.8 seconds
Started Jul 07 05:28:59 PM PDT 24
Finished Jul 07 05:29:00 PM PDT 24
Peak memory 206924 kb
Host smart-b9c06b9e-bb91-4063-a431-5bcd8f82c320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4111544175 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_csb_read.4111544175
Directory /workspace/5.spi_device_csb_read/latest

Test location /workspace/coverage/default/5.spi_device_flash_all.3533185406
Short name T243
Test name
Test status
Simulation time 9653188553 ps
CPU time 40.29 seconds
Started Jul 07 05:28:59 PM PDT 24
Finished Jul 07 05:29:40 PM PDT 24
Peak memory 250248 kb
Host smart-72b950e0-ed5e-4968-b9c1-a224d707fa39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533185406 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_all.3533185406
Directory /workspace/5.spi_device_flash_all/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm.325923623
Short name T29
Test name
Test status
Simulation time 2671109507 ps
CPU time 53.74 seconds
Started Jul 07 05:28:56 PM PDT 24
Finished Jul 07 05:29:50 PM PDT 24
Peak memory 241084 kb
Host smart-ce5107ad-bd5b-4f51-8c23-97709633c39a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=325923623 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm.325923623
Directory /workspace/5.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/5.spi_device_flash_and_tpm_min_idle.2909570955
Short name T654
Test name
Test status
Simulation time 9143264431 ps
CPU time 81.51 seconds
Started Jul 07 05:28:51 PM PDT 24
Finished Jul 07 05:30:13 PM PDT 24
Peak memory 241064 kb
Host smart-25a73dcf-372a-4939-bd79-7208c9f965d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909570955 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_and_tpm_min_idle
.2909570955
Directory /workspace/5.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode.1843588825
Short name T570
Test name
Test status
Simulation time 974286800 ps
CPU time 5.86 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 224492 kb
Host smart-d8e1cf9c-f86b-4dc4-906e-2b59e0066a57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1843588825 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode.1843588825
Directory /workspace/5.spi_device_flash_mode/latest

Test location /workspace/coverage/default/5.spi_device_flash_mode_ignore_cmds.4133282646
Short name T191
Test name
Test status
Simulation time 41380567099 ps
CPU time 290.49 seconds
Started Jul 07 05:28:46 PM PDT 24
Finished Jul 07 05:33:37 PM PDT 24
Peak memory 254620 kb
Host smart-6e3c50ff-e6a6-4811-a1b5-fcc13647b513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4133282646 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_flash_mode_ignore_cmds
.4133282646
Directory /workspace/5.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/5.spi_device_intercept.3471759534
Short name T664
Test name
Test status
Simulation time 1456564625 ps
CPU time 7.1 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:29:03 PM PDT 24
Peak memory 224488 kb
Host smart-4b4dff32-b04e-4f98-891e-4f3a4680fd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471759534 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_intercept.3471759534
Directory /workspace/5.spi_device_intercept/latest

Test location /workspace/coverage/default/5.spi_device_mailbox.4230642839
Short name T721
Test name
Test status
Simulation time 45673479 ps
CPU time 2.58 seconds
Started Jul 07 05:29:04 PM PDT 24
Finished Jul 07 05:29:07 PM PDT 24
Peak memory 232612 kb
Host smart-71c47704-aa95-4cf3-b5fa-9c67f9fc43b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4230642839 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_mailbox.4230642839
Directory /workspace/5.spi_device_mailbox/latest

Test location /workspace/coverage/default/5.spi_device_pass_addr_payload_swap.4264244867
Short name T272
Test name
Test status
Simulation time 7490868848 ps
CPU time 20.85 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:25 PM PDT 24
Peak memory 232600 kb
Host smart-d9647a28-0105-4e7e-bb6b-d7c1636baf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4264244867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_addr_payload_swap
.4264244867
Directory /workspace/5.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/5.spi_device_pass_cmd_filtering.1123660794
Short name T775
Test name
Test status
Simulation time 1869890689 ps
CPU time 6.61 seconds
Started Jul 07 05:29:01 PM PDT 24
Finished Jul 07 05:29:08 PM PDT 24
Peak memory 240544 kb
Host smart-808917ae-8c0e-49a0-bbfa-05f574a5180d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123660794 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_pass_cmd_filtering.1123660794
Directory /workspace/5.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/5.spi_device_read_buffer_direct.3430890356
Short name T58
Test name
Test status
Simulation time 858689940 ps
CPU time 9.41 seconds
Started Jul 07 05:29:04 PM PDT 24
Finished Jul 07 05:29:14 PM PDT 24
Peak memory 219252 kb
Host smart-fdbb98ca-8f20-439b-aea3-e016247dbe61
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3430890356 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_read_buffer_dire
ct.3430890356
Directory /workspace/5.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/5.spi_device_stress_all.1589166057
Short name T798
Test name
Test status
Simulation time 245633782 ps
CPU time 1.22 seconds
Started Jul 07 05:29:15 PM PDT 24
Finished Jul 07 05:29:17 PM PDT 24
Peak memory 207184 kb
Host smart-94eff050-b34a-405c-8c69-425402ea7a24
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589166057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_stres
s_all.1589166057
Directory /workspace/5.spi_device_stress_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_all.1550468115
Short name T579
Test name
Test status
Simulation time 724947419 ps
CPU time 2.11 seconds
Started Jul 07 05:29:05 PM PDT 24
Finished Jul 07 05:29:08 PM PDT 24
Peak memory 216436 kb
Host smart-6f48fb1c-cc58-460e-8101-8190dba6d9f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550468115 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_all.1550468115
Directory /workspace/5.spi_device_tpm_all/latest

Test location /workspace/coverage/default/5.spi_device_tpm_read_hw_reg.234536596
Short name T848
Test name
Test status
Simulation time 15633241692 ps
CPU time 12.03 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:29:02 PM PDT 24
Peak memory 216268 kb
Host smart-7451ae45-2b94-4af4-b77c-46264dfc2ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234536596 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_read_hw_reg.234536596
Directory /workspace/5.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/5.spi_device_tpm_rw.4018828072
Short name T641
Test name
Test status
Simulation time 36277673 ps
CPU time 0.68 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 205640 kb
Host smart-6718d66d-616e-4b3c-9698-9b9504c023a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018828072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_rw.4018828072
Directory /workspace/5.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/5.spi_device_tpm_sts_read.4260711387
Short name T535
Test name
Test status
Simulation time 41737190 ps
CPU time 0.84 seconds
Started Jul 07 05:28:41 PM PDT 24
Finished Jul 07 05:28:43 PM PDT 24
Peak memory 206480 kb
Host smart-5cf39330-e3fe-468e-aff1-3c37c955d479
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260711387 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_tpm_sts_read.4260711387
Directory /workspace/5.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/5.spi_device_upload.2976583350
Short name T866
Test name
Test status
Simulation time 915274863 ps
CPU time 4.39 seconds
Started Jul 07 05:28:59 PM PDT 24
Finished Jul 07 05:29:03 PM PDT 24
Peak memory 224296 kb
Host smart-1d87b443-86aa-4615-bb53-7a126767eed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976583350 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.spi_device_upload.2976583350
Directory /workspace/5.spi_device_upload/latest

Test location /workspace/coverage/default/6.spi_device_alert_test.1277023824
Short name T596
Test name
Test status
Simulation time 16481208 ps
CPU time 0.69 seconds
Started Jul 07 05:28:38 PM PDT 24
Finished Jul 07 05:28:40 PM PDT 24
Peak memory 204988 kb
Host smart-5c3e3f43-9c29-4522-b57c-78c8c577e080
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277023824 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_alert_test.1
277023824
Directory /workspace/6.spi_device_alert_test/latest

Test location /workspace/coverage/default/6.spi_device_cfg_cmd.1081707817
Short name T738
Test name
Test status
Simulation time 1547958134 ps
CPU time 15.15 seconds
Started Jul 07 05:28:58 PM PDT 24
Finished Jul 07 05:29:13 PM PDT 24
Peak memory 224444 kb
Host smart-5a657f96-5944-4bb4-85c7-b617f24afbcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081707817 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_cfg_cmd.1081707817
Directory /workspace/6.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/6.spi_device_csb_read.3482245772
Short name T716
Test name
Test status
Simulation time 22548665 ps
CPU time 0.77 seconds
Started Jul 07 05:29:13 PM PDT 24
Finished Jul 07 05:29:14 PM PDT 24
Peak memory 206528 kb
Host smart-b872d05b-0003-4ea5-8ec5-fa8a6266bec0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482245772 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_csb_read.3482245772
Directory /workspace/6.spi_device_csb_read/latest

Test location /workspace/coverage/default/6.spi_device_flash_all.2898996582
Short name T245
Test name
Test status
Simulation time 3477469112 ps
CPU time 72.69 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:30:17 PM PDT 24
Peak memory 254124 kb
Host smart-af72beac-fae8-43a5-90e4-943187f21109
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898996582 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_all.2898996582
Directory /workspace/6.spi_device_flash_all/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm.1055265142
Short name T250
Test name
Test status
Simulation time 13929955203 ps
CPU time 59.73 seconds
Started Jul 07 05:28:46 PM PDT 24
Finished Jul 07 05:29:46 PM PDT 24
Peak memory 236624 kb
Host smart-7425178f-8da9-47fe-9e7a-a28225eecfff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055265142 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm.1055265142
Directory /workspace/6.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/6.spi_device_flash_and_tpm_min_idle.2170971403
Short name T922
Test name
Test status
Simulation time 13839672519 ps
CPU time 121.43 seconds
Started Jul 07 05:28:41 PM PDT 24
Finished Jul 07 05:30:44 PM PDT 24
Peak memory 249284 kb
Host smart-5c900bc8-45d2-4c9f-8ac5-ad3d1f4735c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170971403 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_and_tpm_min_idle
.2170971403
Directory /workspace/6.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode.2072276696
Short name T633
Test name
Test status
Simulation time 1049318499 ps
CPU time 16.73 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:29:07 PM PDT 24
Peak memory 232696 kb
Host smart-a50fb718-7a31-47d4-b180-0ce0de457176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072276696 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode.2072276696
Directory /workspace/6.spi_device_flash_mode/latest

Test location /workspace/coverage/default/6.spi_device_flash_mode_ignore_cmds.983818611
Short name T505
Test name
Test status
Simulation time 1972021650 ps
CPU time 12.02 seconds
Started Jul 07 05:29:07 PM PDT 24
Finished Jul 07 05:29:20 PM PDT 24
Peak memory 224492 kb
Host smart-7fa781ea-7eff-4887-8203-28b3cf541ad7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983818611 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_flash_mode_ignore_cmds.
983818611
Directory /workspace/6.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/6.spi_device_intercept.1961502635
Short name T830
Test name
Test status
Simulation time 3163816602 ps
CPU time 29.81 seconds
Started Jul 07 05:29:09 PM PDT 24
Finished Jul 07 05:29:39 PM PDT 24
Peak memory 224552 kb
Host smart-df0bf05d-75ca-4910-9c54-04317eae9fe6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961502635 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_intercept.1961502635
Directory /workspace/6.spi_device_intercept/latest

Test location /workspace/coverage/default/6.spi_device_mailbox.3505284014
Short name T279
Test name
Test status
Simulation time 5244127728 ps
CPU time 57.15 seconds
Started Jul 07 05:29:01 PM PDT 24
Finished Jul 07 05:29:59 PM PDT 24
Peak memory 232596 kb
Host smart-ae692770-7ff6-4a26-87ac-17f798cc4a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505284014 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_mailbox.3505284014
Directory /workspace/6.spi_device_mailbox/latest

Test location /workspace/coverage/default/6.spi_device_pass_addr_payload_swap.199033296
Short name T539
Test name
Test status
Simulation time 15886687053 ps
CPU time 20.05 seconds
Started Jul 07 05:29:00 PM PDT 24
Finished Jul 07 05:29:20 PM PDT 24
Peak memory 232628 kb
Host smart-d0031871-0dc3-4361-a66d-ed20e03cc541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=199033296 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_addr_payload_swap.
199033296
Directory /workspace/6.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/6.spi_device_pass_cmd_filtering.176416570
Short name T227
Test name
Test status
Simulation time 5325319887 ps
CPU time 9.5 seconds
Started Jul 07 05:28:56 PM PDT 24
Finished Jul 07 05:29:06 PM PDT 24
Peak memory 224620 kb
Host smart-b182c224-6466-4895-aac2-676b2bcc4666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176416570 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_pass_cmd_filtering.176416570
Directory /workspace/6.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/6.spi_device_read_buffer_direct.477247341
Short name T438
Test name
Test status
Simulation time 212585335 ps
CPU time 4.88 seconds
Started Jul 07 05:28:36 PM PDT 24
Finished Jul 07 05:28:42 PM PDT 24
Peak memory 220732 kb
Host smart-83b190e7-0220-4634-8f31-9032ef235ecd
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=477247341 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_read_buffer_direc
t.477247341
Directory /workspace/6.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/6.spi_device_tpm_all.3000481821
Short name T709
Test name
Test status
Simulation time 3746998674 ps
CPU time 10.21 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:14 PM PDT 24
Peak memory 216316 kb
Host smart-ad88fde8-9995-4ad1-9d0f-00226d821959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000481821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_all.3000481821
Directory /workspace/6.spi_device_tpm_all/latest

Test location /workspace/coverage/default/6.spi_device_tpm_read_hw_reg.3736935657
Short name T999
Test name
Test status
Simulation time 9670211279 ps
CPU time 24.82 seconds
Started Jul 07 05:28:35 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 216328 kb
Host smart-c3d544c4-6025-4330-8aa9-7def5f3d3885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736935657 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_read_hw_reg.3736935657
Directory /workspace/6.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/6.spi_device_tpm_rw.3618132058
Short name T381
Test name
Test status
Simulation time 628876210 ps
CPU time 1.25 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:28:57 PM PDT 24
Peak memory 207756 kb
Host smart-82ab80ad-3b5d-4122-90ee-fc3ae08f2c02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618132058 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_rw.3618132058
Directory /workspace/6.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/6.spi_device_tpm_sts_read.2837088161
Short name T834
Test name
Test status
Simulation time 45944543 ps
CPU time 0.92 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:28:59 PM PDT 24
Peak memory 207016 kb
Host smart-1c7158f7-2548-4b6b-adb3-aa54b2d8b467
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837088161 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_tpm_sts_read.2837088161
Directory /workspace/6.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/6.spi_device_upload.3121323223
Short name T748
Test name
Test status
Simulation time 89231319 ps
CPU time 3.45 seconds
Started Jul 07 05:29:01 PM PDT 24
Finished Jul 07 05:29:05 PM PDT 24
Peak memory 232420 kb
Host smart-cca819f2-4bad-447d-9306-bbbb139731ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121323223 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.spi_device_upload.3121323223
Directory /workspace/6.spi_device_upload/latest

Test location /workspace/coverage/default/7.spi_device_alert_test.4132976379
Short name T805
Test name
Test status
Simulation time 11355523 ps
CPU time 0.72 seconds
Started Jul 07 05:29:05 PM PDT 24
Finished Jul 07 05:29:06 PM PDT 24
Peak memory 205864 kb
Host smart-ed6464e1-526d-4133-ab21-b5edf466e3bb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132976379 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_alert_test.4
132976379
Directory /workspace/7.spi_device_alert_test/latest

Test location /workspace/coverage/default/7.spi_device_cfg_cmd.2838220265
Short name T639
Test name
Test status
Simulation time 2131665810 ps
CPU time 6.29 seconds
Started Jul 07 05:29:01 PM PDT 24
Finished Jul 07 05:29:08 PM PDT 24
Peak memory 232664 kb
Host smart-1a455854-853f-4f6d-ac3f-f484873d3a5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838220265 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_cfg_cmd.2838220265
Directory /workspace/7.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/7.spi_device_csb_read.2711843494
Short name T336
Test name
Test status
Simulation time 111617273 ps
CPU time 0.82 seconds
Started Jul 07 05:28:53 PM PDT 24
Finished Jul 07 05:28:54 PM PDT 24
Peak memory 206628 kb
Host smart-ce2d1214-b80e-4656-9a23-7eeb4bc91410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711843494 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_csb_read.2711843494
Directory /workspace/7.spi_device_csb_read/latest

Test location /workspace/coverage/default/7.spi_device_flash_all.3040256692
Short name T300
Test name
Test status
Simulation time 45907573433 ps
CPU time 341.6 seconds
Started Jul 07 05:29:04 PM PDT 24
Finished Jul 07 05:34:46 PM PDT 24
Peak memory 267300 kb
Host smart-f5851374-3b3d-47f4-a0a8-a778df9a2ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3040256692 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_all.3040256692
Directory /workspace/7.spi_device_flash_all/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm.2079273019
Short name T172
Test name
Test status
Simulation time 18715211772 ps
CPU time 171.18 seconds
Started Jul 07 05:28:48 PM PDT 24
Finished Jul 07 05:31:40 PM PDT 24
Peak memory 255656 kb
Host smart-3aeaff2d-23d8-4819-ab50-9c06e69c576b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079273019 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm.2079273019
Directory /workspace/7.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/7.spi_device_flash_and_tpm_min_idle.21898749
Short name T392
Test name
Test status
Simulation time 12570086224 ps
CPU time 42.21 seconds
Started Jul 07 05:28:56 PM PDT 24
Finished Jul 07 05:29:39 PM PDT 24
Peak memory 249260 kb
Host smart-95b63700-d30d-441c-8f2f-44c8420dfa1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21898749 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_and_tpm_min_idle.21898749
Directory /workspace/7.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode.2651552736
Short name T316
Test name
Test status
Simulation time 4207235093 ps
CPU time 26.56 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:29:17 PM PDT 24
Peak memory 232704 kb
Host smart-25cb3576-1bdf-4d0b-8ff5-61b514b4a14d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651552736 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode.2651552736
Directory /workspace/7.spi_device_flash_mode/latest

Test location /workspace/coverage/default/7.spi_device_flash_mode_ignore_cmds.618741546
Short name T953
Test name
Test status
Simulation time 14550758741 ps
CPU time 20.55 seconds
Started Jul 07 05:28:52 PM PDT 24
Finished Jul 07 05:29:13 PM PDT 24
Peak memory 224604 kb
Host smart-b659688c-8310-489c-b1f3-f1e28ae5bd34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618741546 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_flash_mode_ignore_cmds.
618741546
Directory /workspace/7.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/7.spi_device_intercept.4027838107
Short name T864
Test name
Test status
Simulation time 2685068074 ps
CPU time 22.4 seconds
Started Jul 07 05:29:16 PM PDT 24
Finished Jul 07 05:29:39 PM PDT 24
Peak memory 232824 kb
Host smart-1d57bb4b-a6da-47ae-b434-9d1150b019e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027838107 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_intercept.4027838107
Directory /workspace/7.spi_device_intercept/latest

Test location /workspace/coverage/default/7.spi_device_mailbox.1956916496
Short name T827
Test name
Test status
Simulation time 1206890424 ps
CPU time 7.19 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:29:02 PM PDT 24
Peak memory 232708 kb
Host smart-4b49b871-047e-4097-97c0-902879f79ed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956916496 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_mailbox.1956916496
Directory /workspace/7.spi_device_mailbox/latest

Test location /workspace/coverage/default/7.spi_device_pass_addr_payload_swap.3807587632
Short name T268
Test name
Test status
Simulation time 620485353 ps
CPU time 3.81 seconds
Started Jul 07 05:29:05 PM PDT 24
Finished Jul 07 05:29:10 PM PDT 24
Peak memory 224428 kb
Host smart-cf9c7fdf-8866-4ccd-aa93-e3f45bdf00cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807587632 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_addr_payload_swap
.3807587632
Directory /workspace/7.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/7.spi_device_pass_cmd_filtering.2028255076
Short name T609
Test name
Test status
Simulation time 42384411343 ps
CPU time 21.03 seconds
Started Jul 07 05:28:48 PM PDT 24
Finished Jul 07 05:29:10 PM PDT 24
Peak memory 239688 kb
Host smart-586db027-61c6-4115-82b3-62c17d0cb358
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028255076 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_pass_cmd_filtering.2028255076
Directory /workspace/7.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/7.spi_device_read_buffer_direct.397093259
Short name T682
Test name
Test status
Simulation time 750835378 ps
CPU time 9.17 seconds
Started Jul 07 05:28:49 PM PDT 24
Finished Jul 07 05:28:58 PM PDT 24
Peak memory 221912 kb
Host smart-3f41a852-f888-4f57-ab9d-0471652a4354
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=397093259 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_read_buffer_direc
t.397093259
Directory /workspace/7.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/7.spi_device_stress_all.3807734072
Short name T994
Test name
Test status
Simulation time 26647752199 ps
CPU time 278.92 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:33:42 PM PDT 24
Peak memory 257164 kb
Host smart-55668b26-cf1b-439c-89b6-a31229f43b6f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807734072 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_stres
s_all.3807734072
Directory /workspace/7.spi_device_stress_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_all.2212492054
Short name T558
Test name
Test status
Simulation time 13676539 ps
CPU time 0.78 seconds
Started Jul 07 05:28:52 PM PDT 24
Finished Jul 07 05:28:54 PM PDT 24
Peak memory 205720 kb
Host smart-1bb393f3-8dd7-481d-b4c7-a51a87df95fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212492054 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_all.2212492054
Directory /workspace/7.spi_device_tpm_all/latest

Test location /workspace/coverage/default/7.spi_device_tpm_read_hw_reg.2926048867
Short name T337
Test name
Test status
Simulation time 64896198846 ps
CPU time 17.01 seconds
Started Jul 07 05:29:05 PM PDT 24
Finished Jul 07 05:29:23 PM PDT 24
Peak memory 216328 kb
Host smart-5a7eeecb-f528-47a1-8f97-87fefb5b4ef5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926048867 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_read_hw_reg.2926048867
Directory /workspace/7.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/7.spi_device_tpm_rw.3993556416
Short name T583
Test name
Test status
Simulation time 64670734 ps
CPU time 0.96 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:42 PM PDT 24
Peak memory 206936 kb
Host smart-4b0902a4-ab39-457d-94da-0881bb904e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993556416 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_rw.3993556416
Directory /workspace/7.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/7.spi_device_tpm_sts_read.1963416294
Short name T669
Test name
Test status
Simulation time 41331978 ps
CPU time 0.74 seconds
Started Jul 07 05:29:00 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 205260 kb
Host smart-fff759b3-d747-49f7-8c49-274476fc7001
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963416294 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_tpm_sts_read.1963416294
Directory /workspace/7.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/7.spi_device_upload.2810965783
Short name T264
Test name
Test status
Simulation time 3145177861 ps
CPU time 4.83 seconds
Started Jul 07 05:28:52 PM PDT 24
Finished Jul 07 05:28:57 PM PDT 24
Peak memory 232740 kb
Host smart-5486a02f-18cb-4d0c-bd0d-c0916b76cd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810965783 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.spi_device_upload.2810965783
Directory /workspace/7.spi_device_upload/latest

Test location /workspace/coverage/default/8.spi_device_alert_test.2959809539
Short name T613
Test name
Test status
Simulation time 41440105 ps
CPU time 0.74 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:28:59 PM PDT 24
Peak memory 205156 kb
Host smart-ae4dd7c8-4aaf-4d7a-b74f-4f91719b0ebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2959809539 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_alert_test.2
959809539
Directory /workspace/8.spi_device_alert_test/latest

Test location /workspace/coverage/default/8.spi_device_cfg_cmd.1120484124
Short name T932
Test name
Test status
Simulation time 2244907094 ps
CPU time 5.53 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:28:56 PM PDT 24
Peak memory 232736 kb
Host smart-8ad82832-04f1-415e-90d1-ad9c56683d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1120484124 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_cfg_cmd.1120484124
Directory /workspace/8.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/8.spi_device_csb_read.3680391764
Short name T577
Test name
Test status
Simulation time 19756692 ps
CPU time 0.78 seconds
Started Jul 07 05:29:05 PM PDT 24
Finished Jul 07 05:29:07 PM PDT 24
Peak memory 206612 kb
Host smart-ebcb7f28-bd82-4b20-8068-5c7431768c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3680391764 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_csb_read.3680391764
Directory /workspace/8.spi_device_csb_read/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm.3055153636
Short name T233
Test name
Test status
Simulation time 77894853498 ps
CPU time 272.1 seconds
Started Jul 07 05:28:53 PM PDT 24
Finished Jul 07 05:33:26 PM PDT 24
Peak memory 255012 kb
Host smart-445f94e7-80ee-47bc-8642-2d313a91f379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055153636 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm.3055153636
Directory /workspace/8.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/8.spi_device_flash_and_tpm_min_idle.1649034133
Short name T137
Test name
Test status
Simulation time 90770893279 ps
CPU time 268.18 seconds
Started Jul 07 05:29:14 PM PDT 24
Finished Jul 07 05:33:43 PM PDT 24
Peak memory 265628 kb
Host smart-6bdb0e3c-7fbb-4331-b7d4-d4520b80a4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1649034133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_and_tpm_min_idle
.1649034133
Directory /workspace/8.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/8.spi_device_flash_mode_ignore_cmds.2753389896
Short name T289
Test name
Test status
Simulation time 1266771926 ps
CPU time 22 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:26 PM PDT 24
Peak memory 249092 kb
Host smart-01621d64-bd4c-4fdb-b9fc-4dcce424c9e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753389896 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_flash_mode_ignore_cmds
.2753389896
Directory /workspace/8.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/8.spi_device_intercept.3786541287
Short name T207
Test name
Test status
Simulation time 1729665320 ps
CPU time 10.38 seconds
Started Jul 07 05:28:47 PM PDT 24
Finished Jul 07 05:28:58 PM PDT 24
Peak memory 224416 kb
Host smart-10239ad0-eaca-4352-aa39-780a68ddbcb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786541287 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_intercept.3786541287
Directory /workspace/8.spi_device_intercept/latest

Test location /workspace/coverage/default/8.spi_device_mailbox.2093896105
Short name T196
Test name
Test status
Simulation time 6165536688 ps
CPU time 23.07 seconds
Started Jul 07 05:29:07 PM PDT 24
Finished Jul 07 05:29:31 PM PDT 24
Peak memory 232804 kb
Host smart-09a588c8-c0e7-4ca5-a46d-ed12319a0b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093896105 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_mailbox.2093896105
Directory /workspace/8.spi_device_mailbox/latest

Test location /workspace/coverage/default/8.spi_device_pass_addr_payload_swap.893252893
Short name T692
Test name
Test status
Simulation time 365593707 ps
CPU time 2.43 seconds
Started Jul 07 05:29:00 PM PDT 24
Finished Jul 07 05:29:03 PM PDT 24
Peak memory 224352 kb
Host smart-599e8271-11cd-4580-8f3e-ad25d9c69dad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893252893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_addr_payload_swap.
893252893
Directory /workspace/8.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/8.spi_device_pass_cmd_filtering.2457809726
Short name T632
Test name
Test status
Simulation time 803785707 ps
CPU time 2.63 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:06 PM PDT 24
Peak memory 224436 kb
Host smart-67fb1d3c-2e81-4769-b31b-3a834c326cd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457809726 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_pass_cmd_filtering.2457809726
Directory /workspace/8.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/8.spi_device_read_buffer_direct.569376821
Short name T142
Test name
Test status
Simulation time 1324363788 ps
CPU time 18.55 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:29:26 PM PDT 24
Peak memory 218720 kb
Host smart-5f9bafd8-8c81-4447-b904-32e68c7e400e
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=569376821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_read_buffer_direc
t.569376821
Directory /workspace/8.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/8.spi_device_stress_all.1687105071
Short name T50
Test name
Test status
Simulation time 29953753795 ps
CPU time 85.13 seconds
Started Jul 07 05:29:04 PM PDT 24
Finished Jul 07 05:30:30 PM PDT 24
Peak memory 253388 kb
Host smart-e8355bb1-9616-4df6-bdcf-740e00b0e954
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687105071 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_stres
s_all.1687105071
Directory /workspace/8.spi_device_stress_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_all.811346989
Short name T446
Test name
Test status
Simulation time 29254526248 ps
CPU time 33.72 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:29:15 PM PDT 24
Peak memory 217632 kb
Host smart-f2690991-0942-496e-94ad-3dceabf71fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=811346989 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_all.811346989
Directory /workspace/8.spi_device_tpm_all/latest

Test location /workspace/coverage/default/8.spi_device_tpm_read_hw_reg.3170863997
Short name T554
Test name
Test status
Simulation time 55116214628 ps
CPU time 10.6 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:29:09 PM PDT 24
Peak memory 215960 kb
Host smart-e60e69f2-3e90-46cc-bc14-f3d013bb4a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3170863997 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_read_hw_reg.3170863997
Directory /workspace/8.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/8.spi_device_tpm_rw.651276133
Short name T900
Test name
Test status
Simulation time 66968202 ps
CPU time 1.39 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:28:59 PM PDT 24
Peak memory 216080 kb
Host smart-d53374a4-2fc4-4993-b214-707a40bbaa2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651276133 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_rw.651276133
Directory /workspace/8.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/8.spi_device_tpm_sts_read.1871513010
Short name T893
Test name
Test status
Simulation time 60356349 ps
CPU time 0.93 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:42 PM PDT 24
Peak memory 205940 kb
Host smart-4e91d8ea-3f56-4da6-95b5-19c3cc3b3f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871513010 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_tpm_sts_read.1871513010
Directory /workspace/8.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/8.spi_device_upload.1407103023
Short name T879
Test name
Test status
Simulation time 219025157 ps
CPU time 2.35 seconds
Started Jul 07 05:29:01 PM PDT 24
Finished Jul 07 05:29:04 PM PDT 24
Peak memory 226980 kb
Host smart-dcbd2851-9690-4e63-8d23-e789e7d132ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407103023 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.spi_device_upload.1407103023
Directory /workspace/8.spi_device_upload/latest

Test location /workspace/coverage/default/9.spi_device_alert_test.3837346332
Short name T847
Test name
Test status
Simulation time 11449557 ps
CPU time 0.74 seconds
Started Jul 07 05:28:58 PM PDT 24
Finished Jul 07 05:28:59 PM PDT 24
Peak memory 205528 kb
Host smart-84c36b0b-f703-44c1-8764-044f89421aa6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837346332 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_comm
on_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_alert_test.3
837346332
Directory /workspace/9.spi_device_alert_test/latest

Test location /workspace/coverage/default/9.spi_device_cfg_cmd.1526303649
Short name T732
Test name
Test status
Simulation time 158907237 ps
CPU time 4.05 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:45 PM PDT 24
Peak memory 232664 kb
Host smart-113ec73f-11bc-46ba-b05a-d4aaafdddf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526303649 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_cfg_cmd_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_cfg_cmd.1526303649
Directory /workspace/9.spi_device_cfg_cmd/latest

Test location /workspace/coverage/default/9.spi_device_csb_read.2646003946
Short name T772
Test name
Test status
Simulation time 115251965 ps
CPU time 0.78 seconds
Started Jul 07 05:29:06 PM PDT 24
Finished Jul 07 05:29:08 PM PDT 24
Peak memory 206920 kb
Host smart-d8db505e-5d06-4e4f-a118-899308974e6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646003946 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_csb_read_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_csb_read.2646003946
Directory /workspace/9.spi_device_csb_read/latest

Test location /workspace/coverage/default/9.spi_device_flash_all.326620349
Short name T983
Test name
Test status
Simulation time 116242391987 ps
CPU time 111.71 seconds
Started Jul 07 05:28:41 PM PDT 24
Finished Jul 07 05:30:34 PM PDT 24
Peak memory 240968 kb
Host smart-00b3d423-2a62-45ab-a248-8690b558bd8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=326620349 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_all_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_all.326620349
Directory /workspace/9.spi_device_flash_all/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm.991612492
Short name T46
Test name
Test status
Simulation time 3137866270 ps
CPU time 59.91 seconds
Started Jul 07 05:28:40 PM PDT 24
Finished Jul 07 05:29:41 PM PDT 24
Peak memory 249300 kb
Host smart-b9be4bce-1805-45ea-9100-25222a3fd381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991612492 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm.991612492
Directory /workspace/9.spi_device_flash_and_tpm/latest

Test location /workspace/coverage/default/9.spi_device_flash_and_tpm_min_idle.4165071129
Short name T976
Test name
Test status
Simulation time 3766497306 ps
CPU time 29.76 seconds
Started Jul 07 05:28:55 PM PDT 24
Finished Jul 07 05:29:26 PM PDT 24
Peak memory 232900 kb
Host smart-5cb760c1-1ca7-4f8d-9cf7-61af1d6413fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165071129 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_and_tpm_min_idle_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_and_tpm_min_idle
.4165071129
Directory /workspace/9.spi_device_flash_and_tpm_min_idle/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode.3145800860
Short name T352
Test name
Test status
Simulation time 623430906 ps
CPU time 4.12 seconds
Started Jul 07 05:29:16 PM PDT 24
Finished Jul 07 05:29:21 PM PDT 24
Peak memory 232708 kb
Host smart-99a543b6-029e-4fbc-9e53-b8cc56f7b753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3145800860 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode.3145800860
Directory /workspace/9.spi_device_flash_mode/latest

Test location /workspace/coverage/default/9.spi_device_flash_mode_ignore_cmds.2629885440
Short name T198
Test name
Test status
Simulation time 3084053870 ps
CPU time 26.42 seconds
Started Jul 07 05:28:59 PM PDT 24
Finished Jul 07 05:29:26 PM PDT 24
Peak memory 220584 kb
Host smart-f3c65cbe-e62a-43d3-a7e8-c6cc6e9915b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629885440 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_flash_mode_ignore_cmds_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_flash_mode_ignore_cmds
.2629885440
Directory /workspace/9.spi_device_flash_mode_ignore_cmds/latest

Test location /workspace/coverage/default/9.spi_device_intercept.2488186316
Short name T628
Test name
Test status
Simulation time 1585102532 ps
CPU time 21.84 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:29:03 PM PDT 24
Peak memory 224708 kb
Host smart-5d2a3981-5aab-4d8f-bfb0-7fd20cb58e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488186316 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_intercept_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_intercept.2488186316
Directory /workspace/9.spi_device_intercept/latest

Test location /workspace/coverage/default/9.spi_device_mailbox.3438744821
Short name T768
Test name
Test status
Simulation time 1346685822 ps
CPU time 7.6 seconds
Started Jul 07 05:28:50 PM PDT 24
Finished Jul 07 05:28:58 PM PDT 24
Peak memory 232716 kb
Host smart-c34491c9-ce2b-4db3-adb3-3811d5fb3e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438744821 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_mailbox_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_mailbox.3438744821
Directory /workspace/9.spi_device_mailbox/latest

Test location /workspace/coverage/default/9.spi_device_pass_addr_payload_swap.125859913
Short name T555
Test name
Test status
Simulation time 1124948637 ps
CPU time 3.26 seconds
Started Jul 07 05:29:00 PM PDT 24
Finished Jul 07 05:29:04 PM PDT 24
Peak memory 224488 kb
Host smart-8cc62db7-4f8d-4f98-9dc6-ab9b616b8046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125859913 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_addr_payload_swap_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_addr_payload_swap.
125859913
Directory /workspace/9.spi_device_pass_addr_payload_swap/latest

Test location /workspace/coverage/default/9.spi_device_pass_cmd_filtering.1413329600
Short name T587
Test name
Test status
Simulation time 3816684631 ps
CPU time 17.67 seconds
Started Jul 07 05:28:49 PM PDT 24
Finished Jul 07 05:29:07 PM PDT 24
Peak memory 240796 kb
Host smart-95236a64-7782-4198-a0f2-eec3c1216846
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1413329600 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_pass_cmd_filtering_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_pass_cmd_filtering.1413329600
Directory /workspace/9.spi_device_pass_cmd_filtering/latest

Test location /workspace/coverage/default/9.spi_device_read_buffer_direct.3112140479
Short name T370
Test name
Test status
Simulation time 1123312214 ps
CPU time 3.91 seconds
Started Jul 07 05:29:00 PM PDT 24
Finished Jul 07 05:29:04 PM PDT 24
Peak memory 219356 kb
Host smart-02ed9283-7327-41cf-9307-9ce560ec917a
User root
Command /workspace/default/simv +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/h
w/dv/tools/sim.tcl +ntb_random_seed=3112140479 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_read_buffer_direct_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_read_buffer_dire
ct.3112140479
Directory /workspace/9.spi_device_read_buffer_direct/latest

Test location /workspace/coverage/default/9.spi_device_stress_all.1775408750
Short name T162
Test name
Test status
Simulation time 49194232 ps
CPU time 1 seconds
Started Jul 07 05:29:05 PM PDT 24
Finished Jul 07 05:29:06 PM PDT 24
Peak memory 206784 kb
Host smart-a54fae24-b747-41f5-a9df-9defb7170d00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775408750 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_s
tress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_stres
s_all.1775408750
Directory /workspace/9.spi_device_stress_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_all.3838772057
Short name T992
Test name
Test status
Simulation time 1954119315 ps
CPU time 16.03 seconds
Started Jul 07 05:29:00 PM PDT 24
Finished Jul 07 05:29:16 PM PDT 24
Peak memory 215580 kb
Host smart-42e00944-fb72-4d35-b0cc-53ecc0b9243a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838772057 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_all_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_all.3838772057
Directory /workspace/9.spi_device_tpm_all/latest

Test location /workspace/coverage/default/9.spi_device_tpm_read_hw_reg.1727035725
Short name T933
Test name
Test status
Simulation time 100925251 ps
CPU time 1.03 seconds
Started Jul 07 05:29:03 PM PDT 24
Finished Jul 07 05:29:05 PM PDT 24
Peak memory 206696 kb
Host smart-69db25a6-c84f-4f72-a404-e09c1735f567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727035725 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_read_hw_reg_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_read_hw_reg.1727035725
Directory /workspace/9.spi_device_tpm_read_hw_reg/latest

Test location /workspace/coverage/default/9.spi_device_tpm_rw.3618715893
Short name T324
Test name
Test status
Simulation time 475968875 ps
CPU time 2.97 seconds
Started Jul 07 05:28:57 PM PDT 24
Finished Jul 07 05:29:01 PM PDT 24
Peak memory 216196 kb
Host smart-4d942e67-f725-42fa-ad4f-c3c5737fcb75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618715893 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_rw_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_rw.3618715893
Directory /workspace/9.spi_device_tpm_rw/latest

Test location /workspace/coverage/default/9.spi_device_tpm_sts_read.311872253
Short name T773
Test name
Test status
Simulation time 82637697 ps
CPU time 0.92 seconds
Started Jul 07 05:28:39 PM PDT 24
Finished Jul 07 05:28:41 PM PDT 24
Peak memory 205988 kb
Host smart-6e65cdbb-9f4c-48b9-ab54-a14f86e11d02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311872253 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_tpm_sts_read_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_tpm_sts_read.311872253
Directory /workspace/9.spi_device_tpm_sts_read/latest

Test location /workspace/coverage/default/9.spi_device_upload.1721200588
Short name T557
Test name
Test status
Simulation time 771116135 ps
CPU time 4.37 seconds
Started Jul 07 05:29:08 PM PDT 24
Finished Jul 07 05:29:13 PM PDT 24
Peak memory 232704 kb
Host smart-3d7e9965-95a8-4805-808e-21497a31ef1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721200588 -assert nopostproc +UVM_TESTNAME=spi_device_base_test +UVM_TEST_SEQ=spi_device_upload_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.spi_device_upload.1721200588
Directory /workspace/9.spi_device_upload/latest
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