Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	2685516	1			T1	1835		T2	1		T3	112
all_values[1]	2685516	1			T1	1835		T2	1		T3	112
all_values[2]	2685516	1			T1	1835		T2	1		T3	112
all_values[3]	2685516	1			T1	1835		T2	1		T3	112
all_values[4]	2685516	1			T1	1835		T2	1		T3	112
all_values[5]	2685516	1			T1	1835		T2	1		T3	112
all_values[6]	2685516	1			T1	1835		T2	1		T3	112
all_values[7]	2685516	1			T1	1835		T2	1		T3	112

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21077842

1

T1

14680

T2

8

T3

896

auto[1]

406286

1

T16

46

T17

50

T19

18

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

21460410

1

T1

14680

T2

8

T3

896

auto[1]

23718

1

T10

344

T13

209

T29

145

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	2641401	1			T1	1835		T2	1		T3	112
all_values[0]	auto[0]	auto[1]	11376	1			T10	184		T13	116		T29	95
all_values[0]	auto[1]	auto[0]	32490	1			T16	7		T17	2		T19	1
all_values[0]	auto[1]	auto[1]	249	1			T16	3		T17	5		T19	1
all_values[1]	auto[0]	auto[0]	2610756	1			T1	1835		T2	1		T3	112
all_values[1]	auto[0]	auto[1]	7271	1			T10	104		T13	80		T29	50
all_values[1]	auto[1]	auto[0]	67258	1			T16	1		T20	6		T21	6
all_values[1]	auto[1]	auto[1]	231	1			T16	2		T17	5		T19	1
all_values[2]	auto[0]	auto[0]	2650193	1			T1	1835		T2	1		T3	112
all_values[2]	auto[0]	auto[1]	2632	1			T10	56		T13	13		T16	48
all_values[2]	auto[1]	auto[0]	32496	1			T16	5		T17	3		T20	5
all_values[2]	auto[1]	auto[1]	195	1			T16	1		T17	5		T20	3
all_values[3]	auto[0]	auto[0]	2614164	1			T1	1835		T2	1		T3	112
all_values[3]	auto[0]	auto[1]	197	1			T16	6		T17	1		T20	5
all_values[3]	auto[1]	auto[0]	70974	1			T17	5		T19	3		T20	9
all_values[3]	auto[1]	auto[1]	181	1			T16	2		T17	2		T21	7
all_values[4]	auto[0]	auto[0]	2618221	1			T1	1835		T2	1		T3	112
all_values[4]	auto[0]	auto[1]	176	1			T16	3		T17	2		T20	4
all_values[4]	auto[1]	auto[0]	66946	1			T16	4		T17	2		T19	1
all_values[4]	auto[1]	auto[1]	173	1			T16	1		T17	2		T20	6
all_values[5]	auto[0]	auto[0]	2650101	1			T1	1835		T2	1		T3	112
all_values[5]	auto[0]	auto[1]	140	1			T16	1		T17	1		T20	3
all_values[5]	auto[1]	auto[0]	35131	1			T16	8		T17	7		T19	4
all_values[5]	auto[1]	auto[1]	144	1			T16	2		T17	2		T19	1
all_values[6]	auto[0]	auto[0]	2652638	1			T1	1835		T2	1		T3	112
all_values[6]	auto[0]	auto[1]	171	1			T16	4		T17	3		T20	5
all_values[6]	auto[1]	auto[0]	32528	1			T16	2		T17	3		T19	3
all_values[6]	auto[1]	auto[1]	179	1			T16	3		T17	2		T20	1
all_values[7]	auto[0]	auto[0]	2618195	1			T1	1835		T2	1		T3	112
all_values[7]	auto[0]	auto[1]	210	1			T16	1		T17	1		T19	1
all_values[7]	auto[1]	auto[0]	66918	1			T16	2		T17	4		T19	1
all_values[7]	auto[1]	auto[1]	193	1			T16	3		T17	1		T19	2