Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	84	2	82	97.62

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_mode	4	0	4	100.00	100	1	1	0
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_busy	2	0	2	100.00	100	1	1	2
cp_dummy_cycles	9	0	9	100.00	100	1	1	0
cp_is_flash	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	0
cp_num_lanes	2	0	2	100.00	100	1	1	0
cp_opcode	11	0	11	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2
cp_upload	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_cmd_info_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_modeXdirXaddrXswap	48	0	48	100.00	100	1	1	0
cr_modeXdummyXnum_lanes	36	2	34	94.44	100	1	1	0

Summary for Variable cp_addr_mode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for cp_addr_mode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[SpiFlashAddrDisabled]	31869	1			T3	8		T4	2		T10	153
auto[SpiFlashAddrCfg]	7504	1			T3	4		T7	4		T10	47
auto[SpiFlashAddr3b]	8936	1			T3	2		T10	65		T12	46
auto[SpiFlashAddr4b]	7305	1			T3	4		T9	6		T10	60

---

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30621

1

T3

18

T4

2

T9

6

auto[1]

24993

1

T7

4

T10

115

T12

186

---

Summary for Variable cp_busy

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30111

1

T3

12

T4

2

T9

3

auto[1]

25503

1

T3

6

T7

4

T9

3

---

Summary for Variable cp_dummy_cycles

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	9	0	9	100.00

User Defined Bins for cp_dummy_cycles

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	36539	1			T3	12		T4	2		T10	178
values[1]	1051	1			T10	8		T12	13		T13	6
values[2]	1429	1			T10	14		T12	7		T13	8
values[3]	1505	1			T10	17		T12	11		T13	5
values[4]	1369	1			T10	6		T12	11		T13	16
values[5]	1404	1			T10	22		T12	10		T13	12
values[6]	1442	1			T3	2		T10	9		T12	5
values[7]	1393	1			T10	10		T12	8		T13	6
values[8]	9482	1			T3	4		T7	4		T9	6

---

Summary for Variable cp_is_flash

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_flash

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23716

1

T3

18

T4

2

T7

4

auto[1]

31898

1

T9

6

T12

462

T29

345

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

read

52565

1

T3

18

T4

2

T7

4

write

3049

1

T10

18

T12

19

T13

12

---

Summary for Variable cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_num_lanes

Excluded/Illegal bins

NAME	COUNT	STATUS
others	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

valids[0x0]

18864

1

T3

8

T4

2

T7

4

valids[0x1]

36750

1

T3

10

T9

1

T10

182

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
internal_process_ops[0x9f]	1471	1			T10	11		T11	2		T12	10
internal_process_ops[0x5a]	1588	1			T10	13		T12	9		T13	13
internal_process_ops[0x05]	18306	1			T3	4		T10	56		T12	247
internal_process_ops[0x35]	1579	1			T10	7		T12	9		T13	3
internal_process_ops[0x15]	1608	1			T3	4		T10	10		T12	12
internal_process_ops[0x03]	988	1			T9	1		T10	12		T12	2
internal_process_ops[0x0b]	963	1			T3	2		T10	7		T12	1
internal_process_ops[0x3b]	955	1			T10	9		T12	1		T13	4
internal_process_ops[0x6b]	912	1			T3	2		T7	2		T9	3
internal_process_ops[0xbb]	1030	1			T9	2		T10	13		T12	3
internal_process_ops[0xeb]	957	1			T7	2		T10	8		T12	4

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

54094

1

T3

18

T4

2

T7

4

auto[1]

1520

1

T10

5

T12

9

T13

6

---

Summary for Variable cp_upload

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_upload

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

53341

1

T3

18

T4

2

T7

4

auto[1]

2273

1

T10

12

T12

21

T13

7

---

Summary for Cross cr_modeXdirXaddrXswap

Samples crossed: cp_is_flash cp_is_write cp_addr_mode cp_addr_swap_en cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	0	48	100.00
Automatically Generated Cross Bins	48	0	48	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_modeXdirXaddrXswap

Bins

cp_is_flash

cp_is_write

cp_addr_mode

cp_addr_swap_en

cp_payload_swap_en

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

6915

1

T3

8

T4

2

T10

119

auto[0]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

4713

1

T10

25

T13

28

T16

25

auto[0]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1894

1

T3

4

T10

30

T13

10

auto[0]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1608

1

T7

4

T10

13

T13

11

auto[0]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2128

1

T3

2

T10

25

T13

16

auto[0]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

1886

1

T10

38

T13

25

T16

20

auto[0]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1775

1

T3

4

T10

24

T13

24

auto[0]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1486

1

T10

33

T13

16

T16

9

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

73

1

T10

4

T45

1

T43

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

62

1

T10

2

T16

1

T45

1

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

86

1

T10

1

T27

2

T43

2

auto[0]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

105

1

T10

2

T13

1

T16

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

96

1

T10

3

T16

3

T27

2

auto[0]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

74

1

T16

1

T27

2

T44

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

78

1

T10

1

T13

2

T16

1

auto[0]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

84

1

T45

1

T18

2

T46

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

90

1

T13

2

T27

5

T44

3

auto[0]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

75

1

T13

2

T16

1

T27

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

84

1

T10

2

T13

2

T16

1

auto[0]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

82

1

T13

2

T43

1

T18

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

85

1

T10

2

T44

1

T167

4

auto[0]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

80

1

T10

1

T27

1

T46

1

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

65

1

T16

1

T45

1

T43

2

auto[0]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

92

1

T13

1

T16

1

T27

2

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

10925

1

T12

199

T29

54

T30

26

auto[1]

read

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

8561

1

T12

141

T29

186

T30

23

auto[1]

read

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

1646

1

T12

18

T29

12

T30

4

auto[1]

read

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

1640

1

T12

14

T29

14

T30

12

auto[1]

read

auto[SpiFlashAddr3b]

auto[0]

auto[0]

2132

1

T12

18

T29

25

T30

3

auto[1]

read

auto[SpiFlashAddr3b]

auto[1]

auto[0]

2002

1

T12

22

T29

9

T30

15

auto[1]

read

auto[SpiFlashAddr4b]

auto[0]

auto[0]

1700

1

T9

6

T12

26

T29

16

auto[1]

read

auto[SpiFlashAddr4b]

auto[1]

auto[0]

1554

1

T12

5

T29

14

T30

10

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[0]

113

1

T12

2

T29

4

T30

3

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[0]

auto[1]

103

1

T12

2

T29

1

T30

1

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[0]

100

1

T12

1

T89

1

T18

2

auto[1]

write

auto[SpiFlashAddrDisabled]

auto[1]

auto[1]

113

1

T12

1

T30

1

T89

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[0]

94

1

T30

2

T31

1

T83

3

auto[1]

write

auto[SpiFlashAddrCfg]

auto[0]

auto[1]

104

1

T12

3

T83

1

T19

1

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[0]

90

1

T16

3

T31

2

T168

2

auto[1]

write

auto[SpiFlashAddrCfg]

auto[1]

auto[1]

96

1

T12

1

T29

2

T30

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[0]

140

1

T12

4

T31

1

T83

1

auto[1]

write

auto[SpiFlashAddr3b]

auto[0]

auto[1]

96

1

T12

2

T29

1

T30

4

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[0]

108

1

T29

3

T31

3

T83

2

auto[1]

write

auto[SpiFlashAddr3b]

auto[1]

auto[1]

113

1

T30

2

T16

1

T83

4

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[0]

100

1

T12

2

T31

4

T83

1

auto[1]

write

auto[SpiFlashAddr4b]

auto[0]

auto[1]

121

1

T29

2

T83

6

T89

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[0]

127

1

T12

1

T29

2

T30

2

auto[1]

write

auto[SpiFlashAddr4b]

auto[1]

auto[1]

120

1

T16

1

T31

4

T83

4

User Defined Cross Bins for cr_modeXdirXaddrXswap

Excluded/Illegal bins

NAME	COUNT	STATUS
payload_swap_writes	0	Excluded

---

Summary for Cross cr_modeXdummyXnum_lanes

Samples crossed: cp_is_flash cp_dummy_cycles cp_num_lanes

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	36	2	34	94.44	2

Automatically Generated Cross Bins for cr_modeXdummyXnum_lanes

Element holes

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	NUMBER	STATUS
*	[values[1]]	[valids[0x0]]	--	--	2

Covered bins

cp_is_flash	cp_dummy_cycles	cp_num_lanes	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	valids[0x0]	3285	1			T3	2		T4	2		T10	50
auto[0]	values[0]	valids[0x1]	10797	1			T3	10		T10	128		T11	2
auto[0]	values[1]	valids[0x1]	469	1			T10	8		T13	6		T16	6
auto[0]	values[2]	valids[0x0]	464	1			T10	9		T13	6		T27	6
auto[0]	values[2]	valids[0x1]	244	1			T10	5		T13	2		T16	2
auto[0]	values[3]	valids[0x0]	473	1			T10	10		T13	3		T16	9
auto[0]	values[3]	valids[0x1]	273	1			T10	7		T13	2		T14	4
auto[0]	values[4]	valids[0x0]	478	1			T10	6		T13	11		T16	4
auto[0]	values[4]	valids[0x1]	243	1			T13	5		T16	5		T27	5
auto[0]	values[5]	valids[0x0]	472	1			T10	11		T13	2		T16	5
auto[0]	values[5]	valids[0x1]	258	1			T10	11		T13	10		T16	4
auto[0]	values[6]	valids[0x0]	461	1			T3	2		T10	5		T13	3
auto[0]	values[6]	valids[0x1]	309	1			T10	4		T13	1		T16	1
auto[0]	values[7]	valids[0x0]	495	1			T10	6		T13	2		T16	4
auto[0]	values[7]	valids[0x1]	229	1			T10	4		T13	4		T16	2
auto[0]	values[8]	valids[0x0]	2934	1			T3	4		T7	4		T10	46
auto[0]	values[8]	valids[0x1]	1832	1			T10	15		T13	17		T14	2
auto[1]	values[0]	valids[0x0]	4452	1			T12	56		T29	35		T30	18
auto[1]	values[0]	valids[0x1]	18005	1			T12	304		T29	231		T30	63
auto[1]	values[1]	valids[0x1]	582	1			T12	13		T30	3		T16	4
auto[1]	values[2]	valids[0x0]	436	1			T12	5		T29	6		T30	2
auto[1]	values[2]	valids[0x1]	285	1			T12	2		T29	3		T30	4
auto[1]	values[3]	valids[0x0]	467	1			T12	8		T29	1		T30	2
auto[1]	values[3]	valids[0x1]	292	1			T12	3		T30	2		T16	1
auto[1]	values[4]	valids[0x0]	384	1			T12	8		T29	4		T16	1
auto[1]	values[4]	valids[0x1]	264	1			T12	3		T29	1		T30	5
auto[1]	values[5]	valids[0x0]	412	1			T12	5		T29	4		T30	3
auto[1]	values[5]	valids[0x1]	262	1			T12	5		T16	3		T31	4
auto[1]	values[6]	valids[0x0]	392	1			T12	5		T29	4		T30	2
auto[1]	values[6]	valids[0x1]	280	1			T29	2		T30	1		T83	1
auto[1]	values[7]	valids[0x0]	448	1			T12	6		T29	4		T30	1
auto[1]	values[7]	valids[0x1]	221	1			T12	2		T29	1		T16	1
auto[1]	values[8]	valids[0x0]	2811	1			T9	5		T12	22		T29	27
auto[1]	values[8]	valids[0x1]	1905	1			T9	1		T12	15		T29	22