Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::flash_status_cg

Group : spi_device_env_pkg::spi_device_env_cov::flash_status_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	16	0	16	100.00
Crosses	72	0	72	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_busy_bit	2	0	2	100.00	100	1	1	2
cp_is_host_read	2	0	2	100.00	100	1	1	2
cp_other_status	8	0	8	100.00	100	1	1	8
cp_sw_read_while_csb_active	2	0	2	100.00	100	1	1	2
cp_wel_bit	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::flash_status_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all_except_csb	64	0	64	100.00	100	1	1	0
cr_busyXwelXcsb	8	0	8	100.00	100	1	1	0

Summary for Variable cp_busy_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_busy_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3243980

1

T3

10593

T4

570

T7

1

auto[1]

26333

1

T10

45

T12

242

T13

16

---

Summary for Variable cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_host_read

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

938148

1

T3

1

T4

570

T7

1

auto[1]

2332165

1

T3

10592

T10

14675

T12

9234

---

Summary for Variable cp_other_status

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for cp_other_status

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:524287]	634651	1			T3	10593		T4	190		T7	1
auto[524288:1048575]	362353	1			T4	93		T9	421		T10	1513
auto[1048576:1572863]	395368	1			T4	102		T9	120		T10	2322
auto[1572864:2097151]	400733	1			T4	185		T10	3095		T12	3535
auto[2097152:2621439]	335153	1			T10	3278		T12	35		T13	2614
auto[2621440:3145727]	401279	1			T9	93		T10	494		T12	670
auto[3145728:3670015]	380980	1			T9	166		T10	1043		T12	808
auto[3670016:4194303]	359796	1			T9	2		T10	5		T12	433

---

Summary for Variable cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_sw_read_while_csb_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2366150

1

T3

10593

T4

13

T7

1

auto[1]

904163

1

T4

557

T9

889

T10

2

---

Summary for Variable cp_wel_bit

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_wel_bit

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2777739

1

T3

10593

T4

570

T7

1

auto[1]

492574

1

T10

4130

T12

2626

T13

2759

---

Summary for Cross cr_all_except_csb

Samples crossed: cp_busy_bit cp_wel_bit cp_other_status cp_is_host_read

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for cr_all_except_csb

Bins

cp_busy_bit	cp_wel_bit	cp_other_status	cp_is_host_read	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0:524287]	auto[0]	203114	1			T3	1		T4	190		T7	1
auto[0]	auto[0]	auto[0:524287]	auto[1]	357949	1			T3	10592		T10	2999		T12	1037
auto[0]	auto[0]	auto[524288:1048575]	auto[0]	100949	1			T4	93		T9	421		T10	10
auto[0]	auto[0]	auto[524288:1048575]	auto[1]	213127	1			T10	1166		T12	1980		T29	268
auto[0]	auto[0]	auto[1048576:1572863]	auto[0]	100512	1			T4	102		T9	120		T10	9
auto[0]	auto[0]	auto[1048576:1572863]	auto[1]	222906	1			T10	2304		T12	1		T13	387
auto[0]	auto[0]	auto[1572864:2097151]	auto[0]	102439	1			T4	185		T10	6		T12	5
auto[0]	auto[0]	auto[1572864:2097151]	auto[1]	218149	1			T10	2820		T12	1594		T13	640
auto[0]	auto[0]	auto[2097152:2621439]	auto[0]	103812	1			T10	3		T12	5		T13	5
auto[0]	auto[0]	auto[2097152:2621439]	auto[1]	165780	1			T10	2		T12	2		T13	2609
auto[0]	auto[0]	auto[2621440:3145727]	auto[0]	113750	1			T9	93		T10	3		T12	10
auto[0]	auto[0]	auto[2621440:3145727]	auto[1]	237150	1			T10	234		T12	643		T13	769
auto[0]	auto[0]	auto[3145728:3670015]	auto[0]	98183	1			T9	166		T10	11		T12	5
auto[0]	auto[0]	auto[3145728:3670015]	auto[1]	210104	1			T10	1028		T12	779		T29	1716
auto[0]	auto[0]	auto[3670016:4194303]	auto[0]	95526	1			T9	2		T10	5		T12	7
auto[0]	auto[0]	auto[3670016:4194303]	auto[1]	212898	1			T12	388		T13	3224		T29	1
auto[0]	auto[1]	auto[0:524287]	auto[0]	5364	1			T10	2		T12	2		T13	7
auto[0]	auto[1]	auto[0:524287]	auto[1]	64343	1			T13	2739		T30	1077		T16	193
auto[0]	auto[1]	auto[524288:1048575]	auto[0]	2006	1			T10	6		T12	2		T13	2
auto[0]	auto[1]	auto[524288:1048575]	auto[1]	43924	1			T10	326		T12	691		T13	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[0]	987	1			T13	1		T29	2		T30	1
auto[0]	auto[1]	auto[1048576:1572863]	auto[1]	68052	1			T29	1017		T27	2572		T31	768
auto[0]	auto[1]	auto[1572864:2097151]	auto[0]	1514	1			T10	3		T12	5		T16	1
auto[0]	auto[1]	auto[1572864:2097151]	auto[1]	75233	1			T10	260		T12	1898		T31	512
auto[0]	auto[1]	auto[2097152:2621439]	auto[0]	1441	1			T10	5		T12	1		T27	24
auto[0]	auto[1]	auto[2097152:2621439]	auto[1]	59376	1			T10	3247		T16	650		T83	636
auto[0]	auto[1]	auto[2621440:3145727]	auto[0]	934	1			T12	1		T13	2		T16	5
auto[0]	auto[1]	auto[2621440:3145727]	auto[1]	47025	1			T10	256		T16	1019		T27	4
auto[0]	auto[1]	auto[3145728:3670015]	auto[0]	588	1			T10	1		T29	2		T16	2
auto[0]	auto[1]	auto[3145728:3670015]	auto[1]	69023	1			T29	581		T16	256		T31	768
auto[0]	auto[1]	auto[3670016:4194303]	auto[0]	3107	1			T27	2		T31	4		T43	28
auto[0]	auto[1]	auto[3670016:4194303]	auto[1]	44715	1			T31	5		T89	2372		T18	6
auto[1]	auto[0]	auto[0:524287]	auto[0]	437	1			T12	5		T13	2		T29	1
auto[1]	auto[0]	auto[0:524287]	auto[1]	2780	1			T12	53		T13	3		T29	19
auto[1]	auto[0]	auto[524288:1048575]	auto[0]	375	1			T10	1		T12	2		T29	2
auto[1]	auto[0]	auto[524288:1048575]	auto[1]	1626	1			T12	14		T29	6		T30	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[0]	380	1			T10	3		T12	1		T13	1
auto[1]	auto[0]	auto[1048576:1572863]	auto[1]	1804	1			T10	6		T12	3		T13	1
auto[1]	auto[0]	auto[1572864:2097151]	auto[0]	429	1			T10	2		T12	3		T29	4
auto[1]	auto[0]	auto[1572864:2097151]	auto[1]	2256	1			T10	4		T12	30		T29	17
auto[1]	auto[0]	auto[2097152:2621439]	auto[0]	456	1			T10	1		T12	2		T29	4
auto[1]	auto[0]	auto[2097152:2621439]	auto[1]	3642	1			T12	25		T29	100		T16	7
auto[1]	auto[0]	auto[2621440:3145727]	auto[0]	354	1			T10	1		T12	3		T13	1
auto[1]	auto[0]	auto[2621440:3145727]	auto[1]	1247	1			T12	13		T13	1		T30	2
auto[1]	auto[0]	auto[3145728:3670015]	auto[0]	414	1			T10	1		T12	1		T30	1
auto[1]	auto[0]	auto[3145728:3670015]	auto[1]	2089	1			T10	2		T12	23		T31	72
auto[1]	auto[0]	auto[3670016:4194303]	auto[0]	377	1			T12	2		T29	1		T30	4
auto[1]	auto[0]	auto[3670016:4194303]	auto[1]	2725	1			T12	36		T29	2		T30	5
auto[1]	auto[1]	auto[0:524287]	auto[0]	132	1			T13	2		T30	1		T16	2
auto[1]	auto[1]	auto[0:524287]	auto[1]	532	1			T13	2		T16	2		T280	47
auto[1]	auto[1]	auto[524288:1048575]	auto[0]	46	1			T10	2		T12	2		T13	1
auto[1]	auto[1]	auto[524288:1048575]	auto[1]	300	1			T10	2		T12	24		T13	2
auto[1]	auto[1]	auto[1048576:1572863]	auto[0]	90	1			T29	1		T27	6		T83	1
auto[1]	auto[1]	auto[1048576:1572863]	auto[1]	637	1			T29	8		T18	22		T46	2
auto[1]	auto[1]	auto[1572864:2097151]	auto[0]	93	1			T43	8		T83	1		T89	3
auto[1]	auto[1]	auto[1572864:2097151]	auto[1]	620	1			T89	145		T18	20		T168	13
auto[1]	auto[1]	auto[2097152:2621439]	auto[0]	85	1			T10	1		T83	2		T19	1
auto[1]	auto[1]	auto[2097152:2621439]	auto[1]	561	1			T10	19		T83	2		T19	6
auto[1]	auto[1]	auto[2621440:3145727]	auto[0]	88	1			T16	1		T27	9		T83	1
auto[1]	auto[1]	auto[2621440:3145727]	auto[1]	731	1			T16	3		T83	2		T18	23
auto[1]	auto[1]	auto[3145728:3670015]	auto[0]	85	1			T27	3		T83	1		T267	3
auto[1]	auto[1]	auto[3145728:3670015]	auto[1]	494	1			T43	81		T83	1		T268	7
auto[1]	auto[1]	auto[3670016:4194303]	auto[0]	81	1			T43	3		T18	2		T281	1
auto[1]	auto[1]	auto[3670016:4194303]	auto[1]	367	1			T18	19		T281	5		T279	3

---

Summary for Cross cr_busyXwelXcsb

Samples crossed: cp_busy_bit cp_wel_bit cp_sw_read_while_csb_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for cr_busyXwelXcsb

Bins

cp_busy_bit	cp_wel_bit	cp_sw_read_while_csb_active	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	1863689	1			T3	10593		T4	13		T7	1
auto[0]	auto[0]	auto[1]	892659	1			T4	557		T9	889		T12	8
auto[0]	auto[1]	auto[0]	476826	1			T10	4105		T12	2598		T13	2752
auto[0]	auto[1]	auto[1]	10806	1			T10	1		T12	2		T48	745
auto[1]	auto[0]	auto[0]	20820	1			T10	20		T12	203		T13	8
auto[1]	auto[0]	auto[1]	571	1			T10	1		T12	13		T13	1
auto[1]	auto[1]	auto[0]	4815	1			T10	24		T12	24		T13	7
auto[1]	auto[1]	auto[1]	127	1			T12	2		T27	7		T45	1