Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	12	0	12	100.00
Crosses	32	0	32	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	8	0	8	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	32	0	32	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	2685516	1			T1	1835		T2	1		T3	112
all_pins[1]	2685516	1			T1	1835		T2	1		T3	112
all_pins[2]	2685516	1			T1	1835		T2	1		T3	112
all_pins[3]	2685516	1			T1	1835		T2	1		T3	112
all_pins[4]	2685516	1			T1	1835		T2	1		T3	112
all_pins[5]	2685516	1			T1	1835		T2	1		T3	112
all_pins[6]	2685516	1			T1	1835		T2	1		T3	112
all_pins[7]	2685516	1			T1	1835		T2	1		T3	112

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	21452039	1			T1	14680		T2	8		T3	896
values[0x1]	32089	1			T16	17		T17	24		T19	5
transitions[0x0=>0x1]	31674	1			T16	10		T17	12		T19	4
transitions[0x1=>0x0]	31688	1			T16	10		T17	12		T19	4

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	32	0	32	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	2685251	1			T1	1835		T2	1		T3	112
all_pins[0]	values[0x1]	265	1			T16	3		T17	5		T19	1
all_pins[0]	transitions[0x0=>0x1]	184	1			T16	2		T17	2		T19	1
all_pins[0]	transitions[0x1=>0x0]	162	1			T16	1		T17	2		T19	1
all_pins[1]	values[0x0]	2685273	1			T1	1835		T2	1		T3	112
all_pins[1]	values[0x1]	243	1			T16	2		T17	5		T19	1
all_pins[1]	transitions[0x0=>0x1]	178	1			T16	1		T17	2		T19	1
all_pins[1]	transitions[0x1=>0x0]	133	1			T17	2		T20	1		T21	9
all_pins[2]	values[0x0]	2685318	1			T1	1835		T2	1		T3	112
all_pins[2]	values[0x1]	198	1			T16	1		T17	5		T20	3
all_pins[2]	transitions[0x0=>0x1]	137	1			T16	1		T17	3		T20	3
all_pins[2]	transitions[0x1=>0x0]	120	1			T16	2		T21	5		T22	5
all_pins[3]	values[0x0]	2685335	1			T1	1835		T2	1		T3	112
all_pins[3]	values[0x1]	181	1			T16	2		T17	2		T21	7
all_pins[3]	transitions[0x0=>0x1]	144	1			T16	1		T17	2		T21	7
all_pins[3]	transitions[0x1=>0x0]	136	1			T17	2		T20	6		T21	7
all_pins[4]	values[0x0]	2685343	1			T1	1835		T2	1		T3	112
all_pins[4]	values[0x1]	173	1			T16	1		T17	2		T20	6
all_pins[4]	transitions[0x0=>0x1]	139	1			T16	1		T17	1		T20	4
all_pins[4]	transitions[0x1=>0x0]	547	1			T16	2		T17	1		T19	1
all_pins[5]	values[0x0]	2684935	1			T1	1835		T2	1		T3	112
all_pins[5]	values[0x1]	581	1			T16	2		T17	2		T19	1
all_pins[5]	transitions[0x0=>0x1]	544	1			T16	1		T19	1		T20	6
all_pins[5]	transitions[0x1=>0x0]	30218	1			T16	2		T20	1		T21	5
all_pins[6]	values[0x0]	2655261	1			T1	1835		T2	1		T3	112
all_pins[6]	values[0x1]	30255	1			T16	3		T17	2		T20	1
all_pins[6]	transitions[0x0=>0x1]	30211	1			T16	1		T17	1		T20	1
all_pins[6]	transitions[0x1=>0x0]	149	1			T16	1		T19	2		T20	6
all_pins[7]	values[0x0]	2685323	1			T1	1835		T2	1		T3	112
all_pins[7]	values[0x1]	193	1			T16	3		T17	1		T19	2
all_pins[7]	transitions[0x0=>0x1]	137	1			T16	2		T17	1		T19	1
all_pins[7]	transitions[0x1=>0x0]	223	1			T16	2		T17	5		T20	4