Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	0	128	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_swap_en	2	0	2	100.00	100	1	1	2
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_addr_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	0	128	100.00	100	1	1	0

Summary for Variable cp_addr_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_addr_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

13347

1

T3

18

T4

2

T10

210

auto[1]

10369

1

T7

4

T10

115

T13

88

---

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3304	1			T13	27		T16	20		T117	14
values[1]	3047	1			T10	74		T13	20		T16	23
values[2]	2884	1			T7	4		T10	62		T27	20
values[3]	3487	1			T10	20		T13	40		T48	6
values[4]	2542	1			T10	20		T93	6		T16	21
values[5]	2813	1			T3	18		T10	60		T13	49
values[6]	2666	1			T4	2		T10	25		T13	40
values[7]	2973	1			T10	64		T11	6		T13	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	3044	1			T10	20		T13	62		T15	24
values[1]	3301	1			T10	22		T13	40		T16	21
values[2]	2979	1			T3	18		T4	2		T10	82
values[3]	2727	1			T10	20		T11	6		T13	47
values[4]	2771	1			T10	68		T16	23		T27	40
values[5]	3542	1			T93	6		T16	24		T27	20
values[6]	2665	1			T7	4		T10	49		T27	20
values[7]	2687	1			T10	64		T13	20		T14	22

---

Summary for Cross cr_all

Samples crossed: cp_addr_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	0	128	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_addr_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	143	1			T117	14		T43	7		T196	14
auto[0]	values[0]	values[1]	130	1			T170	15		T233	12		T189	24
auto[0]	values[0]	values[2]	252	1			T16	17		T102	24		T94	6
auto[0]	values[0]	values[3]	349	1			T13	8		T46	13		T91	15
auto[0]	values[0]	values[4]	407	1			T276	22		T193	8		T196	8
auto[0]	values[0]	values[5]	163	1			T178	9		T177	2		T278	13
auto[0]	values[0]	values[6]	174	1			T46	12		T38	16		T188	12
auto[0]	values[0]	values[7]	270	1			T209	10		T47	15		T33	24
auto[0]	values[1]	values[0]	125	1			T44	8		T188	9		T233	8
auto[0]	values[1]	values[1]	223	1			T13	14		T136	38		T183	14
auto[0]	values[1]	values[2]	136	1			T10	14		T43	22		T282	10
auto[0]	values[1]	values[3]	264	1			T18	17		T47	13		T273	10
auto[0]	values[1]	values[4]	240	1			T16	14		T22	12		T178	11
auto[0]	values[1]	values[5]	229	1			T27	17		T45	16		T43	11
auto[0]	values[1]	values[6]	284	1			T10	22		T27	14		T91	15
auto[0]	values[1]	values[7]	215	1			T10	12		T44	14		T81	11
auto[0]	values[2]	values[0]	174	1			T10	8		T51	15		T173	10
auto[0]	values[2]	values[1]	345	1			T10	16		T18	54		T91	9
auto[0]	values[2]	values[2]	200	1			T27	10		T18	12		T91	15
auto[0]	values[2]	values[3]	87	1			T51	15		T283	2		T54	8
auto[0]	values[2]	values[4]	161	1			T175	11		T22	8		T233	18
auto[0]	values[2]	values[5]	157	1			T18	13		T175	15		T188	11
auto[0]	values[2]	values[6]	244	1			T10	17		T46	18		T272	14
auto[0]	values[2]	values[7]	200	1			T45	15		T47	12		T32	15
auto[0]	values[3]	values[0]	238	1			T13	13		T48	6		T27	13
auto[0]	values[3]	values[1]	407	1			T46	14		T47	13		T284	14
auto[0]	values[3]	values[2]	251	1			T27	9		T205	20		T175	16
auto[0]	values[3]	values[3]	283	1			T16	11		T27	9		T18	91
auto[0]	values[3]	values[4]	243	1			T10	11		T27	16		T190	10
auto[0]	values[3]	values[5]	221	1			T18	12		T47	10		T51	16
auto[0]	values[3]	values[6]	206	1			T33	28		T81	12		T60	56
auto[0]	values[3]	values[7]	87	1			T13	5		T27	12		T45	15
auto[0]	values[4]	values[0]	153	1			T18	8		T47	10		T170	10
auto[0]	values[4]	values[1]	246	1			T16	10		T47	10		T195	20
auto[0]	values[4]	values[2]	112	1			T27	8		T45	8		T285	2
auto[0]	values[4]	values[3]	117	1			T202	12		T22	5		T33	10
auto[0]	values[4]	values[4]	263	1			T167	22		T33	9		T60	79
auto[0]	values[4]	values[5]	296	1			T93	6		T47	32		T91	8
auto[0]	values[4]	values[6]	92	1			T60	10		T159	7		T207	10
auto[0]	values[4]	values[7]	101	1			T10	14		T161	21		T286	2
auto[0]	values[5]	values[0]	153	1			T13	13		T15	24		T27	12
auto[0]	values[5]	values[1]	229	1			T43	10		T91	9		T175	8
auto[0]	values[5]	values[2]	416	1			T3	18		T10	31		T13	12
auto[0]	values[5]	values[3]	166	1			T10	13		T33	15		T178	10
auto[0]	values[5]	values[4]	126	1			T91	13		T196	10		T184	2
auto[0]	values[5]	values[5]	177	1			T16	15		T18	12		T46	12
auto[0]	values[5]	values[6]	176	1			T176	6		T46	16		T170	14
auto[0]	values[5]	values[7]	246	1			T14	22		T44	15		T43	9
auto[0]	values[6]	values[0]	159	1			T13	14		T51	10		T60	10
auto[0]	values[6]	values[1]	231	1			T13	15		T36	6		T199	6
auto[0]	values[6]	values[2]	234	1			T4	2		T196	13		T173	9
auto[0]	values[6]	values[3]	256	1			T16	14		T50	83		T159	19
auto[0]	values[6]	values[4]	136	1			T10	15		T27	16		T131	2
auto[0]	values[6]	values[5]	189	1			T44	23		T45	11		T32	14
auto[0]	values[6]	values[6]	128	1			T91	7		T196	12		T287	6
auto[0]	values[6]	values[7]	158	1			T238	42		T33	9		T51	11
auto[0]	values[7]	values[0]	234	1			T45	12		T187	26		T91	15
auto[0]	values[7]	values[1]	172	1			T27	14		T91	14		T183	7
auto[0]	values[7]	values[2]	181	1			T10	13		T32	15		T51	16
auto[0]	values[7]	values[3]	147	1			T11	6		T13	14		T27	15
auto[0]	values[7]	values[4]	209	1			T10	11		T200	98		T201	6
auto[0]	values[7]	values[5]	308	1			T203	14		T175	20		T239	8
auto[0]	values[7]	values[6]	203	1			T43	15		T91	11		T188	11
auto[0]	values[7]	values[7]	225	1			T10	13		T16	8		T175	13
auto[1]	values[0]	values[0]	182	1			T43	13		T196	6		T183	86
auto[1]	values[0]	values[1]	111	1			T170	5		T233	10		T189	16
auto[1]	values[0]	values[2]	137	1			T16	3		T18	11		T224	16
auto[1]	values[0]	values[3]	148	1			T13	19		T46	7		T91	5
auto[1]	values[0]	values[4]	116	1			T193	16		T196	12		T171	6
auto[1]	values[0]	values[5]	198	1			T172	16		T178	11		T288	10
auto[1]	values[0]	values[6]	226	1			T46	8		T38	4		T188	8
auto[1]	values[0]	values[7]	298	1			T47	25		T33	20		T80	13
auto[1]	values[1]	values[0]	118	1			T44	12		T188	11		T233	12
auto[1]	values[1]	values[1]	161	1			T13	6		T183	6		T233	9
auto[1]	values[1]	values[2]	101	1			T10	8		T43	18		T194	8
auto[1]	values[1]	values[3]	183	1			T18	34		T47	7		T175	22
auto[1]	values[1]	values[4]	144	1			T16	9		T22	8		T178	9
auto[1]	values[1]	values[5]	326	1			T27	3		T45	4		T43	9
auto[1]	values[1]	values[6]	120	1			T10	7		T27	6		T91	5
auto[1]	values[1]	values[7]	178	1			T10	11		T44	35		T81	9
auto[1]	values[2]	values[0]	181	1			T10	12		T227	4		T51	8
auto[1]	values[2]	values[1]	264	1			T10	6		T18	7		T91	11
auto[1]	values[2]	values[2]	217	1			T27	10		T186	12		T18	13
auto[1]	values[2]	values[3]	99	1			T51	6		T54	43		T289	5
auto[1]	values[2]	values[4]	107	1			T175	14		T22	12		T233	6
auto[1]	values[2]	values[5]	154	1			T18	7		T175	29		T188	9
auto[1]	values[2]	values[6]	206	1			T7	4		T10	3		T46	10
auto[1]	values[2]	values[7]	88	1			T45	5		T47	8		T32	10
auto[1]	values[3]	values[0]	248	1			T13	7		T27	7		T183	9
auto[1]	values[3]	values[1]	202	1			T46	34		T47	7		T272	12
auto[1]	values[3]	values[2]	138	1			T27	11		T175	4		T33	8
auto[1]	values[3]	values[3]	159	1			T16	18		T27	11		T18	16
auto[1]	values[3]	values[4]	161	1			T10	9		T27	4		T183	9
auto[1]	values[3]	values[5]	242	1			T18	8		T47	10		T51	12
auto[1]	values[3]	values[6]	232	1			T33	17		T81	11		T60	22
auto[1]	values[3]	values[7]	169	1			T13	15		T27	8		T100	2
auto[1]	values[4]	values[0]	110	1			T18	16		T47	10		T170	10
auto[1]	values[4]	values[1]	184	1			T16	11		T47	10		T175	8
auto[1]	values[4]	values[2]	154	1			T27	12		T45	12		T188	11
auto[1]	values[4]	values[3]	163	1			T202	8		T22	17		T33	10
auto[1]	values[4]	values[4]	204	1			T33	14		T60	50		T38	23
auto[1]	values[4]	values[5]	186	1			T47	7		T91	12		T183	7
auto[1]	values[4]	values[6]	91	1			T60	15		T159	13		T232	11
auto[1]	values[4]	values[7]	70	1			T10	6		T290	16		T161	10
auto[1]	values[5]	values[0]	146	1			T13	9		T27	8		T45	8
auto[1]	values[5]	values[1]	163	1			T43	10		T91	11		T175	12
auto[1]	values[5]	values[2]	154	1			T10	9		T13	15		T46	16
auto[1]	values[5]	values[3]	115	1			T10	7		T33	5		T178	10
auto[1]	values[5]	values[4]	59	1			T91	7		T196	10		T229	6
auto[1]	values[5]	values[5]	253	1			T16	9		T18	8		T46	16
auto[1]	values[5]	values[6]	56	1			T46	7		T170	6		T60	5
auto[1]	values[5]	values[7]	178	1			T44	5		T43	11		T46	6
auto[1]	values[6]	values[0]	420	1			T13	6		T51	10		T60	28
auto[1]	values[6]	values[1]	111	1			T13	5		T32	5		T33	8
auto[1]	values[6]	values[2]	148	1			T196	7		T173	18		T161	15
auto[1]	values[6]	values[3]	91	1			T16	6		T159	7		T171	7
auto[1]	values[6]	values[4]	79	1			T10	10		T27	4		T175	11
auto[1]	values[6]	values[5]	176	1			T44	5		T45	9		T32	13
auto[1]	values[6]	values[6]	87	1			T91	13		T196	8		T189	15
auto[1]	values[6]	values[7]	63	1			T238	4		T33	15		T51	11
auto[1]	values[7]	values[0]	260	1			T45	8		T91	5		T238	84
auto[1]	values[7]	values[1]	122	1			T27	6		T91	6		T183	13
auto[1]	values[7]	values[2]	148	1			T10	7		T32	5		T51	8
auto[1]	values[7]	values[3]	100	1			T13	6		T27	5		T22	11
auto[1]	values[7]	values[4]	116	1			T10	12		T18	9		T91	11
auto[1]	values[7]	values[5]	267	1			T175	21		T239	13		T81	6
auto[1]	values[7]	values[6]	140	1			T43	5		T197	10		T91	9
auto[1]	values[7]	values[7]	141	1			T10	8		T16	12		T175	7