Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	13	0	13	100.00
Crosses	60	0	60	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_addr_type	5	0	5	100.00	100	1	1	0
cp_filtered	2	0	2	100.00	100	1	1	2
cp_opcode	6	0	6	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_mailbox_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	60	0	60	100.00	100	1	1	0

Summary for Variable cp_addr_type

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for cp_addr_type

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[ReadAddrWithinMailbox]	356	1			T10	6		T13	1		T16	2
auto[ReadAddrCrossIntoMailbox]	307	1			T10	8		T13	4		T16	3
auto[ReadAddrCrossOutOfMailbox]	277	1			T10	4		T13	4		T16	1
auto[ReadAddrCrossAllMailbox]	182	1			T10	4		T13	1		T16	2
auto[ReadAddrOutsideMailbox]	3029	1			T3	4		T7	4		T10	39

---

Summary for Variable cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_filtered

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2074

1

T3

2

T7

2

T10

32

auto[1]

2077

1

T3

2

T7

2

T10

29

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	714	1			T10	12		T13	5		T16	5
read_ops[0x0b]	689	1			T3	2		T10	7		T13	4
read_ops[0x3b]	711	1			T10	9		T13	4		T16	5
read_ops[0x6b]	634	1			T3	2		T7	2		T10	12
read_ops[0xbb]	711	1			T10	13		T13	7		T15	6
read_ops[0xeb]	692	1			T7	2		T10	8		T13	3

---

Summary for Cross cr_all

Samples crossed: cp_opcode cp_addr_type cp_filtered

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	60	0	60	100.00

Automatically Generated Cross Bins for cr_all

Bins

cp_opcode	cp_addr_type	cp_filtered	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T27	1		T18	2		T291	1
read_ops[0x03]	auto[ReadAddrWithinMailbox]	auto[1]	32	1			T10	2		T46	1		T175	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[0]	22	1			T16	1		T91	1		T175	1
read_ops[0x03]	auto[ReadAddrCrossIntoMailbox]	auto[1]	30	1			T10	1		T13	1		T45	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	20	1			T43	2		T91	1		T60	1
read_ops[0x03]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	24	1			T13	1		T45	1		T43	2
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T43	1		T91	1		T175	1
read_ops[0x03]	auto[ReadAddrCrossAllMailbox]	auto[1]	18	1			T10	1		T16	2		T45	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[0]	248	1			T10	4		T13	1		T16	1
read_ops[0x03]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T10	4		T13	2		T16	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[0]	28	1			T13	1		T27	1		T43	1
read_ops[0x0b]	auto[ReadAddrWithinMailbox]	auto[1]	21	1			T45	1		T18	1		T193	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	28	1			T10	2		T13	1		T183	1
read_ops[0x0b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	22	1			T27	1		T18	2		T91	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	24	1			T27	1		T18	1		T91	1
read_ops[0x0b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T27	1		T91	2		T60	2
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T10	2		T45	1		T178	1
read_ops[0x0b]	auto[ReadAddrCrossAllMailbox]	auto[1]	13	1			T239	1		T22	1		T178	1
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[0]	262	1			T3	1		T10	2		T13	2
read_ops[0x0b]	auto[ReadAddrOutsideMailbox]	auto[1]	252	1			T3	1		T10	1		T27	3
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T10	3		T27	1		T203	2
read_ops[0x3b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T203	2		T43	1		T18	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	25	1			T10	1		T46	1		T175	1
read_ops[0x3b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	25	1			T13	2		T27	1		T43	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	13	1			T10	1		T18	1		T91	1
read_ops[0x3b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	21	1			T18	2		T239	1		T33	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[0]	18	1			T27	2		T183	1		T60	1
read_ops[0x3b]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T196	1		T178	1		T188	1
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[0]	255	1			T10	1		T13	1		T16	5
read_ops[0x3b]	auto[ReadAddrOutsideMailbox]	auto[1]	278	1			T10	3		T13	1		T27	6
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[0]	36	1			T10	1		T203	1		T45	2
read_ops[0x6b]	auto[ReadAddrWithinMailbox]	auto[1]	27	1			T203	1		T46	1		T183	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[0]	33	1			T10	2		T27	1		T91	1
read_ops[0x6b]	auto[ReadAddrCrossIntoMailbox]	auto[1]	18	1			T10	1		T175	1		T60	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	27	1			T27	1		T91	1		T175	1
read_ops[0x6b]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	17	1			T10	1		T32	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T10	1		T91	1		T33	1
read_ops[0x6b]	auto[ReadAddrCrossAllMailbox]	auto[1]	9	1			T47	1		T32	1		T161	1
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[0]	235	1			T3	1		T7	1		T10	3
read_ops[0x6b]	auto[ReadAddrOutsideMailbox]	auto[1]	215	1			T3	1		T7	1		T10	3
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[0]	34	1			T203	1		T91	1		T175	2
read_ops[0xbb]	auto[ReadAddrWithinMailbox]	auto[1]	36	1			T16	1		T203	1		T175	2
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	26	1			T43	1		T46	1		T47	1
read_ops[0xbb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	28	1			T10	1		T16	2		T193	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	28	1			T10	1		T13	2		T46	1
read_ops[0xbb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	28	1			T10	1		T16	1		T91	1
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T33	1		T60	1		T292	2
read_ops[0xbb]	auto[ReadAddrCrossAllMailbox]	auto[1]	15	1			T47	1		T196	1		T51	1
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[0]	249	1			T10	6		T13	2		T15	3
read_ops[0xbb]	auto[ReadAddrOutsideMailbox]	auto[1]	250	1			T10	4		T13	3		T15	3
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[0]	25	1			T91	1		T282	1		T193	1
read_ops[0xeb]	auto[ReadAddrWithinMailbox]	auto[1]	31	1			T16	1		T47	1		T91	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[0]	24	1			T27	1		T45	1		T46	1
read_ops[0xeb]	auto[ReadAddrCrossIntoMailbox]	auto[1]	26	1			T27	1		T91	1		T175	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[0]	29	1			T13	1		T91	1		T196	1
read_ops[0xeb]	auto[ReadAddrCrossOutOfMailbox]	auto[1]	25	1			T46	2		T175	1		T239	2
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[0]	17	1			T13	1		T273	2		T175	1
read_ops[0xeb]	auto[ReadAddrCrossAllMailbox]	auto[1]	8	1			T18	1		T273	2		T175	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[0]	240	1			T7	1		T10	2		T13	1
read_ops[0xeb]	auto[ReadAddrOutsideMailbox]	auto[1]	267	1			T7	1		T10	6		T16	6