Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

Group : spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
99.32	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	18	0	18	100.00
Crosses	128	1	127	99.22

Variables for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_data	8	0	8	100.00	100	1	1	0
cp_mask	8	0	8	100.00	100	1	1	0
cp_payload_swap_en	2	0	2	100.00	100	1	1	2

Crosses for Group spi_device_env_pkg::spi_device_env_cov::passthrough_payload_swap_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	128	1	127	99.22	100	1	1	0

Summary for Variable cp_data

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_data

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2598	1			T10	40		T27	20		T94	6
values[1]	3008	1			T10	23		T13	20		T93	6
values[2]	2544	1			T10	65		T13	22		T16	41
values[3]	3126	1			T10	54		T13	27		T16	23
values[4]	3327	1			T10	20		T13	20		T14	22
values[5]	2890	1			T4	2		T7	4		T10	41
values[6]	3012	1			T10	40		T11	6		T13	40
values[7]	3211	1			T3	18		T10	42		T13	20

---

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_mask

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0]	2915	1			T13	62		T15	24		T16	49
values[1]	2828	1			T10	25		T13	27		T16	23
values[2]	2679	1			T10	60		T93	6		T27	20
values[3]	2994	1			T10	70		T13	47		T14	22
values[4]	3441	1			T7	4		T10	42		T169	4
values[5]	3191	1			T10	66		T11	6		T13	20
values[6]	2923	1			T3	18		T10	42		T13	20
values[7]	2745	1			T4	2		T10	20		T13	20

---

Summary for Variable cp_payload_swap_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_payload_swap_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

23062

1

T3

18

T4

2

T7

4

auto[1]

654

1

T10

5

T13

6

T16

6

---

Summary for Cross cr_all

Samples crossed: cp_payload_swap_en cp_data cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	128	1	127	99.22	1

Automatically Generated Cross Bins for cr_all

Uncovered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	NUMBER	STATUS
[auto[1]]	[values[7]]	[values[7]]	0	1	1

Covered bins

cp_payload_swap_en	cp_data	cp_mask	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	values[0]	values[0]	152	1			T47	20		T170	16		T171	20
auto[0]	values[0]	values[1]	385	1			T94	6		T43	20		T172	16
auto[0]	values[0]	values[2]	428	1			T10	20		T91	38		T173	24
auto[0]	values[0]	values[3]	249	1			T60	20		T171	18		T174	8
auto[0]	values[0]	values[4]	448	1			T131	2		T91	19		T175	20
auto[0]	values[0]	values[5]	388	1			T10	20		T27	20		T176	6
auto[0]	values[0]	values[6]	312	1			T167	22		T81	69		T177	2
auto[0]	values[0]	values[7]	162	1			T46	22		T178	100		T179	20
auto[0]	values[1]	values[0]	468	1			T18	19		T91	20		T81	20
auto[0]	values[1]	values[1]	291	1			T91	20		T180	20		T181	2
auto[0]	values[1]	values[2]	266	1			T93	6		T27	20		T45	39
auto[0]	values[1]	values[3]	258	1			T13	19		T16	24		T27	17
auto[0]	values[1]	values[4]	474	1			T47	40		T175	45		T182	14
auto[0]	values[1]	values[5]	499	1			T10	23		T44	18		T43	16
auto[0]	values[1]	values[6]	301	1			T183	20		T33	20		T184	2
auto[0]	values[1]	values[7]	360	1			T44	20		T183	80		T159	90
auto[0]	values[2]	values[0]	357	1			T13	22		T27	20		T91	17
auto[0]	values[2]	values[1]	279	1			T18	23		T185	2		T33	23
auto[0]	values[2]	values[2]	313	1			T36	6		T186	12		T187	26
auto[0]	values[2]	values[3]	216	1			T10	20		T16	41		T188	20
auto[0]	values[2]	values[4]	292	1			T18	19		T183	39		T189	18
auto[0]	values[2]	values[5]	461	1			T10	23		T27	18		T100	2
auto[0]	values[2]	values[6]	255	1			T10	20		T190	10		T191	10
auto[0]	values[2]	values[7]	294	1			T46	28		T175	22		T192	4
auto[0]	values[3]	values[0]	396	1			T193	25		T194	8		T22	20
auto[0]	values[3]	values[1]	502	1			T10	25		T13	24		T16	21
auto[0]	values[3]	values[2]	274	1			T18	26		T91	20		T175	20
auto[0]	values[3]	values[3]	350	1			T10	29		T195	20		T22	19
auto[0]	values[3]	values[4]	469	1			T175	22		T196	20		T60	27
auto[0]	values[3]	values[5]	349	1			T50	83		T46	19		T175	21
auto[0]	values[3]	values[6]	246	1			T197	10		T198	20		T56	16
auto[0]	values[3]	values[7]	445	1			T18	61		T91	20		T175	20
auto[0]	values[4]	values[0]	337	1			T16	18		T199	6		T33	40
auto[0]	values[4]	values[1]	341	1			T18	22		T33	19		T60	38
auto[0]	values[4]	values[2]	507	1			T200	98		T47	56		T183	20
auto[0]	values[4]	values[3]	343	1			T14	22		T46	47		T47	20
auto[0]	values[4]	values[4]	292	1			T10	20		T18	19		T91	20
auto[0]	values[4]	values[5]	435	1			T13	18		T46	70		T171	36
auto[0]	values[4]	values[6]	538	1			T43	18		T201	6		T18	40
auto[0]	values[4]	values[7]	431	1			T44	48		T45	19		T46	20
auto[0]	values[5]	values[0]	410	1			T13	20		T15	24		T16	27
auto[0]	values[5]	values[1]	482	1			T27	19		T45	19		T81	21
auto[0]	values[5]	values[2]	257	1			T136	38		T202	18		T51	21
auto[0]	values[5]	values[3]	381	1			T10	20		T13	27		T43	19
auto[0]	values[5]	values[4]	265	1			T7	4		T46	20		T81	20
auto[0]	values[5]	values[5]	284	1			T44	28		T203	14		T18	86
auto[0]	values[5]	values[6]	508	1			T10	20		T16	20		T45	20
auto[0]	values[5]	values[7]	238	1			T4	2		T48	6		T22	22
auto[0]	values[6]	values[0]	340	1			T13	20		T27	40		T22	22
auto[0]	values[6]	values[1]	289	1			T27	20		T43	38		T159	20
auto[0]	values[6]	values[2]	370	1			T10	39		T196	20		T32	96
auto[0]	values[6]	values[3]	578	1			T47	20		T51	24		T204	217
auto[0]	values[6]	values[4]	448	1			T91	20		T175	23		T33	20
auto[0]	values[6]	values[5]	323	1			T11	6		T27	20		T91	18
auto[0]	values[6]	values[6]	303	1			T13	20		T27	20		T47	20
auto[0]	values[6]	values[7]	282	1			T43	17		T205	20		T91	19
auto[0]	values[7]	values[0]	361	1			T175	25		T183	180		T206	18
auto[0]	values[7]	values[1]	189	1			T27	20		T18	20		T188	19
auto[0]	values[7]	values[2]	186	1			T46	20		T207	10		T208	16
auto[0]	values[7]	values[3]	536	1			T209	10		T32	17		T33	32
auto[0]	values[7]	values[4]	669	1			T10	21		T169	4		T193	21
auto[0]	values[7]	values[5]	342	1			T117	14		T45	20		T196	20
auto[0]	values[7]	values[6]	377	1			T3	18		T45	20		T175	41
auto[0]	values[7]	values[7]	481	1			T10	20		T13	20		T27	20
auto[1]	values[0]	values[0]	6	1			T170	4		T210	1		T211	1
auto[1]	values[0]	values[1]	7	1			T212	1		T213	4		T214	2
auto[1]	values[0]	values[2]	13	1			T91	2		T215	2		T216	2
auto[1]	values[0]	values[3]	9	1			T171	2		T217	2		T218	1
auto[1]	values[0]	values[4]	9	1			T91	1		T196	4		T161	1
auto[1]	values[0]	values[5]	17	1			T60	2		T216	1		T218	3
auto[1]	values[0]	values[6]	11	1			T81	3		T219	3		T220	1
auto[1]	values[0]	values[7]	2	1			T46	1		T178	1		-	-
auto[1]	values[1]	values[0]	19	1			T18	1		T178	2		T188	1
auto[1]	values[1]	values[1]	6	1			T221	2		T222	1		T54	1
auto[1]	values[1]	values[2]	8	1			T45	1		T223	3		T224	1
auto[1]	values[1]	values[3]	10	1			T13	1		T27	3		T171	2
auto[1]	values[1]	values[4]	8	1			T175	4		T225	1		T226	1
auto[1]	values[1]	values[5]	21	1			T44	2		T43	4		T175	1
auto[1]	values[1]	values[6]	12	1			T227	2		T159	1		T223	1
auto[1]	values[1]	values[7]	7	1			T183	3		T159	1		T179	1
auto[1]	values[2]	values[0]	11	1			T91	3		T183	2		T33	1
auto[1]	values[2]	values[1]	8	1			T18	1		T51	1		T159	1
auto[1]	values[2]	values[2]	9	1			T188	1		T216	5		T228	1
auto[1]	values[2]	values[3]	3	1			T226	1		T211	2		-	-
auto[1]	values[2]	values[4]	6	1			T18	1		T183	1		T189	2
auto[1]	values[2]	values[5]	20	1			T27	2		T33	1		T218	2
auto[1]	values[2]	values[6]	11	1			T10	2		T229	3		T230	1
auto[1]	values[2]	values[7]	9	1			T175	3		T215	1		T229	1
auto[1]	values[3]	values[0]	13	1			T33	1		T170	3		T188	1
auto[1]	values[3]	values[1]	13	1			T13	3		T16	2		T81	1
auto[1]	values[3]	values[2]	13	1			T18	5		T225	2		T54	2
auto[1]	values[3]	values[3]	15	1			T22	2		T33	6		T161	2
auto[1]	values[3]	values[4]	17	1			T60	1		T231	1		T232	2
auto[1]	values[3]	values[5]	11	1			T46	1		T233	2		T229	5
auto[1]	values[3]	values[6]	6	1			T178	1		T233	2		T234	3
auto[1]	values[3]	values[7]	7	1			T51	2		T225	1		T235	1
auto[1]	values[4]	values[0]	16	1			T16	2		T60	3		T38	3
auto[1]	values[4]	values[1]	9	1			T18	2		T33	1		T188	1
auto[1]	values[4]	values[2]	15	1			T47	3		T32	1		T171	1
auto[1]	values[4]	values[3]	8	1			T46	1		T91	2		T33	1
auto[1]	values[4]	values[4]	5	1			T18	1		T170	1		T236	1
auto[1]	values[4]	values[5]	20	1			T13	2		T237	1		T163	3
auto[1]	values[4]	values[6]	22	1			T43	2		T91	1		T238	1
auto[1]	values[4]	values[7]	8	1			T44	1		T45	1		T239	1
auto[1]	values[5]	values[0]	21	1			T16	2		T60	1		T224	2
auto[1]	values[5]	values[1]	12	1			T27	1		T45	1		T51	3
auto[1]	values[5]	values[2]	5	1			T202	2		T240	2		T241	1
auto[1]	values[5]	values[3]	6	1			T10	1		T43	1		T225	2
auto[1]	values[5]	values[4]	6	1			T242	1		T218	1		T241	4
auto[1]	values[5]	values[5]	2	1			T18	1		T189	1		-	-
auto[1]	values[5]	values[6]	4	1			T226	2		T243	2		-	-
auto[1]	values[5]	values[7]	9	1			T244	4		T213	1		T241	3
auto[1]	values[6]	values[0]	6	1			T22	1		T173	2		T212	3
auto[1]	values[6]	values[1]	10	1			T43	2		T189	1		T245	1
auto[1]	values[6]	values[2]	10	1			T10	1		T32	2		T217	4
auto[1]	values[6]	values[3]	19	1			T159	4		T231	3		T236	5
auto[1]	values[6]	values[4]	7	1			T224	2		T246	2		T247	2
auto[1]	values[6]	values[5]	11	1			T91	2		T224	1		T230	3
auto[1]	values[6]	values[6]	6	1			T163	1		T226	3		T248	2
auto[1]	values[6]	values[7]	10	1			T43	3		T91	1		T81	1
auto[1]	values[7]	values[0]	2	1			T237	1		T55	1		-	-
auto[1]	values[7]	values[1]	5	1			T188	1		T222	1		T249	2
auto[1]	values[7]	values[2]	5	1			T208	2		T224	1		T250	1
auto[1]	values[7]	values[3]	13	1			T32	3		T173	1		T251	1
auto[1]	values[7]	values[4]	26	1			T10	1		T193	3		T51	1
auto[1]	values[7]	values[5]	8	1			T224	1		T242	1		T55	5
auto[1]	values[7]	values[6]	11	1			T22	1		T188	2		T171	2