Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.77	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	48	2	46	95.83

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	8	0	8	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=7}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	48	2	46	95.83	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	748	1			T16	8		T17	10		T19	4
all_values[1]	748	1			T16	8		T17	10		T19	4
all_values[2]	748	1			T16	8		T17	10		T19	4
all_values[3]	748	1			T16	8		T17	10		T19	4
all_values[4]	748	1			T16	8		T17	10		T19	4
all_values[5]	748	1			T16	8		T17	10		T19	4
all_values[6]	748	1			T16	8		T17	10		T19	4
all_values[7]	748	1			T16	8		T17	10		T19	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3123

1

T16

33

T17

29

T19

21

auto[1]

2861

1

T16

31

T17

51

T19

11

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2351

1

T16

20

T17

30

T19

19

auto[1]

3633

1

T16

44

T17

50

T19

13

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3433

1

T16

38

T17

47

T19

23

auto[1]

2551

1

T16

26

T17

33

T19

9

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	48	2	46	95.83	2
Automatically Generated Cross Bins	48	2	46	95.83	2
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Element holes

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	NUMBER	STATUS
[all_values[5]]	[auto[0]]	*	[auto[1]]	--	--	2

Covered bins

cp_intr	cp_intr_test	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	auto[0]	147	1			T19	1		T20	7		T21	4
all_values[0]	auto[0]	auto[0]	auto[1]	63	1			T17	2		T19	1		T20	1
all_values[0]	auto[0]	auto[1]	auto[0]	146	1			T16	1		T17	2		T20	1
all_values[0]	auto[0]	auto[1]	auto[1]	79	1			T16	2		T17	1		T20	4
all_values[0]	auto[1]	auto[0]	auto[1]	148	1			T16	2		T17	1		T19	1
all_values[0]	auto[1]	auto[1]	auto[1]	165	1			T16	3		T17	4		T19	1
all_values[1]	auto[0]	auto[0]	auto[0]	141	1			T16	4		T19	2		T20	3
all_values[1]	auto[0]	auto[0]	auto[1]	77	1			T16	1		T17	3		T19	1
all_values[1]	auto[0]	auto[1]	auto[0]	123	1			T16	1		T20	2		T21	3
all_values[1]	auto[0]	auto[1]	auto[1]	84	1			T16	1		T17	2		T20	1
all_values[1]	auto[1]	auto[0]	auto[1]	190	1			T16	1		T17	3		T19	1
all_values[1]	auto[1]	auto[1]	auto[1]	133	1			T17	2		T20	5		T21	4
all_values[2]	auto[0]	auto[0]	auto[0]	143	1			T16	1		T19	1		T20	3
all_values[2]	auto[0]	auto[0]	auto[1]	72	1			T16	2		T17	1		T19	1
all_values[2]	auto[0]	auto[1]	auto[0]	122	1			T16	1		T17	1		T20	1
all_values[2]	auto[0]	auto[1]	auto[1]	80	1			T17	2		T20	2		T21	3
all_values[2]	auto[1]	auto[0]	auto[1]	164	1			T16	2		T17	1		T19	2
all_values[2]	auto[1]	auto[1]	auto[1]	167	1			T16	2		T17	5		T20	3
all_values[3]	auto[0]	auto[0]	auto[0]	143	1			T17	2		T19	2		T20	5
all_values[3]	auto[0]	auto[0]	auto[1]	72	1			T16	4		T20	2		T21	2
all_values[3]	auto[0]	auto[1]	auto[0]	118	1			T17	4		T19	2		T20	4
all_values[3]	auto[0]	auto[1]	auto[1]	84	1			T16	1		T17	1		T21	2
all_values[3]	auto[1]	auto[0]	auto[1]	176	1			T16	2		T17	1		T20	5
all_values[3]	auto[1]	auto[1]	auto[1]	155	1			T16	1		T17	2		T20	2
all_values[4]	auto[0]	auto[0]	auto[0]	156	1			T16	1		T17	3		T19	3
all_values[4]	auto[0]	auto[0]	auto[1]	73	1			T16	1		T20	1		T21	4
all_values[4]	auto[0]	auto[1]	auto[0]	130	1			T16	2		T17	2		T20	2
all_values[4]	auto[0]	auto[1]	auto[1]	71	1			T16	1		T20	3		T21	3
all_values[4]	auto[1]	auto[0]	auto[1]	161	1			T16	2		T17	3		T20	6
all_values[4]	auto[1]	auto[1]	auto[1]	157	1			T16	1		T17	2		T19	1
all_values[5]	auto[0]	auto[0]	auto[0]	226	1			T17	1		T19	1		T20	5
all_values[5]	auto[0]	auto[1]	auto[0]	238	1			T16	5		T17	6		T19	2
all_values[5]	auto[1]	auto[0]	auto[1]	155	1			T16	2		T20	2		T21	7
all_values[5]	auto[1]	auto[1]	auto[1]	129	1			T16	1		T17	3		T19	1
all_values[6]	auto[0]	auto[0]	auto[0]	162	1			T16	1		T17	1		T19	2
all_values[6]	auto[0]	auto[0]	auto[1]	72	1			T16	2		T17	2		T20	2
all_values[6]	auto[0]	auto[1]	auto[0]	119	1			T17	2		T19	2		T20	6
all_values[6]	auto[0]	auto[1]	auto[1]	83	1			T16	1		T17	2		T21	1
all_values[6]	auto[1]	auto[0]	auto[1]	176	1			T16	1		T20	6		T21	6
all_values[6]	auto[1]	auto[1]	auto[1]	136	1			T16	3		T17	3		T20	2
all_values[7]	auto[0]	auto[0]	auto[0]	128	1			T16	2		T17	4		T19	1
all_values[7]	auto[0]	auto[0]	auto[1]	79	1			T20	2		T21	3		T22	1
all_values[7]	auto[0]	auto[1]	auto[0]	109	1			T16	1		T17	2		T20	2
all_values[7]	auto[0]	auto[1]	auto[1]	93	1			T16	2		T17	1		T19	1
all_values[7]	auto[1]	auto[0]	auto[1]	199	1			T16	2		T17	1		T19	1
all_values[7]	auto[1]	auto[1]	auto[1]	140	1			T16	1		T17	2		T19	1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal