Unified Coverage Report :: Group :: spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

Group : spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_spi_device_env_0.1/spi_device_env_cov.sv

---

Summary for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	11	0	11	100.00
Crosses	30	0	30	100.00

Variables for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_active	2	0	2	100.00	100	1	1	2
cp_is_hw_return	2	0	2	100.00	100	1	1	2
cp_is_write	2	0	2	100.00	100	1	1	2
cp_locality	5	0	5	100.00	100	1	1	0

Crosses for Group spi_device_env_pkg::spi_device_env_cov::tpm_sts_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cr_all	30	0	30	100.00	100	1	1	0

Summary for Variable cp_active

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_active

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1879

1

T1

4

T2

2

T8

1

auto[1]

1791

1

T1

8

T2

3

T8

2

---

Summary for Variable cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_hw_return

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2023

1

T1

12

T10

10

T13

15

auto[1]

1647

1

T2

5

T8

3

T10

6

---

Summary for Variable cp_is_write

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_is_write

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2887

1

T1

8

T2

5

T8

3

auto[1]

783

1

T1

4

T10

5

T13

5

---

Summary for Variable cp_locality

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for cp_locality

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid[0]	740	1			T1	2		T2	1		T10	4
valid[1]	777	1			T1	3		T2	2		T10	5
valid[2]	680	1			T1	1		T8	2		T10	2
valid[3]	731	1			T1	3		T2	2		T10	3
valid[4]	742	1			T1	3		T8	1		T10	2

---

Summary for Cross cr_all

Samples crossed: cp_is_write cp_active cp_locality cp_is_hw_return

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	30	0	30	100.00
Automatically Generated Cross Bins	30	0	30	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cr_all

Bins

cp_is_write	cp_active	cp_locality	cp_is_hw_return	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	valid[0]	auto[0]	116	1			T10	1		T29	2		T30	1
auto[0]	auto[0]	valid[0]	auto[1]	173	1			T10	1		T13	1		T31	1
auto[0]	auto[0]	valid[1]	auto[0]	122	1			T13	2		T29	2		T30	1
auto[0]	auto[0]	valid[1]	auto[1]	162	1			T2	1		T31	1		T315	1
auto[0]	auto[0]	valid[2]	auto[0]	125	1			T13	2		T16	2		T49	2
auto[0]	auto[0]	valid[2]	auto[1]	166	1			T13	1		T31	1		T37	1
auto[0]	auto[0]	valid[3]	auto[0]	137	1			T1	1		T13	1		T30	1
auto[0]	auto[0]	valid[3]	auto[1]	160	1			T2	1		T10	1		T31	1
auto[0]	auto[0]	valid[4]	auto[0]	143	1			T1	2		T13	1		T16	4
auto[0]	auto[0]	valid[4]	auto[1]	177	1			T8	1		T13	1		T31	1
auto[0]	auto[1]	valid[0]	auto[0]	131	1			T1	1		T16	7		T49	1
auto[0]	auto[1]	valid[0]	auto[1]	162	1			T2	1		T10	1		T30	1
auto[0]	auto[1]	valid[1]	auto[0]	128	1			T1	2		T10	2		T29	1
auto[0]	auto[1]	valid[1]	auto[1]	197	1			T2	1		T10	1		T31	1
auto[0]	auto[1]	valid[2]	auto[0]	111	1			T10	1		T13	1		T16	2
auto[0]	auto[1]	valid[2]	auto[1]	136	1			T8	2		T88	1		T83	1
auto[0]	auto[1]	valid[3]	auto[0]	110	1			T1	1		T13	1		T16	3
auto[0]	auto[1]	valid[3]	auto[1]	156	1			T2	1		T10	2		T13	1
auto[0]	auto[1]	valid[4]	auto[0]	117	1			T1	1		T10	1		T13	2
auto[0]	auto[1]	valid[4]	auto[1]	158	1			T37	1		T49	1		T88	1
auto[1]	auto[0]	valid[0]	auto[0]	81	1			T10	1		T29	1		T49	1
auto[1]	auto[0]	valid[1]	auto[0]	88	1			T29	2		T306	1		T18	1
auto[1]	auto[0]	valid[2]	auto[0]	66	1			T1	1		T13	1		T16	1
auto[1]	auto[0]	valid[3]	auto[0]	88	1			T30	1		T16	1		T49	2
auto[1]	auto[0]	valid[4]	auto[0]	75	1			T29	1		T16	1		T83	1
auto[1]	auto[1]	valid[0]	auto[0]	77	1			T1	1		T13	1		T30	1
auto[1]	auto[1]	valid[1]	auto[0]	80	1			T1	1		T10	2		T13	1
auto[1]	auto[1]	valid[2]	auto[0]	76	1			T10	1		T29	1		T31	1
auto[1]	auto[1]	valid[3]	auto[0]	80	1			T1	1		T16	1		T18	1
auto[1]	auto[1]	valid[4]	auto[0]	72	1			T10	1		T13	2		T49	1

User Defined Cross Bins for cr_all

Excluded/Illegal bins

NAME	COUNT	STATUS
invalid	0	Illegal